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559d6701 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/core.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "CORE" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/err.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/seq_file.h> | |
31 | #include <linux/debugfs.h> | |
32 | #include <linux/io.h> | |
33 | #include <linux/device.h> | |
8a2cfea8 | 34 | #include <linux/regulator/consumer.h> |
559d6701 TV |
35 | |
36 | #include <plat/display.h> | |
37 | #include <plat/clock.h> | |
38 | ||
39 | #include "dss.h" | |
40 | ||
41 | static struct { | |
42 | struct platform_device *pdev; | |
43 | int ctx_id; | |
44 | ||
45 | struct clk *dss_ick; | |
46 | struct clk *dss1_fck; | |
47 | struct clk *dss2_fck; | |
48 | struct clk *dss_54m_fck; | |
49 | struct clk *dss_96m_fck; | |
50 | unsigned num_clks_enabled; | |
8a2cfea8 TV |
51 | |
52 | struct regulator *vdds_dsi_reg; | |
53 | struct regulator *vdds_sdi_reg; | |
54 | struct regulator *vdda_dac_reg; | |
559d6701 TV |
55 | } core; |
56 | ||
57 | static void dss_clk_enable_all_no_ctx(void); | |
58 | static void dss_clk_disable_all_no_ctx(void); | |
59 | static void dss_clk_enable_no_ctx(enum dss_clock clks); | |
60 | static void dss_clk_disable_no_ctx(enum dss_clock clks); | |
61 | ||
62 | static char *def_disp_name; | |
63 | module_param_named(def_disp, def_disp_name, charp, 0); | |
64 | MODULE_PARM_DESC(def_disp_name, "default display name"); | |
65 | ||
66 | #ifdef DEBUG | |
67 | unsigned int dss_debug; | |
68 | module_param_named(debug, dss_debug, bool, 0644); | |
69 | #endif | |
70 | ||
71 | /* CONTEXT */ | |
72 | static int dss_get_ctx_id(void) | |
73 | { | |
74 | struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; | |
75 | int r; | |
76 | ||
77 | if (!pdata->get_last_off_on_transaction_id) | |
78 | return 0; | |
79 | r = pdata->get_last_off_on_transaction_id(&core.pdev->dev); | |
80 | if (r < 0) { | |
81 | dev_err(&core.pdev->dev, "getting transaction ID failed, " | |
82 | "will force context restore\n"); | |
83 | r = -1; | |
84 | } | |
85 | return r; | |
86 | } | |
87 | ||
88 | int dss_need_ctx_restore(void) | |
89 | { | |
90 | int id = dss_get_ctx_id(); | |
91 | ||
92 | if (id < 0 || id != core.ctx_id) { | |
93 | DSSDBG("ctx id %d -> id %d\n", | |
94 | core.ctx_id, id); | |
95 | core.ctx_id = id; | |
96 | return 1; | |
97 | } else { | |
98 | return 0; | |
99 | } | |
100 | } | |
101 | ||
102 | static void save_all_ctx(void) | |
103 | { | |
104 | DSSDBG("save context\n"); | |
105 | ||
106 | dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); | |
107 | ||
108 | dss_save_context(); | |
109 | dispc_save_context(); | |
110 | #ifdef CONFIG_OMAP2_DSS_DSI | |
111 | dsi_save_context(); | |
112 | #endif | |
113 | ||
114 | dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); | |
115 | } | |
116 | ||
117 | static void restore_all_ctx(void) | |
118 | { | |
119 | DSSDBG("restore context\n"); | |
120 | ||
121 | dss_clk_enable_all_no_ctx(); | |
122 | ||
123 | dss_restore_context(); | |
124 | dispc_restore_context(); | |
125 | #ifdef CONFIG_OMAP2_DSS_DSI | |
126 | dsi_restore_context(); | |
127 | #endif | |
128 | ||
129 | dss_clk_disable_all_no_ctx(); | |
130 | } | |
131 | ||
5c18df85 | 132 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) |
559d6701 TV |
133 | /* CLOCKS */ |
134 | static void core_dump_clocks(struct seq_file *s) | |
135 | { | |
136 | int i; | |
137 | struct clk *clocks[5] = { | |
138 | core.dss_ick, | |
139 | core.dss1_fck, | |
140 | core.dss2_fck, | |
141 | core.dss_54m_fck, | |
142 | core.dss_96m_fck | |
143 | }; | |
144 | ||
145 | seq_printf(s, "- CORE -\n"); | |
146 | ||
147 | seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled); | |
148 | ||
149 | for (i = 0; i < 5; i++) { | |
150 | if (!clocks[i]) | |
151 | continue; | |
152 | seq_printf(s, "%-15s\t%lu\t%d\n", | |
153 | clocks[i]->name, | |
154 | clk_get_rate(clocks[i]), | |
155 | clocks[i]->usecount); | |
156 | } | |
157 | } | |
5c18df85 | 158 | #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ |
559d6701 TV |
159 | |
160 | static int dss_get_clock(struct clk **clock, const char *clk_name) | |
161 | { | |
162 | struct clk *clk; | |
163 | ||
164 | clk = clk_get(&core.pdev->dev, clk_name); | |
165 | ||
166 | if (IS_ERR(clk)) { | |
167 | DSSERR("can't get clock %s", clk_name); | |
168 | return PTR_ERR(clk); | |
169 | } | |
170 | ||
171 | *clock = clk; | |
172 | ||
173 | DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); | |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
178 | static int dss_get_clocks(void) | |
179 | { | |
180 | int r; | |
181 | ||
182 | core.dss_ick = NULL; | |
183 | core.dss1_fck = NULL; | |
184 | core.dss2_fck = NULL; | |
185 | core.dss_54m_fck = NULL; | |
186 | core.dss_96m_fck = NULL; | |
187 | ||
188 | r = dss_get_clock(&core.dss_ick, "ick"); | |
189 | if (r) | |
190 | goto err; | |
191 | ||
192 | r = dss_get_clock(&core.dss1_fck, "dss1_fck"); | |
193 | if (r) | |
194 | goto err; | |
195 | ||
196 | r = dss_get_clock(&core.dss2_fck, "dss2_fck"); | |
197 | if (r) | |
198 | goto err; | |
199 | ||
200 | r = dss_get_clock(&core.dss_54m_fck, "tv_fck"); | |
201 | if (r) | |
202 | goto err; | |
203 | ||
204 | r = dss_get_clock(&core.dss_96m_fck, "video_fck"); | |
205 | if (r) | |
206 | goto err; | |
207 | ||
208 | return 0; | |
209 | ||
210 | err: | |
211 | if (core.dss_ick) | |
212 | clk_put(core.dss_ick); | |
213 | if (core.dss1_fck) | |
214 | clk_put(core.dss1_fck); | |
215 | if (core.dss2_fck) | |
216 | clk_put(core.dss2_fck); | |
217 | if (core.dss_54m_fck) | |
218 | clk_put(core.dss_54m_fck); | |
219 | if (core.dss_96m_fck) | |
220 | clk_put(core.dss_96m_fck); | |
221 | ||
222 | return r; | |
223 | } | |
224 | ||
225 | static void dss_put_clocks(void) | |
226 | { | |
227 | if (core.dss_96m_fck) | |
228 | clk_put(core.dss_96m_fck); | |
229 | clk_put(core.dss_54m_fck); | |
230 | clk_put(core.dss1_fck); | |
231 | clk_put(core.dss2_fck); | |
232 | clk_put(core.dss_ick); | |
233 | } | |
234 | ||
235 | unsigned long dss_clk_get_rate(enum dss_clock clk) | |
236 | { | |
237 | switch (clk) { | |
238 | case DSS_CLK_ICK: | |
239 | return clk_get_rate(core.dss_ick); | |
240 | case DSS_CLK_FCK1: | |
241 | return clk_get_rate(core.dss1_fck); | |
242 | case DSS_CLK_FCK2: | |
243 | return clk_get_rate(core.dss2_fck); | |
244 | case DSS_CLK_54M: | |
245 | return clk_get_rate(core.dss_54m_fck); | |
246 | case DSS_CLK_96M: | |
247 | return clk_get_rate(core.dss_96m_fck); | |
248 | } | |
249 | ||
250 | BUG(); | |
251 | return 0; | |
252 | } | |
253 | ||
254 | static unsigned count_clk_bits(enum dss_clock clks) | |
255 | { | |
256 | unsigned num_clks = 0; | |
257 | ||
258 | if (clks & DSS_CLK_ICK) | |
259 | ++num_clks; | |
260 | if (clks & DSS_CLK_FCK1) | |
261 | ++num_clks; | |
262 | if (clks & DSS_CLK_FCK2) | |
263 | ++num_clks; | |
264 | if (clks & DSS_CLK_54M) | |
265 | ++num_clks; | |
266 | if (clks & DSS_CLK_96M) | |
267 | ++num_clks; | |
268 | ||
269 | return num_clks; | |
270 | } | |
271 | ||
272 | static void dss_clk_enable_no_ctx(enum dss_clock clks) | |
273 | { | |
274 | unsigned num_clks = count_clk_bits(clks); | |
275 | ||
276 | if (clks & DSS_CLK_ICK) | |
277 | clk_enable(core.dss_ick); | |
278 | if (clks & DSS_CLK_FCK1) | |
279 | clk_enable(core.dss1_fck); | |
280 | if (clks & DSS_CLK_FCK2) | |
281 | clk_enable(core.dss2_fck); | |
282 | if (clks & DSS_CLK_54M) | |
283 | clk_enable(core.dss_54m_fck); | |
284 | if (clks & DSS_CLK_96M) | |
285 | clk_enable(core.dss_96m_fck); | |
286 | ||
287 | core.num_clks_enabled += num_clks; | |
288 | } | |
289 | ||
290 | void dss_clk_enable(enum dss_clock clks) | |
291 | { | |
e2962649 TV |
292 | bool check_ctx = core.num_clks_enabled == 0; |
293 | ||
559d6701 TV |
294 | dss_clk_enable_no_ctx(clks); |
295 | ||
e2962649 | 296 | if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) |
559d6701 TV |
297 | restore_all_ctx(); |
298 | } | |
299 | ||
300 | static void dss_clk_disable_no_ctx(enum dss_clock clks) | |
301 | { | |
302 | unsigned num_clks = count_clk_bits(clks); | |
303 | ||
304 | if (clks & DSS_CLK_ICK) | |
305 | clk_disable(core.dss_ick); | |
306 | if (clks & DSS_CLK_FCK1) | |
307 | clk_disable(core.dss1_fck); | |
308 | if (clks & DSS_CLK_FCK2) | |
309 | clk_disable(core.dss2_fck); | |
310 | if (clks & DSS_CLK_54M) | |
311 | clk_disable(core.dss_54m_fck); | |
312 | if (clks & DSS_CLK_96M) | |
313 | clk_disable(core.dss_96m_fck); | |
314 | ||
315 | core.num_clks_enabled -= num_clks; | |
316 | } | |
317 | ||
318 | void dss_clk_disable(enum dss_clock clks) | |
319 | { | |
320 | if (cpu_is_omap34xx()) { | |
321 | unsigned num_clks = count_clk_bits(clks); | |
322 | ||
323 | BUG_ON(core.num_clks_enabled < num_clks); | |
324 | ||
325 | if (core.num_clks_enabled == num_clks) | |
326 | save_all_ctx(); | |
327 | } | |
328 | ||
329 | dss_clk_disable_no_ctx(clks); | |
330 | } | |
331 | ||
332 | static void dss_clk_enable_all_no_ctx(void) | |
333 | { | |
334 | enum dss_clock clks; | |
335 | ||
336 | clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; | |
337 | if (cpu_is_omap34xx()) | |
338 | clks |= DSS_CLK_96M; | |
339 | dss_clk_enable_no_ctx(clks); | |
340 | } | |
341 | ||
342 | static void dss_clk_disable_all_no_ctx(void) | |
343 | { | |
344 | enum dss_clock clks; | |
345 | ||
346 | clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; | |
347 | if (cpu_is_omap34xx()) | |
348 | clks |= DSS_CLK_96M; | |
349 | dss_clk_disable_no_ctx(clks); | |
350 | } | |
351 | ||
352 | static void dss_clk_disable_all(void) | |
353 | { | |
354 | enum dss_clock clks; | |
355 | ||
356 | clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; | |
357 | if (cpu_is_omap34xx()) | |
358 | clks |= DSS_CLK_96M; | |
359 | dss_clk_disable(clks); | |
360 | } | |
361 | ||
8a2cfea8 TV |
362 | /* REGULATORS */ |
363 | ||
364 | struct regulator *dss_get_vdds_dsi(void) | |
365 | { | |
366 | struct regulator *reg; | |
367 | ||
368 | if (core.vdds_dsi_reg != NULL) | |
369 | return core.vdds_dsi_reg; | |
370 | ||
371 | reg = regulator_get(&core.pdev->dev, "vdds_dsi"); | |
372 | if (!IS_ERR(reg)) | |
373 | core.vdds_dsi_reg = reg; | |
374 | ||
375 | return reg; | |
376 | } | |
377 | ||
378 | struct regulator *dss_get_vdds_sdi(void) | |
379 | { | |
380 | struct regulator *reg; | |
381 | ||
382 | if (core.vdds_sdi_reg != NULL) | |
383 | return core.vdds_sdi_reg; | |
384 | ||
385 | reg = regulator_get(&core.pdev->dev, "vdds_sdi"); | |
386 | if (!IS_ERR(reg)) | |
387 | core.vdds_sdi_reg = reg; | |
388 | ||
389 | return reg; | |
390 | } | |
391 | ||
392 | struct regulator *dss_get_vdda_dac(void) | |
393 | { | |
394 | struct regulator *reg; | |
395 | ||
396 | if (core.vdda_dac_reg != NULL) | |
397 | return core.vdda_dac_reg; | |
398 | ||
399 | reg = regulator_get(&core.pdev->dev, "vdda_dac"); | |
400 | if (!IS_ERR(reg)) | |
401 | core.vdda_dac_reg = reg; | |
402 | ||
403 | return reg; | |
404 | } | |
405 | ||
559d6701 TV |
406 | /* DEBUGFS */ |
407 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) | |
408 | static void dss_debug_dump_clocks(struct seq_file *s) | |
409 | { | |
410 | core_dump_clocks(s); | |
411 | dss_dump_clocks(s); | |
412 | dispc_dump_clocks(s); | |
413 | #ifdef CONFIG_OMAP2_DSS_DSI | |
414 | dsi_dump_clocks(s); | |
415 | #endif | |
416 | } | |
417 | ||
418 | static int dss_debug_show(struct seq_file *s, void *unused) | |
419 | { | |
420 | void (*func)(struct seq_file *) = s->private; | |
421 | func(s); | |
422 | return 0; | |
423 | } | |
424 | ||
425 | static int dss_debug_open(struct inode *inode, struct file *file) | |
426 | { | |
427 | return single_open(file, dss_debug_show, inode->i_private); | |
428 | } | |
429 | ||
430 | static const struct file_operations dss_debug_fops = { | |
431 | .open = dss_debug_open, | |
432 | .read = seq_read, | |
433 | .llseek = seq_lseek, | |
434 | .release = single_release, | |
435 | }; | |
436 | ||
437 | static struct dentry *dss_debugfs_dir; | |
438 | ||
439 | static int dss_initialize_debugfs(void) | |
440 | { | |
441 | dss_debugfs_dir = debugfs_create_dir("omapdss", NULL); | |
442 | if (IS_ERR(dss_debugfs_dir)) { | |
443 | int err = PTR_ERR(dss_debugfs_dir); | |
444 | dss_debugfs_dir = NULL; | |
445 | return err; | |
446 | } | |
447 | ||
448 | debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir, | |
449 | &dss_debug_dump_clocks, &dss_debug_fops); | |
450 | ||
853525d7 | 451 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
dfc0fd8d TV |
452 | debugfs_create_file("dispc_irq", S_IRUGO, dss_debugfs_dir, |
453 | &dispc_dump_irqs, &dss_debug_fops); | |
853525d7 | 454 | #endif |
dfc0fd8d | 455 | |
853525d7 | 456 | #if defined(CONFIG_OMAP2_DSS_DSI) && defined(CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS) |
dfc0fd8d TV |
457 | debugfs_create_file("dsi_irq", S_IRUGO, dss_debugfs_dir, |
458 | &dsi_dump_irqs, &dss_debug_fops); | |
459 | #endif | |
460 | ||
559d6701 TV |
461 | debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir, |
462 | &dss_dump_regs, &dss_debug_fops); | |
463 | debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir, | |
464 | &dispc_dump_regs, &dss_debug_fops); | |
465 | #ifdef CONFIG_OMAP2_DSS_RFBI | |
466 | debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir, | |
467 | &rfbi_dump_regs, &dss_debug_fops); | |
468 | #endif | |
469 | #ifdef CONFIG_OMAP2_DSS_DSI | |
470 | debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir, | |
471 | &dsi_dump_regs, &dss_debug_fops); | |
472 | #endif | |
473 | #ifdef CONFIG_OMAP2_DSS_VENC | |
474 | debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir, | |
475 | &venc_dump_regs, &dss_debug_fops); | |
476 | #endif | |
477 | return 0; | |
478 | } | |
479 | ||
480 | static void dss_uninitialize_debugfs(void) | |
481 | { | |
482 | if (dss_debugfs_dir) | |
483 | debugfs_remove_recursive(dss_debugfs_dir); | |
484 | } | |
368a148e JN |
485 | #else /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */ |
486 | static inline int dss_initialize_debugfs(void) | |
487 | { | |
488 | return 0; | |
489 | } | |
490 | static inline void dss_uninitialize_debugfs(void) | |
491 | { | |
492 | } | |
559d6701 TV |
493 | #endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */ |
494 | ||
495 | /* PLATFORM DEVICE */ | |
496 | static int omap_dss_probe(struct platform_device *pdev) | |
497 | { | |
498 | struct omap_dss_board_info *pdata = pdev->dev.platform_data; | |
499 | int skip_init = 0; | |
500 | int r; | |
501 | int i; | |
502 | ||
503 | core.pdev = pdev; | |
504 | ||
505 | dss_init_overlay_managers(pdev); | |
506 | dss_init_overlays(pdev); | |
507 | ||
508 | r = dss_get_clocks(); | |
509 | if (r) | |
510 | goto fail0; | |
511 | ||
512 | dss_clk_enable_all_no_ctx(); | |
513 | ||
514 | core.ctx_id = dss_get_ctx_id(); | |
515 | DSSDBG("initial ctx id %u\n", core.ctx_id); | |
516 | ||
517 | #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT | |
518 | /* DISPC_CONTROL */ | |
519 | if (omap_readl(0x48050440) & 1) /* LCD enabled? */ | |
520 | skip_init = 1; | |
521 | #endif | |
522 | ||
523 | r = dss_init(skip_init); | |
524 | if (r) { | |
525 | DSSERR("Failed to initialize DSS\n"); | |
526 | goto fail0; | |
527 | } | |
528 | ||
559d6701 TV |
529 | r = rfbi_init(); |
530 | if (r) { | |
531 | DSSERR("Failed to initialize rfbi\n"); | |
532 | goto fail0; | |
533 | } | |
559d6701 | 534 | |
8a2cfea8 | 535 | r = dpi_init(pdev); |
559d6701 TV |
536 | if (r) { |
537 | DSSERR("Failed to initialize dpi\n"); | |
538 | goto fail0; | |
539 | } | |
540 | ||
541 | r = dispc_init(); | |
542 | if (r) { | |
543 | DSSERR("Failed to initialize dispc\n"); | |
544 | goto fail0; | |
545 | } | |
368a148e | 546 | |
559d6701 TV |
547 | r = venc_init(pdev); |
548 | if (r) { | |
549 | DSSERR("Failed to initialize venc\n"); | |
550 | goto fail0; | |
551 | } | |
368a148e | 552 | |
559d6701 | 553 | if (cpu_is_omap34xx()) { |
559d6701 TV |
554 | r = sdi_init(skip_init); |
555 | if (r) { | |
556 | DSSERR("Failed to initialize SDI\n"); | |
557 | goto fail0; | |
558 | } | |
368a148e | 559 | |
559d6701 TV |
560 | r = dsi_init(pdev); |
561 | if (r) { | |
562 | DSSERR("Failed to initialize DSI\n"); | |
563 | goto fail0; | |
564 | } | |
559d6701 TV |
565 | } |
566 | ||
559d6701 TV |
567 | r = dss_initialize_debugfs(); |
568 | if (r) | |
569 | goto fail0; | |
559d6701 TV |
570 | |
571 | for (i = 0; i < pdata->num_devices; ++i) { | |
572 | struct omap_dss_device *dssdev = pdata->devices[i]; | |
573 | ||
574 | r = omap_dss_register_device(dssdev); | |
575 | if (r) | |
576 | DSSERR("device reg failed %d\n", i); | |
577 | ||
578 | if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0) | |
579 | pdata->default_device = dssdev; | |
580 | } | |
581 | ||
582 | dss_clk_disable_all(); | |
583 | ||
584 | return 0; | |
585 | ||
586 | /* XXX fail correctly */ | |
587 | fail0: | |
588 | return r; | |
589 | } | |
590 | ||
591 | static int omap_dss_remove(struct platform_device *pdev) | |
592 | { | |
593 | struct omap_dss_board_info *pdata = pdev->dev.platform_data; | |
594 | int i; | |
595 | int c; | |
596 | ||
559d6701 | 597 | dss_uninitialize_debugfs(); |
559d6701 | 598 | |
559d6701 | 599 | venc_exit(); |
559d6701 TV |
600 | dispc_exit(); |
601 | dpi_exit(); | |
559d6701 | 602 | rfbi_exit(); |
559d6701 | 603 | if (cpu_is_omap34xx()) { |
559d6701 | 604 | dsi_exit(); |
559d6701 | 605 | sdi_exit(); |
559d6701 TV |
606 | } |
607 | ||
608 | dss_exit(); | |
609 | ||
610 | /* these should be removed at some point */ | |
611 | c = core.dss_ick->usecount; | |
612 | if (c > 0) { | |
613 | DSSERR("warning: dss_ick usecount %d, disabling\n", c); | |
614 | while (c-- > 0) | |
615 | clk_disable(core.dss_ick); | |
616 | } | |
617 | ||
618 | c = core.dss1_fck->usecount; | |
619 | if (c > 0) { | |
620 | DSSERR("warning: dss1_fck usecount %d, disabling\n", c); | |
621 | while (c-- > 0) | |
622 | clk_disable(core.dss1_fck); | |
623 | } | |
624 | ||
625 | c = core.dss2_fck->usecount; | |
626 | if (c > 0) { | |
627 | DSSERR("warning: dss2_fck usecount %d, disabling\n", c); | |
628 | while (c-- > 0) | |
629 | clk_disable(core.dss2_fck); | |
630 | } | |
631 | ||
632 | c = core.dss_54m_fck->usecount; | |
633 | if (c > 0) { | |
634 | DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c); | |
635 | while (c-- > 0) | |
636 | clk_disable(core.dss_54m_fck); | |
637 | } | |
638 | ||
639 | if (core.dss_96m_fck) { | |
640 | c = core.dss_96m_fck->usecount; | |
641 | if (c > 0) { | |
642 | DSSERR("warning: dss_96m_fck usecount %d, disabling\n", | |
643 | c); | |
644 | while (c-- > 0) | |
645 | clk_disable(core.dss_96m_fck); | |
646 | } | |
647 | } | |
648 | ||
649 | dss_put_clocks(); | |
650 | ||
651 | dss_uninit_overlays(pdev); | |
652 | dss_uninit_overlay_managers(pdev); | |
653 | ||
654 | for (i = 0; i < pdata->num_devices; ++i) | |
655 | omap_dss_unregister_device(pdata->devices[i]); | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
660 | static void omap_dss_shutdown(struct platform_device *pdev) | |
661 | { | |
662 | DSSDBG("shutdown\n"); | |
663 | dss_disable_all_devices(); | |
664 | } | |
665 | ||
666 | static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state) | |
667 | { | |
668 | DSSDBG("suspend %d\n", state.event); | |
669 | ||
670 | return dss_suspend_all_devices(); | |
671 | } | |
672 | ||
673 | static int omap_dss_resume(struct platform_device *pdev) | |
674 | { | |
675 | DSSDBG("resume\n"); | |
676 | ||
677 | return dss_resume_all_devices(); | |
678 | } | |
679 | ||
680 | static struct platform_driver omap_dss_driver = { | |
681 | .probe = omap_dss_probe, | |
682 | .remove = omap_dss_remove, | |
683 | .shutdown = omap_dss_shutdown, | |
684 | .suspend = omap_dss_suspend, | |
685 | .resume = omap_dss_resume, | |
686 | .driver = { | |
687 | .name = "omapdss", | |
688 | .owner = THIS_MODULE, | |
689 | }, | |
690 | }; | |
691 | ||
692 | /* BUS */ | |
693 | static int dss_bus_match(struct device *dev, struct device_driver *driver) | |
694 | { | |
695 | struct omap_dss_device *dssdev = to_dss_device(dev); | |
696 | ||
697 | DSSDBG("bus_match. dev %s/%s, drv %s\n", | |
698 | dev_name(dev), dssdev->driver_name, driver->name); | |
699 | ||
700 | return strcmp(dssdev->driver_name, driver->name) == 0; | |
701 | } | |
702 | ||
703 | static ssize_t device_name_show(struct device *dev, | |
704 | struct device_attribute *attr, char *buf) | |
705 | { | |
706 | struct omap_dss_device *dssdev = to_dss_device(dev); | |
707 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
708 | dssdev->name ? | |
709 | dssdev->name : ""); | |
710 | } | |
711 | ||
712 | static struct device_attribute default_dev_attrs[] = { | |
713 | __ATTR(name, S_IRUGO, device_name_show, NULL), | |
714 | __ATTR_NULL, | |
715 | }; | |
716 | ||
717 | static ssize_t driver_name_show(struct device_driver *drv, char *buf) | |
718 | { | |
719 | struct omap_dss_driver *dssdrv = to_dss_driver(drv); | |
720 | return snprintf(buf, PAGE_SIZE, "%s\n", | |
721 | dssdrv->driver.name ? | |
722 | dssdrv->driver.name : ""); | |
723 | } | |
724 | static struct driver_attribute default_drv_attrs[] = { | |
725 | __ATTR(name, S_IRUGO, driver_name_show, NULL), | |
726 | __ATTR_NULL, | |
727 | }; | |
728 | ||
729 | static struct bus_type dss_bus_type = { | |
730 | .name = "omapdss", | |
731 | .match = dss_bus_match, | |
732 | .dev_attrs = default_dev_attrs, | |
733 | .drv_attrs = default_drv_attrs, | |
734 | }; | |
735 | ||
736 | static void dss_bus_release(struct device *dev) | |
737 | { | |
738 | DSSDBG("bus_release\n"); | |
739 | } | |
740 | ||
741 | static struct device dss_bus = { | |
742 | .release = dss_bus_release, | |
743 | }; | |
744 | ||
745 | struct bus_type *dss_get_bus(void) | |
746 | { | |
747 | return &dss_bus_type; | |
748 | } | |
749 | ||
750 | /* DRIVER */ | |
751 | static int dss_driver_probe(struct device *dev) | |
752 | { | |
753 | int r; | |
754 | struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver); | |
755 | struct omap_dss_device *dssdev = to_dss_device(dev); | |
756 | struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; | |
757 | bool force; | |
758 | ||
759 | DSSDBG("driver_probe: dev %s/%s, drv %s\n", | |
760 | dev_name(dev), dssdev->driver_name, | |
761 | dssdrv->driver.name); | |
762 | ||
763 | dss_init_device(core.pdev, dssdev); | |
764 | ||
e020f9af TV |
765 | force = pdata->default_device == dssdev; |
766 | dss_recheck_connections(dssdev, force); | |
559d6701 TV |
767 | |
768 | r = dssdrv->probe(dssdev); | |
769 | ||
770 | if (r) { | |
771 | DSSERR("driver probe failed: %d\n", r); | |
c121b152 | 772 | dss_uninit_device(core.pdev, dssdev); |
559d6701 TV |
773 | return r; |
774 | } | |
775 | ||
776 | DSSDBG("probe done for device %s\n", dev_name(dev)); | |
777 | ||
778 | dssdev->driver = dssdrv; | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
783 | static int dss_driver_remove(struct device *dev) | |
784 | { | |
785 | struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver); | |
786 | struct omap_dss_device *dssdev = to_dss_device(dev); | |
787 | ||
788 | DSSDBG("driver_remove: dev %s/%s\n", dev_name(dev), | |
789 | dssdev->driver_name); | |
790 | ||
791 | dssdrv->remove(dssdev); | |
792 | ||
793 | dss_uninit_device(core.pdev, dssdev); | |
794 | ||
795 | dssdev->driver = NULL; | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
800 | int omap_dss_register_driver(struct omap_dss_driver *dssdriver) | |
801 | { | |
802 | dssdriver->driver.bus = &dss_bus_type; | |
803 | dssdriver->driver.probe = dss_driver_probe; | |
804 | dssdriver->driver.remove = dss_driver_remove; | |
96adcece TV |
805 | |
806 | if (dssdriver->get_resolution == NULL) | |
807 | dssdriver->get_resolution = omapdss_default_get_resolution; | |
a2699504 TV |
808 | if (dssdriver->get_recommended_bpp == NULL) |
809 | dssdriver->get_recommended_bpp = | |
810 | omapdss_default_get_recommended_bpp; | |
96adcece | 811 | |
559d6701 TV |
812 | return driver_register(&dssdriver->driver); |
813 | } | |
814 | EXPORT_SYMBOL(omap_dss_register_driver); | |
815 | ||
816 | void omap_dss_unregister_driver(struct omap_dss_driver *dssdriver) | |
817 | { | |
818 | driver_unregister(&dssdriver->driver); | |
819 | } | |
820 | EXPORT_SYMBOL(omap_dss_unregister_driver); | |
821 | ||
822 | /* DEVICE */ | |
823 | static void reset_device(struct device *dev, int check) | |
824 | { | |
825 | u8 *dev_p = (u8 *)dev; | |
826 | u8 *dev_end = dev_p + sizeof(*dev); | |
827 | void *saved_pdata; | |
828 | ||
829 | saved_pdata = dev->platform_data; | |
830 | if (check) { | |
831 | /* | |
832 | * Check if there is any other setting than platform_data | |
833 | * in struct device; warn that these will be reset by our | |
834 | * init. | |
835 | */ | |
836 | dev->platform_data = NULL; | |
837 | while (dev_p < dev_end) { | |
838 | if (*dev_p) { | |
839 | WARN("%s: struct device fields will be " | |
840 | "discarded\n", | |
841 | __func__); | |
842 | break; | |
843 | } | |
844 | dev_p++; | |
845 | } | |
846 | } | |
847 | memset(dev, 0, sizeof(*dev)); | |
848 | dev->platform_data = saved_pdata; | |
849 | } | |
850 | ||
851 | ||
852 | static void omap_dss_dev_release(struct device *dev) | |
853 | { | |
854 | reset_device(dev, 0); | |
855 | } | |
856 | ||
857 | int omap_dss_register_device(struct omap_dss_device *dssdev) | |
858 | { | |
859 | static int dev_num; | |
559d6701 TV |
860 | |
861 | WARN_ON(!dssdev->driver_name); | |
862 | ||
863 | reset_device(&dssdev->dev, 1); | |
864 | dssdev->dev.bus = &dss_bus_type; | |
865 | dssdev->dev.parent = &dss_bus; | |
866 | dssdev->dev.release = omap_dss_dev_release; | |
867 | dev_set_name(&dssdev->dev, "display%d", dev_num++); | |
e020f9af | 868 | return device_register(&dssdev->dev); |
559d6701 TV |
869 | } |
870 | ||
871 | void omap_dss_unregister_device(struct omap_dss_device *dssdev) | |
872 | { | |
873 | device_unregister(&dssdev->dev); | |
559d6701 TV |
874 | } |
875 | ||
876 | /* BUS */ | |
877 | static int omap_dss_bus_register(void) | |
878 | { | |
879 | int r; | |
880 | ||
881 | r = bus_register(&dss_bus_type); | |
882 | if (r) { | |
883 | DSSERR("bus register failed\n"); | |
884 | return r; | |
885 | } | |
886 | ||
887 | dev_set_name(&dss_bus, "omapdss"); | |
888 | r = device_register(&dss_bus); | |
889 | if (r) { | |
890 | DSSERR("bus driver register failed\n"); | |
891 | bus_unregister(&dss_bus_type); | |
892 | return r; | |
893 | } | |
894 | ||
895 | return 0; | |
896 | } | |
897 | ||
898 | /* INIT */ | |
899 | ||
900 | #ifdef CONFIG_OMAP2_DSS_MODULE | |
901 | static void omap_dss_bus_unregister(void) | |
902 | { | |
903 | device_unregister(&dss_bus); | |
904 | ||
905 | bus_unregister(&dss_bus_type); | |
906 | } | |
907 | ||
908 | static int __init omap_dss_init(void) | |
909 | { | |
910 | int r; | |
911 | ||
912 | r = omap_dss_bus_register(); | |
913 | if (r) | |
914 | return r; | |
915 | ||
916 | r = platform_driver_register(&omap_dss_driver); | |
917 | if (r) { | |
918 | omap_dss_bus_unregister(); | |
919 | return r; | |
920 | } | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
925 | static void __exit omap_dss_exit(void) | |
926 | { | |
8a2cfea8 TV |
927 | if (core.vdds_dsi_reg != NULL) { |
928 | regulator_put(core.vdds_dsi_reg); | |
929 | core.vdds_dsi_reg = NULL; | |
930 | } | |
931 | ||
932 | if (core.vdds_sdi_reg != NULL) { | |
933 | regulator_put(core.vdds_sdi_reg); | |
934 | core.vdds_sdi_reg = NULL; | |
935 | } | |
936 | ||
937 | if (core.vdda_dac_reg != NULL) { | |
938 | regulator_put(core.vdda_dac_reg); | |
939 | core.vdda_dac_reg = NULL; | |
940 | } | |
941 | ||
559d6701 TV |
942 | platform_driver_unregister(&omap_dss_driver); |
943 | ||
944 | omap_dss_bus_unregister(); | |
945 | } | |
946 | ||
947 | module_init(omap_dss_init); | |
948 | module_exit(omap_dss_exit); | |
949 | #else | |
950 | static int __init omap_dss_init(void) | |
951 | { | |
952 | return omap_dss_bus_register(); | |
953 | } | |
954 | ||
955 | static int __init omap_dss_init2(void) | |
956 | { | |
957 | return platform_driver_register(&omap_dss_driver); | |
958 | } | |
959 | ||
960 | core_initcall(omap_dss_init); | |
961 | device_initcall(omap_dss_init2); | |
962 | #endif | |
963 | ||
964 | MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>"); | |
965 | MODULE_DESCRIPTION("OMAP2/3 Display Subsystem"); | |
966 | MODULE_LICENSE("GPL v2"); | |
967 |