[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / omap2 / displays / panel-tpo-td043mtea1.c

/*
 * LCD panel driver for TPO TD043MTEA1
 *
 * Author: Gražvydas Ignotas <notasas@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio.h>
#include <linux/err.h>
#include <linux/slab.h>

#include <video/omapdss.h>

#define TPO_R02_MODE(x)		((x) & 7)
#define TPO_R02_MODE_800x480	7
#define TPO_R02_NCLK_RISING	BIT(3)
#define TPO_R02_HSYNC_HIGH	BIT(4)
#define TPO_R02_VSYNC_HIGH	BIT(5)

#define TPO_R03_NSTANDBY	BIT(0)
#define TPO_R03_EN_CP_CLK	BIT(1)
#define TPO_R03_EN_VGL_PUMP	BIT(2)
#define TPO_R03_EN_PWM		BIT(3)
#define TPO_R03_DRIVING_CAP_100	BIT(4)
#define TPO_R03_EN_PRE_CHARGE	BIT(6)
#define TPO_R03_SOFTWARE_CTL	BIT(7)

#define TPO_R04_NFLIP_H		BIT(0)
#define TPO_R04_NFLIP_V		BIT(1)
#define TPO_R04_CP_CLK_FREQ_1H	BIT(2)
#define TPO_R04_VGL_FREQ_1H	BIT(4)

#define TPO_R03_VAL_NORMAL (TPO_R03_NSTANDBY | TPO_R03_EN_CP_CLK | \
			TPO_R03_EN_VGL_PUMP |  TPO_R03_EN_PWM | \
			TPO_R03_DRIVING_CAP_100 | TPO_R03_EN_PRE_CHARGE | \
			TPO_R03_SOFTWARE_CTL)

#define TPO_R03_VAL_STANDBY (TPO_R03_DRIVING_CAP_100 | \
			TPO_R03_EN_PRE_CHARGE | TPO_R03_SOFTWARE_CTL)

static const u16 tpo_td043_def_gamma[12] = {
	105, 315, 381, 431, 490, 537, 579, 686, 780, 837, 880, 1023
};

struct tpo_td043_device {
	struct spi_device *spi;
	struct regulator *vcc_reg;
	int nreset_gpio;
	u16 gamma[12];
	u32 mode;
	u32 hmirror:1;
	u32 vmirror:1;
	u32 powered_on:1;
	u32 spi_suspended:1;
	u32 power_on_resume:1;
};

static int tpo_td043_write(struct spi_device *spi, u8 addr, u8 data)
{
	struct spi_message	m;
	struct spi_transfer	xfer;
	u16			w;
	int			r;

	spi_message_init(&m);

	memset(&xfer, 0, sizeof(xfer));

	w = ((u16)addr << 10) | (1 << 8) | data;
	xfer.tx_buf = &w;
	xfer.bits_per_word = 16;
	xfer.len = 2;
	spi_message_add_tail(&xfer, &m);

	r = spi_sync(spi, &m);
	if (r < 0)
		dev_warn(&spi->dev, "failed to write to LCD reg (%d)\n", r);
	return r;
}

static void tpo_td043_write_gamma(struct spi_device *spi, u16 gamma[12])
{
	u8 i, val;

	/* gamma bits [9:8] */
	for (val = i = 0; i < 4; i++)
		val |= (gamma[i] & 0x300) >> ((i + 1) * 2);
	tpo_td043_write(spi, 0x11, val);

	for (val = i = 0; i < 4; i++)
		val |= (gamma[i+4] & 0x300) >> ((i + 1) * 2);
	tpo_td043_write(spi, 0x12, val);

	for (val = i = 0; i < 4; i++)
		val |= (gamma[i+8] & 0x300) >> ((i + 1) * 2);
	tpo_td043_write(spi, 0x13, val);

	/* gamma bits [7:0] */
	for (val = i = 0; i < 12; i++)
		tpo_td043_write(spi, 0x14 + i, gamma[i] & 0xff);
}

static int tpo_td043_write_mirror(struct spi_device *spi, bool h, bool v)
{
	u8 reg4 = TPO_R04_NFLIP_H | TPO_R04_NFLIP_V | \
		TPO_R04_CP_CLK_FREQ_1H | TPO_R04_VGL_FREQ_1H;
	if (h)
		reg4 &= ~TPO_R04_NFLIP_H;
	if (v)
		reg4 &= ~TPO_R04_NFLIP_V;

	return tpo_td043_write(spi, 4, reg4);
}

static int tpo_td043_set_hmirror(struct omap_dss_device *dssdev, bool enable)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);

	tpo_td043->hmirror = enable;
	return tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror,
			tpo_td043->vmirror);
}

static bool tpo_td043_get_hmirror(struct omap_dss_device *dssdev)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);

	return tpo_td043->hmirror;
}

static ssize_t tpo_td043_vmirror_show(struct device *dev,
	struct device_attribute *attr, char *buf)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);

	return snprintf(buf, PAGE_SIZE, "%d\n", tpo_td043->vmirror);
}

static ssize_t tpo_td043_vmirror_store(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
	int val;
	int ret;

	ret = kstrtoint(buf, 0, &val);
	if (ret < 0)
		return ret;

	val = !!val;

	ret = tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror, val);
	if (ret < 0)
		return ret;

	tpo_td043->vmirror = val;

	return count;
}

static ssize_t tpo_td043_mode_show(struct device *dev,
	struct device_attribute *attr, char *buf)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);

	return snprintf(buf, PAGE_SIZE, "%d\n", tpo_td043->mode);
}

static ssize_t tpo_td043_mode_store(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
	long val;
	int ret;

	ret = kstrtol(buf, 0, &val);
	if (ret != 0 || val & ~7)
		return -EINVAL;

	tpo_td043->mode = val;

	val |= TPO_R02_NCLK_RISING;
	tpo_td043_write(tpo_td043->spi, 2, val);

	return count;
}

static ssize_t tpo_td043_gamma_show(struct device *dev,
	struct device_attribute *attr, char *buf)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
	ssize_t len = 0;
	int ret;
	int i;

	for (i = 0; i < ARRAY_SIZE(tpo_td043->gamma); i++) {
		ret = snprintf(buf + len, PAGE_SIZE - len, "%u ",
				tpo_td043->gamma[i]);
		if (ret < 0)
			return ret;
		len += ret;
	}
	buf[len - 1] = '\n';

	return len;
}

static ssize_t tpo_td043_gamma_store(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
	unsigned int g[12];
	int ret;
	int i;

	ret = sscanf(buf, "%u %u %u %u %u %u %u %u %u %u %u %u",
			&g[0], &g[1], &g[2], &g[3], &g[4], &g[5],
			&g[6], &g[7], &g[8], &g[9], &g[10], &g[11]);

	if (ret != 12)
		return -EINVAL;

	for (i = 0; i < 12; i++)
		tpo_td043->gamma[i] = g[i];

	tpo_td043_write_gamma(tpo_td043->spi, tpo_td043->gamma);

	return count;
}

static DEVICE_ATTR(vmirror, S_IRUGO | S_IWUSR,
		tpo_td043_vmirror_show, tpo_td043_vmirror_store);
static DEVICE_ATTR(mode, S_IRUGO | S_IWUSR,
		tpo_td043_mode_show, tpo_td043_mode_store);
static DEVICE_ATTR(gamma, S_IRUGO | S_IWUSR,
		tpo_td043_gamma_show, tpo_td043_gamma_store);

static struct attribute *tpo_td043_attrs[] = {
	&dev_attr_vmirror.attr,
	&dev_attr_mode.attr,
	&dev_attr_gamma.attr,
	NULL,
};

static struct attribute_group tpo_td043_attr_group = {
	.attrs = tpo_td043_attrs,
};

static const struct omap_video_timings tpo_td043_timings = {
	.x_res		= 800,
	.y_res		= 480,

	.pixel_clock	= 36000,

	.hsw		= 1,
	.hfp		= 68,
	.hbp		= 214,

	.vsw		= 1,
	.vfp		= 39,
	.vbp		= 34,

	.vsync_level	= OMAPDSS_SIG_ACTIVE_LOW,
	.hsync_level	= OMAPDSS_SIG_ACTIVE_LOW,
	.data_pclk_edge	= OMAPDSS_DRIVE_SIG_FALLING_EDGE,
	.de_level	= OMAPDSS_SIG_ACTIVE_HIGH,
	.sync_pclk_edge	= OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
};

static int tpo_td043_power_on(struct tpo_td043_device *tpo_td043)
{
	int nreset_gpio = tpo_td043->nreset_gpio;
	int r;

	if (tpo_td043->powered_on)
		return 0;

	r = regulator_enable(tpo_td043->vcc_reg);
	if (r != 0)
		return r;

	/* wait for panel to stabilize */
	msleep(160);

	if (gpio_is_valid(nreset_gpio))
		gpio_set_value(nreset_gpio, 1);

	tpo_td043_write(tpo_td043->spi, 2,
			TPO_R02_MODE(tpo_td043->mode) | TPO_R02_NCLK_RISING);
	tpo_td043_write(tpo_td043->spi, 3, TPO_R03_VAL_NORMAL);
	tpo_td043_write(tpo_td043->spi, 0x20, 0xf0);
	tpo_td043_write(tpo_td043->spi, 0x21, 0xf0);
	tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror,
			tpo_td043->vmirror);
	tpo_td043_write_gamma(tpo_td043->spi, tpo_td043->gamma);

	tpo_td043->powered_on = 1;
	return 0;
}

static void tpo_td043_power_off(struct tpo_td043_device *tpo_td043)
{
	int nreset_gpio = tpo_td043->nreset_gpio;

	if (!tpo_td043->powered_on)
		return;

	tpo_td043_write(tpo_td043->spi, 3,
			TPO_R03_VAL_STANDBY | TPO_R03_EN_PWM);

	if (gpio_is_valid(nreset_gpio))
		gpio_set_value(nreset_gpio, 0);

	/* wait for at least 2 vsyncs before cutting off power */
	msleep(50);

	tpo_td043_write(tpo_td043->spi, 3, TPO_R03_VAL_STANDBY);

	regulator_disable(tpo_td043->vcc_reg);

	tpo_td043->powered_on = 0;
}

static int tpo_td043_enable_dss(struct omap_dss_device *dssdev)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
	int r;

	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
		return 0;

	omapdss_dpi_set_timings(dssdev, &dssdev->panel.timings);
	omapdss_dpi_set_data_lines(dssdev, dssdev->phy.dpi.data_lines);

	r = omapdss_dpi_display_enable(dssdev);
	if (r)
		goto err0;

	if (dssdev->platform_enable) {
		r = dssdev->platform_enable(dssdev);
		if (r)
			goto err1;
	}

	/*
	 * If we are resuming from system suspend, SPI clocks might not be
	 * enabled yet, so we'll program the LCD from SPI PM resume callback.
	 */
	if (!tpo_td043->spi_suspended) {
		r = tpo_td043_power_on(tpo_td043);
		if (r)
			goto err1;
	}

	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;

	return 0;
err1:
	omapdss_dpi_display_disable(dssdev);
err0:
	return r;
}

static void tpo_td043_disable_dss(struct omap_dss_device *dssdev)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);

	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
		return;

	if (dssdev->platform_disable)
		dssdev->platform_disable(dssdev);

	omapdss_dpi_display_disable(dssdev);

	if (!tpo_td043->spi_suspended)
		tpo_td043_power_off(tpo_td043);
}

static int tpo_td043_enable(struct omap_dss_device *dssdev)
{
	dev_dbg(&dssdev->dev, "enable\n");

	return tpo_td043_enable_dss(dssdev);
}

static void tpo_td043_disable(struct omap_dss_device *dssdev)
{
	dev_dbg(&dssdev->dev, "disable\n");

	tpo_td043_disable_dss(dssdev);

	dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}

static int tpo_td043_probe(struct omap_dss_device *dssdev)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
	int nreset_gpio = dssdev->reset_gpio;
	int ret = 0;

	dev_dbg(&dssdev->dev, "probe\n");

	if (tpo_td043 == NULL) {
		dev_err(&dssdev->dev, "missing tpo_td043_device\n");
		return -ENODEV;
	}

	dssdev->panel.timings = tpo_td043_timings;
	dssdev->ctrl.pixel_size = 24;

	tpo_td043->mode = TPO_R02_MODE_800x480;
	memcpy(tpo_td043->gamma, tpo_td043_def_gamma, sizeof(tpo_td043->gamma));

	tpo_td043->vcc_reg = regulator_get(&dssdev->dev, "vcc");
	if (IS_ERR(tpo_td043->vcc_reg)) {
		dev_err(&dssdev->dev, "failed to get LCD VCC regulator\n");
		ret = PTR_ERR(tpo_td043->vcc_reg);
		goto fail_regulator;
	}

	if (gpio_is_valid(nreset_gpio)) {
		ret = gpio_request_one(nreset_gpio, GPIOF_OUT_INIT_LOW,
					"lcd reset");
		if (ret < 0) {
			dev_err(&dssdev->dev, "couldn't request reset GPIO\n");
			goto fail_gpio_req;
		}
	}

	ret = sysfs_create_group(&dssdev->dev.kobj, &tpo_td043_attr_group);
	if (ret)
		dev_warn(&dssdev->dev, "failed to create sysfs files\n");

	return 0;

fail_gpio_req:
	regulator_put(tpo_td043->vcc_reg);
fail_regulator:
	kfree(tpo_td043);
	return ret;
}

static void tpo_td043_remove(struct omap_dss_device *dssdev)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
	int nreset_gpio = dssdev->reset_gpio;

	dev_dbg(&dssdev->dev, "remove\n");

	sysfs_remove_group(&dssdev->dev.kobj, &tpo_td043_attr_group);
	regulator_put(tpo_td043->vcc_reg);
	if (gpio_is_valid(nreset_gpio))
		gpio_free(nreset_gpio);
}

static void tpo_td043_set_timings(struct omap_dss_device *dssdev,
		struct omap_video_timings *timings)
{
	omapdss_dpi_set_timings(dssdev, timings);

	dssdev->panel.timings = *timings;
}

static int tpo_td043_check_timings(struct omap_dss_device *dssdev,
		struct omap_video_timings *timings)
{
	return dpi_check_timings(dssdev, timings);
}

static struct omap_dss_driver tpo_td043_driver = {
	.probe		= tpo_td043_probe,
	.remove		= tpo_td043_remove,

	.enable		= tpo_td043_enable,
	.disable	= tpo_td043_disable,
	.set_mirror	= tpo_td043_set_hmirror,
	.get_mirror	= tpo_td043_get_hmirror,

	.set_timings	= tpo_td043_set_timings,
	.check_timings	= tpo_td043_check_timings,

	.driver         = {
		.name	= "tpo_td043mtea1_panel",
		.owner  = THIS_MODULE,
	},
};

static int tpo_td043_spi_probe(struct spi_device *spi)
{
	struct omap_dss_device *dssdev = spi->dev.platform_data;
	struct tpo_td043_device *tpo_td043;
	int ret;

	if (dssdev == NULL) {
		dev_err(&spi->dev, "missing dssdev\n");
		return -ENODEV;
	}

	spi->bits_per_word = 16;
	spi->mode = SPI_MODE_0;

	ret = spi_setup(spi);
	if (ret < 0) {
		dev_err(&spi->dev, "spi_setup failed: %d\n", ret);
		return ret;
	}

	tpo_td043 = kzalloc(sizeof(*tpo_td043), GFP_KERNEL);
	if (tpo_td043 == NULL)
		return -ENOMEM;

	tpo_td043->spi = spi;
	tpo_td043->nreset_gpio = dssdev->reset_gpio;
	dev_set_drvdata(&spi->dev, tpo_td043);
	dev_set_drvdata(&dssdev->dev, tpo_td043);

	omap_dss_register_driver(&tpo_td043_driver);

	return 0;
}

static int tpo_td043_spi_remove(struct spi_device *spi)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&spi->dev);

	omap_dss_unregister_driver(&tpo_td043_driver);
	kfree(tpo_td043);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int tpo_td043_spi_suspend(struct device *dev)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);

	dev_dbg(dev, "tpo_td043_spi_suspend, tpo %p\n", tpo_td043);

	tpo_td043->power_on_resume = tpo_td043->powered_on;
	tpo_td043_power_off(tpo_td043);
	tpo_td043->spi_suspended = 1;

	return 0;
}

static int tpo_td043_spi_resume(struct device *dev)
{
	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
	int ret;

	dev_dbg(dev, "tpo_td043_spi_resume\n");

	if (tpo_td043->power_on_resume) {
		ret = tpo_td043_power_on(tpo_td043);
		if (ret)
			return ret;
	}
	tpo_td043->spi_suspended = 0;

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(tpo_td043_spi_pm,
	tpo_td043_spi_suspend, tpo_td043_spi_resume);

static struct spi_driver tpo_td043_spi_driver = {
	.driver = {
		.name	= "tpo_td043mtea1_panel_spi",
		.owner	= THIS_MODULE,
		.pm	= &tpo_td043_spi_pm,
	},
	.probe	= tpo_td043_spi_probe,
	.remove	= tpo_td043_spi_remove,
};

module_spi_driver(tpo_td043_spi_driver);

MODULE_AUTHOR("Gražvydas Ignotas <notasas@gmail.com>");
MODULE_DESCRIPTION("TPO TD043MTEA1 LCD Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
9ce4ad0a GI	1	/*
	2	* LCD panel driver for TPO TD043MTEA1
	3	*
	4	* Author: Gražvydas Ignotas <notasas@gmail.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/delay.h>
	14	#include <linux/spi/spi.h>
	15	#include <linux/regulator/consumer.h>
	16	#include <linux/gpio.h>
	17	#include <linux/err.h>
5a0e3ad6	18	#include <linux/slab.h>
9ce4ad0a	19
a0b38cc4	20	#include <video/omapdss.h>
9ce4ad0a GI	21
	22	#define TPO_R02_MODE(x) ((x) & 7)
	23	#define TPO_R02_MODE_800x480 7
	24	#define TPO_R02_NCLK_RISING BIT(3)
	25	#define TPO_R02_HSYNC_HIGH BIT(4)
	26	#define TPO_R02_VSYNC_HIGH BIT(5)
	27
	28	#define TPO_R03_NSTANDBY BIT(0)
	29	#define TPO_R03_EN_CP_CLK BIT(1)
	30	#define TPO_R03_EN_VGL_PUMP BIT(2)
	31	#define TPO_R03_EN_PWM BIT(3)
	32	#define TPO_R03_DRIVING_CAP_100 BIT(4)
	33	#define TPO_R03_EN_PRE_CHARGE BIT(6)
	34	#define TPO_R03_SOFTWARE_CTL BIT(7)
	35
	36	#define TPO_R04_NFLIP_H BIT(0)
	37	#define TPO_R04_NFLIP_V BIT(1)
	38	#define TPO_R04_CP_CLK_FREQ_1H BIT(2)
	39	#define TPO_R04_VGL_FREQ_1H BIT(4)
	40
	41	#define TPO_R03_VAL_NORMAL (TPO_R03_NSTANDBY \| TPO_R03_EN_CP_CLK \| \
	42	TPO_R03_EN_VGL_PUMP \| TPO_R03_EN_PWM \| \
	43	TPO_R03_DRIVING_CAP_100 \| TPO_R03_EN_PRE_CHARGE \| \
	44	TPO_R03_SOFTWARE_CTL)
	45
	46	#define TPO_R03_VAL_STANDBY (TPO_R03_DRIVING_CAP_100 \| \
	47	TPO_R03_EN_PRE_CHARGE \| TPO_R03_SOFTWARE_CTL)
	48
	49	static const u16 tpo_td043_def_gamma[12] = {
4306b721	50	105, 315, 381, 431, 490, 537, 579, 686, 780, 837, 880, 1023
9ce4ad0a GI	51	};
	52
	53	struct tpo_td043_device {
	54	struct spi_device *spi;
	55	struct regulator *vcc_reg;
8df4f5ce	56	int nreset_gpio;
9ce4ad0a GI	57	u16 gamma[12];
	58	u32 mode;
	59	u32 hmirror:1;
	60	u32 vmirror:1;
8df4f5ce GI	61	u32 powered_on:1;
	62	u32 spi_suspended:1;
	63	u32 power_on_resume:1;
9ce4ad0a GI	64	};
	65
	66	static int tpo_td043_write(struct spi_device *spi, u8 addr, u8 data)
	67	{
	68	struct spi_message m;
	69	struct spi_transfer xfer;
	70	u16 w;
	71	int r;
	72
	73	spi_message_init(&m);
	74
	75	memset(&xfer, 0, sizeof(xfer));
	76
	77	w = ((u16)addr << 10) \| (1 << 8) \| data;
	78	xfer.tx_buf = &w;
	79	xfer.bits_per_word = 16;
	80	xfer.len = 2;
	81	spi_message_add_tail(&xfer, &m);
	82
	83	r = spi_sync(spi, &m);
	84	if (r < 0)
	85	dev_warn(&spi->dev, "failed to write to LCD reg (%d)\n", r);
	86	return r;
	87	}
	88
	89	static void tpo_td043_write_gamma(struct spi_device *spi, u16 gamma[12])
	90	{
	91	u8 i, val;
	92
	93	/* gamma bits [9:8] */
	94	for (val = i = 0; i < 4; i++)
	95	val \|= (gamma[i] & 0x300) >> ((i + 1) * 2);
	96	tpo_td043_write(spi, 0x11, val);
	97
	98	for (val = i = 0; i < 4; i++)
	99	val \|= (gamma[i+4] & 0x300) >> ((i + 1) * 2);
	100	tpo_td043_write(spi, 0x12, val);
	101
	102	for (val = i = 0; i < 4; i++)
	103	val \|= (gamma[i+8] & 0x300) >> ((i + 1) * 2);
	104	tpo_td043_write(spi, 0x13, val);
	105
	106	/* gamma bits [7:0] */
	107	for (val = i = 0; i < 12; i++)
	108	tpo_td043_write(spi, 0x14 + i, gamma[i] & 0xff);
	109	}
	110
	111	static int tpo_td043_write_mirror(struct spi_device *spi, bool h, bool v)
	112	{
	113	u8 reg4 = TPO_R04_NFLIP_H \| TPO_R04_NFLIP_V \| \
	114	TPO_R04_CP_CLK_FREQ_1H \| TPO_R04_VGL_FREQ_1H;
	115	if (h)
	116	reg4 &= ~TPO_R04_NFLIP_H;
	117	if (v)
	118	reg4 &= ~TPO_R04_NFLIP_V;
	119
	120	return tpo_td043_write(spi, 4, reg4);
	121	}
	122
	123	static int tpo_td043_set_hmirror(struct omap_dss_device *dssdev, bool enable)
	124	{
	125	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
	126
	127	tpo_td043->hmirror = enable;
128	return tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror,
129	tpo_td043->vmirror);
130	}
131
132	static bool tpo_td043_get_hmirror(struct omap_dss_device *dssdev)
133	{
134	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
135
136	return tpo_td043->hmirror;
137	}
138
139	static ssize_t tpo_td043_vmirror_show(struct device *dev,
140	struct device_attribute attr, char buf)
141	{
142	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
143
144	return snprintf(buf, PAGE_SIZE, "%d\n", tpo_td043->vmirror);
145	}
146
147	static ssize_t tpo_td043_vmirror_store(struct device *dev,
148	struct device_attribute attr, const char buf, size_t count)
149	{
150	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
e3502ce9	151	int val;
9ce4ad0a GI	152	int ret;
9ce4ad0a GI	153
e3502ce9	154	ret = kstrtoint(buf, 0, &val);
9ce4ad0a GI	155	if (ret < 0)
	156	return ret;
	157
e3502ce9 TV	158	val = !!val;
e3502ce9 TV	159
9ce4ad0a GI	160	ret = tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror, val);
	161	if (ret < 0)
	162	return ret;
	163
	164	tpo_td043->vmirror = val;
	165
	166	return count;
	167	}
	168
	169	static ssize_t tpo_td043_mode_show(struct device *dev,
	170	struct device_attribute attr, char buf)
	171	{
	172	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
	173
	174	return snprintf(buf, PAGE_SIZE, "%d\n", tpo_td043->mode);
	175	}
	176
	177	static ssize_t tpo_td043_mode_store(struct device *dev,
	178	struct device_attribute attr, const char buf, size_t count)
	179	{
	180	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
	181	long val;
	182	int ret;
	183
e3502ce9	184	ret = kstrtol(buf, 0, &val);
9ce4ad0a GI	185	if (ret != 0 \|\| val & ~7)
	186	return -EINVAL;
	187
	188	tpo_td043->mode = val;
	189
	190	val \|= TPO_R02_NCLK_RISING;
	191	tpo_td043_write(tpo_td043->spi, 2, val);
	192
	193	return count;
	194	}
	195
	196	static ssize_t tpo_td043_gamma_show(struct device *dev,
	197	struct device_attribute attr, char buf)
	198	{
	199	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
	200	ssize_t len = 0;
	201	int ret;
	202	int i;
	203
	204	for (i = 0; i < ARRAY_SIZE(tpo_td043->gamma); i++) {
	205	ret = snprintf(buf + len, PAGE_SIZE - len, "%u ",
	206	tpo_td043->gamma[i]);
	207	if (ret < 0)
	208	return ret;
	209	len += ret;
	210	}
	211	buf[len - 1] = '\n';
	212
	213	return len;
	214	}
	215
	216	static ssize_t tpo_td043_gamma_store(struct device *dev,
	217	struct device_attribute attr, const char buf, size_t count)
	218	{
	219	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
	220	unsigned int g[12];
	221	int ret;
	222	int i;
	223
	224	ret = sscanf(buf, "%u %u %u %u %u %u %u %u %u %u %u %u",
	225	&g[0], &g[1], &g[2], &g[3], &g[4], &g[5],
	226	&g[6], &g[7], &g[8], &g[9], &g[10], &g[11]);
	227
	228	if (ret != 12)
	229	return -EINVAL;
	230
	231	for (i = 0; i < 12; i++)
	232	tpo_td043->gamma[i] = g[i];
	233
	234	tpo_td043_write_gamma(tpo_td043->spi, tpo_td043->gamma);
	235
	236	return count;
	237	}
	238
	239	static DEVICE_ATTR(vmirror, S_IRUGO \| S_IWUSR,
	240	tpo_td043_vmirror_show, tpo_td043_vmirror_store);
	241	static DEVICE_ATTR(mode, S_IRUGO \| S_IWUSR,
	242	tpo_td043_mode_show, tpo_td043_mode_store);
	243	static DEVICE_ATTR(gamma, S_IRUGO \| S_IWUSR,
	244	tpo_td043_gamma_show, tpo_td043_gamma_store);
	245
	246	static struct attribute *tpo_td043_attrs[] = {
	247	&dev_attr_vmirror.attr,
	248	&dev_attr_mode.attr,
249	&dev_attr_gamma.attr,
250	NULL,
251	};
252
253	static struct attribute_group tpo_td043_attr_group = {
254	.attrs = tpo_td043_attrs,
255	};
256
257	static const struct omap_video_timings tpo_td043_timings = {
258	.x_res = 800,
259	.y_res = 480,
260
261	.pixel_clock = 36000,
262
263	.hsw = 1,
264	.hfp = 68,
265	.hbp = 214,
266
267	.vsw = 1,
268	.vfp = 39,
269	.vbp = 34,
a8d5e41c AT	270
	271	.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
	272	.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
	273	.data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
	274	.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
	275	.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
9ce4ad0a GI	276	};
9ce4ad0a GI	277
8df4f5ce	278	static int tpo_td043_power_on(struct tpo_td043_device *tpo_td043)
9ce4ad0a	279	{
8df4f5ce	280	int nreset_gpio = tpo_td043->nreset_gpio;
956107ea	281	int r;
9ce4ad0a	282
8df4f5ce	283	if (tpo_td043->powered_on)
18016e35 SM	284	return 0;
18016e35 SM	285
956107ea MB	286	r = regulator_enable(tpo_td043->vcc_reg);
	287	if (r != 0)
	288	return r;
9ce4ad0a	289
2c83af49	290	/* wait for panel to stabilize */
9ce4ad0a GI	291	msleep(160);
	292
	293	if (gpio_is_valid(nreset_gpio))
	294	gpio_set_value(nreset_gpio, 1);
	295
	296	tpo_td043_write(tpo_td043->spi, 2,
	297	TPO_R02_MODE(tpo_td043->mode) \| TPO_R02_NCLK_RISING);
	298	tpo_td043_write(tpo_td043->spi, 3, TPO_R03_VAL_NORMAL);
	299	tpo_td043_write(tpo_td043->spi, 0x20, 0xf0);
	300	tpo_td043_write(tpo_td043->spi, 0x21, 0xf0);
	301	tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror,
	302	tpo_td043->vmirror);
	303	tpo_td043_write_gamma(tpo_td043->spi, tpo_td043->gamma);
	304
8df4f5ce	305	tpo_td043->powered_on = 1;
9ce4ad0a GI	306	return 0;
	307	}
	308
8df4f5ce	309	static void tpo_td043_power_off(struct tpo_td043_device *tpo_td043)
9ce4ad0a	310	{
8df4f5ce	311	int nreset_gpio = tpo_td043->nreset_gpio;
9ce4ad0a	312
8df4f5ce	313	if (!tpo_td043->powered_on)
18016e35 SM	314	return;
18016e35 SM	315
9ce4ad0a GI	316	tpo_td043_write(tpo_td043->spi, 3,
	317	TPO_R03_VAL_STANDBY \| TPO_R03_EN_PWM);
	318
	319	if (gpio_is_valid(nreset_gpio))
	320	gpio_set_value(nreset_gpio, 0);
	321
	322	/* wait for at least 2 vsyncs before cutting off power */
	323	msleep(50);
	324
	325	tpo_td043_write(tpo_td043->spi, 3, TPO_R03_VAL_STANDBY);
	326
	327	regulator_disable(tpo_td043->vcc_reg);
	328
8df4f5ce GI	329	tpo_td043->powered_on = 0;
	330	}
	331
	332	static int tpo_td043_enable_dss(struct omap_dss_device *dssdev)
	333	{
	334	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
	335	int r;
	336
	337	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
	338	return 0;
	339
c499144c	340	omapdss_dpi_set_timings(dssdev, &dssdev->panel.timings);
c6b393d4	341	omapdss_dpi_set_data_lines(dssdev, dssdev->phy.dpi.data_lines);
c499144c	342
8df4f5ce GI	343	r = omapdss_dpi_display_enable(dssdev);
	344	if (r)
	345	goto err0;
	346
	347	if (dssdev->platform_enable) {
	348	r = dssdev->platform_enable(dssdev);
	349	if (r)
	350	goto err1;
	351	}
	352
	353	/*
	354	* If we are resuming from system suspend, SPI clocks might not be
	355	* enabled yet, so we'll program the LCD from SPI PM resume callback.
	356	*/
	357	if (!tpo_td043->spi_suspended) {
	358	r = tpo_td043_power_on(tpo_td043);
	359	if (r)
	360	goto err1;
	361	}
	362
	363	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
	364
	365	return 0;
	366	err1:
	367	omapdss_dpi_display_disable(dssdev);
	368	err0:
	369	return r;
	370	}
	371
	372	static void tpo_td043_disable_dss(struct omap_dss_device *dssdev)
	373	{
	374	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
	375
	376	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
	377	return;
	378
9ce4ad0a GI	379	if (dssdev->platform_disable)
9ce4ad0a GI	380	dssdev->platform_disable(dssdev);
37ac60e4 TV	381
37ac60e4 TV	382	omapdss_dpi_display_disable(dssdev);
8df4f5ce GI	383
	384	if (!tpo_td043->spi_suspended)
	385	tpo_td043_power_off(tpo_td043);
37ac60e4 TV	386	}
	387
	388	static int tpo_td043_enable(struct omap_dss_device *dssdev)
	389	{
37ac60e4 TV	390	dev_dbg(&dssdev->dev, "enable\n");
37ac60e4 TV	391
8df4f5ce	392	return tpo_td043_enable_dss(dssdev);
37ac60e4 TV	393	}
	394
	395	static void tpo_td043_disable(struct omap_dss_device *dssdev)
	396	{
	397	dev_dbg(&dssdev->dev, "disable\n");
	398
8df4f5ce	399	tpo_td043_disable_dss(dssdev);
37ac60e4 TV	400
37ac60e4 TV	401	dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
9ce4ad0a GI	402	}
9ce4ad0a GI	403
9ce4ad0a GI	404	static int tpo_td043_probe(struct omap_dss_device *dssdev)
	405	{
	406	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
	407	int nreset_gpio = dssdev->reset_gpio;
	408	int ret = 0;
	409
	410	dev_dbg(&dssdev->dev, "probe\n");
	411
	412	if (tpo_td043 == NULL) {
	413	dev_err(&dssdev->dev, "missing tpo_td043_device\n");
	414	return -ENODEV;
	415	}
	416
9ce4ad0a GI	417	dssdev->panel.timings = tpo_td043_timings;
	418	dssdev->ctrl.pixel_size = 24;
	419
	420	tpo_td043->mode = TPO_R02_MODE_800x480;
	421	memcpy(tpo_td043->gamma, tpo_td043_def_gamma, sizeof(tpo_td043->gamma));
	422
	423	tpo_td043->vcc_reg = regulator_get(&dssdev->dev, "vcc");
	424	if (IS_ERR(tpo_td043->vcc_reg)) {
	425	dev_err(&dssdev->dev, "failed to get LCD VCC regulator\n");
	426	ret = PTR_ERR(tpo_td043->vcc_reg);
	427	goto fail_regulator;
	428	}
	429
	430	if (gpio_is_valid(nreset_gpio)) {
f8bd4934 JH	431	ret = gpio_request_one(nreset_gpio, GPIOF_OUT_INIT_LOW,
f8bd4934 JH	432	"lcd reset");
9ce4ad0a GI	433	if (ret < 0) {
	434	dev_err(&dssdev->dev, "couldn't request reset GPIO\n");
	435	goto fail_gpio_req;
	436	}
9ce4ad0a GI	437	}
	438
	439	ret = sysfs_create_group(&dssdev->dev.kobj, &tpo_td043_attr_group);
	440	if (ret)
	441	dev_warn(&dssdev->dev, "failed to create sysfs files\n");
	442
	443	return 0;
	444
9ce4ad0a GI	445	fail_gpio_req:
	446	regulator_put(tpo_td043->vcc_reg);
	447	fail_regulator:
	448	kfree(tpo_td043);
	449	return ret;
	450	}
	451
	452	static void tpo_td043_remove(struct omap_dss_device *dssdev)
	453	{
	454	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&dssdev->dev);
	455	int nreset_gpio = dssdev->reset_gpio;
	456
	457	dev_dbg(&dssdev->dev, "remove\n");
	458
	459	sysfs_remove_group(&dssdev->dev.kobj, &tpo_td043_attr_group);
	460	regulator_put(tpo_td043->vcc_reg);
	461	if (gpio_is_valid(nreset_gpio))
	462	gpio_free(nreset_gpio);
	463	}
	464
31e8dfe1 GI	465	static void tpo_td043_set_timings(struct omap_dss_device *dssdev,
	466	struct omap_video_timings *timings)
	467	{
c499144c	468	omapdss_dpi_set_timings(dssdev, timings);
bdcae3cc AT	469
bdcae3cc AT	470	dssdev->panel.timings = *timings;
31e8dfe1 GI	471	}
	472
	473	static int tpo_td043_check_timings(struct omap_dss_device *dssdev,
	474	struct omap_video_timings *timings)
	475	{
	476	return dpi_check_timings(dssdev, timings);
	477	}
	478
9ce4ad0a GI	479	static struct omap_dss_driver tpo_td043_driver = {
	480	.probe = tpo_td043_probe,
	481	.remove = tpo_td043_remove,
	482
	483	.enable = tpo_td043_enable,
	484	.disable = tpo_td043_disable,
9ce4ad0a GI	485	.set_mirror = tpo_td043_set_hmirror,
	486	.get_mirror = tpo_td043_get_hmirror,
	487
31e8dfe1 GI	488	.set_timings = tpo_td043_set_timings,
	489	.check_timings = tpo_td043_check_timings,
	490
9ce4ad0a GI	491	.driver = {
	492	.name = "tpo_td043mtea1_panel",
	493	.owner = THIS_MODULE,
	494	},
	495	};
	496
	497	static int tpo_td043_spi_probe(struct spi_device *spi)
	498	{
	499	struct omap_dss_device *dssdev = spi->dev.platform_data;
	500	struct tpo_td043_device *tpo_td043;
	501	int ret;
	502
	503	if (dssdev == NULL) {
	504	dev_err(&spi->dev, "missing dssdev\n");
	505	return -ENODEV;
	506	}
	507
	508	spi->bits_per_word = 16;
	509	spi->mode = SPI_MODE_0;
	510
	511	ret = spi_setup(spi);
	512	if (ret < 0) {
	513	dev_err(&spi->dev, "spi_setup failed: %d\n", ret);
	514	return ret;
	515	}
	516
	517	tpo_td043 = kzalloc(sizeof(*tpo_td043), GFP_KERNEL);
	518	if (tpo_td043 == NULL)
	519	return -ENOMEM;
	520
	521	tpo_td043->spi = spi;
8df4f5ce	522	tpo_td043->nreset_gpio = dssdev->reset_gpio;
9ce4ad0a GI	523	dev_set_drvdata(&spi->dev, tpo_td043);
	524	dev_set_drvdata(&dssdev->dev, tpo_td043);
	525
	526	omap_dss_register_driver(&tpo_td043_driver);
	527
	528	return 0;
	529	}
	530
48c68c4f	531	static int tpo_td043_spi_remove(struct spi_device *spi)
9ce4ad0a GI	532	{
	533	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(&spi->dev);
	534
	535	omap_dss_unregister_driver(&tpo_td043_driver);
	536	kfree(tpo_td043);
	537
	538	return 0;
	539	}
	540
8df4f5ce GI	541	#ifdef CONFIG_PM_SLEEP
	542	static int tpo_td043_spi_suspend(struct device *dev)
	543	{
	544	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
	545
	546	dev_dbg(dev, "tpo_td043_spi_suspend, tpo %p\n", tpo_td043);
	547
	548	tpo_td043->power_on_resume = tpo_td043->powered_on;
	549	tpo_td043_power_off(tpo_td043);
	550	tpo_td043->spi_suspended = 1;
	551
	552	return 0;
	553	}
	554
	555	static int tpo_td043_spi_resume(struct device *dev)
	556	{
	557	struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
	558	int ret;
	559
	560	dev_dbg(dev, "tpo_td043_spi_resume\n");
	561
	562	if (tpo_td043->power_on_resume) {
	563	ret = tpo_td043_power_on(tpo_td043);
	564	if (ret)
	565	return ret;
	566	}
	567	tpo_td043->spi_suspended = 0;
	568
	569	return 0;
	570	}
	571	#endif
	572
	573	static SIMPLE_DEV_PM_OPS(tpo_td043_spi_pm,
	574	tpo_td043_spi_suspend, tpo_td043_spi_resume);
	575
9ce4ad0a GI	576	static struct spi_driver tpo_td043_spi_driver = {
	577	.driver = {
	578	.name = "tpo_td043mtea1_panel_spi",
9ce4ad0a	579	.owner = THIS_MODULE,
8df4f5ce	580	.pm = &tpo_td043_spi_pm,
9ce4ad0a GI	581	},
9ce4ad0a GI	582	.probe = tpo_td043_spi_probe,
48c68c4f	583	.remove = tpo_td043_spi_remove,
9ce4ad0a GI	584	};
9ce4ad0a GI	585
c6d242aa	586	module_spi_driver(tpo_td043_spi_driver);
9ce4ad0a GI	587
	588	MODULE_AUTHOR("Gražvydas Ignotas <notasas@gmail.com>");
	589	MODULE_DESCRIPTION("TPO TD043MTEA1 LCD Driver");
	590	MODULE_LICENSE("GPL");