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1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver | |
3 | * | |
4 | * Copyright 2004 Antonino Daplas <adaplas@pol.net> | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file COPYING in the main directory of this archive | |
8 | * for more details. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/config.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/string.h> | |
17 | #include <linux/mm.h> | |
18 | #include <linux/tty.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/fb.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/pci.h> | |
24 | #ifdef CONFIG_MTRR | |
25 | #include <asm/mtrr.h> | |
26 | #endif | |
27 | #ifdef CONFIG_PPC_OF | |
28 | #include <asm/prom.h> | |
29 | #include <asm/pci-bridge.h> | |
30 | #endif | |
31 | #ifdef CONFIG_PMAC_BACKLIGHT | |
32 | #include <asm/backlight.h> | |
33 | #endif | |
34 | ||
35 | #include "nv_local.h" | |
36 | #include "nv_type.h" | |
37 | #include "nv_proto.h" | |
38 | #include "nv_dma.h" | |
39 | ||
40 | #ifndef CONFIG_PCI /* sanity check */ | |
41 | #error This driver requires PCI support. | |
42 | #endif | |
43 | ||
44 | #undef CONFIG_FB_NVIDIA_DEBUG | |
45 | #ifdef CONFIG_FB_NVIDIA_DEBUG | |
46 | #define NVTRACE printk | |
47 | #else | |
48 | #define NVTRACE if (0) printk | |
49 | #endif | |
50 | ||
51 | #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__) | |
52 | #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__) | |
53 | ||
54 | #ifdef CONFIG_FB_NVIDIA_DEBUG | |
55 | #define assert(expr) \ | |
56 | if (!(expr)) { \ | |
57 | printk( "Assertion failed! %s,%s,%s,line=%d\n",\ | |
58 | #expr,__FILE__,__FUNCTION__,__LINE__); \ | |
59 | BUG(); \ | |
60 | } | |
61 | #else | |
62 | #define assert(expr) | |
63 | #endif | |
64 | ||
65 | #define PFX "nvidiafb: " | |
66 | ||
67 | /* HW cursor parameters */ | |
68 | #define MAX_CURS 32 | |
69 | ||
70 | static struct pci_device_id nvidiafb_pci_tbl[] = { | |
71 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, | |
72 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
73 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, | |
74 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
75 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, | |
76 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
77 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN, | |
78 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
79 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, | |
80 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
81 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2, | |
82 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
83 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, | |
84 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
85 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR, | |
86 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
87 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR, | |
88 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
89 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO, | |
90 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
91 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX, | |
92 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
93 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2, | |
94 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
95 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO, | |
96 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
97 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR, | |
98 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
99 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS, | |
100 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
101 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2, | |
102 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
103 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA, | |
104 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
105 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO, | |
106 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
107 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460, | |
108 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
109 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440, | |
110 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
111 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420, | |
112 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
113 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE, | |
114 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
115 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO, | |
116 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
117 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO, | |
118 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
119 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO, | |
120 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
121 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32, | |
122 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
123 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL, | |
124 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
125 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64, | |
126 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
127 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200, | |
128 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
129 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL, | |
130 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
131 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL, | |
132 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
133 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16, | |
134 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
135 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X, | |
136 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
137 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X, | |
138 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
139 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X, | |
140 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
141 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO, | |
142 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
143 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO, | |
144 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
145 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL, | |
146 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
147 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC, | |
148 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
149 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS, | |
150 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
151 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL, | |
152 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
153 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2, | |
154 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
155 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3, | |
156 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
157 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1, | |
158 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
159 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2, | |
160 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
161 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC, | |
162 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
163 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600, | |
164 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
165 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400, | |
166 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
167 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200, | |
168 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
169 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL, | |
170 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
171 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL, | |
172 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
173 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL, | |
174 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
175 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800, | |
176 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
177 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X, | |
178 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
179 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE, | |
180 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
181 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO, | |
182 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
183 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL, | |
184 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
185 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL, | |
186 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
187 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL, | |
188 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
189 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA, | |
190 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
191 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800, | |
192 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
193 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000, | |
194 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
195 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000, | |
196 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
197 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA, | |
198 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
199 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600, | |
200 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
201 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE, | |
202 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
203 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600, | |
204 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
205 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650, | |
206 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
207 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700, | |
208 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
209 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200, | |
210 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
211 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA, | |
212 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
213 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1, | |
214 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
215 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE, | |
216 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
217 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200, | |
218 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
219 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250, | |
220 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
221 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32, | |
222 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
223 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200, | |
224 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
225 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI, | |
226 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
227 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500, | |
228 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
229 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300, | |
230 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
231 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100, | |
232 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
233 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA, | |
234 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
235 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900, | |
236 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
237 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT, | |
238 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
239 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA, | |
240 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
241 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000, | |
242 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
243 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA, | |
244 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
245 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700, | |
246 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
247 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE, | |
248 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
249 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE, | |
250 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
251 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1, | |
252 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
253 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2, | |
254 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
255 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000, | |
256 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
257 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100, | |
258 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
259 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500, | |
260 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
261 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100, | |
262 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
263 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700, | |
264 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
265 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT, | |
266 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
267 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA, | |
268 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
269 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800, | |
270 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
271 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE, | |
272 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
273 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT, | |
274 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
275 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000, | |
276 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
277 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT, | |
278 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
279 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600, | |
280 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
281 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL, | |
282 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
283 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540, | |
284 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
285 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200, | |
286 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
287 | {PCI_VENDOR_ID_NVIDIA, 0x0252, | |
288 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
289 | {PCI_VENDOR_ID_NVIDIA, 0x0313, | |
290 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
291 | {PCI_VENDOR_ID_NVIDIA, 0x0316, | |
292 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
293 | {PCI_VENDOR_ID_NVIDIA, 0x0317, | |
294 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
295 | {PCI_VENDOR_ID_NVIDIA, 0x031D, | |
296 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
297 | {PCI_VENDOR_ID_NVIDIA, 0x031E, | |
298 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
299 | {PCI_VENDOR_ID_NVIDIA, 0x031F, | |
300 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
301 | {PCI_VENDOR_ID_NVIDIA, 0x0329, | |
302 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
303 | {PCI_VENDOR_ID_NVIDIA, 0x032F, | |
304 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
305 | {PCI_VENDOR_ID_NVIDIA, 0x0345, | |
306 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
307 | {PCI_VENDOR_ID_NVIDIA, 0x0349, | |
308 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
309 | {PCI_VENDOR_ID_NVIDIA, 0x034B, | |
310 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
311 | {PCI_VENDOR_ID_NVIDIA, 0x034F, | |
312 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
313 | {PCI_VENDOR_ID_NVIDIA, 0x00c0, | |
314 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
315 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A, | |
316 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
317 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A_LE, | |
318 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
319 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800, | |
320 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
321 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA, | |
322 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
323 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_GO1400, | |
324 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
325 | {PCI_VENDOR_ID_NVIDIA, 0x00cd, | |
326 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
327 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_1400, | |
328 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
329 | {PCI_VENDOR_ID_NVIDIA, 0x0142, | |
330 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
331 | {PCI_VENDOR_ID_NVIDIA, 0x0143, | |
332 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
333 | {PCI_VENDOR_ID_NVIDIA, 0x0144, | |
334 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
335 | {PCI_VENDOR_ID_NVIDIA, 0x0145, | |
336 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
337 | {PCI_VENDOR_ID_NVIDIA, 0x0146, | |
338 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
339 | {PCI_VENDOR_ID_NVIDIA, 0x0147, | |
340 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
341 | {PCI_VENDOR_ID_NVIDIA, 0x0148, | |
342 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
343 | {PCI_VENDOR_ID_NVIDIA, 0x0149, | |
344 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
345 | {PCI_VENDOR_ID_NVIDIA, 0x014b, | |
346 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
347 | {PCI_VENDOR_ID_NVIDIA, 0x14c, | |
348 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
349 | {PCI_VENDOR_ID_NVIDIA, 0x014d, | |
350 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
351 | {PCI_VENDOR_ID_NVIDIA, 0x0160, | |
352 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
353 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE, | |
354 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
355 | {PCI_VENDOR_ID_NVIDIA, 0x0162, | |
356 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
357 | {PCI_VENDOR_ID_NVIDIA, 0x0163, | |
358 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
359 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200, | |
360 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
361 | {PCI_VENDOR_ID_NVIDIA, 0x0165, | |
362 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
363 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250, | |
364 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
365 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1, | |
366 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
367 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1, | |
368 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
369 | {PCI_VENDOR_ID_NVIDIA, 0x0169, | |
370 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
371 | {PCI_VENDOR_ID_NVIDIA, 0x016b, | |
372 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
373 | {PCI_VENDOR_ID_NVIDIA, 0x016c, | |
374 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
375 | {PCI_VENDOR_ID_NVIDIA, 0x016d, | |
376 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
377 | {PCI_VENDOR_ID_NVIDIA, 0x016e, | |
378 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
379 | {PCI_VENDOR_ID_NVIDIA, 0x0210, | |
380 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
381 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B, | |
382 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
383 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE, | |
384 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
385 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT, | |
386 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
7015faa7 CC |
387 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT, |
388 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
389 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX, | |
390 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
391 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800, | |
392 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
393 | {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX, | |
394 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1da177e4 LT |
395 | {PCI_VENDOR_ID_NVIDIA, 0x021d, |
396 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
397 | {PCI_VENDOR_ID_NVIDIA, 0x021e, | |
398 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
399 | {PCI_VENDOR_ID_NVIDIA, 0x0220, | |
400 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
401 | {PCI_VENDOR_ID_NVIDIA, 0x0221, | |
402 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
403 | {PCI_VENDOR_ID_NVIDIA, 0x0222, | |
404 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
405 | {PCI_VENDOR_ID_NVIDIA, 0x0228, | |
406 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
407 | {0,} /* terminate list */ | |
408 | }; | |
409 | ||
410 | MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl); | |
411 | ||
412 | /* command line data, set in nvidiafb_setup() */ | |
413 | static int flatpanel __devinitdata = -1; /* Autodetect later */ | |
b8c49ef6 | 414 | static int fpdither __devinitdata = -1; |
1da177e4 LT |
415 | static int forceCRTC __devinitdata = -1; |
416 | static int hwcur __devinitdata = 0; | |
417 | static int noaccel __devinitdata = 0; | |
418 | static int noscale __devinitdata = 0; | |
419 | static int paneltweak __devinitdata = 0; | |
917bb077 | 420 | static int vram __devinitdata = 0; |
1da177e4 LT |
421 | #ifdef CONFIG_MTRR |
422 | static int nomtrr __devinitdata = 0; | |
423 | #endif | |
424 | ||
425 | static char *mode_option __devinitdata = NULL; | |
426 | ||
427 | static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = { | |
428 | .type = FB_TYPE_PACKED_PIXELS, | |
429 | .xpanstep = 8, | |
430 | .ypanstep = 1, | |
431 | }; | |
432 | ||
433 | static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = { | |
434 | .xres = 640, | |
435 | .yres = 480, | |
436 | .xres_virtual = 640, | |
437 | .yres_virtual = 480, | |
438 | .bits_per_pixel = 8, | |
439 | .red = {0, 8, 0}, | |
440 | .green = {0, 8, 0}, | |
441 | .blue = {0, 8, 0}, | |
442 | .transp = {0, 0, 0}, | |
443 | .activate = FB_ACTIVATE_NOW, | |
444 | .height = -1, | |
445 | .width = -1, | |
446 | .pixclock = 39721, | |
447 | .left_margin = 40, | |
448 | .right_margin = 24, | |
449 | .upper_margin = 32, | |
450 | .lower_margin = 11, | |
451 | .hsync_len = 96, | |
452 | .vsync_len = 2, | |
453 | .vmode = FB_VMODE_NONINTERLACED | |
454 | }; | |
455 | ||
456 | /* | |
457 | * Backlight control | |
458 | */ | |
459 | #ifdef CONFIG_PMAC_BACKLIGHT | |
460 | ||
461 | static int nvidia_backlight_levels[] = { | |
462 | 0x158, | |
463 | 0x192, | |
464 | 0x1c6, | |
465 | 0x200, | |
466 | 0x234, | |
467 | 0x268, | |
468 | 0x2a2, | |
469 | 0x2d6, | |
470 | 0x310, | |
471 | 0x344, | |
472 | 0x378, | |
473 | 0x3b2, | |
474 | 0x3e6, | |
475 | 0x41a, | |
476 | 0x454, | |
477 | 0x534, | |
478 | }; | |
479 | ||
480 | /* ------------------------------------------------------------------------- * | |
481 | * | |
482 | * Backlight operations | |
483 | * | |
484 | * ------------------------------------------------------------------------- */ | |
485 | ||
486 | static int nvidia_set_backlight_enable(int on, int level, void *data) | |
487 | { | |
c439e345 | 488 | struct nvidia_par *par = data; |
1da177e4 LT |
489 | u32 tmp_pcrt, tmp_pmc, fpcontrol; |
490 | ||
491 | tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF; | |
492 | tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC; | |
493 | fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC; | |
494 | ||
495 | if (on && (level > BACKLIGHT_OFF)) { | |
496 | tmp_pcrt |= 0x1; | |
497 | tmp_pmc |= (1 << 31); // backlight bit | |
498 | tmp_pmc |= nvidia_backlight_levels[level - 1] << 16; | |
499 | } | |
500 | ||
501 | if (on) | |
502 | fpcontrol |= par->fpSyncs; | |
503 | else | |
504 | fpcontrol |= 0x20000022; | |
505 | ||
506 | NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt); | |
507 | NV_WR32(par->PMC, 0x10F0, tmp_pmc); | |
508 | NV_WR32(par->PRAMDAC, 0x848, fpcontrol); | |
509 | ||
510 | return 0; | |
511 | } | |
512 | ||
513 | static int nvidia_set_backlight_level(int level, void *data) | |
514 | { | |
515 | return nvidia_set_backlight_enable(1, level, data); | |
516 | } | |
517 | ||
518 | static struct backlight_controller nvidia_backlight_controller = { | |
519 | nvidia_set_backlight_enable, | |
520 | nvidia_set_backlight_level | |
521 | }; | |
522 | ||
523 | #endif /* CONFIG_PMAC_BACKLIGHT */ | |
524 | ||
525 | static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8, | |
526 | u16 bg, u16 fg, u32 w, u32 h) | |
527 | { | |
f1ab5dac | 528 | u32 *data = (u32 *) data8; |
1da177e4 LT |
529 | int i, j, k = 0; |
530 | u32 b, tmp; | |
1da177e4 LT |
531 | |
532 | w = (w + 1) & ~1; | |
533 | ||
534 | for (i = 0; i < h; i++) { | |
535 | b = *data++; | |
536 | reverse_order(&b); | |
537 | ||
538 | for (j = 0; j < w / 2; j++) { | |
539 | tmp = 0; | |
540 | #if defined (__BIG_ENDIAN) | |
541 | tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; | |
542 | b <<= 1; | |
543 | tmp |= (b & (1 << 31)) ? fg : bg; | |
544 | b <<= 1; | |
545 | #else | |
546 | tmp = (b & 1) ? fg : bg; | |
547 | b >>= 1; | |
548 | tmp |= (b & 1) ? fg << 16 : bg << 16; | |
549 | b >>= 1; | |
550 | #endif | |
551 | NV_WR32(&par->CURSOR[k++], 0, tmp); | |
552 | } | |
553 | k += (MAX_CURS - w) / 2; | |
554 | } | |
555 | } | |
556 | ||
557 | static void nvidia_write_clut(struct nvidia_par *par, | |
558 | u8 regnum, u8 red, u8 green, u8 blue) | |
559 | { | |
560 | NVWriteDacMask(par, 0xff); | |
561 | NVWriteDacWriteAddr(par, regnum); | |
562 | NVWriteDacData(par, red); | |
563 | NVWriteDacData(par, green); | |
564 | NVWriteDacData(par, blue); | |
565 | } | |
566 | ||
567 | static void nvidia_read_clut(struct nvidia_par *par, | |
568 | u8 regnum, u8 * red, u8 * green, u8 * blue) | |
569 | { | |
570 | NVWriteDacMask(par, 0xff); | |
571 | NVWriteDacReadAddr(par, regnum); | |
572 | *red = NVReadDacData(par); | |
573 | *green = NVReadDacData(par); | |
574 | *blue = NVReadDacData(par); | |
575 | } | |
576 | ||
577 | static int nvidia_panel_tweak(struct nvidia_par *par, | |
578 | struct _riva_hw_state *state) | |
579 | { | |
580 | int tweak = 0; | |
581 | ||
582 | if (par->paneltweak) { | |
583 | tweak = par->paneltweak; | |
584 | } else { | |
585 | /* begin flat panel hacks */ | |
586 | /* This is unfortunate, but some chips need this register | |
587 | tweaked or else you get artifacts where adjacent pixels are | |
588 | swapped. There are no hard rules for what to set here so all | |
589 | we can do is experiment and apply hacks. */ | |
590 | ||
591 | if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) { | |
592 | /* At least one NV34 laptop needs this workaround. */ | |
593 | tweak = -1; | |
594 | } | |
595 | ||
596 | if((par->Chipset & 0xfff0) == 0x0310) { | |
597 | tweak = 1; | |
598 | } | |
599 | /* end flat panel hacks */ | |
600 | } | |
601 | ||
602 | return tweak; | |
603 | } | |
604 | ||
605 | static void nvidia_save_vga(struct nvidia_par *par, | |
606 | struct _riva_hw_state *state) | |
607 | { | |
608 | int i; | |
609 | ||
610 | NVTRACE_ENTER(); | |
611 | NVLockUnlock(par, 0); | |
612 | ||
613 | NVUnloadStateExt(par, state); | |
614 | ||
615 | state->misc_output = NVReadMiscOut(par); | |
616 | ||
617 | for (i = 0; i < NUM_CRT_REGS; i++) | |
618 | state->crtc[i] = NVReadCrtc(par, i); | |
619 | ||
620 | for (i = 0; i < NUM_ATC_REGS; i++) | |
621 | state->attr[i] = NVReadAttr(par, i); | |
622 | ||
623 | for (i = 0; i < NUM_GRC_REGS; i++) | |
624 | state->gra[i] = NVReadGr(par, i); | |
625 | ||
626 | for (i = 0; i < NUM_SEQ_REGS; i++) | |
627 | state->seq[i] = NVReadSeq(par, i); | |
628 | NVTRACE_LEAVE(); | |
629 | } | |
630 | ||
85f1503a BH |
631 | #undef DUMP_REG |
632 | ||
1da177e4 LT |
633 | static void nvidia_write_regs(struct nvidia_par *par) |
634 | { | |
635 | struct _riva_hw_state *state = &par->ModeReg; | |
636 | int i; | |
637 | ||
638 | NVTRACE_ENTER(); | |
1da177e4 LT |
639 | |
640 | NVLoadStateExt(par, state); | |
641 | ||
642 | NVWriteMiscOut(par, state->misc_output); | |
643 | ||
85f1503a BH |
644 | for (i = 1; i < NUM_SEQ_REGS; i++) { |
645 | #ifdef DUMP_REG | |
646 | printk(" SEQ[%02x] = %08x\n", i, state->seq[i]); | |
647 | #endif | |
648 | NVWriteSeq(par, i, state->seq[i]); | |
649 | } | |
650 | ||
651 | /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */ | |
652 | NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80); | |
653 | ||
1da177e4 LT |
654 | for (i = 0; i < NUM_CRT_REGS; i++) { |
655 | switch (i) { | |
656 | case 0x19: | |
657 | case 0x20 ... 0x40: | |
658 | break; | |
659 | default: | |
85f1503a BH |
660 | #ifdef DUMP_REG |
661 | printk("CRTC[%02x] = %08x\n", i, state->crtc[i]); | |
662 | #endif | |
1da177e4 LT |
663 | NVWriteCrtc(par, i, state->crtc[i]); |
664 | } | |
665 | } | |
666 | ||
85f1503a BH |
667 | for (i = 0; i < NUM_GRC_REGS; i++) { |
668 | #ifdef DUMP_REG | |
669 | printk(" GRA[%02x] = %08x\n", i, state->gra[i]); | |
670 | #endif | |
1da177e4 | 671 | NVWriteGr(par, i, state->gra[i]); |
85f1503a BH |
672 | } |
673 | ||
674 | for (i = 0; i < NUM_ATC_REGS; i++) { | |
675 | #ifdef DUMP_REG | |
676 | printk("ATTR[%02x] = %08x\n", i, state->attr[i]); | |
677 | #endif | |
678 | NVWriteAttr(par, i, state->attr[i]); | |
679 | } | |
1da177e4 | 680 | |
1da177e4 LT |
681 | NVTRACE_LEAVE(); |
682 | } | |
683 | ||
85f1503a BH |
684 | static void nvidia_vga_protect(struct nvidia_par *par, int on) |
685 | { | |
686 | unsigned char tmp; | |
687 | ||
688 | if (on) { | |
689 | /* | |
690 | * Turn off screen and disable sequencer. | |
691 | */ | |
692 | tmp = NVReadSeq(par, 0x01); | |
693 | ||
694 | NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */ | |
695 | NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */ | |
696 | } else { | |
697 | /* | |
698 | * Reenable sequencer, then turn on screen. | |
699 | */ | |
700 | ||
701 | tmp = NVReadSeq(par, 0x01); | |
702 | ||
703 | NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */ | |
704 | NVWriteSeq(par, 0x00, 0x03); /* End Reset */ | |
705 | } | |
706 | } | |
707 | ||
708 | ||
709 | ||
1da177e4 LT |
710 | static int nvidia_calc_regs(struct fb_info *info) |
711 | { | |
712 | struct nvidia_par *par = info->par; | |
713 | struct _riva_hw_state *state = &par->ModeReg; | |
b8c90945 | 714 | int i, depth = fb_get_color_depth(&info->var, &info->fix); |
1da177e4 LT |
715 | int h_display = info->var.xres / 8 - 1; |
716 | int h_start = (info->var.xres + info->var.right_margin) / 8 - 1; | |
717 | int h_end = (info->var.xres + info->var.right_margin + | |
718 | info->var.hsync_len) / 8 - 1; | |
719 | int h_total = (info->var.xres + info->var.right_margin + | |
720 | info->var.hsync_len + info->var.left_margin) / 8 - 5; | |
721 | int h_blank_s = h_display; | |
722 | int h_blank_e = h_total + 4; | |
723 | int v_display = info->var.yres - 1; | |
724 | int v_start = info->var.yres + info->var.lower_margin - 1; | |
725 | int v_end = (info->var.yres + info->var.lower_margin + | |
726 | info->var.vsync_len) - 1; | |
727 | int v_total = (info->var.yres + info->var.lower_margin + | |
728 | info->var.vsync_len + info->var.upper_margin) - 2; | |
729 | int v_blank_s = v_display; | |
730 | int v_blank_e = v_total + 1; | |
731 | ||
732 | /* | |
733 | * Set all CRTC values. | |
734 | */ | |
735 | ||
736 | if (info->var.vmode & FB_VMODE_INTERLACED) | |
737 | v_total |= 1; | |
738 | ||
739 | if (par->FlatPanel == 1) { | |
740 | v_start = v_total - 3; | |
741 | v_end = v_total - 2; | |
742 | v_blank_s = v_start; | |
743 | h_start = h_total - 5; | |
744 | h_end = h_total - 2; | |
745 | h_blank_e = h_total + 4; | |
746 | } | |
747 | ||
748 | state->crtc[0x0] = Set8Bits(h_total); | |
749 | state->crtc[0x1] = Set8Bits(h_display); | |
750 | state->crtc[0x2] = Set8Bits(h_blank_s); | |
751 | state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0) | |
752 | | SetBit(7); | |
753 | state->crtc[0x4] = Set8Bits(h_start); | |
754 | state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7) | |
755 | | SetBitField(h_end, 4: 0, 4:0); | |
756 | state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0); | |
757 | state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0) | |
758 | | SetBitField(v_display, 8: 8, 1:1) | |
759 | | SetBitField(v_start, 8: 8, 2:2) | |
760 | | SetBitField(v_blank_s, 8: 8, 3:3) | |
761 | | SetBit(4) | |
762 | | SetBitField(v_total, 9: 9, 5:5) | |
763 | | SetBitField(v_display, 9: 9, 6:6) | |
764 | | SetBitField(v_start, 9: 9, 7:7); | |
765 | state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5) | |
766 | | SetBit(6) | |
767 | | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00); | |
768 | state->crtc[0x10] = Set8Bits(v_start); | |
769 | state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5); | |
770 | state->crtc[0x12] = Set8Bits(v_display); | |
771 | state->crtc[0x13] = ((info->var.xres_virtual / 8) * | |
772 | (info->var.bits_per_pixel / 8)); | |
773 | state->crtc[0x15] = Set8Bits(v_blank_s); | |
774 | state->crtc[0x16] = Set8Bits(v_blank_e); | |
775 | ||
776 | state->attr[0x10] = 0x01; | |
777 | ||
778 | if (par->Television) | |
779 | state->attr[0x11] = 0x00; | |
780 | ||
781 | state->screen = SetBitField(h_blank_e, 6: 6, 4:4) | |
782 | | SetBitField(v_blank_s, 10: 10, 3:3) | |
783 | | SetBitField(v_start, 10: 10, 2:2) | |
784 | | SetBitField(v_display, 10: 10, 1:1) | |
785 | | SetBitField(v_total, 10: 10, 0:0); | |
786 | ||
787 | state->horiz = SetBitField(h_total, 8: 8, 0:0) | |
788 | | SetBitField(h_display, 8: 8, 1:1) | |
789 | | SetBitField(h_blank_s, 8: 8, 2:2) | |
790 | | SetBitField(h_start, 8: 8, 3:3); | |
791 | ||
792 | state->extra = SetBitField(v_total, 11: 11, 0:0) | |
793 | | SetBitField(v_display, 11: 11, 2:2) | |
794 | | SetBitField(v_start, 11: 11, 4:4) | |
795 | | SetBitField(v_blank_s, 11: 11, 6:6); | |
796 | ||
797 | if (info->var.vmode & FB_VMODE_INTERLACED) { | |
798 | h_total = (h_total >> 1) & ~1; | |
799 | state->interlace = Set8Bits(h_total); | |
800 | state->horiz |= SetBitField(h_total, 8: 8, 4:4); | |
801 | } else { | |
802 | state->interlace = 0xff; /* interlace off */ | |
803 | } | |
804 | ||
805 | /* | |
806 | * Calculate the extended registers. | |
807 | */ | |
808 | ||
809 | if (depth < 24) | |
810 | i = depth; | |
811 | else | |
812 | i = 32; | |
813 | ||
814 | if (par->Architecture >= NV_ARCH_10) | |
815 | par->CURSOR = (volatile u32 __iomem *)(info->screen_base + | |
816 | par->CursorStart); | |
817 | ||
818 | if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) | |
819 | state->misc_output &= ~0x40; | |
820 | else | |
821 | state->misc_output |= 0x40; | |
822 | if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) | |
823 | state->misc_output &= ~0x80; | |
824 | else | |
825 | state->misc_output |= 0x80; | |
826 | ||
827 | NVCalcStateExt(par, state, i, info->var.xres_virtual, | |
828 | info->var.xres, info->var.yres_virtual, | |
829 | 1000000000 / info->var.pixclock, info->var.vmode); | |
830 | ||
831 | state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff; | |
832 | if (par->FlatPanel == 1) { | |
833 | state->pixel |= (1 << 7); | |
834 | ||
835 | if (!par->fpScaler || (par->fpWidth <= info->var.xres) | |
836 | || (par->fpHeight <= info->var.yres)) { | |
837 | state->scale |= (1 << 8); | |
838 | } | |
839 | ||
840 | if (!par->crtcSync_read) { | |
841 | state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828); | |
842 | par->crtcSync_read = 1; | |
843 | } | |
844 | ||
845 | par->PanelTweak = nvidia_panel_tweak(par, state); | |
846 | } | |
847 | ||
848 | state->vpll = state->pll; | |
849 | state->vpll2 = state->pll; | |
850 | state->vpllB = state->pllB; | |
851 | state->vpll2B = state->pllB; | |
852 | ||
853 | VGA_WR08(par->PCIO, 0x03D4, 0x1C); | |
854 | state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5); | |
855 | ||
856 | if (par->CRTCnumber) { | |
857 | state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000; | |
858 | state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000; | |
859 | state->crtcOwner = 3; | |
860 | state->pllsel |= 0x20000800; | |
861 | state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508); | |
862 | if (par->twoStagePLL) | |
863 | state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578); | |
864 | } else if (par->twoHeads) { | |
865 | state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000; | |
866 | state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000; | |
867 | state->crtcOwner = 0; | |
868 | state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); | |
869 | if (par->twoStagePLL) | |
870 | state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); | |
871 | } | |
872 | ||
873 | state->cursorConfig = 0x00000100; | |
874 | ||
875 | if (info->var.vmode & FB_VMODE_DOUBLE) | |
876 | state->cursorConfig |= (1 << 4); | |
877 | ||
878 | if (par->alphaCursor) { | |
879 | if ((par->Chipset & 0x0ff0) != 0x0110) | |
880 | state->cursorConfig |= 0x04011000; | |
881 | else | |
882 | state->cursorConfig |= 0x14011000; | |
883 | state->general |= (1 << 29); | |
884 | } else | |
885 | state->cursorConfig |= 0x02000000; | |
886 | ||
887 | if (par->twoHeads) { | |
888 | if ((par->Chipset & 0x0ff0) == 0x0110) { | |
889 | state->dither = NV_RD32(par->PRAMDAC, 0x0528) & | |
890 | ~0x00010000; | |
891 | if (par->FPDither) | |
892 | state->dither |= 0x00010000; | |
893 | } else { | |
894 | state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1; | |
895 | if (par->FPDither) | |
896 | state->dither |= 1; | |
897 | } | |
898 | } | |
899 | ||
900 | state->timingH = 0; | |
901 | state->timingV = 0; | |
902 | state->displayV = info->var.xres; | |
903 | ||
904 | return 0; | |
905 | } | |
906 | ||
907 | static void nvidia_init_vga(struct fb_info *info) | |
908 | { | |
909 | struct nvidia_par *par = info->par; | |
910 | struct _riva_hw_state *state = &par->ModeReg; | |
911 | int i; | |
912 | ||
913 | for (i = 0; i < 0x10; i++) | |
914 | state->attr[i] = i; | |
915 | state->attr[0x10] = 0x41; | |
85f1503a | 916 | state->attr[0x11] = 0xff; |
1da177e4 LT |
917 | state->attr[0x12] = 0x0f; |
918 | state->attr[0x13] = 0x00; | |
919 | state->attr[0x14] = 0x00; | |
920 | ||
921 | memset(state->crtc, 0x00, NUM_CRT_REGS); | |
922 | state->crtc[0x0a] = 0x20; | |
923 | state->crtc[0x17] = 0xe3; | |
924 | state->crtc[0x18] = 0xff; | |
925 | state->crtc[0x28] = 0x40; | |
926 | ||
927 | memset(state->gra, 0x00, NUM_GRC_REGS); | |
928 | state->gra[0x05] = 0x40; | |
929 | state->gra[0x06] = 0x05; | |
930 | state->gra[0x07] = 0x0f; | |
931 | state->gra[0x08] = 0xff; | |
932 | ||
933 | state->seq[0x00] = 0x03; | |
934 | state->seq[0x01] = 0x01; | |
935 | state->seq[0x02] = 0x0f; | |
936 | state->seq[0x03] = 0x00; | |
937 | state->seq[0x04] = 0x0e; | |
938 | ||
939 | state->misc_output = 0xeb; | |
940 | } | |
941 | ||
942 | static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor) | |
943 | { | |
944 | struct nvidia_par *par = info->par; | |
945 | u8 data[MAX_CURS * MAX_CURS / 8]; | |
1da177e4 | 946 | int i, set = cursor->set; |
f1ab5dac | 947 | u16 fg, bg; |
1da177e4 | 948 | |
7a482425 | 949 | if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) |
f1ab5dac | 950 | return -ENXIO; |
1da177e4 LT |
951 | |
952 | NVShowHideCursor(par, 0); | |
953 | ||
954 | if (par->cursor_reset) { | |
955 | set = FB_CUR_SETALL; | |
956 | par->cursor_reset = 0; | |
957 | } | |
958 | ||
959 | if (set & FB_CUR_SETSIZE) | |
960 | memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2); | |
961 | ||
962 | if (set & FB_CUR_SETPOS) { | |
963 | u32 xx, yy, temp; | |
964 | ||
965 | yy = cursor->image.dy - info->var.yoffset; | |
966 | xx = cursor->image.dx - info->var.xoffset; | |
967 | temp = xx & 0xFFFF; | |
968 | temp |= yy << 16; | |
969 | ||
970 | NV_WR32(par->PRAMDAC, 0x0000300, temp); | |
971 | } | |
972 | ||
973 | if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { | |
974 | u32 bg_idx = cursor->image.bg_color; | |
975 | u32 fg_idx = cursor->image.fg_color; | |
976 | u32 s_pitch = (cursor->image.width + 7) >> 3; | |
977 | u32 d_pitch = MAX_CURS / 8; | |
978 | u8 *dat = (u8 *) cursor->image.data; | |
979 | u8 *msk = (u8 *) cursor->mask; | |
980 | u8 *src; | |
981 | ||
982 | src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC); | |
983 | ||
984 | if (src) { | |
985 | switch (cursor->rop) { | |
986 | case ROP_XOR: | |
f1ab5dac | 987 | for (i = 0; i < s_pitch * cursor->image.height; i++) |
1da177e4 LT |
988 | src[i] = dat[i] ^ msk[i]; |
989 | break; | |
990 | case ROP_COPY: | |
991 | default: | |
f1ab5dac | 992 | for (i = 0; i < s_pitch * cursor->image.height; i++) |
1da177e4 LT |
993 | src[i] = dat[i] & msk[i]; |
994 | break; | |
995 | } | |
996 | ||
f1ab5dac JS |
997 | fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, |
998 | cursor->image.height); | |
1da177e4 LT |
999 | |
1000 | bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | | |
1001 | ((info->cmap.green[bg_idx] & 0xf8) << 2) | | |
1002 | ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15; | |
1003 | ||
1004 | fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | | |
1005 | ((info->cmap.green[fg_idx] & 0xf8) << 2) | | |
1006 | ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15; | |
1007 | ||
1008 | NVLockUnlock(par, 0); | |
1009 | ||
1010 | nvidiafb_load_cursor_image(par, data, bg, fg, | |
1011 | cursor->image.width, | |
1012 | cursor->image.height); | |
1013 | kfree(src); | |
1014 | } | |
1015 | } | |
1016 | ||
1017 | if (cursor->enable) | |
1018 | NVShowHideCursor(par, 1); | |
1019 | ||
1020 | return 0; | |
1021 | } | |
1022 | ||
1023 | static int nvidiafb_set_par(struct fb_info *info) | |
1024 | { | |
1025 | struct nvidia_par *par = info->par; | |
1026 | ||
1027 | NVTRACE_ENTER(); | |
1028 | ||
1029 | NVLockUnlock(par, 1); | |
b8c49ef6 | 1030 | if (!par->FlatPanel || !par->twoHeads) |
1da177e4 LT |
1031 | par->FPDither = 0; |
1032 | ||
b8c49ef6 BH |
1033 | if (par->FPDither < 0) { |
1034 | if ((par->Chipset & 0x0ff0) == 0x0110) | |
1035 | par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528) | |
1036 | & 0x00010000); | |
1037 | else | |
1038 | par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1); | |
1039 | printk(KERN_INFO PFX "Flat panel dithering %s\n", | |
1040 | par->FPDither ? "enabled" : "disabled"); | |
1041 | } | |
1042 | ||
b8c90945 AD |
1043 | info->fix.visual = (info->var.bits_per_pixel == 8) ? |
1044 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; | |
1045 | ||
1da177e4 LT |
1046 | nvidia_init_vga(info); |
1047 | nvidia_calc_regs(info); | |
1da177e4 LT |
1048 | |
1049 | NVLockUnlock(par, 0); | |
1050 | if (par->twoHeads) { | |
1051 | VGA_WR08(par->PCIO, 0x03D4, 0x44); | |
1052 | VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner); | |
1053 | NVLockUnlock(par, 0); | |
1054 | } | |
1055 | ||
85f1503a BH |
1056 | nvidia_vga_protect(par, 1); |
1057 | ||
1058 | nvidia_write_regs(par); | |
1059 | ||
1060 | #if defined (__BIG_ENDIAN) | |
1061 | /* turn on LFB swapping */ | |
1062 | { | |
1063 | unsigned char tmp; | |
1064 | ||
1065 | VGA_WR08(par->PCIO, 0x3d4, 0x46); | |
1066 | tmp = VGA_RD08(par->PCIO, 0x3d5); | |
1067 | tmp |= (1 << 7); | |
1068 | VGA_WR08(par->PCIO, 0x3d5, tmp); | |
1069 | } | |
1070 | #endif | |
1071 | ||
1da177e4 LT |
1072 | info->fix.line_length = (info->var.xres_virtual * |
1073 | info->var.bits_per_pixel) >> 3; | |
1da177e4 LT |
1074 | if (info->var.accel_flags) { |
1075 | info->fbops->fb_imageblit = nvidiafb_imageblit; | |
1076 | info->fbops->fb_fillrect = nvidiafb_fillrect; | |
1077 | info->fbops->fb_copyarea = nvidiafb_copyarea; | |
1078 | info->fbops->fb_sync = nvidiafb_sync; | |
1079 | info->pixmap.scan_align = 4; | |
1080 | info->flags &= ~FBINFO_HWACCEL_DISABLED; | |
1081 | NVResetGraphics(info); | |
1082 | } else { | |
1083 | info->fbops->fb_imageblit = cfb_imageblit; | |
1084 | info->fbops->fb_fillrect = cfb_fillrect; | |
1085 | info->fbops->fb_copyarea = cfb_copyarea; | |
1086 | info->fbops->fb_sync = NULL; | |
1087 | info->pixmap.scan_align = 1; | |
1088 | info->flags |= FBINFO_HWACCEL_DISABLED; | |
1089 | } | |
1090 | ||
1091 | par->cursor_reset = 1; | |
1092 | ||
85f1503a | 1093 | nvidia_vga_protect(par, 0); |
1da177e4 LT |
1094 | |
1095 | NVTRACE_LEAVE(); | |
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green, | |
1100 | unsigned blue, unsigned transp, | |
1101 | struct fb_info *info) | |
1102 | { | |
1103 | struct nvidia_par *par = info->par; | |
1104 | int i; | |
1105 | ||
1106 | NVTRACE_ENTER(); | |
1107 | if (regno >= (1 << info->var.green.length)) | |
1108 | return -EINVAL; | |
1109 | ||
1110 | if (info->var.grayscale) { | |
1111 | /* gray = 0.30*R + 0.59*G + 0.11*B */ | |
1112 | red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; | |
1113 | } | |
1114 | ||
1115 | if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { | |
1116 | ((u32 *) info->pseudo_palette)[regno] = | |
1117 | (regno << info->var.red.offset) | | |
1118 | (regno << info->var.green.offset) | | |
1119 | (regno << info->var.blue.offset); | |
1120 | } | |
1121 | ||
1122 | switch (info->var.bits_per_pixel) { | |
1123 | case 8: | |
1124 | /* "transparent" stuff is completely ignored. */ | |
1125 | nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); | |
1126 | break; | |
1127 | case 16: | |
1128 | if (info->var.green.length == 5) { | |
1129 | for (i = 0; i < 8; i++) { | |
1130 | nvidia_write_clut(par, regno * 8 + i, red >> 8, | |
1131 | green >> 8, blue >> 8); | |
1132 | } | |
1133 | } else { | |
1134 | u8 r, g, b; | |
1135 | ||
1136 | if (regno < 32) { | |
1137 | for (i = 0; i < 8; i++) { | |
1138 | nvidia_write_clut(par, regno * 8 + i, | |
1139 | red >> 8, green >> 8, | |
1140 | blue >> 8); | |
1141 | } | |
1142 | } | |
1143 | ||
1144 | nvidia_read_clut(par, regno * 4, &r, &g, &b); | |
1145 | ||
1146 | for (i = 0; i < 4; i++) | |
1147 | nvidia_write_clut(par, regno * 4 + i, r, | |
1148 | green >> 8, b); | |
1149 | } | |
1150 | break; | |
1151 | case 32: | |
1152 | nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); | |
1153 | break; | |
1154 | default: | |
1155 | /* do nothing */ | |
1156 | break; | |
1157 | } | |
1158 | ||
1159 | NVTRACE_LEAVE(); | |
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | static int nvidiafb_check_var(struct fb_var_screeninfo *var, | |
1164 | struct fb_info *info) | |
1165 | { | |
1166 | struct nvidia_par *par = info->par; | |
1167 | int memlen, vramlen, mode_valid = 0; | |
1168 | int pitch, err = 0; | |
1169 | ||
1170 | NVTRACE_ENTER(); | |
1171 | ||
1172 | var->transp.offset = 0; | |
1173 | var->transp.length = 0; | |
1174 | ||
1175 | var->xres &= ~7; | |
1176 | ||
1177 | if (var->bits_per_pixel <= 8) | |
1178 | var->bits_per_pixel = 8; | |
1179 | else if (var->bits_per_pixel <= 16) | |
1180 | var->bits_per_pixel = 16; | |
1181 | else | |
1182 | var->bits_per_pixel = 32; | |
1183 | ||
1184 | switch (var->bits_per_pixel) { | |
1185 | case 8: | |
1186 | var->red.offset = 0; | |
1187 | var->red.length = 8; | |
1188 | var->green.offset = 0; | |
1189 | var->green.length = 8; | |
1190 | var->blue.offset = 0; | |
1191 | var->blue.length = 8; | |
1192 | var->transp.offset = 0; | |
1193 | var->transp.length = 0; | |
1194 | break; | |
1195 | case 16: | |
1196 | var->green.length = (var->green.length < 6) ? 5 : 6; | |
1197 | var->red.length = 5; | |
1198 | var->blue.length = 5; | |
1199 | var->transp.length = 6 - var->green.length; | |
1200 | var->blue.offset = 0; | |
1201 | var->green.offset = 5; | |
1202 | var->red.offset = 5 + var->green.length; | |
1203 | var->transp.offset = (5 + var->red.offset) & 15; | |
1204 | break; | |
1205 | case 32: /* RGBA 8888 */ | |
1206 | var->red.offset = 16; | |
1207 | var->red.length = 8; | |
1208 | var->green.offset = 8; | |
1209 | var->green.length = 8; | |
1210 | var->blue.offset = 0; | |
1211 | var->blue.length = 8; | |
1212 | var->transp.length = 8; | |
1213 | var->transp.offset = 24; | |
1214 | break; | |
1215 | } | |
1216 | ||
1217 | var->red.msb_right = 0; | |
1218 | var->green.msb_right = 0; | |
1219 | var->blue.msb_right = 0; | |
1220 | var->transp.msb_right = 0; | |
1221 | ||
1222 | if (!info->monspecs.hfmax || !info->monspecs.vfmax || | |
1223 | !info->monspecs.dclkmax || !fb_validate_mode(var, info)) | |
1224 | mode_valid = 1; | |
1225 | ||
1226 | /* calculate modeline if supported by monitor */ | |
1227 | if (!mode_valid && info->monspecs.gtf) { | |
1228 | if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) | |
1229 | mode_valid = 1; | |
1230 | } | |
1231 | ||
1232 | if (!mode_valid) { | |
1233 | struct fb_videomode *mode; | |
1234 | ||
1235 | mode = fb_find_best_mode(var, &info->modelist); | |
1236 | if (mode) { | |
1237 | fb_videomode_to_var(var, mode); | |
1238 | mode_valid = 1; | |
1239 | } | |
1240 | } | |
1241 | ||
1242 | if (!mode_valid && info->monspecs.modedb_len) | |
1243 | return -EINVAL; | |
1244 | ||
1245 | if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres || | |
1246 | par->fpHeight < var->yres)) | |
1247 | return -EINVAL; | |
1248 | ||
1249 | if (var->yres_virtual < var->yres) | |
1250 | var->yres_virtual = var->yres; | |
1251 | ||
1252 | if (var->xres_virtual < var->xres) | |
1253 | var->xres_virtual = var->xres; | |
1254 | ||
1255 | var->xres_virtual = (var->xres_virtual + 63) & ~63; | |
1256 | ||
917bb077 | 1257 | vramlen = info->screen_size; |
1da177e4 LT |
1258 | pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8; |
1259 | memlen = pitch * var->yres_virtual; | |
1260 | ||
1261 | if (memlen > vramlen) { | |
1262 | var->yres_virtual = vramlen / pitch; | |
1263 | ||
1264 | if (var->yres_virtual < var->yres) { | |
1265 | var->yres_virtual = var->yres; | |
1266 | var->xres_virtual = vramlen / var->yres_virtual; | |
1267 | var->xres_virtual /= var->bits_per_pixel / 8; | |
1268 | var->xres_virtual &= ~63; | |
1269 | pitch = (var->xres_virtual * | |
1270 | var->bits_per_pixel + 7) / 8; | |
1271 | memlen = pitch * var->yres; | |
1272 | ||
1273 | if (var->xres_virtual < var->xres) { | |
1274 | printk("nvidiafb: required video memory, " | |
1275 | "%d bytes, for %dx%d-%d (virtual) " | |
1276 | "is out of range\n", | |
1277 | memlen, var->xres_virtual, | |
1278 | var->yres_virtual, var->bits_per_pixel); | |
1279 | err = -ENOMEM; | |
1280 | } | |
1281 | } | |
1282 | } | |
1283 | ||
1284 | if (var->accel_flags) { | |
1285 | if (var->yres_virtual > 0x7fff) | |
1286 | var->yres_virtual = 0x7fff; | |
1287 | if (var->xres_virtual > 0x7fff) | |
1288 | var->xres_virtual = 0x7fff; | |
1289 | } | |
1290 | ||
1291 | var->xres_virtual &= ~63; | |
1292 | ||
1293 | NVTRACE_LEAVE(); | |
1294 | ||
1295 | return err; | |
1296 | } | |
1297 | ||
1298 | static int nvidiafb_pan_display(struct fb_var_screeninfo *var, | |
1299 | struct fb_info *info) | |
1300 | { | |
1301 | struct nvidia_par *par = info->par; | |
1302 | u32 total; | |
1303 | ||
3c8d61bc | 1304 | total = var->yoffset * info->fix.line_length + var->xoffset; |
1da177e4 LT |
1305 | |
1306 | NVSetStartAddress(par, total); | |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | ||
1311 | static int nvidiafb_blank(int blank, struct fb_info *info) | |
1312 | { | |
1313 | struct nvidia_par *par = info->par; | |
1314 | unsigned char tmp, vesa; | |
1315 | ||
1316 | tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */ | |
1317 | vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */ | |
1318 | ||
1319 | NVTRACE_ENTER(); | |
1320 | ||
1321 | if (blank) | |
1322 | tmp |= 0x20; | |
1323 | ||
1324 | switch (blank) { | |
1325 | case FB_BLANK_UNBLANK: | |
1326 | case FB_BLANK_NORMAL: | |
1327 | break; | |
1328 | case FB_BLANK_VSYNC_SUSPEND: | |
1329 | vesa |= 0x80; | |
1330 | break; | |
1331 | case FB_BLANK_HSYNC_SUSPEND: | |
1332 | vesa |= 0x40; | |
1333 | break; | |
1334 | case FB_BLANK_POWERDOWN: | |
1335 | vesa |= 0xc0; | |
1336 | break; | |
1337 | } | |
1338 | ||
1339 | NVWriteSeq(par, 0x01, tmp); | |
1340 | NVWriteCrtc(par, 0x1a, vesa); | |
1341 | ||
1342 | #ifdef CONFIG_PMAC_BACKLIGHT | |
1343 | if (par->FlatPanel && _machine == _MACH_Pmac) { | |
1344 | set_backlight_enable(!blank); | |
1345 | } | |
1346 | #endif | |
1347 | ||
1348 | NVTRACE_LEAVE(); | |
1349 | ||
1350 | return 0; | |
1351 | } | |
1352 | ||
1353 | static struct fb_ops nvidia_fb_ops = { | |
1354 | .owner = THIS_MODULE, | |
1355 | .fb_check_var = nvidiafb_check_var, | |
1356 | .fb_set_par = nvidiafb_set_par, | |
1357 | .fb_setcolreg = nvidiafb_setcolreg, | |
1358 | .fb_pan_display = nvidiafb_pan_display, | |
1359 | .fb_blank = nvidiafb_blank, | |
1360 | .fb_fillrect = nvidiafb_fillrect, | |
1361 | .fb_copyarea = nvidiafb_copyarea, | |
1362 | .fb_imageblit = nvidiafb_imageblit, | |
1363 | .fb_cursor = nvidiafb_cursor, | |
1364 | .fb_sync = nvidiafb_sync, | |
1365 | }; | |
1366 | ||
1367 | static int __devinit nvidia_set_fbinfo(struct fb_info *info) | |
1368 | { | |
1369 | struct fb_monspecs *specs = &info->monspecs; | |
1370 | struct fb_videomode modedb; | |
1371 | struct nvidia_par *par = info->par; | |
1372 | int lpitch; | |
1373 | ||
1374 | NVTRACE_ENTER(); | |
1375 | info->flags = FBINFO_DEFAULT | |
1376 | | FBINFO_HWACCEL_IMAGEBLIT | |
1377 | | FBINFO_HWACCEL_FILLRECT | |
1378 | | FBINFO_HWACCEL_COPYAREA | |
1379 | | FBINFO_HWACCEL_YPAN; | |
1380 | ||
1381 | fb_videomode_to_modelist(info->monspecs.modedb, | |
1382 | info->monspecs.modedb_len, &info->modelist); | |
1383 | fb_var_to_videomode(&modedb, &nvidiafb_default_var); | |
1384 | ||
1385 | if (specs->modedb != NULL) { | |
5ee1ef96 | 1386 | struct fb_videomode *modedb; |
1da177e4 | 1387 | |
5ee1ef96 AD |
1388 | modedb = fb_find_best_display(specs, &info->modelist); |
1389 | fb_videomode_to_var(&nvidiafb_default_var, modedb); | |
1da177e4 | 1390 | nvidiafb_default_var.bits_per_pixel = 8; |
db6778db AD |
1391 | } else if (par->fpWidth && par->fpHeight) { |
1392 | char buf[16]; | |
1393 | ||
1394 | memset(buf, 0, 16); | |
948a95ff | 1395 | snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight); |
db6778db AD |
1396 | fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb, |
1397 | specs->modedb_len, &modedb, 8); | |
1da177e4 LT |
1398 | } |
1399 | ||
1400 | if (mode_option) | |
1401 | fb_find_mode(&nvidiafb_default_var, info, mode_option, | |
1402 | specs->modedb, specs->modedb_len, &modedb, 8); | |
1403 | ||
1404 | info->var = nvidiafb_default_var; | |
1405 | info->fix.visual = (info->var.bits_per_pixel == 8) ? | |
1406 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; | |
1407 | info->pseudo_palette = par->pseudo_palette; | |
1408 | fb_alloc_cmap(&info->cmap, 256, 0); | |
1409 | fb_destroy_modedb(info->monspecs.modedb); | |
1410 | info->monspecs.modedb = NULL; | |
1411 | ||
1412 | /* maximize virtual vertical length */ | |
1413 | lpitch = info->var.xres_virtual * | |
1414 | ((info->var.bits_per_pixel + 7) >> 3); | |
917bb077 | 1415 | info->var.yres_virtual = info->screen_size / lpitch; |
1da177e4 LT |
1416 | |
1417 | info->pixmap.scan_align = 4; | |
1418 | info->pixmap.buf_align = 4; | |
58a60643 | 1419 | info->pixmap.access_align = 32; |
1da177e4 LT |
1420 | info->pixmap.size = 8 * 1024; |
1421 | info->pixmap.flags = FB_PIXMAP_SYSTEM; | |
1422 | ||
7a482425 | 1423 | if (!hwcur) |
c465e05a | 1424 | info->fbops->fb_cursor = NULL; |
7a482425 | 1425 | |
1da177e4 LT |
1426 | info->var.accel_flags = (!noaccel); |
1427 | ||
1428 | switch (par->Architecture) { | |
1429 | case NV_ARCH_04: | |
1430 | info->fix.accel = FB_ACCEL_NV4; | |
1431 | break; | |
1432 | case NV_ARCH_10: | |
1433 | info->fix.accel = FB_ACCEL_NV_10; | |
1434 | break; | |
1435 | case NV_ARCH_20: | |
1436 | info->fix.accel = FB_ACCEL_NV_20; | |
1437 | break; | |
1438 | case NV_ARCH_30: | |
1439 | info->fix.accel = FB_ACCEL_NV_30; | |
1440 | break; | |
1441 | case NV_ARCH_40: | |
1442 | info->fix.accel = FB_ACCEL_NV_40; | |
1443 | break; | |
1444 | } | |
1445 | ||
1446 | NVTRACE_LEAVE(); | |
1447 | ||
1448 | return nvidiafb_check_var(&info->var, info); | |
1449 | } | |
1450 | ||
1451 | static u32 __devinit nvidia_get_arch(struct pci_dev *pd) | |
1452 | { | |
1453 | u32 arch = 0; | |
1454 | ||
1455 | switch (pd->device & 0x0ff0) { | |
1456 | case 0x0100: /* GeForce 256 */ | |
1457 | case 0x0110: /* GeForce2 MX */ | |
1458 | case 0x0150: /* GeForce2 */ | |
1459 | case 0x0170: /* GeForce4 MX */ | |
1460 | case 0x0180: /* GeForce4 MX (8x AGP) */ | |
1461 | case 0x01A0: /* nForce */ | |
1462 | case 0x01F0: /* nForce2 */ | |
1463 | arch = NV_ARCH_10; | |
1464 | break; | |
1465 | case 0x0200: /* GeForce3 */ | |
1466 | case 0x0250: /* GeForce4 Ti */ | |
1467 | case 0x0280: /* GeForce4 Ti (8x AGP) */ | |
1468 | arch = NV_ARCH_20; | |
1469 | break; | |
1470 | case 0x0300: /* GeForceFX 5800 */ | |
1471 | case 0x0310: /* GeForceFX 5600 */ | |
1472 | case 0x0320: /* GeForceFX 5200 */ | |
1473 | case 0x0330: /* GeForceFX 5900 */ | |
1474 | case 0x0340: /* GeForceFX 5700 */ | |
1475 | arch = NV_ARCH_30; | |
1476 | break; | |
1477 | case 0x0040: | |
1478 | case 0x00C0: | |
1479 | case 0x0120: | |
1480 | case 0x0130: | |
1481 | case 0x0140: | |
1482 | case 0x0160: | |
1483 | case 0x01D0: | |
1484 | case 0x0090: | |
1485 | case 0x0210: | |
1486 | case 0x0220: | |
1487 | case 0x0230: | |
0137ecfd BH |
1488 | case 0x0290: |
1489 | case 0x0390: | |
1da177e4 LT |
1490 | arch = NV_ARCH_40; |
1491 | break; | |
1492 | case 0x0020: /* TNT, TNT2 */ | |
1493 | arch = NV_ARCH_04; | |
1494 | break; | |
1495 | default: /* unknown architecture */ | |
1496 | break; | |
1497 | } | |
1498 | ||
1499 | return arch; | |
1500 | } | |
1501 | ||
1502 | static int __devinit nvidiafb_probe(struct pci_dev *pd, | |
1503 | const struct pci_device_id *ent) | |
1504 | { | |
1505 | struct nvidia_par *par; | |
1506 | struct fb_info *info; | |
1507 | unsigned short cmd; | |
1508 | ||
1509 | ||
1510 | NVTRACE_ENTER(); | |
1511 | assert(pd != NULL); | |
1512 | ||
1513 | info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev); | |
1514 | ||
1515 | if (!info) | |
1516 | goto err_out; | |
1517 | ||
c439e345 | 1518 | par = info->par; |
1da177e4 LT |
1519 | par->pci_dev = pd; |
1520 | ||
1521 | info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL); | |
1522 | ||
1523 | if (info->pixmap.addr == NULL) | |
1524 | goto err_out_kfree; | |
1525 | ||
1526 | memset(info->pixmap.addr, 0, 8 * 1024); | |
1527 | ||
1528 | if (pci_enable_device(pd)) { | |
1529 | printk(KERN_ERR PFX "cannot enable PCI device\n"); | |
1530 | goto err_out_enable; | |
1531 | } | |
1532 | ||
1533 | if (pci_request_regions(pd, "nvidiafb")) { | |
1534 | printk(KERN_ERR PFX "cannot request PCI regions\n"); | |
1535 | goto err_out_request; | |
1536 | } | |
1537 | ||
1538 | par->Architecture = nvidia_get_arch(pd); | |
1539 | ||
1540 | par->Chipset = (pd->vendor << 16) | pd->device; | |
1541 | printk(KERN_INFO PFX "nVidia device/chipset %X\n", par->Chipset); | |
1542 | ||
1da177e4 LT |
1543 | if (par->Architecture == 0) { |
1544 | printk(KERN_ERR PFX "unknown NV_ARCH\n"); | |
1545 | goto err_out_free_base0; | |
1546 | } | |
1547 | ||
1548 | sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); | |
1549 | ||
1550 | par->FlatPanel = flatpanel; | |
1da177e4 LT |
1551 | if (flatpanel == 1) |
1552 | printk(KERN_INFO PFX "flatpanel support enabled\n"); | |
b8c49ef6 | 1553 | par->FPDither = fpdither; |
1da177e4 LT |
1554 | |
1555 | par->CRTCnumber = forceCRTC; | |
1556 | par->FpScale = (!noscale); | |
1557 | par->paneltweak = paneltweak; | |
1558 | ||
1559 | /* enable IO and mem if not already done */ | |
1560 | pci_read_config_word(pd, PCI_COMMAND, &cmd); | |
1561 | cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); | |
1562 | pci_write_config_word(pd, PCI_COMMAND, cmd); | |
1563 | ||
1564 | nvidiafb_fix.mmio_start = pci_resource_start(pd, 0); | |
1565 | nvidiafb_fix.smem_start = pci_resource_start(pd, 1); | |
1566 | nvidiafb_fix.mmio_len = pci_resource_len(pd, 0); | |
1567 | ||
1568 | par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); | |
1569 | ||
1570 | if (!par->REGS) { | |
1571 | printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); | |
1572 | goto err_out_free_base0; | |
1573 | } | |
1574 | ||
1575 | NVCommonSetup(info); | |
1576 | ||
1577 | par->FbAddress = nvidiafb_fix.smem_start; | |
1578 | par->FbMapSize = par->RamAmountKBytes * 1024; | |
917bb077 AD |
1579 | if (vram && vram * 1024 * 1024 < par->FbMapSize) |
1580 | par->FbMapSize = vram * 1024 * 1024; | |
1581 | ||
1582 | /* Limit amount of vram to 64 MB */ | |
1583 | if (par->FbMapSize > 64 * 1024 * 1024) | |
1584 | par->FbMapSize = 64 * 1024 * 1024; | |
1585 | ||
0137ecfd BH |
1586 | if(par->Architecture >= NV_ARCH_40) |
1587 | par->FbUsableSize = par->FbMapSize - (560 * 1024); | |
1588 | else | |
1589 | par->FbUsableSize = par->FbMapSize - (128 * 1024); | |
1da177e4 LT |
1590 | par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 : |
1591 | 16 * 1024; | |
1592 | par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize; | |
0137ecfd BH |
1593 | par->CursorStart = par->FbUsableSize + (32 * 1024); |
1594 | ||
1da177e4 | 1595 | info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize); |
917bb077 AD |
1596 | info->screen_size = par->FbUsableSize; |
1597 | nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024; | |
1da177e4 LT |
1598 | |
1599 | if (!info->screen_base) { | |
1600 | printk(KERN_ERR PFX "cannot ioremap FB base\n"); | |
1601 | goto err_out_free_base1; | |
1602 | } | |
1603 | ||
1604 | par->FbStart = info->screen_base; | |
1605 | ||
1606 | #ifdef CONFIG_MTRR | |
1607 | if (!nomtrr) { | |
1608 | par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start, | |
917bb077 AD |
1609 | par->RamAmountKBytes * 1024, |
1610 | MTRR_TYPE_WRCOMB, 1); | |
1da177e4 LT |
1611 | if (par->mtrr.vram < 0) { |
1612 | printk(KERN_ERR PFX "unable to setup MTRR\n"); | |
1613 | } else { | |
1614 | par->mtrr.vram_valid = 1; | |
1615 | /* let there be speed */ | |
1616 | printk(KERN_INFO PFX "MTRR set to ON\n"); | |
1617 | } | |
1618 | } | |
1619 | #endif /* CONFIG_MTRR */ | |
1620 | ||
1621 | info->fbops = &nvidia_fb_ops; | |
1622 | info->fix = nvidiafb_fix; | |
1623 | ||
1624 | if (nvidia_set_fbinfo(info) < 0) { | |
1625 | printk(KERN_ERR PFX "error setting initial video mode\n"); | |
1626 | goto err_out_iounmap_fb; | |
1627 | } | |
1628 | ||
1629 | nvidia_save_vga(par, &par->SavedReg); | |
1630 | ||
1631 | if (register_framebuffer(info) < 0) { | |
1632 | printk(KERN_ERR PFX "error registering nVidia framebuffer\n"); | |
1633 | goto err_out_iounmap_fb; | |
1634 | } | |
1635 | ||
1636 | pci_set_drvdata(pd, info); | |
1637 | ||
1638 | printk(KERN_INFO PFX | |
1639 | "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n", | |
1640 | info->fix.id, | |
1641 | par->FbMapSize / (1024 * 1024), info->fix.smem_start); | |
1642 | #ifdef CONFIG_PMAC_BACKLIGHT | |
1643 | if (par->FlatPanel && _machine == _MACH_Pmac) | |
1644 | register_backlight_controller(&nvidia_backlight_controller, | |
1645 | par, "mnca"); | |
1646 | #endif | |
1647 | NVTRACE_LEAVE(); | |
1648 | return 0; | |
1649 | ||
1650 | err_out_iounmap_fb: | |
1651 | iounmap(info->screen_base); | |
917bb077 | 1652 | err_out_free_base1: |
1da177e4 LT |
1653 | fb_destroy_modedb(info->monspecs.modedb); |
1654 | nvidia_delete_i2c_busses(par); | |
1da177e4 LT |
1655 | iounmap(par->REGS); |
1656 | err_out_free_base0: | |
1657 | pci_release_regions(pd); | |
1658 | err_out_request: | |
1659 | pci_disable_device(pd); | |
1660 | err_out_enable: | |
1661 | kfree(info->pixmap.addr); | |
1662 | err_out_kfree: | |
1663 | framebuffer_release(info); | |
1664 | err_out: | |
1665 | return -ENODEV; | |
1666 | } | |
1667 | ||
1668 | static void __exit nvidiafb_remove(struct pci_dev *pd) | |
1669 | { | |
1670 | struct fb_info *info = pci_get_drvdata(pd); | |
1671 | struct nvidia_par *par = info->par; | |
1672 | ||
1673 | NVTRACE_ENTER(); | |
1674 | if (!info) | |
1675 | return; | |
1676 | ||
1677 | unregister_framebuffer(info); | |
1678 | #ifdef CONFIG_MTRR | |
1679 | if (par->mtrr.vram_valid) | |
1680 | mtrr_del(par->mtrr.vram, info->fix.smem_start, | |
1681 | info->fix.smem_len); | |
1682 | #endif /* CONFIG_MTRR */ | |
1683 | ||
1684 | iounmap(info->screen_base); | |
1685 | fb_destroy_modedb(info->monspecs.modedb); | |
1686 | nvidia_delete_i2c_busses(par); | |
1687 | iounmap(par->REGS); | |
1688 | pci_release_regions(pd); | |
1689 | pci_disable_device(pd); | |
1690 | kfree(info->pixmap.addr); | |
1691 | framebuffer_release(info); | |
1692 | pci_set_drvdata(pd, NULL); | |
1693 | NVTRACE_LEAVE(); | |
1694 | } | |
1695 | ||
1696 | /* ------------------------------------------------------------------------- * | |
1697 | * | |
1698 | * initialization | |
1699 | * | |
1700 | * ------------------------------------------------------------------------- */ | |
1701 | ||
1702 | #ifndef MODULE | |
1703 | static int __devinit nvidiafb_setup(char *options) | |
1704 | { | |
1705 | char *this_opt; | |
1706 | ||
1707 | NVTRACE_ENTER(); | |
1708 | if (!options || !*options) | |
1709 | return 0; | |
1710 | ||
1711 | while ((this_opt = strsep(&options, ",")) != NULL) { | |
1712 | if (!strncmp(this_opt, "forceCRTC", 9)) { | |
1713 | char *p; | |
1714 | ||
1715 | p = this_opt + 9; | |
1716 | if (!*p || !*(++p)) | |
1717 | continue; | |
1718 | forceCRTC = *p - '0'; | |
1719 | if (forceCRTC < 0 || forceCRTC > 1) | |
1720 | forceCRTC = -1; | |
1721 | } else if (!strncmp(this_opt, "flatpanel", 9)) { | |
1722 | flatpanel = 1; | |
1723 | } else if (!strncmp(this_opt, "hwcur", 5)) { | |
1724 | hwcur = 1; | |
1725 | } else if (!strncmp(this_opt, "noaccel", 6)) { | |
1726 | noaccel = 1; | |
1727 | } else if (!strncmp(this_opt, "noscale", 7)) { | |
1728 | noscale = 1; | |
1729 | } else if (!strncmp(this_opt, "paneltweak:", 11)) { | |
1730 | paneltweak = simple_strtoul(this_opt+11, NULL, 0); | |
917bb077 AD |
1731 | } else if (!strncmp(this_opt, "vram:", 5)) { |
1732 | vram = simple_strtoul(this_opt+5, NULL, 0); | |
1da177e4 LT |
1733 | #ifdef CONFIG_MTRR |
1734 | } else if (!strncmp(this_opt, "nomtrr", 6)) { | |
1735 | nomtrr = 1; | |
1736 | #endif | |
b8c49ef6 BH |
1737 | } else if (!strncmp(this_opt, "fpdither:", 9)) { |
1738 | fpdither = simple_strtol(this_opt+9, NULL, 0); | |
1da177e4 LT |
1739 | } else |
1740 | mode_option = this_opt; | |
1741 | } | |
1742 | NVTRACE_LEAVE(); | |
1743 | return 0; | |
1744 | } | |
1745 | #endif /* !MODULE */ | |
1746 | ||
1747 | static struct pci_driver nvidiafb_driver = { | |
1748 | .name = "nvidiafb", | |
1749 | .id_table = nvidiafb_pci_tbl, | |
1750 | .probe = nvidiafb_probe, | |
1751 | .remove = __exit_p(nvidiafb_remove), | |
1752 | }; | |
1753 | ||
1754 | /* ------------------------------------------------------------------------- * | |
1755 | * | |
1756 | * modularization | |
1757 | * | |
1758 | * ------------------------------------------------------------------------- */ | |
1759 | ||
1760 | static int __devinit nvidiafb_init(void) | |
1761 | { | |
1762 | #ifndef MODULE | |
1763 | char *option = NULL; | |
1764 | ||
1765 | if (fb_get_options("nvidiafb", &option)) | |
1766 | return -ENODEV; | |
1767 | nvidiafb_setup(option); | |
1768 | #endif | |
1769 | return pci_register_driver(&nvidiafb_driver); | |
1770 | } | |
1771 | ||
1772 | module_init(nvidiafb_init); | |
1773 | ||
1774 | #ifdef MODULE | |
1775 | static void __exit nvidiafb_exit(void) | |
1776 | { | |
1777 | pci_unregister_driver(&nvidiafb_driver); | |
1778 | } | |
1779 | ||
1780 | module_exit(nvidiafb_exit); | |
1781 | ||
1782 | module_param(flatpanel, int, 0); | |
1783 | MODULE_PARM_DESC(flatpanel, | |
1784 | "Enables experimental flat panel support for some chipsets. " | |
b8c49ef6 BH |
1785 | "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); |
1786 | module_param(fpdither, int, 0); | |
1787 | MODULE_PARM_DESC(fpdither, | |
1788 | "Enables dithering of flat panel for 6 bits panels. " | |
1789 | "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); | |
1da177e4 LT |
1790 | module_param(hwcur, int, 0); |
1791 | MODULE_PARM_DESC(hwcur, | |
1792 | "Enables hardware cursor implementation. (0 or 1=enabled) " | |
1793 | "(default=0)"); | |
1794 | module_param(noaccel, int, 0); | |
1795 | MODULE_PARM_DESC(noaccel, | |
1796 | "Disables hardware acceleration. (0 or 1=disable) " | |
1797 | "(default=0)"); | |
1798 | module_param(noscale, int, 0); | |
1799 | MODULE_PARM_DESC(noscale, | |
1800 | "Disables screen scaleing. (0 or 1=disable) " | |
1801 | "(default=0, do scaling)"); | |
1802 | module_param(paneltweak, int, 0); | |
1803 | MODULE_PARM_DESC(paneltweak, | |
1804 | "Tweak display settings for flatpanels. " | |
1805 | "(default=0, no tweaks)"); | |
1806 | module_param(forceCRTC, int, 0); | |
1807 | MODULE_PARM_DESC(forceCRTC, | |
1808 | "Forces usage of a particular CRTC in case autodetection " | |
1809 | "fails. (0 or 1) (default=autodetect)"); | |
917bb077 AD |
1810 | module_param(vram, int, 0); |
1811 | MODULE_PARM_DESC(vram, | |
1812 | "amount of framebuffer memory to remap in MiB" | |
1813 | "(default=0 - remap entire memory)"); | |
c439e345 AD |
1814 | module_param(mode_option, charp, 0); |
1815 | MODULE_PARM_DESC(mode_option, "Specify initial video mode"); | |
1816 | ||
1da177e4 LT |
1817 | #ifdef CONFIG_MTRR |
1818 | module_param(nomtrr, bool, 0); | |
1819 | MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) " | |
1820 | "(default=0)"); | |
1821 | #endif | |
1822 | ||
1823 | MODULE_AUTHOR("Antonino Daplas"); | |
1824 | MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset"); | |
1825 | MODULE_LICENSE("GPL"); | |
1826 | #endif /* MODULE */ | |
1827 |