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vga16fb: remove open_lock mutex
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / neofb.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/neofb.c -- NeoMagic Framebuffer Driver
3 *
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
5 *
6 *
7 * Card specific code is based on XFree86's neomagic driver.
8 * Framebuffer framework code is based on code of cyber2000fb.
9 *
10 * This file is subject to the terms and conditions of the GNU General
11 * Public License. See the file COPYING in the main directory of this
12 * archive for more details.
13 *
14 *
15 * 0.4.1
16 * - Cosmetic changes (dok)
17 *
18 * 0.4
19 * - Toshiba Libretto support, allow modes larger than LCD size if
20 * LCD is disabled, keep BIOS settings if internal/external display
21 * haven't been enabled explicitly
22 * (Thomas J. Moore <dark@mama.indstate.edu>)
23 *
24 * 0.3.3
25 * - Porting over to new fbdev api. (jsimmons)
26 *
27 * 0.3.2
28 * - got rid of all floating point (dok)
29 *
30 * 0.3.1
31 * - added module license (dok)
32 *
33 * 0.3
34 * - hardware accelerated clear and move for 2200 and above (dok)
35 * - maximum allowed dotclock is handled now (dok)
36 *
37 * 0.2.1
38 * - correct panning after X usage (dok)
39 * - added module and kernel parameters (dok)
40 * - no stretching if external display is enabled (dok)
41 *
42 * 0.2
43 * - initial version (dok)
44 *
45 *
46 * TODO
47 * - ioctl for internal/external switching
48 * - blanking
49 * - 32bit depth support, maybe impossible
50 * - disable pan-on-sync, need specs
51 *
52 * BUGS
53 * - white margin on bootup like with tdfxfb (colormap problem?)
54 *
55 */
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/kernel.h>
59#include <linux/errno.h>
60#include <linux/string.h>
61#include <linux/mm.h>
1da177e4
LT		 62#include <linux/slab.h>
63#include <linux/delay.h>
64#include <linux/fb.h>
65#include <linux/pci.h>
66#include <linux/init.h>
67#ifdef CONFIG_TOSHIBA
68#include <linux/toshiba.h>
1da177e4
LT		 69#endif
70
71#include <asm/io.h>
72#include <asm/irq.h>
73#include <asm/pgtable.h>
74#include <asm/system.h>
1da177e4
LT		 75
76#ifdef CONFIG_MTRR
77#include <asm/mtrr.h>
78#endif
79
80#include <video/vga.h>
81#include <video/neomagic.h>
82
83#define NEOFB_VERSION "0.4.2"
84
85/* --------------------------------------------------------------------- */
86
87static int internal;
88static int external;
89static int libretto;
90static int nostretch;
91static int nopciburst;
92static char *mode_option __devinitdata = NULL;
93
94#ifdef MODULE
95
96MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@convergence.de>");
97MODULE_LICENSE("GPL");
98MODULE_DESCRIPTION("FBDev driver for NeoMagic PCI Chips");
99module_param(internal, bool, 0);
100MODULE_PARM_DESC(internal, "Enable output on internal LCD Display.");
101module_param(external, bool, 0);
102MODULE_PARM_DESC(external, "Enable output on external CRT.");
103module_param(libretto, bool, 0);
104MODULE_PARM_DESC(libretto, "Force Libretto 100/110 800x480 LCD.");
105module_param(nostretch, bool, 0);
106MODULE_PARM_DESC(nostretch,
107 "Disable stretching of modes smaller than LCD.");
108module_param(nopciburst, bool, 0);
109MODULE_PARM_DESC(nopciburst, "Disable PCI burst mode.");
110module_param(mode_option, charp, 0);
111MODULE_PARM_DESC(mode_option, "Preferred video mode ('640x480-8@60', etc)");
112
113#endif
114
115
116/* --------------------------------------------------------------------- */
117
118static biosMode bios8[] = {
119 {320, 240, 0x40},
120 {300, 400, 0x42},
121 {640, 400, 0x20},
122 {640, 480, 0x21},
123 {800, 600, 0x23},
124 {1024, 768, 0x25},
125};
126
127static biosMode bios16[] = {
128 {320, 200, 0x2e},
129 {320, 240, 0x41},
130 {300, 400, 0x43},
131 {640, 480, 0x31},
132 {800, 600, 0x34},
133 {1024, 768, 0x37},
134};
135
136static biosMode bios24[] = {
137 {640, 480, 0x32},
138 {800, 600, 0x35},
139 {1024, 768, 0x38}
140};
141
142#ifdef NO_32BIT_SUPPORT_YET
143/* FIXME: guessed values, wrong */
144static biosMode bios32[] = {
145 {640, 480, 0x33},
146 {800, 600, 0x36},
147 {1024, 768, 0x39}
148};
149#endif
150
151static inline void write_le32(int regindex, u32 val, const struct neofb_par *par)
152{
153 writel(val, par->neo2200 + par->cursorOff + regindex);
154}
155
156static int neoFindMode(int xres, int yres, int depth)
157{
158 int xres_s;
159 int i, size;
160 biosMode *mode;
161
162 switch (depth) {
163 case 8:
d1ae418e 164 size = ARRAY_SIZE(bios8);
1da177e4
LT		 165 mode = bios8;
166 break;
167 case 16:
d1ae418e 168 size = ARRAY_SIZE(bios16);
1da177e4
LT		 169 mode = bios16;
170 break;
171 case 24:
d1ae418e 172 size = ARRAY_SIZE(bios24);
1da177e4
LT		 173 mode = bios24;
174 break;
175#ifdef NO_32BIT_SUPPORT_YET
176 case 32:
d1ae418e 177 size = ARRAY_SIZE(bios32);
1da177e4
LT		 178 mode = bios32;
179 break;
180#endif
181 default:
182 return 0;
183 }
184
185 for (i = 0; i < size; i++) {
186 if (xres <= mode[i].x_res) {
187 xres_s = mode[i].x_res;
188 for (; i < size; i++) {
189 if (mode[i].x_res != xres_s)
190 return mode[i - 1].mode;
191 if (yres <= mode[i].y_res)
192 return mode[i].mode;
193 }
194 }
195 }
196 return mode[size - 1].mode;
197}
198
199/*
200 * neoCalcVCLK --
201 *
202 * Determine the closest clock frequency to the one requested.
203 */
1da177e4
LT		 204#define MAX_N 127
205#define MAX_D 31
206#define MAX_F 1
207
208static void neoCalcVCLK(const struct fb_info *info,
209 struct neofb_par *par, long freq)
210{
211 int n, d, f;
212 int n_best = 0, d_best = 0, f_best = 0;
7fc80b7b 213 long f_best_diff = 0x7ffff;
1da177e4
LT		 214
215 for (f = 0; f <= MAX_F; f++)
7fc80b7b
KH		 216 for (d = 0; d <= MAX_D; d++)
217 for (n = 0; n <= MAX_N; n++) {
218 long f_out;
219 long f_diff;
220
221 f_out = ((14318 * (n + 1)) / (d + 1)) >> f;
222 f_diff = abs(f_out - freq);
223 if (f_diff <= f_best_diff) {
1da177e4
LT		 224 f_best_diff = f_diff;
225 n_best = n;
226 d_best = d;
227 f_best = f;
228 }
7fc80b7b
KH		 229 if (f_out > freq)
230 break;
1da177e4
LT		 231 }
232
233 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
234 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
235 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
236 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
237 /* NOT_DONE: We are trying the full range of the 2200 clock.
238 We should be able to try n up to 2047 */
239 par->VCLK3NumeratorLow = n_best;
240 par->VCLK3NumeratorHigh = (f_best << 7);
241 } else
242 par->VCLK3NumeratorLow = n_best | (f_best << 7);
243
244 par->VCLK3Denominator = d_best;
245
246#ifdef NEOFB_DEBUG
7fc80b7b
KH		 247 printk(KERN_DEBUG "neoVCLK: f:%ld NumLow=%d NumHi=%d Den=%d Df=%ld\n",
248 freq,
1da177e4
LT		 249 par->VCLK3NumeratorLow,
250 par->VCLK3NumeratorHigh,
7fc80b7b 251 par->VCLK3Denominator, f_best_diff);
1da177e4
LT		 252#endif
253}
254
255/*
256 * vgaHWInit --
257 * Handle the initialization, etc. of a screen.
258 * Return FALSE on failure.
259 */
260
261static int vgaHWInit(const struct fb_var_screeninfo *var,
c6b044d6 262 struct neofb_par *par)
1da177e4 263{
c6b044d6
KH		 264 int hsync_end = var->xres + var->right_margin + var->hsync_len;
265 int htotal = (hsync_end + var->left_margin) >> 3;
266 int vsync_start = var->yres + var->lower_margin;
267 int vsync_end = vsync_start + var->vsync_len;
268 int vtotal = vsync_end + var->upper_margin;
269
1da177e4
LT		 270 par->MiscOutReg = 0x23;
271
c6b044d6 272 if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
1da177e4
LT		 273 par->MiscOutReg |= 0x40;
274
c6b044d6 275 if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
1da177e4
LT		 276 par->MiscOutReg |= 0x80;
277
278 /*
279 * Time Sequencer
280 */
281 par->Sequencer[0] = 0x00;
282 par->Sequencer[1] = 0x01;
283 par->Sequencer[2] = 0x0F;
284 par->Sequencer[3] = 0x00; /* Font select */
285 par->Sequencer[4] = 0x0E; /* Misc */
286
287 /*
288 * CRTC Controller
289 */
c6b044d6
KH		 290 par->CRTC[0] = htotal - 5;
291 par->CRTC[1] = (var->xres >> 3) - 1;
292 par->CRTC[2] = (var->xres >> 3) - 1;
293 par->CRTC[3] = ((htotal - 1) & 0x1F) | 0x80;
294 par->CRTC[4] = ((var->xres + var->right_margin) >> 3);
295 par->CRTC[5] = (((htotal - 1) & 0x20) << 2)
296 | (((hsync_end >> 3)) & 0x1F);
297 par->CRTC[6] = (vtotal - 2) & 0xFF;
298 par->CRTC[7] = (((vtotal - 2) & 0x100) >> 8)
299 | (((var->yres - 1) & 0x100) >> 7)
300 | ((vsync_start & 0x100) >> 6)
301 | (((var->yres - 1) & 0x100) >> 5)
302 | 0x10 | (((vtotal - 2) & 0x200) >> 4)
303 | (((var->yres - 1) & 0x200) >> 3)
304 | ((vsync_start & 0x200) >> 2);
1da177e4 305 par->CRTC[8] = 0x00;
c6b044d6 306 par->CRTC[9] = (((var->yres - 1) & 0x200) >> 4) | 0x40;
1da177e4 307
c6b044d6 308 if (var->vmode & FB_VMODE_DOUBLE)
1da177e4
LT		 309 par->CRTC[9] |= 0x80;
310
311 par->CRTC[10] = 0x00;
312 par->CRTC[11] = 0x00;
313 par->CRTC[12] = 0x00;
314 par->CRTC[13] = 0x00;
315 par->CRTC[14] = 0x00;
316 par->CRTC[15] = 0x00;
c6b044d6
KH		 317 par->CRTC[16] = vsync_start & 0xFF;
318 par->CRTC[17] = (vsync_end & 0x0F) | 0x20;
319 par->CRTC[18] = (var->yres - 1) & 0xFF;
1da177e4
LT		 320 par->CRTC[19] = var->xres_virtual >> 4;
321 par->CRTC[20] = 0x00;
c6b044d6
KH		 322 par->CRTC[21] = (var->yres - 1) & 0xFF;
323 par->CRTC[22] = (vtotal - 1) & 0xFF;
1da177e4
LT		 324 par->CRTC[23] = 0xC3;
325 par->CRTC[24] = 0xFF;
326
327 /*
328 * are these unnecessary?
329 * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN | KGA_ENABLE_ON_ZERO);
330 * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN | KGA_ENABLE_ON_ZERO);
331 */
332
333 /*
334 * Graphics Display Controller
335 */
336 par->Graphics[0] = 0x00;
337 par->Graphics[1] = 0x00;
338 par->Graphics[2] = 0x00;
339 par->Graphics[3] = 0x00;
340 par->Graphics[4] = 0x00;
341 par->Graphics[5] = 0x40;
342 par->Graphics[6] = 0x05; /* only map 64k VGA memory !!!! */
343 par->Graphics[7] = 0x0F;
344 par->Graphics[8] = 0xFF;
345
346
347 par->Attribute[0] = 0x00; /* standard colormap translation */
348 par->Attribute[1] = 0x01;
349 par->Attribute[2] = 0x02;
350 par->Attribute[3] = 0x03;
351 par->Attribute[4] = 0x04;
352 par->Attribute[5] = 0x05;
353 par->Attribute[6] = 0x06;
354 par->Attribute[7] = 0x07;
355 par->Attribute[8] = 0x08;
356 par->Attribute[9] = 0x09;
357 par->Attribute[10] = 0x0A;
358 par->Attribute[11] = 0x0B;
359 par->Attribute[12] = 0x0C;
360 par->Attribute[13] = 0x0D;
361 par->Attribute[14] = 0x0E;
362 par->Attribute[15] = 0x0F;
363 par->Attribute[16] = 0x41;
364 par->Attribute[17] = 0xFF;
365 par->Attribute[18] = 0x0F;
366 par->Attribute[19] = 0x00;
367 par->Attribute[20] = 0x00;
368 return 0;
369}
370
371static void vgaHWLock(struct vgastate *state)
372{
373 /* Protect CRTC[0-7] */
374 vga_wcrt(state->vgabase, 0x11, vga_rcrt(state->vgabase, 0x11) | 0x80);
375}
376
377static void vgaHWUnlock(void)
378{
379 /* Unprotect CRTC[0-7] */
380 vga_wcrt(NULL, 0x11, vga_rcrt(NULL, 0x11) & ~0x80);
381}
382
383static void neoLock(struct vgastate *state)
384{
385 vga_wgfx(state->vgabase, 0x09, 0x00);
386 vgaHWLock(state);
387}
388
389static void neoUnlock(void)
390{
391 vgaHWUnlock();
392 vga_wgfx(NULL, 0x09, 0x26);
393}
394
395/*
396 * VGA Palette management
397 */
398static int paletteEnabled = 0;
399
400static inline void VGAenablePalette(void)
401{
402 vga_r(NULL, VGA_IS1_RC);
403 vga_w(NULL, VGA_ATT_W, 0x00);
404 paletteEnabled = 1;
405}
406
407static inline void VGAdisablePalette(void)
408{
409 vga_r(NULL, VGA_IS1_RC);
410 vga_w(NULL, VGA_ATT_W, 0x20);
411 paletteEnabled = 0;
412}
413
414static inline void VGAwATTR(u8 index, u8 value)
415{
416 if (paletteEnabled)
417 index &= ~0x20;
418 else
419 index |= 0x20;
420
421 vga_r(NULL, VGA_IS1_RC);
422 vga_wattr(NULL, index, value);
423}
424
425static void vgaHWProtect(int on)
426{
427 unsigned char tmp;
428
0716a8ea 429 tmp = vga_rseq(NULL, 0x01);
1da177e4
LT		 430 if (on) {
431 /*
432 * Turn off screen and disable sequencer.
433 */
1da177e4
LT		 434 vga_wseq(NULL, 0x00, 0x01); /* Synchronous Reset */
435 vga_wseq(NULL, 0x01, tmp | 0x20); /* disable the display */
436
437 VGAenablePalette();
438 } else {
439 /*
440 * Reenable sequencer, then turn on screen.
441 */
1da177e4
LT		 442 vga_wseq(NULL, 0x01, tmp & ~0x20); /* reenable display */
443 vga_wseq(NULL, 0x00, 0x03); /* clear synchronousreset */
444
445 VGAdisablePalette();
446 }
447}
448
449static void vgaHWRestore(const struct fb_info *info,
450 const struct neofb_par *par)
451{
452 int i;
453
454 vga_w(NULL, VGA_MIS_W, par->MiscOutReg);
455
456 for (i = 1; i < 5; i++)
457 vga_wseq(NULL, i, par->Sequencer[i]);
458
459 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or CRTC[17] */
460 vga_wcrt(NULL, 17, par->CRTC[17] & ~0x80);
461
462 for (i = 0; i < 25; i++)
463 vga_wcrt(NULL, i, par->CRTC[i]);
464
465 for (i = 0; i < 9; i++)
466 vga_wgfx(NULL, i, par->Graphics[i]);
467
468 VGAenablePalette();
469
470 for (i = 0; i < 21; i++)
471 VGAwATTR(i, par->Attribute[i]);
472
473 VGAdisablePalette();
474}
475
476
477/* -------------------- Hardware specific routines ------------------------- */
478
479/*
480 * Hardware Acceleration for Neo2200+
481 */
482static inline int neo2200_sync(struct fb_info *info)
483{
9f19bc56 484 struct neofb_par *par = info->par;
1da177e4 485
1ca6b62f
KH		 486 while (readl(&par->neo2200->bltStat) & 1)
487 cpu_relax();
1da177e4
LT		 488 return 0;
489}
490
491static inline void neo2200_wait_fifo(struct fb_info *info,
492 int requested_fifo_space)
493{
494 // ndev->neo.waitfifo_calls++;
495 // ndev->neo.waitfifo_sum += requested_fifo_space;
496
497 /* FIXME: does not work
498 if (neo_fifo_space < requested_fifo_space)
499 {
500 neo_fifo_waitcycles++;
501
502 while (1)
503 {
504 neo_fifo_space = (neo2200->bltStat >> 8);
505 if (neo_fifo_space >= requested_fifo_space)
506 break;
507 }
508 }
509 else
510 {
511 neo_fifo_cache_hits++;
512 }
513
514 neo_fifo_space -= requested_fifo_space;
515 */
516
517 neo2200_sync(info);
518}
519
520static inline void neo2200_accel_init(struct fb_info *info,
521 struct fb_var_screeninfo *var)
522{
9f19bc56 523 struct neofb_par *par = info->par;
1da177e4
LT		 524 Neo2200 __iomem *neo2200 = par->neo2200;
525 u32 bltMod, pitch;
526
527 neo2200_sync(info);
528
529 switch (var->bits_per_pixel) {
530 case 8:
531 bltMod = NEO_MODE1_DEPTH8;
532 pitch = var->xres_virtual;
533 break;
534 case 15:
535 case 16:
536 bltMod = NEO_MODE1_DEPTH16;
537 pitch = var->xres_virtual * 2;
538 break;
539 case 24:
540 bltMod = NEO_MODE1_DEPTH24;
541 pitch = var->xres_virtual * 3;
542 break;
543 default:
544 printk(KERN_ERR
545 "neofb: neo2200_accel_init: unexpected bits per pixel!\n");
546 return;
547 }
548
549 writel(bltMod << 16, &neo2200->bltStat);
550 writel((pitch << 16) | pitch, &neo2200->pitch);
551}
552
553/* --------------------------------------------------------------------- */
554
555static int
556neofb_open(struct fb_info *info, int user)
557{
9f19bc56 558 struct neofb_par *par = info->par;
1da177e4 559
c4f28e54
JS		 560 mutex_lock(&par->open_lock);
561 if (!par->ref_count) {
1da177e4
LT		 562 memset(&par->state, 0, sizeof(struct vgastate));
563 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
564 save_vga(&par->state);
565 }
c4f28e54
JS		 566 par->ref_count++;
567 mutex_unlock(&par->open_lock);
568
1da177e4
LT		 569 return 0;
570}
571
572static int
573neofb_release(struct fb_info *info, int user)
574{
9f19bc56 575 struct neofb_par *par = info->par;
1da177e4 576
c4f28e54
JS		 577 mutex_lock(&par->open_lock);
578 if (!par->ref_count) {
579 mutex_unlock(&par->open_lock);
1da177e4 580 return -EINVAL;
c4f28e54
JS		 581 }
582 if (par->ref_count == 1) {
1da177e4
LT		 583 restore_vga(&par->state);
584 }
c4f28e54
JS		 585 par->ref_count--;
586 mutex_unlock(&par->open_lock);
587
1da177e4
LT		 588 return 0;
589}
590
591static int
592neofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
593{
9f19bc56 594 struct neofb_par *par = info->par;
1da177e4
LT		 595 int memlen, vramlen;
596 int mode_ok = 0;
597
598 DBG("neofb_check_var");
599
1ca6b62f 600 if (PICOS2KHZ(var->pixclock) > par->maxClock)
1da177e4
LT		 601 return -EINVAL;
602
1da177e4
LT		 603 /* Is the mode larger than the LCD panel? */
604 if (par->internal_display &&
605 ((var->xres > par->NeoPanelWidth) ||
606 (var->yres > par->NeoPanelHeight))) {
607 printk(KERN_INFO
608 "Mode (%dx%d) larger than the LCD panel (%dx%d)\n",
609 var->xres, var->yres, par->NeoPanelWidth,
610 par->NeoPanelHeight);
611 return -EINVAL;
612 }
613
614 /* Is the mode one of the acceptable sizes? */
615 if (!par->internal_display)
616 mode_ok = 1;
617 else {
618 switch (var->xres) {
619 case 1280:
620 if (var->yres == 1024)
621 mode_ok = 1;
622 break;
623 case 1024:
624 if (var->yres == 768)
625 mode_ok = 1;
626 break;
627 case 800:
628 if (var->yres == (par->libretto ? 480 : 600))
629 mode_ok = 1;
630 break;
631 case 640:
632 if (var->yres == 480)
633 mode_ok = 1;
634 break;
635 }
636 }
637
638 if (!mode_ok) {
639 printk(KERN_INFO
640 "Mode (%dx%d) won't display properly on LCD\n",
641 var->xres, var->yres);
642 return -EINVAL;
643 }
644
645 var->red.msb_right = 0;
646 var->green.msb_right = 0;
647 var->blue.msb_right = 0;
41988d6e 648 var->transp.msb_right = 0;
1da177e4 649
0716a8ea
KH		 650 var->transp.offset = 0;
651 var->transp.length = 0;
1da177e4
LT		 652 switch (var->bits_per_pixel) {
653 case 8: /* PSEUDOCOLOUR, 256 */
1da177e4
LT		 654 var->red.offset = 0;
655 var->red.length = 8;
656 var->green.offset = 0;
657 var->green.length = 8;
658 var->blue.offset = 0;
659 var->blue.length = 8;
660 break;
661
662 case 16: /* DIRECTCOLOUR, 64k */
1da177e4
LT		 663 var->red.offset = 11;
664 var->red.length = 5;
665 var->green.offset = 5;
666 var->green.length = 6;
667 var->blue.offset = 0;
668 var->blue.length = 5;
669 break;
670
671 case 24: /* TRUECOLOUR, 16m */
1da177e4
LT		 672 var->red.offset = 16;
673 var->red.length = 8;
674 var->green.offset = 8;
675 var->green.length = 8;
676 var->blue.offset = 0;
677 var->blue.length = 8;
678 break;
679
680#ifdef NO_32BIT_SUPPORT_YET
681 case 32: /* TRUECOLOUR, 16m */
682 var->transp.offset = 24;
683 var->transp.length = 8;
684 var->red.offset = 16;
685 var->red.length = 8;
686 var->green.offset = 8;
687 var->green.length = 8;
688 var->blue.offset = 0;
689 var->blue.length = 8;
690 break;
691#endif
692 default:
693 printk(KERN_WARNING "neofb: no support for %dbpp\n",
694 var->bits_per_pixel);
695 return -EINVAL;
696 }
697
698 vramlen = info->fix.smem_len;
699 if (vramlen > 4 * 1024 * 1024)
700 vramlen = 4 * 1024 * 1024;
701
1da177e4
LT		 702 if (var->xres_virtual < var->xres)
703 var->xres_virtual = var->xres;
704
705 memlen = var->xres_virtual * var->bits_per_pixel * var->yres_virtual >> 3;
706
707 if (memlen > vramlen) {
708 var->yres_virtual = vramlen * 8 / (var->xres_virtual *
709 var->bits_per_pixel);
710 memlen = var->xres_virtual * var->bits_per_pixel *
711 var->yres_virtual / 8;
712 }
713
714 /* we must round yres/xres down, we already rounded y/xres_virtual up
715 if it was possible. We should return -EINVAL, but I disagree */
716 if (var->yres_virtual < var->yres)
717 var->yres = var->yres_virtual;
1da177e4
LT		 718 if (var->xoffset + var->xres > var->xres_virtual)
719 var->xoffset = var->xres_virtual - var->xres;
720 if (var->yoffset + var->yres > var->yres_virtual)
721 var->yoffset = var->yres_virtual - var->yres;
722
723 var->nonstd = 0;
724 var->height = -1;
725 var->width = -1;
726
727 if (var->bits_per_pixel >= 24 || !par->neo2200)
728 var->accel_flags &= ~FB_ACCELF_TEXT;
729 return 0;
730}
731
732static int neofb_set_par(struct fb_info *info)
733{
9f19bc56 734 struct neofb_par *par = info->par;
1da177e4
LT		 735 unsigned char temp;
736 int i, clock_hi = 0;
737 int lcd_stretch;
738 int hoffset, voffset;
c6b044d6 739 int vsync_start, vtotal;
1da177e4
LT		 740
741 DBG("neofb_set_par");
742
743 neoUnlock();
744
745 vgaHWProtect(1); /* Blank the screen */
746
c6b044d6
KH		 747 vsync_start = info->var.yres + info->var.lower_margin;
748 vtotal = vsync_start + info->var.vsync_len + info->var.upper_margin;
1da177e4
LT		 749
750 /*
751 * This will allocate the datastructure and initialize all of the
752 * generic VGA registers.
753 */
754
c6b044d6 755 if (vgaHWInit(&info->var, par))
1da177e4
LT		 756 return -EINVAL;
757
758 /*
759 * The default value assigned by vgaHW.c is 0x41, but this does
760 * not work for NeoMagic.
761 */
762 par->Attribute[16] = 0x01;
763
764 switch (info->var.bits_per_pixel) {
765 case 8:
766 par->CRTC[0x13] = info->var.xres_virtual >> 3;
767 par->ExtCRTOffset = info->var.xres_virtual >> 11;
768 par->ExtColorModeSelect = 0x11;
769 break;
770 case 16:
771 par->CRTC[0x13] = info->var.xres_virtual >> 2;
772 par->ExtCRTOffset = info->var.xres_virtual >> 10;
773 par->ExtColorModeSelect = 0x13;
774 break;
775 case 24:
776 par->CRTC[0x13] = (info->var.xres_virtual * 3) >> 3;
777 par->ExtCRTOffset = (info->var.xres_virtual * 3) >> 11;
778 par->ExtColorModeSelect = 0x14;
779 break;
780#ifdef NO_32BIT_SUPPORT_YET
781 case 32: /* FIXME: guessed values */
782 par->CRTC[0x13] = info->var.xres_virtual >> 1;
783 par->ExtCRTOffset = info->var.xres_virtual >> 9;
784 par->ExtColorModeSelect = 0x15;
785 break;
786#endif
787 default:
788 break;
789 }
790
791 par->ExtCRTDispAddr = 0x10;
792
793 /* Vertical Extension */
c6b044d6
KH		 794 par->VerticalExt = (((vtotal - 2) & 0x400) >> 10)
795 | (((info->var.yres - 1) & 0x400) >> 9)
796 | (((vsync_start) & 0x400) >> 8)
797 | (((vsync_start) & 0x400) >> 7);
1da177e4
LT		 798
799 /* Fast write bursts on unless disabled. */
800 if (par->pci_burst)
801 par->SysIfaceCntl1 = 0x30;
802 else
803 par->SysIfaceCntl1 = 0x00;
804
805 par->SysIfaceCntl2 = 0xc0; /* VESA Bios sets this to 0x80! */
806
9f672004
CT		 807 /* Initialize: by default, we want display config register to be read */
808 par->PanelDispCntlRegRead = 1;
809
1da177e4
LT		 810 /* Enable any user specified display devices. */
811 par->PanelDispCntlReg1 = 0x00;
812 if (par->internal_display)
813 par->PanelDispCntlReg1 |= 0x02;
814 if (par->external_display)
815 par->PanelDispCntlReg1 |= 0x01;
816
817 /* If the user did not specify any display devices, then... */
818 if (par->PanelDispCntlReg1 == 0x00) {
819 /* Default to internal (i.e., LCD) only. */
4836f574 820 par->PanelDispCntlReg1 = vga_rgfx(NULL, 0x20) & 0x03;
1da177e4
LT		 821 }
822
823 /* If we are using a fixed mode, then tell the chip we are. */
824 switch (info->var.xres) {
825 case 1280:
826 par->PanelDispCntlReg1 |= 0x60;
827 break;
828 case 1024:
829 par->PanelDispCntlReg1 |= 0x40;
830 break;
831 case 800:
832 par->PanelDispCntlReg1 |= 0x20;
833 break;
834 case 640:
835 default:
836 break;
837 }
838
839 /* Setup shadow register locking. */
840 switch (par->PanelDispCntlReg1 & 0x03) {
841 case 0x01: /* External CRT only mode: */
842 par->GeneralLockReg = 0x00;
843 /* We need to program the VCLK for external display only mode. */
844 par->ProgramVCLK = 1;
845 break;
846 case 0x02: /* Internal LCD only mode: */
847 case 0x03: /* Simultaneous internal/external (LCD/CRT) mode: */
848 par->GeneralLockReg = 0x01;
849 /* Don't program the VCLK when using the LCD. */
850 par->ProgramVCLK = 0;
851 break;
852 }
853
854 /*
855 * If the screen is to be stretched, turn on stretching for the
856 * various modes.
857 *
858 * OPTION_LCD_STRETCH means stretching should be turned off!
859 */
860 par->PanelDispCntlReg2 = 0x00;
861 par->PanelDispCntlReg3 = 0x00;
862
863 if (par->lcd_stretch && (par->PanelDispCntlReg1 == 0x02) && /* LCD only */
864 (info->var.xres != par->NeoPanelWidth)) {
865 switch (info->var.xres) {
866 case 320: /* Needs testing. KEM -- 24 May 98 */
867 case 400: /* Needs testing. KEM -- 24 May 98 */
868 case 640:
869 case 800:
870 case 1024:
871 lcd_stretch = 1;
872 par->PanelDispCntlReg2 |= 0xC6;
873 break;
874 default:
875 lcd_stretch = 0;
876 /* No stretching in these modes. */
877 }
878 } else
879 lcd_stretch = 0;
880
881 /*
882 * If the screen is to be centerd, turn on the centering for the
883 * various modes.
884 */
885 par->PanelVertCenterReg1 = 0x00;
886 par->PanelVertCenterReg2 = 0x00;
887 par->PanelVertCenterReg3 = 0x00;
888 par->PanelVertCenterReg4 = 0x00;
889 par->PanelVertCenterReg5 = 0x00;
890 par->PanelHorizCenterReg1 = 0x00;
891 par->PanelHorizCenterReg2 = 0x00;
892 par->PanelHorizCenterReg3 = 0x00;
893 par->PanelHorizCenterReg4 = 0x00;
894 par->PanelHorizCenterReg5 = 0x00;
895
896
897 if (par->PanelDispCntlReg1 & 0x02) {
898 if (info->var.xres == par->NeoPanelWidth) {
899 /*
900 * No centering required when the requested display width
901 * equals the panel width.
902 */
903 } else {
904 par->PanelDispCntlReg2 |= 0x01;
905 par->PanelDispCntlReg3 |= 0x10;
906
907 /* Calculate the horizontal and vertical offsets. */
908 if (!lcd_stretch) {
909 hoffset =
910 ((par->NeoPanelWidth -
911 info->var.xres) >> 4) - 1;
912 voffset =
913 ((par->NeoPanelHeight -
914 info->var.yres) >> 1) - 2;
915 } else {
916 /* Stretched modes cannot be centered. */
917 hoffset = 0;
918 voffset = 0;
919 }
920
921 switch (info->var.xres) {
922 case 320: /* Needs testing. KEM -- 24 May 98 */
923 par->PanelHorizCenterReg3 = hoffset;
924 par->PanelVertCenterReg2 = voffset;
925 break;
926 case 400: /* Needs testing. KEM -- 24 May 98 */
927 par->PanelHorizCenterReg4 = hoffset;
928 par->PanelVertCenterReg1 = voffset;
929 break;
930 case 640:
931 par->PanelHorizCenterReg1 = hoffset;
932 par->PanelVertCenterReg3 = voffset;
933 break;
934 case 800:
935 par->PanelHorizCenterReg2 = hoffset;
936 par->PanelVertCenterReg4 = voffset;
937 break;
938 case 1024:
939 par->PanelHorizCenterReg5 = hoffset;
940 par->PanelVertCenterReg5 = voffset;
941 break;
942 case 1280:
943 default:
944 /* No centering in these modes. */
945 break;
946 }
947 }
948 }
949
950 par->biosMode =
951 neoFindMode(info->var.xres, info->var.yres,
952 info->var.bits_per_pixel);
953
954 /*
955 * Calculate the VCLK that most closely matches the requested dot
956 * clock.
957 */
c6b044d6 958 neoCalcVCLK(info, par, PICOS2KHZ(info->var.pixclock));
1da177e4
LT		 959
960 /* Since we program the clocks ourselves, always use VCLK3. */
961 par->MiscOutReg |= 0x0C;
962
963 /* alread unlocked above */
964 /* BOGUS vga_wgfx(NULL, 0x09, 0x26); */
965
966 /* don't know what this is, but it's 0 from bootup anyway */
967 vga_wgfx(NULL, 0x15, 0x00);
968
969 /* was set to 0x01 by my bios in text and vesa modes */
970 vga_wgfx(NULL, 0x0A, par->GeneralLockReg);
971
972 /*
973 * The color mode needs to be set before calling vgaHWRestore
974 * to ensure the DAC is initialized properly.
975 *
976 * NOTE: Make sure we don't change bits make sure we don't change
977 * any reserved bits.
978 */
979 temp = vga_rgfx(NULL, 0x90);
980 switch (info->fix.accel) {
981 case FB_ACCEL_NEOMAGIC_NM2070:
982 temp &= 0xF0; /* Save bits 7:4 */
983 temp |= (par->ExtColorModeSelect & ~0xF0);
984 break;
985 case FB_ACCEL_NEOMAGIC_NM2090:
986 case FB_ACCEL_NEOMAGIC_NM2093:
987 case FB_ACCEL_NEOMAGIC_NM2097:
988 case FB_ACCEL_NEOMAGIC_NM2160:
989 case FB_ACCEL_NEOMAGIC_NM2200:
990 case FB_ACCEL_NEOMAGIC_NM2230:
991 case FB_ACCEL_NEOMAGIC_NM2360:
992 case FB_ACCEL_NEOMAGIC_NM2380:
993 temp &= 0x70; /* Save bits 6:4 */
994 temp |= (par->ExtColorModeSelect & ~0x70);
995 break;
996 }
997
998 vga_wgfx(NULL, 0x90, temp);
999
1000 /*
1001 * In some rare cases a lockup might occur if we don't delay
1002 * here. (Reported by Miles Lane)
1003 */
1004 //mdelay(200);
1005
1006 /*
1007 * Disable horizontal and vertical graphics and text expansions so
1008 * that vgaHWRestore works properly.
1009 */
1010 temp = vga_rgfx(NULL, 0x25);
1011 temp &= 0x39;
1012 vga_wgfx(NULL, 0x25, temp);
1013
1014 /*
1015 * Sleep for 200ms to make sure that the two operations above have
1016 * had time to take effect.
1017 */
1018 mdelay(200);
1019
1020 /*
1021 * This function handles restoring the generic VGA registers. */
1022 vgaHWRestore(info, par);
1023
1024 /* linear colormap for non palettized modes */
1025 switch (info->var.bits_per_pixel) {
1026 case 8:
1027 /* PseudoColor, 256 */
1028 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1029 break;
1030 case 16:
1031 /* TrueColor, 64k */
1032 info->fix.visual = FB_VISUAL_TRUECOLOR;
1033
1034 for (i = 0; i < 64; i++) {
1035 outb(i, 0x3c8);
1036
1037 outb(i << 1, 0x3c9);
1038 outb(i, 0x3c9);
1039 outb(i << 1, 0x3c9);
1040 }
1041 break;
1042 case 24:
1043#ifdef NO_32BIT_SUPPORT_YET
1044 case 32:
1045#endif
1046 /* TrueColor, 16m */
1047 info->fix.visual = FB_VISUAL_TRUECOLOR;
1048
1049 for (i = 0; i < 256; i++) {
1050 outb(i, 0x3c8);
1051
1052 outb(i, 0x3c9);
1053 outb(i, 0x3c9);
1054 outb(i, 0x3c9);
1055 }
1056 break;
1057 }
1058
1059 vga_wgfx(NULL, 0x0E, par->ExtCRTDispAddr);
1060 vga_wgfx(NULL, 0x0F, par->ExtCRTOffset);
1061 temp = vga_rgfx(NULL, 0x10);
1062 temp &= 0x0F; /* Save bits 3:0 */
1063 temp |= (par->SysIfaceCntl1 & ~0x0F); /* VESA Bios sets bit 1! */
1064 vga_wgfx(NULL, 0x10, temp);
1065
1066 vga_wgfx(NULL, 0x11, par->SysIfaceCntl2);
1067 vga_wgfx(NULL, 0x15, 0 /*par->SingleAddrPage */ );
1068 vga_wgfx(NULL, 0x16, 0 /*par->DualAddrPage */ );
1069
1070 temp = vga_rgfx(NULL, 0x20);
1071 switch (info->fix.accel) {
1072 case FB_ACCEL_NEOMAGIC_NM2070:
1073 temp &= 0xFC; /* Save bits 7:2 */
1074 temp |= (par->PanelDispCntlReg1 & ~0xFC);
1075 break;
1076 case FB_ACCEL_NEOMAGIC_NM2090:
1077 case FB_ACCEL_NEOMAGIC_NM2093:
1078 case FB_ACCEL_NEOMAGIC_NM2097:
1079 case FB_ACCEL_NEOMAGIC_NM2160:
1080 temp &= 0xDC; /* Save bits 7:6,4:2 */
1081 temp |= (par->PanelDispCntlReg1 & ~0xDC);
1082 break;
1083 case FB_ACCEL_NEOMAGIC_NM2200:
1084 case FB_ACCEL_NEOMAGIC_NM2230:
1085 case FB_ACCEL_NEOMAGIC_NM2360:
1086 case FB_ACCEL_NEOMAGIC_NM2380:
1087 temp &= 0x98; /* Save bits 7,4:3 */
1088 temp |= (par->PanelDispCntlReg1 & ~0x98);
1089 break;
1090 }
1091 vga_wgfx(NULL, 0x20, temp);
1092
1093 temp = vga_rgfx(NULL, 0x25);
1094 temp &= 0x38; /* Save bits 5:3 */
1095 temp |= (par->PanelDispCntlReg2 & ~0x38);
1096 vga_wgfx(NULL, 0x25, temp);
1097
1098 if (info->fix.accel != FB_ACCEL_NEOMAGIC_NM2070) {
1099 temp = vga_rgfx(NULL, 0x30);
1100 temp &= 0xEF; /* Save bits 7:5 and bits 3:0 */
1101 temp |= (par->PanelDispCntlReg3 & ~0xEF);
1102 vga_wgfx(NULL, 0x30, temp);
1103 }
1104
1105 vga_wgfx(NULL, 0x28, par->PanelVertCenterReg1);
1106 vga_wgfx(NULL, 0x29, par->PanelVertCenterReg2);
1107 vga_wgfx(NULL, 0x2a, par->PanelVertCenterReg3);
1108
1109 if (info->fix.accel != FB_ACCEL_NEOMAGIC_NM2070) {
1110 vga_wgfx(NULL, 0x32, par->PanelVertCenterReg4);
1111 vga_wgfx(NULL, 0x33, par->PanelHorizCenterReg1);
1112 vga_wgfx(NULL, 0x34, par->PanelHorizCenterReg2);
1113 vga_wgfx(NULL, 0x35, par->PanelHorizCenterReg3);
1114 }
1115
1116 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2160)
1117 vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
1118
1119 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
1120 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
1121 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
1122 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
1123 vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
1124 vga_wgfx(NULL, 0x37, par->PanelVertCenterReg5);
1125 vga_wgfx(NULL, 0x38, par->PanelHorizCenterReg5);
1126
1127 clock_hi = 1;
1128 }
1129
1130 /* Program VCLK3 if needed. */
1131 if (par->ProgramVCLK && ((vga_rgfx(NULL, 0x9B) != par->VCLK3NumeratorLow)
1132 || (vga_rgfx(NULL, 0x9F) != par->VCLK3Denominator)
1133 || (clock_hi && ((vga_rgfx(NULL, 0x8F) & ~0x0f)
1134 != (par->VCLK3NumeratorHigh &
1135 ~0x0F))))) {
1136 vga_wgfx(NULL, 0x9B, par->VCLK3NumeratorLow);
1137 if (clock_hi) {
1138 temp = vga_rgfx(NULL, 0x8F);
1139 temp &= 0x0F; /* Save bits 3:0 */
1140 temp |= (par->VCLK3NumeratorHigh & ~0x0F);
1141 vga_wgfx(NULL, 0x8F, temp);
1142 }
1143 vga_wgfx(NULL, 0x9F, par->VCLK3Denominator);
1144 }
1145
1146 if (par->biosMode)
1147 vga_wcrt(NULL, 0x23, par->biosMode);
1148
1149 vga_wgfx(NULL, 0x93, 0xc0); /* Gives 5x faster framebuffer writes !!! */
1150
1151 /* Program vertical extension register */
1152 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
1153 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
1154 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
1155 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
1156 vga_wcrt(NULL, 0x70, par->VerticalExt);
1157 }
1158
1159 vgaHWProtect(0); /* Turn on screen */
1160
1161 /* Calling this also locks offset registers required in update_start */
1162 neoLock(&par->state);
1163
1164 info->fix.line_length =
1165 info->var.xres_virtual * (info->var.bits_per_pixel >> 3);
1166
1167 switch (info->fix.accel) {
1168 case FB_ACCEL_NEOMAGIC_NM2200:
1169 case FB_ACCEL_NEOMAGIC_NM2230:
1170 case FB_ACCEL_NEOMAGIC_NM2360:
1171 case FB_ACCEL_NEOMAGIC_NM2380:
1172 neo2200_accel_init(info, &info->var);
1173 break;
1174 default:
1175 break;
1176 }
1177 return 0;
1178}
1179
d15d56f9
KH		 1180/*
1181 * Pan or Wrap the Display
1182 */
1183static int neofb_pan_display(struct fb_var_screeninfo *var,
1184 struct fb_info *info)
1da177e4 1185{
9f19bc56 1186 struct neofb_par *par = info->par;
1da177e4
LT		 1187 struct vgastate *state = &par->state;
1188 int oldExtCRTDispAddr;
1189 int Base;
1190
1191 DBG("neofb_update_start");
1192
1193 Base = (var->yoffset * var->xres_virtual + var->xoffset) >> 2;
1194 Base *= (var->bits_per_pixel + 7) / 8;
1195
1196 neoUnlock();
1197
1198 /*
1199 * These are the generic starting address registers.
1200 */
1201 vga_wcrt(state->vgabase, 0x0C, (Base & 0x00FF00) >> 8);
1202 vga_wcrt(state->vgabase, 0x0D, (Base & 0x00FF));
1203
1204 /*
1205 * Make sure we don't clobber some other bits that might already
1206 * have been set. NOTE: NM2200 has a writable bit 3, but it shouldn't
1207 * be needed.
1208 */
1209 oldExtCRTDispAddr = vga_rgfx(NULL, 0x0E);
1210 vga_wgfx(state->vgabase, 0x0E, (((Base >> 16) & 0x0f) | (oldExtCRTDispAddr & 0xf0)));
1211
1212 neoLock(state);
1da177e4 1213
1da177e4
LT		 1214 return 0;
1215}
1216
1217static int neofb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1218 u_int transp, struct fb_info *fb)
1219{
1220 if (regno >= fb->cmap.len || regno > 255)
1221 return -EINVAL;
1222
a2b7d2e9 1223 if (fb->var.bits_per_pixel <= 8) {
1da177e4
LT		 1224 outb(regno, 0x3c8);
1225
1226 outb(red >> 10, 0x3c9);
1227 outb(green >> 10, 0x3c9);
1228 outb(blue >> 10, 0x3c9);
a2b7d2e9
AD		 1229 } else if (regno < 16) {
1230 switch (fb->var.bits_per_pixel) {
1231 case 16:
1232 ((u32 *) fb->pseudo_palette)[regno] =
1da177e4
LT		 1233 ((red & 0xf800)) | ((green & 0xfc00) >> 5) |
1234 ((blue & 0xf800) >> 11);
a2b7d2e9
AD		 1235 break;
1236 case 24:
1237 ((u32 *) fb->pseudo_palette)[regno] =
1da177e4
LT		 1238 ((red & 0xff00) << 8) | ((green & 0xff00)) |
1239 ((blue & 0xff00) >> 8);
a2b7d2e9 1240 break;
1da177e4 1241#ifdef NO_32BIT_SUPPORT_YET
a2b7d2e9
AD		 1242 case 32:
1243 ((u32 *) fb->pseudo_palette)[regno] =
1da177e4
LT		 1244 ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) |
1245 ((green & 0xff00)) | ((blue & 0xff00) >> 8);
a2b7d2e9 1246 break;
1da177e4 1247#endif
a2b7d2e9
AD		 1248 default:
1249 return 1;
1250 }
1da177e4 1251 }
a2b7d2e9 1252
1da177e4
LT		 1253 return 0;
1254}
1255
1256/*
1257 * (Un)Blank the display.
1258 */
1259static int neofb_blank(int blank_mode, struct fb_info *info)
1260{
1261 /*
1262 * Blank the screen if blank_mode != 0, else unblank.
1263 * Return 0 if blanking succeeded, != 0 if un-/blanking failed due to
1264 * e.g. a video mode which doesn't support it. Implements VESA suspend
1265 * and powerdown modes for monitors, and backlight control on LCDs.
1266 * blank_mode == 0: unblanked (backlight on)
1267 * blank_mode == 1: blank (backlight on)
1268 * blank_mode == 2: suspend vsync (backlight off)
1269 * blank_mode == 3: suspend hsync (backlight off)
1270 * blank_mode == 4: powerdown (backlight off)
1271 *
1272 * wms...Enable VESA DPMS compatible powerdown mode
1273 * run "setterm -powersave powerdown" to take advantage
1274 */
9f19bc56 1275 struct neofb_par *par = info->par;
4efefd1d 1276 int seqflags, lcdflags, dpmsflags, reg, tmpdisp;
9f672004 1277
10ee39fe 1278 /*
4efefd1d
CT		 1279 * Read back the register bits related to display configuration. They might
1280 * have been changed underneath the driver via Fn key stroke.
1281 */
1282 neoUnlock();
1283 tmpdisp = vga_rgfx(NULL, 0x20) & 0x03;
1284 neoLock(&par->state);
1285
1286 /* In case we blank the screen, we want to store the possibly new
1287 * configuration in the driver. During un-blank, we re-apply this setting,
1288 * since the LCD bit will be cleared in order to switch off the backlight.
10ee39fe 1289 */
9f672004 1290 if (par->PanelDispCntlRegRead) {
4efefd1d 1291 par->PanelDispCntlReg1 = tmpdisp;
9f672004
CT		 1292 }
1293 par->PanelDispCntlRegRead = !blank_mode;
10ee39fe 1294
1da177e4
LT		 1295 switch (blank_mode) {
1296 case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */
1297 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1298 lcdflags = 0; /* LCD off */
1299 dpmsflags = NEO_GR01_SUPPRESS_HSYNC |
1300 NEO_GR01_SUPPRESS_VSYNC;
1301#ifdef CONFIG_TOSHIBA
1302 /* Do we still need this ? */
1303 /* attempt to turn off backlight on toshiba; also turns off external */
1304 {
1305 SMMRegisters regs;
1306
1307 regs.eax = 0xff00; /* HCI_SET */
1308 regs.ebx = 0x0002; /* HCI_BACKLIGHT */
1309 regs.ecx = 0x0000; /* HCI_DISABLE */
1310 tosh_smm(&regs);
1311 }
1312#endif
1313 break;
1314 case FB_BLANK_HSYNC_SUSPEND: /* hsync off */
1315 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1316 lcdflags = 0; /* LCD off */
1317 dpmsflags = NEO_GR01_SUPPRESS_HSYNC;
1318 break;
1319 case FB_BLANK_VSYNC_SUSPEND: /* vsync off */
1320 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1321 lcdflags = 0; /* LCD off */
1322 dpmsflags = NEO_GR01_SUPPRESS_VSYNC;
1323 break;
1324 case FB_BLANK_NORMAL: /* just blank screen (backlight stays on) */
1325 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
4efefd1d
CT		 1326 /*
1327 * During a blank operation with the LID shut, we might store "LCD off"
1328 * by mistake. Due to timing issues, the BIOS may switch the lights
1329 * back on, and we turn it back off once we "unblank".
1330 *
1331 * So here is an attempt to implement ">=" - if we are in the process
1332 * of unblanking, and the LCD bit is unset in the driver but set in the
1333 * register, we must keep it.
1334 */
1335 lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
10ee39fe 1336 dpmsflags = 0x00; /* no hsync/vsync suppression */
1da177e4
LT		 1337 break;
1338 case FB_BLANK_UNBLANK: /* unblank */
1339 seqflags = 0; /* Enable sequencer */
4efefd1d 1340 lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
1da177e4
LT		 1341 dpmsflags = 0x00; /* no hsync/vsync suppression */
1342#ifdef CONFIG_TOSHIBA
1343 /* Do we still need this ? */
1344 /* attempt to re-enable backlight/external on toshiba */
1345 {
1346 SMMRegisters regs;
1347
1348 regs.eax = 0xff00; /* HCI_SET */
1349 regs.ebx = 0x0002; /* HCI_BACKLIGHT */
1350 regs.ecx = 0x0001; /* HCI_ENABLE */
1351 tosh_smm(&regs);
1352 }
1353#endif
1354 break;
1355 default: /* Anything else we don't understand; return 1 to tell
1356 * fb_blank we didn't aactually do anything */
1357 return 1;
1358 }
1359
1360 neoUnlock();
1361 reg = (vga_rseq(NULL, 0x01) & ~0x20) | seqflags;
1362 vga_wseq(NULL, 0x01, reg);
1363 reg = (vga_rgfx(NULL, 0x20) & ~0x02) | lcdflags;
1364 vga_wgfx(NULL, 0x20, reg);
1365 reg = (vga_rgfx(NULL, 0x01) & ~0xF0) | 0x80 | dpmsflags;
1366 vga_wgfx(NULL, 0x01, reg);
1367 neoLock(&par->state);
1368 return 0;
1369}
1370
1371static void
1372neo2200_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1373{
9f19bc56 1374 struct neofb_par *par = info->par;
1da177e4
LT		 1375 u_long dst, rop;
1376
1377 dst = rect->dx + rect->dy * info->var.xres_virtual;
1378 rop = rect->rop ? 0x060000 : 0x0c0000;
1379
1380 neo2200_wait_fifo(info, 4);
1381
1382 /* set blt control */
1383 writel(NEO_BC3_FIFO_EN |
1384 NEO_BC0_SRC_IS_FG | NEO_BC3_SKIP_MAPPING |
1385 // NEO_BC3_DST_XY_ADDR |
1386 // NEO_BC3_SRC_XY_ADDR |
1387 rop, &par->neo2200->bltCntl);
1388
1389 switch (info->var.bits_per_pixel) {
1390 case 8:
1391 writel(rect->color, &par->neo2200->fgColor);
1392 break;
1393 case 16:
1394 case 24:
1395 writel(((u32 *) (info->pseudo_palette))[rect->color],
1396 &par->neo2200->fgColor);
1397 break;
1398 }
1399
1400 writel(dst * ((info->var.bits_per_pixel + 7) >> 3),
1401 &par->neo2200->dstStart);
1402 writel((rect->height << 16) | (rect->width & 0xffff),
1403 &par->neo2200->xyExt);
1404}
1405
1406static void
1407neo2200_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1408{
1409 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
9f19bc56 1410 struct neofb_par *par = info->par;
1da177e4
LT		 1411 u_long src, dst, bltCntl;
1412
1413 bltCntl = NEO_BC3_FIFO_EN | NEO_BC3_SKIP_MAPPING | 0x0C0000;
1414
1415 if ((dy > sy) || ((dy == sy) && (dx > sx))) {
1416 /* Start with the lower right corner */
1417 sy += (area->height - 1);
1418 dy += (area->height - 1);
1419 sx += (area->width - 1);
1420 dx += (area->width - 1);
1421
1422 bltCntl |= NEO_BC0_X_DEC | NEO_BC0_DST_Y_DEC | NEO_BC0_SRC_Y_DEC;
1423 }
1424
1425 src = sx * (info->var.bits_per_pixel >> 3) + sy*info->fix.line_length;
1426 dst = dx * (info->var.bits_per_pixel >> 3) + dy*info->fix.line_length;
1427
1428 neo2200_wait_fifo(info, 4);
1429
1430 /* set blt control */
1431 writel(bltCntl, &par->neo2200->bltCntl);
1432
1433 writel(src, &par->neo2200->srcStart);
1434 writel(dst, &par->neo2200->dstStart);
1435 writel((area->height << 16) | (area->width & 0xffff),
1436 &par->neo2200->xyExt);
1437}
1438
1439static void
1440neo2200_imageblit(struct fb_info *info, const struct fb_image *image)
1441{
9f19bc56 1442 struct neofb_par *par = info->par;
1da177e4
LT		 1443 int s_pitch = (image->width * image->depth + 7) >> 3;
1444 int scan_align = info->pixmap.scan_align - 1;
1445 int buf_align = info->pixmap.buf_align - 1;
1446 int bltCntl_flags, d_pitch, data_len;
1447
1448 // The data is padded for the hardware
1449 d_pitch = (s_pitch + scan_align) & ~scan_align;
1450 data_len = ((d_pitch * image->height) + buf_align) & ~buf_align;
1451
1452 neo2200_sync(info);
1453
1454 if (image->depth == 1) {
1455 if (info->var.bits_per_pixel == 24 && image->width < 16) {
1456 /* FIXME. There is a bug with accelerated color-expanded
1457 * transfers in 24 bit mode if the image being transferred
1458 * is less than 16 bits wide. This is due to insufficient
1459 * padding when writing the image. We need to adjust
1460 * struct fb_pixmap. Not yet done. */
1461 return cfb_imageblit(info, image);
1462 }
1463 bltCntl_flags = NEO_BC0_SRC_MONO;
1464 } else if (image->depth == info->var.bits_per_pixel) {
1465 bltCntl_flags = 0;
1466 } else {
1467 /* We don't currently support hardware acceleration if image
1468 * depth is different from display */
1469 return cfb_imageblit(info, image);
1470 }
1471
1472 switch (info->var.bits_per_pixel) {
1473 case 8:
1474 writel(image->fg_color, &par->neo2200->fgColor);
1475 writel(image->bg_color, &par->neo2200->bgColor);
1476 break;
1477 case 16:
1478 case 24:
1479 writel(((u32 *) (info->pseudo_palette))[image->fg_color],
1480 &par->neo2200->fgColor);
1481 writel(((u32 *) (info->pseudo_palette))[image->bg_color],
1482 &par->neo2200->bgColor);
1483 break;
1484 }
1485
1486 writel(NEO_BC0_SYS_TO_VID |
1487 NEO_BC3_SKIP_MAPPING | bltCntl_flags |
1488 // NEO_BC3_DST_XY_ADDR |
1489 0x0c0000, &par->neo2200->bltCntl);
1490
1491 writel(0, &par->neo2200->srcStart);
1492// par->neo2200->dstStart = (image->dy << 16) | (image->dx & 0xffff);
1493 writel(((image->dx & 0xffff) * (info->var.bits_per_pixel >> 3) +
1494 image->dy * info->fix.line_length), &par->neo2200->dstStart);
1495 writel((image->height << 16) | (image->width & 0xffff),
1496 &par->neo2200->xyExt);
1497
1498 memcpy_toio(par->mmio_vbase + 0x100000, image->data, data_len);
1499}
1500
1501static void
1502neofb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1503{
1504 switch (info->fix.accel) {
1505 case FB_ACCEL_NEOMAGIC_NM2200:
1506 case FB_ACCEL_NEOMAGIC_NM2230:
1507 case FB_ACCEL_NEOMAGIC_NM2360:
1508 case FB_ACCEL_NEOMAGIC_NM2380:
1509 neo2200_fillrect(info, rect);
1510 break;
1511 default:
1512 cfb_fillrect(info, rect);
1513 break;
1514 }
1515}
1516
1517static void
1518neofb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1519{
1520 switch (info->fix.accel) {
1521 case FB_ACCEL_NEOMAGIC_NM2200:
1522 case FB_ACCEL_NEOMAGIC_NM2230:
1523 case FB_ACCEL_NEOMAGIC_NM2360:
1524 case FB_ACCEL_NEOMAGIC_NM2380:
1525 neo2200_copyarea(info, area);
1526 break;
1527 default:
1528 cfb_copyarea(info, area);
1529 break;
1530 }
1531}
1532
1533static void
1534neofb_imageblit(struct fb_info *info, const struct fb_image *image)
1535{
1536 switch (info->fix.accel) {
1537 case FB_ACCEL_NEOMAGIC_NM2200:
1538 case FB_ACCEL_NEOMAGIC_NM2230:
1539 case FB_ACCEL_NEOMAGIC_NM2360:
1540 case FB_ACCEL_NEOMAGIC_NM2380:
1541 neo2200_imageblit(info, image);
1542 break;
1543 default:
1544 cfb_imageblit(info, image);
1545 break;
1546 }
1547}
1548
1549static int
1550neofb_sync(struct fb_info *info)
1551{
1552 switch (info->fix.accel) {
1553 case FB_ACCEL_NEOMAGIC_NM2200:
1554 case FB_ACCEL_NEOMAGIC_NM2230:
1555 case FB_ACCEL_NEOMAGIC_NM2360:
1556 case FB_ACCEL_NEOMAGIC_NM2380:
1557 neo2200_sync(info);
1558 break;
1559 default:
1560 break;
1561 }
1562 return 0;
1563}
1564
1565/*
1566static void
1567neofb_draw_cursor(struct fb_info *info, u8 *dst, u8 *src, unsigned int width)
1568{
1569 //memset_io(info->sprite.addr, 0xff, 1);
1570}
1571
1572static int
1573neofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1574{
1575 struct neofb_par *par = (struct neofb_par *) info->par;
1576
1577 * Disable cursor *
1578 write_le32(NEOREG_CURSCNTL, ~NEO_CURS_ENABLE, par);
1579
1580 if (cursor->set & FB_CUR_SETPOS) {
1581 u32 x = cursor->image.dx;
1582 u32 y = cursor->image.dy;
1583
1584 info->cursor.image.dx = x;
1585 info->cursor.image.dy = y;
1586 write_le32(NEOREG_CURSX, x, par);
1587 write_le32(NEOREG_CURSY, y, par);
1588 }
1589
1590 if (cursor->set & FB_CUR_SETSIZE) {
1591 info->cursor.image.height = cursor->image.height;
1592 info->cursor.image.width = cursor->image.width;
1593 }
1594
1595 if (cursor->set & FB_CUR_SETHOT)
1596 info->cursor.hot = cursor->hot;
1597
1598 if (cursor->set & FB_CUR_SETCMAP) {
1599 if (cursor->image.depth == 1) {
1600 u32 fg = cursor->image.fg_color;
1601 u32 bg = cursor->image.bg_color;
1602
1603 info->cursor.image.fg_color = fg;
1604 info->cursor.image.bg_color = bg;
1605
1606 fg = ((fg & 0xff0000) >> 16) | ((fg & 0xff) << 16) | (fg & 0xff00);
1607 bg = ((bg & 0xff0000) >> 16) | ((bg & 0xff) << 16) | (bg & 0xff00);
1608 write_le32(NEOREG_CURSFGCOLOR, fg, par);
1609 write_le32(NEOREG_CURSBGCOLOR, bg, par);
1610 }
1611 }
1612
1613 if (cursor->set & FB_CUR_SETSHAPE)
1614 fb_load_cursor_image(info);
1615
1616 if (info->cursor.enable)
1617 write_le32(NEOREG_CURSCNTL, NEO_CURS_ENABLE, par);
1618 return 0;
1619}
1620*/
1621
1622static struct fb_ops neofb_ops = {
1623 .owner = THIS_MODULE,
1624 .fb_open = neofb_open,
1625 .fb_release = neofb_release,
1626 .fb_check_var = neofb_check_var,
1627 .fb_set_par = neofb_set_par,
1628 .fb_setcolreg = neofb_setcolreg,
1629 .fb_pan_display = neofb_pan_display,
1630 .fb_blank = neofb_blank,
1631 .fb_sync = neofb_sync,
1632 .fb_fillrect = neofb_fillrect,
1633 .fb_copyarea = neofb_copyarea,
1634 .fb_imageblit = neofb_imageblit,
1da177e4
LT		 1635};
1636
1637/* --------------------------------------------------------------------- */
1638
1639static struct fb_videomode __devinitdata mode800x480 = {
1640 .xres = 800,
1641 .yres = 480,
1642 .pixclock = 25000,
1643 .left_margin = 88,
1644 .right_margin = 40,
1645 .upper_margin = 23,
1646 .lower_margin = 1,
1647 .hsync_len = 128,
1648 .vsync_len = 4,
1649 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1650 .vmode = FB_VMODE_NONINTERLACED
1651};
1652
1653static int __devinit neo_map_mmio(struct fb_info *info,
1654 struct pci_dev *dev)
1655{
9f19bc56 1656 struct neofb_par *par = info->par;
1da177e4
LT		 1657
1658 DBG("neo_map_mmio");
1659
1660 switch (info->fix.accel) {
1661 case FB_ACCEL_NEOMAGIC_NM2070:
1662 info->fix.mmio_start = pci_resource_start(dev, 0)+
1663 0x100000;
1664 break;
1665 case FB_ACCEL_NEOMAGIC_NM2090:
1666 case FB_ACCEL_NEOMAGIC_NM2093:
1667 info->fix.mmio_start = pci_resource_start(dev, 0)+
1668 0x200000;
1669 break;
1670 case FB_ACCEL_NEOMAGIC_NM2160:
1671 case FB_ACCEL_NEOMAGIC_NM2097:
1672 case FB_ACCEL_NEOMAGIC_NM2200:
1673 case FB_ACCEL_NEOMAGIC_NM2230:
1674 case FB_ACCEL_NEOMAGIC_NM2360:
1675 case FB_ACCEL_NEOMAGIC_NM2380:
1676 info->fix.mmio_start = pci_resource_start(dev, 1);
1677 break;
1678 default:
1679 info->fix.mmio_start = pci_resource_start(dev, 0);
1680 }
1681 info->fix.mmio_len = MMIO_SIZE;
1682
1683 if (!request_mem_region
1684 (info->fix.mmio_start, MMIO_SIZE, "memory mapped I/O")) {
1685 printk("neofb: memory mapped IO in use\n");
1686 return -EBUSY;
1687 }
1688
1689 par->mmio_vbase = ioremap(info->fix.mmio_start, MMIO_SIZE);
1690 if (!par->mmio_vbase) {
1691 printk("neofb: unable to map memory mapped IO\n");
1692 release_mem_region(info->fix.mmio_start,
1693 info->fix.mmio_len);
1694 return -ENOMEM;
1695 } else
1696 printk(KERN_INFO "neofb: mapped io at %p\n",
1697 par->mmio_vbase);
1698 return 0;
1699}
1700
1701static void neo_unmap_mmio(struct fb_info *info)
1702{
9f19bc56 1703 struct neofb_par *par = info->par;
1da177e4
LT		 1704
1705 DBG("neo_unmap_mmio");
1706
1707 iounmap(par->mmio_vbase);
1708 par->mmio_vbase = NULL;
1709
1710 release_mem_region(info->fix.mmio_start,
1711 info->fix.mmio_len);
1712}
1713
1714static int __devinit neo_map_video(struct fb_info *info,
1715 struct pci_dev *dev, int video_len)
1716{
1717 //unsigned long addr;
1718
1719 DBG("neo_map_video");
1720
1721 info->fix.smem_start = pci_resource_start(dev, 0);
1722 info->fix.smem_len = video_len;
1723
1724 if (!request_mem_region(info->fix.smem_start, info->fix.smem_len,
1725 "frame buffer")) {
1726 printk("neofb: frame buffer in use\n");
1727 return -EBUSY;
1728 }
1729
1730 info->screen_base =
1731 ioremap(info->fix.smem_start, info->fix.smem_len);
1732 if (!info->screen_base) {
1733 printk("neofb: unable to map screen memory\n");
1734 release_mem_region(info->fix.smem_start,
1735 info->fix.smem_len);
1736 return -ENOMEM;
1737 } else
1738 printk(KERN_INFO "neofb: mapped framebuffer at %p\n",
1739 info->screen_base);
1740
1741#ifdef CONFIG_MTRR
1742 ((struct neofb_par *)(info->par))->mtrr =
1743 mtrr_add(info->fix.smem_start, pci_resource_len(dev, 0),
1744 MTRR_TYPE_WRCOMB, 1);
1745#endif
1746
1747 /* Clear framebuffer, it's all white in memory after boot */
1748 memset_io(info->screen_base, 0, info->fix.smem_len);
1749
1750 /* Allocate Cursor drawing pad.
1751 info->fix.smem_len -= PAGE_SIZE;
1752 addr = info->fix.smem_start + info->fix.smem_len;
1753 write_le32(NEOREG_CURSMEMPOS, ((0x000f & (addr >> 10)) << 8) |
1754 ((0x0ff0 & (addr >> 10)) >> 4), par);
1755 addr = (unsigned long) info->screen_base + info->fix.smem_len;
1756 info->sprite.addr = (u8 *) addr; */
1757 return 0;
1758}
1759
1760static void neo_unmap_video(struct fb_info *info)
1761{
1762 DBG("neo_unmap_video");
1763
1764#ifdef CONFIG_MTRR
1765 {
9f19bc56 1766 struct neofb_par *par = info->par;
1da177e4
LT		 1767
1768 mtrr_del(par->mtrr, info->fix.smem_start,
1769 info->fix.smem_len);
1770 }
1771#endif
1772 iounmap(info->screen_base);
1773 info->screen_base = NULL;
1774
1775 release_mem_region(info->fix.smem_start,
1776 info->fix.smem_len);
1777}
1778
1779static int __devinit neo_scan_monitor(struct fb_info *info)
1780{
9f19bc56 1781 struct neofb_par *par = info->par;
1da177e4
LT		 1782 unsigned char type, display;
1783 int w;
1784
1785 // Eventually we will have i2c support.
1786 info->monspecs.modedb = kmalloc(sizeof(struct fb_videomode), GFP_KERNEL);
1787 if (!info->monspecs.modedb)
1788 return -ENOMEM;
1789 info->monspecs.modedb_len = 1;
1790
1791 /* Determine the panel type */
1792 vga_wgfx(NULL, 0x09, 0x26);
1793 type = vga_rgfx(NULL, 0x21);
1794 display = vga_rgfx(NULL, 0x20);
1795 if (!par->internal_display && !par->external_display) {
1796 par->internal_display = display & 2 || !(display & 3) ? 1 : 0;
1797 par->external_display = display & 1;
1798 printk (KERN_INFO "Autodetected %s display\n",
1799 par->internal_display && par->external_display ? "simultaneous" :
1800 par->internal_display ? "internal" : "external");
1801 }
1802
1803 /* Determine panel width -- used in NeoValidMode. */
1804 w = vga_rgfx(NULL, 0x20);
1805 vga_wgfx(NULL, 0x09, 0x00);
1806 switch ((w & 0x18) >> 3) {
1807 case 0x00:
1808 // 640x480@60
1809 par->NeoPanelWidth = 640;
1810 par->NeoPanelHeight = 480;
1811 memcpy(info->monspecs.modedb, &vesa_modes[3], sizeof(struct fb_videomode));
1812 break;
1813 case 0x01:
1814 par->NeoPanelWidth = 800;
1815 if (par->libretto) {
1816 par->NeoPanelHeight = 480;
1817 memcpy(info->monspecs.modedb, &mode800x480, sizeof(struct fb_videomode));
1818 } else {
1819 // 800x600@60
1820 par->NeoPanelHeight = 600;
1821 memcpy(info->monspecs.modedb, &vesa_modes[8], sizeof(struct fb_videomode));
1822 }
1823 break;
1824 case 0x02:
1825 // 1024x768@60
1826 par->NeoPanelWidth = 1024;
1827 par->NeoPanelHeight = 768;
1828 memcpy(info->monspecs.modedb, &vesa_modes[13], sizeof(struct fb_videomode));
1829 break;
1830 case 0x03:
1831 /* 1280x1024@60 panel support needs to be added */
1832#ifdef NOT_DONE
1833 par->NeoPanelWidth = 1280;
1834 par->NeoPanelHeight = 1024;
1835 memcpy(info->monspecs.modedb, &vesa_modes[20], sizeof(struct fb_videomode));
1836 break;
1837#else
1838 printk(KERN_ERR
1839 "neofb: Only 640x480, 800x600/480 and 1024x768 panels are currently supported\n");
1840 return -1;
1841#endif
1842 default:
1843 // 640x480@60
1844 par->NeoPanelWidth = 640;
1845 par->NeoPanelHeight = 480;
1846 memcpy(info->monspecs.modedb, &vesa_modes[3], sizeof(struct fb_videomode));
1847 break;
1848 }
1849
1850 printk(KERN_INFO "Panel is a %dx%d %s %s display\n",
1851 par->NeoPanelWidth,
1852 par->NeoPanelHeight,
1853 (type & 0x02) ? "color" : "monochrome",
1854 (type & 0x10) ? "TFT" : "dual scan");
1855 return 0;
1856}
1857
1858static int __devinit neo_init_hw(struct fb_info *info)
1859{
9f19bc56 1860 struct neofb_par *par = info->par;
1da177e4
LT		 1861 int videoRam = 896;
1862 int maxClock = 65000;
1863 int CursorMem = 1024;
1864 int CursorOff = 0x100;
1da177e4
LT		 1865
1866 DBG("neo_init_hw");
1867
1868 neoUnlock();
1869
1870#if 0
1871 printk(KERN_DEBUG "--- Neo extended register dump ---\n");
1872 for (int w = 0; w < 0x85; w++)
1873 printk(KERN_DEBUG "CR %p: %p\n", (void *) w,
4971bb70 1874 (void *) vga_rcrt(NULL, w));
1da177e4
LT		 1875 for (int w = 0; w < 0xC7; w++)
1876 printk(KERN_DEBUG "GR %p: %p\n", (void *) w,
1877 (void *) vga_rgfx(NULL, w));
1878#endif
1879 switch (info->fix.accel) {
1880 case FB_ACCEL_NEOMAGIC_NM2070:
1881 videoRam = 896;
1882 maxClock = 65000;
1da177e4
LT		 1883 break;
1884 case FB_ACCEL_NEOMAGIC_NM2090:
1885 case FB_ACCEL_NEOMAGIC_NM2093:
1da177e4
LT		 1886 case FB_ACCEL_NEOMAGIC_NM2097:
1887 videoRam = 1152;
1888 maxClock = 80000;
1da177e4
LT		 1889 break;
1890 case FB_ACCEL_NEOMAGIC_NM2160:
1891 videoRam = 2048;
1892 maxClock = 90000;
1da177e4
LT		 1893 break;
1894 case FB_ACCEL_NEOMAGIC_NM2200:
1895 videoRam = 2560;
1896 maxClock = 110000;
1da177e4
LT		 1897 break;
1898 case FB_ACCEL_NEOMAGIC_NM2230:
1899 videoRam = 3008;
1900 maxClock = 110000;
1da177e4
LT		 1901 break;
1902 case FB_ACCEL_NEOMAGIC_NM2360:
1903 videoRam = 4096;
1904 maxClock = 110000;
1da177e4
LT		 1905 break;
1906 case FB_ACCEL_NEOMAGIC_NM2380:
1907 videoRam = 6144;
1908 maxClock = 110000;
1ca6b62f
KH		 1909 break;
1910 }
1911 switch (info->fix.accel) {
1912 case FB_ACCEL_NEOMAGIC_NM2070:
1913 case FB_ACCEL_NEOMAGIC_NM2090:
1914 case FB_ACCEL_NEOMAGIC_NM2093:
1915 CursorMem = 2048;
1916 CursorOff = 0x100;
1917 break;
1918 case FB_ACCEL_NEOMAGIC_NM2097:
1919 case FB_ACCEL_NEOMAGIC_NM2160:
1920 CursorMem = 1024;
1921 CursorOff = 0x100;
1922 break;
1923 case FB_ACCEL_NEOMAGIC_NM2200:
1924 case FB_ACCEL_NEOMAGIC_NM2230:
1925 case FB_ACCEL_NEOMAGIC_NM2360:
1926 case FB_ACCEL_NEOMAGIC_NM2380:
1da177e4
LT		 1927 CursorMem = 1024;
1928 CursorOff = 0x1000;
1da177e4
LT		 1929
1930 par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
1931 break;
1932 }
1933/*
1934 info->sprite.size = CursorMem;
1935 info->sprite.scan_align = 1;
1936 info->sprite.buf_align = 1;
1937 info->sprite.flags = FB_PIXMAP_IO;
1938 info->sprite.outbuf = neofb_draw_cursor;
1939*/
1940 par->maxClock = maxClock;
1941 par->cursorOff = CursorOff;
1ca6b62f 1942 return videoRam * 1024;
1da177e4
LT		 1943}
1944
1945
1946static struct fb_info *__devinit neo_alloc_fb_info(struct pci_dev *dev, const struct
1947 pci_device_id *id)
1948{
1949 struct fb_info *info;
1950 struct neofb_par *par;
1951
9f19bc56 1952 info = framebuffer_alloc(sizeof(struct neofb_par), &dev->dev);
1da177e4
LT		 1953
1954 if (!info)
1955 return NULL;
1956
1957 par = info->par;
1958
1959 info->fix.accel = id->driver_data;
1960
c4f28e54 1961 mutex_init(&par->open_lock);
1da177e4
LT		 1962 par->pci_burst = !nopciburst;
1963 par->lcd_stretch = !nostretch;
1964 par->libretto = libretto;
1965
1966 par->internal_display = internal;
1967 par->external_display = external;
1968 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1969
1970 switch (info->fix.accel) {
1971 case FB_ACCEL_NEOMAGIC_NM2070:
0e904549
AM		 1972 snprintf(info->fix.id, sizeof(info->fix.id),
1973 "MagicGraph 128");
1da177e4
LT		 1974 break;
1975 case FB_ACCEL_NEOMAGIC_NM2090:
0e904549
AM		 1976 snprintf(info->fix.id, sizeof(info->fix.id),
1977 "MagicGraph 128V");
1da177e4
LT		 1978 break;
1979 case FB_ACCEL_NEOMAGIC_NM2093:
0e904549
AM		 1980 snprintf(info->fix.id, sizeof(info->fix.id),
1981 "MagicGraph 128ZV");
1da177e4
LT		 1982 break;
1983 case FB_ACCEL_NEOMAGIC_NM2097:
0e904549
AM		 1984 snprintf(info->fix.id, sizeof(info->fix.id),
1985 "MagicGraph 128ZV+");
1da177e4
LT		 1986 break;
1987 case FB_ACCEL_NEOMAGIC_NM2160:
0e904549
AM		 1988 snprintf(info->fix.id, sizeof(info->fix.id),
1989 "MagicGraph 128XD");
1da177e4
LT		 1990 break;
1991 case FB_ACCEL_NEOMAGIC_NM2200:
0e904549
AM		 1992 snprintf(info->fix.id, sizeof(info->fix.id),
1993 "MagicGraph 256AV");
1da177e4
LT		 1994 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
1995 FBINFO_HWACCEL_COPYAREA |
1996 FBINFO_HWACCEL_FILLRECT;
1997 break;
1998 case FB_ACCEL_NEOMAGIC_NM2230:
0e904549
AM		 1999 snprintf(info->fix.id, sizeof(info->fix.id),
2000 "MagicGraph 256AV+");
1da177e4
LT		 2001 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2002 FBINFO_HWACCEL_COPYAREA |
2003 FBINFO_HWACCEL_FILLRECT;
2004 break;
2005 case FB_ACCEL_NEOMAGIC_NM2360:
0e904549
AM		 2006 snprintf(info->fix.id, sizeof(info->fix.id),
2007 "MagicGraph 256ZX");
1da177e4
LT		 2008 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2009 FBINFO_HWACCEL_COPYAREA |
2010 FBINFO_HWACCEL_FILLRECT;
2011 break;
2012 case FB_ACCEL_NEOMAGIC_NM2380:
0e904549
AM		 2013 snprintf(info->fix.id, sizeof(info->fix.id),
2014 "MagicGraph 256XL+");
1da177e4
LT		 2015 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2016 FBINFO_HWACCEL_COPYAREA |
2017 FBINFO_HWACCEL_FILLRECT;
2018 break;
2019 }
2020
2021 info->fix.type = FB_TYPE_PACKED_PIXELS;
2022 info->fix.type_aux = 0;
2023 info->fix.xpanstep = 0;
2024 info->fix.ypanstep = 4;
2025 info->fix.ywrapstep = 0;
2026 info->fix.accel = id->driver_data;
2027
2028 info->fbops = &neofb_ops;
9f19bc56 2029 info->pseudo_palette = par->palette;
1da177e4
LT		 2030 return info;
2031}
2032
2033static void neo_free_fb_info(struct fb_info *info)
2034{
2035 if (info) {
2036 /*
2037 * Free the colourmap
2038 */
2039 fb_dealloc_cmap(&info->cmap);
2040 framebuffer_release(info);
2041 }
2042}
2043
2044/* --------------------------------------------------------------------- */
2045
2046static int __devinit neofb_probe(struct pci_dev *dev,
2047 const struct pci_device_id *id)
2048{
2049 struct fb_info *info;
2050 u_int h_sync, v_sync;
2051 int video_len, err;
2052
2053 DBG("neofb_probe");
2054
2055 err = pci_enable_device(dev);
2056 if (err)
2057 return err;
2058
2059 err = -ENOMEM;
2060 info = neo_alloc_fb_info(dev, id);
2061 if (!info)
2062 return err;
2063
2064 err = neo_map_mmio(info, dev);
2065 if (err)
2066 goto err_map_mmio;
2067
2068 err = neo_scan_monitor(info);
2069 if (err)
2070 goto err_scan_monitor;
2071
2072 video_len = neo_init_hw(info);
2073 if (video_len < 0) {
2074 err = video_len;
2075 goto err_init_hw;
2076 }
2077
2078 err = neo_map_video(info, dev, video_len);
2079 if (err)
2080 goto err_init_hw;
2081
2082 if (!fb_find_mode(&info->var, info, mode_option, NULL, 0,
2083 info->monspecs.modedb, 16)) {
2084 printk(KERN_ERR "neofb: Unable to find usable video mode.\n");
2085 goto err_map_video;
2086 }
2087
2088 /*
2089 * Calculate the hsync and vsync frequencies. Note that
2090 * we split the 1e12 constant up so that we can preserve
2091 * the precision and fit the results into 32-bit registers.
2092 * (1953125000 * 512 = 1e12)
2093 */
2094 h_sync = 1953125000 / info->var.pixclock;
2095 h_sync =
2096 h_sync * 512 / (info->var.xres + info->var.left_margin +
2097 info->var.right_margin + info->var.hsync_len);
2098 v_sync =
2099 h_sync / (info->var.yres + info->var.upper_margin +
2100 info->var.lower_margin + info->var.vsync_len);
2101
2102 printk(KERN_INFO "neofb v" NEOFB_VERSION
2103 ": %dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2104 info->fix.smem_len >> 10, info->var.xres,
2105 info->var.yres, h_sync / 1000, h_sync % 1000, v_sync);
2106
2107 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
2108 goto err_map_video;
2109
2110 err = register_framebuffer(info);
2111 if (err < 0)
2112 goto err_reg_fb;
2113
2114 printk(KERN_INFO "fb%d: %s frame buffer device\n",
2115 info->node, info->fix.id);
2116
2117 /*
2118 * Our driver data
2119 */
2120 pci_set_drvdata(dev, info);
2121 return 0;
2122
2123err_reg_fb:
2124 fb_dealloc_cmap(&info->cmap);
2125err_map_video:
2126 neo_unmap_video(info);
2127err_init_hw:
2128 fb_destroy_modedb(info->monspecs.modedb);
2129err_scan_monitor:
2130 neo_unmap_mmio(info);
2131err_map_mmio:
2132 neo_free_fb_info(info);
2133 return err;
2134}
2135
2136static void __devexit neofb_remove(struct pci_dev *dev)
2137{
2138 struct fb_info *info = pci_get_drvdata(dev);
2139
2140 DBG("neofb_remove");
2141
2142 if (info) {
2143 /*
2144 * If unregister_framebuffer fails, then
2145 * we will be leaving hooks that could cause
2146 * oopsen laying around.
2147 */
2148 if (unregister_framebuffer(info))
2149 printk(KERN_WARNING
2150 "neofb: danger danger! Oopsen imminent!\n");
2151
2152 neo_unmap_video(info);
2153 fb_destroy_modedb(info->monspecs.modedb);
2154 neo_unmap_mmio(info);
2155 neo_free_fb_info(info);
2156
2157 /*
2158 * Ensure that the driver data is no longer
2159 * valid.
2160 */
2161 pci_set_drvdata(dev, NULL);
2162 }
2163}
2164
2165static struct pci_device_id neofb_devices[] = {
2166 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2070,
2167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2070},
2168
2169 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2090,
2170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2090},
2171
2172 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2093,
2173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2093},
2174
2175 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2097,
2176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2097},
2177
2178 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2160,
2179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2160},
2180
2181 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2200,
2182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2200},
2183
2184 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2230,
2185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2230},
2186
2187 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2360,
2188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2360},
2189
2190 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2380,
2191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2380},
2192
2193 {0, 0, 0, 0, 0, 0, 0}
2194};
2195
2196MODULE_DEVICE_TABLE(pci, neofb_devices);
2197
2198static struct pci_driver neofb_driver = {
2199 .name = "neofb",
2200 .id_table = neofb_devices,
2201 .probe = neofb_probe,
2202 .remove = __devexit_p(neofb_remove)
2203};
2204
2205/* ************************* init in-kernel code ************************** */
2206
2207#ifndef MODULE
2208static int __init neofb_setup(char *options)
2209{
2210 char *this_opt;
2211
2212 DBG("neofb_setup");
2213
2214 if (!options || !*options)
2215 return 0;
2216
2217 while ((this_opt = strsep(&options, ",")) != NULL) {
2218 if (!*this_opt)
2219 continue;
2220
2221 if (!strncmp(this_opt, "internal", 8))
2222 internal = 1;
2223 else if (!strncmp(this_opt, "external", 8))
2224 external = 1;
2225 else if (!strncmp(this_opt, "nostretch", 9))
2226 nostretch = 1;
2227 else if (!strncmp(this_opt, "nopciburst", 10))
2228 nopciburst = 1;
2229 else if (!strncmp(this_opt, "libretto", 8))
2230 libretto = 1;
2231 else
2232 mode_option = this_opt;
2233 }
2234 return 0;
2235}
2236#endif /* MODULE */
2237
2238static int __init neofb_init(void)
2239{
2240#ifndef MODULE
2241 char *option = NULL;
2242
2243 if (fb_get_options("neofb", &option))
2244 return -ENODEV;
2245 neofb_setup(option);
2246#endif
2247 return pci_register_driver(&neofb_driver);
2248}
2249
2250module_init(neofb_init);
2251
2252#ifdef MODULE
2253static void __exit neofb_exit(void)
2254{
2255 pci_unregister_driver(&neofb_driver);
2256}
2257
2258module_exit(neofb_exit);
2259#endif /* MODULE */
kernel source for telekom puls (alcatel/mediatek)