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ARM: mxs: move display timing configurations into device tree
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / mxsfb.c
CommitLineData
f0a523b5
SH		 1/*
2 * Copyright (C) 2010 Juergen Beisert, Pengutronix
3 *
4 * This code is based on:
5 * Author: Vitaly Wool <vital@embeddedalley.com>
6 *
7 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
8 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#define DRIVER_NAME "mxsfb"
21
22/**
23 * @file
24 * @brief LCDIF driver for i.MX23 and i.MX28
25 *
26 * The LCDIF support four modes of operation
27 * - MPU interface (to drive smart displays) -> not supported yet
28 * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet
29 * - Dotclock interface (to drive LC displays with RGB data and sync signals)
30 * - DVI (to drive ITU-R BT656) -> not supported yet
31 *
32 * This driver depends on a correct setup of the pins used for this purpose
33 * (platform specific).
34 *
35 * For the developer: Don't forget to set the data bus width to the display
36 * in the imx_fb_videomode structure. You will else end up with ugly colours.
37 * If you fight against jitter you can vary the clock delay. This is a feature
38 * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give
39 * the required value in the imx_fb_videomode structure.
40 */
41
36893674 42#include <linux/module.h>
f0a523b5 43#include <linux/kernel.h>
73fc610f
SG		 44#include <linux/of_device.h>
45#include <linux/of_gpio.h>
66940653 46#include <video/of_display_timing.h>
f0a523b5
SH		 47#include <linux/platform_device.h>
48#include <linux/clk.h>
49#include <linux/dma-mapping.h>
50#include <linux/io.h>
fe233b9d 51#include <linux/pinctrl/consumer.h>
ce4409b5 52#include <linux/mxsfb.h>
66940653 53#include <video/videomode.h>
f0a523b5
SH		 54
55#define REG_SET 4
56#define REG_CLR 8
57
58#define LCDC_CTRL 0x00
59#define LCDC_CTRL1 0x10
60#define LCDC_V4_CTRL2 0x20
61#define LCDC_V3_TRANSFER_COUNT 0x20
62#define LCDC_V4_TRANSFER_COUNT 0x30
63#define LCDC_V4_CUR_BUF 0x40
64#define LCDC_V4_NEXT_BUF 0x50
65#define LCDC_V3_CUR_BUF 0x30
66#define LCDC_V3_NEXT_BUF 0x40
67#define LCDC_TIMING 0x60
68#define LCDC_VDCTRL0 0x70
69#define LCDC_VDCTRL1 0x80
70#define LCDC_VDCTRL2 0x90
71#define LCDC_VDCTRL3 0xa0
72#define LCDC_VDCTRL4 0xb0
73#define LCDC_DVICTRL0 0xc0
74#define LCDC_DVICTRL1 0xd0
75#define LCDC_DVICTRL2 0xe0
76#define LCDC_DVICTRL3 0xf0
77#define LCDC_DVICTRL4 0x100
78#define LCDC_V4_DATA 0x180
79#define LCDC_V3_DATA 0x1b0
80#define LCDC_V4_DEBUG0 0x1d0
81#define LCDC_V3_DEBUG0 0x1f0
82
83#define CTRL_SFTRST (1 << 31)
84#define CTRL_CLKGATE (1 << 30)
85#define CTRL_BYPASS_COUNT (1 << 19)
86#define CTRL_VSYNC_MODE (1 << 18)
87#define CTRL_DOTCLK_MODE (1 << 17)
88#define CTRL_DATA_SELECT (1 << 16)
89#define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10)
90#define CTRL_GET_BUS_WIDTH(x) (((x) >> 10) & 0x3)
91#define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8)
92#define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3)
93#define CTRL_MASTER (1 << 5)
94#define CTRL_DF16 (1 << 3)
95#define CTRL_DF18 (1 << 2)
96#define CTRL_DF24 (1 << 1)
97#define CTRL_RUN (1 << 0)
98
99#define CTRL1_FIFO_CLEAR (1 << 21)
100#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16)
101#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf)
102
103#define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16)
104#define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff)
105#define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff)
106#define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff)
107
108
109#define VDCTRL0_ENABLE_PRESENT (1 << 28)
110#define VDCTRL0_VSYNC_ACT_HIGH (1 << 27)
111#define VDCTRL0_HSYNC_ACT_HIGH (1 << 26)
112#define VDCTRL0_DOTCLK_ACT_FAILING (1 << 25)
113#define VDCTRL0_ENABLE_ACT_HIGH (1 << 24)
114#define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
115#define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
116#define VDCTRL0_HALF_LINE (1 << 19)
117#define VDCTRL0_HALF_LINE_MODE (1 << 18)
118#define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
119#define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
120
121#define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff)
122#define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff)
123
124#define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
125#define VDCTRL3_VSYNC_ONLY (1 << 28)
126#define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16)
127#define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff)
128#define SET_VERT_WAIT_CNT(x) ((x) & 0xffff)
129#define GET_VERT_WAIT_CNT(x) ((x) & 0xffff)
130
131#define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */
132#define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */
133#define VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
134#define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff)
135
136#define DEBUG0_HSYNC (1 < 26)
137#define DEBUG0_VSYNC (1 < 25)
138
139#define MIN_XRES 120
140#define MIN_YRES 120
141
142#define RED 0
143#define GREEN 1
144#define BLUE 2
145#define TRANSP 3
146
147enum mxsfb_devtype {
148 MXSFB_V3,
149 MXSFB_V4,
150};
151
152/* CPU dependent register offsets */
153struct mxsfb_devdata {
154 unsigned transfer_count;
155 unsigned cur_buf;
156 unsigned next_buf;
157 unsigned debug0;
158 unsigned hs_wdth_mask;
159 unsigned hs_wdth_shift;
160 unsigned ipversion;
161};
162
163struct mxsfb_info {
164 struct fb_info fb_info;
165 struct platform_device *pdev;
166 struct clk *clk;
167 void __iomem *base; /* registers */
168 unsigned allocated_size;
169 int enabled;
170 unsigned ld_intf_width;
171 unsigned dotclk_delay;
172 const struct mxsfb_devdata *devdata;
6a15075e 173 u32 sync;
f0a523b5
SH		 174};
175
176#define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
177#define mxsfb_is_v4(host) (host->devdata->ipversion == 4)
178
179static const struct mxsfb_devdata mxsfb_devdata[] = {
180 [MXSFB_V3] = {
181 .transfer_count = LCDC_V3_TRANSFER_COUNT,
182 .cur_buf = LCDC_V3_CUR_BUF,
183 .next_buf = LCDC_V3_NEXT_BUF,
184 .debug0 = LCDC_V3_DEBUG0,
185 .hs_wdth_mask = 0xff,
186 .hs_wdth_shift = 24,
187 .ipversion = 3,
188 },
189 [MXSFB_V4] = {
190 .transfer_count = LCDC_V4_TRANSFER_COUNT,
191 .cur_buf = LCDC_V4_CUR_BUF,
192 .next_buf = LCDC_V4_NEXT_BUF,
193 .debug0 = LCDC_V4_DEBUG0,
194 .hs_wdth_mask = 0x3fff,
195 .hs_wdth_shift = 18,
196 .ipversion = 4,
197 },
198};
199
200#define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info))
201
202/* mask and shift depends on architecture */
203static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
204{
205 return (val & host->devdata->hs_wdth_mask) <<
206 host->devdata->hs_wdth_shift;
207}
208
209static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
210{
211 return (val >> host->devdata->hs_wdth_shift) &
212 host->devdata->hs_wdth_mask;
213}
214
215static const struct fb_bitfield def_rgb565[] = {
216 [RED] = {
217 .offset = 11,
218 .length = 5,
219 },
220 [GREEN] = {
221 .offset = 5,
222 .length = 6,
223 },
224 [BLUE] = {
225 .offset = 0,
226 .length = 5,
227 },
228 [TRANSP] = { /* no support for transparency */
229 .length = 0,
230 }
231};
232
233static const struct fb_bitfield def_rgb666[] = {
234 [RED] = {
235 .offset = 16,
236 .length = 6,
237 },
238 [GREEN] = {
239 .offset = 8,
240 .length = 6,
241 },
242 [BLUE] = {
243 .offset = 0,
244 .length = 6,
245 },
246 [TRANSP] = { /* no support for transparency */
247 .length = 0,
248 }
249};
250
251static const struct fb_bitfield def_rgb888[] = {
252 [RED] = {
253 .offset = 16,
254 .length = 8,
255 },
256 [GREEN] = {
257 .offset = 8,
258 .length = 8,
259 },
260 [BLUE] = {
261 .offset = 0,
262 .length = 8,
263 },
264 [TRANSP] = { /* no support for transparency */
265 .length = 0,
266 }
267};
268
269static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
270{
271 chan &= 0xffff;
272 chan >>= 16 - bf->length;
273 return chan << bf->offset;
274}
275
276static int mxsfb_check_var(struct fb_var_screeninfo *var,
277 struct fb_info *fb_info)
278{
279 struct mxsfb_info *host = to_imxfb_host(fb_info);
280 const struct fb_bitfield *rgb = NULL;
281
282 if (var->xres < MIN_XRES)
283 var->xres = MIN_XRES;
284 if (var->yres < MIN_YRES)
285 var->yres = MIN_YRES;
286
287 var->xres_virtual = var->xres;
288
289 var->yres_virtual = var->yres;
290
291 switch (var->bits_per_pixel) {
292 case 16:
293 /* always expect RGB 565 */
294 rgb = def_rgb565;
295 break;
296 case 32:
297 switch (host->ld_intf_width) {
298 case STMLCDIF_8BIT:
299 pr_debug("Unsupported LCD bus width mapping\n");
300 break;
301 case STMLCDIF_16BIT:
302 case STMLCDIF_18BIT:
303 /* 24 bit to 18 bit mapping */
304 rgb = def_rgb666;
305 break;
306 case STMLCDIF_24BIT:
307 /* real 24 bit */
308 rgb = def_rgb888;
309 break;
310 }
311 break;
312 default:
313 pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel);
314 return -EINVAL;
315 }
316
317 /*
318 * Copy the RGB parameters for this display
319 * from the machine specific parameters.
320 */
321 var->red = rgb[RED];
322 var->green = rgb[GREEN];
323 var->blue = rgb[BLUE];
324 var->transp = rgb[TRANSP];
325
326 return 0;
327}
328
329static void mxsfb_enable_controller(struct fb_info *fb_info)
330{
331 struct mxsfb_info *host = to_imxfb_host(fb_info);
332 u32 reg;
333
334 dev_dbg(&host->pdev->dev, "%s\n", __func__);
335
ca4c22d3 336 clk_prepare_enable(host->clk);
f0a523b5
SH		 337 clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
338
339 /* if it was disabled, re-enable the mode again */
340 writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
341
342 /* enable the SYNC signals first, then the DMA engine */
343 reg = readl(host->base + LCDC_VDCTRL4);
344 reg |= VDCTRL4_SYNC_SIGNALS_ON;
345 writel(reg, host->base + LCDC_VDCTRL4);
346
347 writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
348
349 host->enabled = 1;
350}
351
352static void mxsfb_disable_controller(struct fb_info *fb_info)
353{
354 struct mxsfb_info *host = to_imxfb_host(fb_info);
355 unsigned loop;
356 u32 reg;
357
358 dev_dbg(&host->pdev->dev, "%s\n", __func__);
359
360 /*
361 * Even if we disable the controller here, it will still continue
362 * until its FIFOs are running out of data
363 */
364 writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR);
365
366 loop = 1000;
367 while (loop) {
368 reg = readl(host->base + LCDC_CTRL);
369 if (!(reg & CTRL_RUN))
370 break;
371 loop--;
372 }
373
6c1ecba8
LW		 374 reg = readl(host->base + LCDC_VDCTRL4);
375 writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
f0a523b5 376
ca4c22d3 377 clk_disable_unprepare(host->clk);
f0a523b5
SH		 378
379 host->enabled = 0;
380}
381
382static int mxsfb_set_par(struct fb_info *fb_info)
383{
384 struct mxsfb_info *host = to_imxfb_host(fb_info);
385 u32 ctrl, vdctrl0, vdctrl4;
386 int line_size, fb_size;
387 int reenable = 0;
388
389 line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
390 fb_size = fb_info->var.yres_virtual * line_size;
391
392 if (fb_size > fb_info->fix.smem_len)
393 return -ENOMEM;
394
395 fb_info->fix.line_length = line_size;
396
397 /*
398 * It seems, you can't re-program the controller if it is still running.
399 * This may lead into shifted pictures (FIFO issue?).
400 * So, first stop the controller and drain its FIFOs
401 */
402 if (host->enabled) {
403 reenable = 1;
404 mxsfb_disable_controller(fb_info);
405 }
406
407 /* clear the FIFOs */
408 writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
409
410 ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
6eab04a8 411 CTRL_SET_BUS_WIDTH(host->ld_intf_width);
f0a523b5
SH		 412
413 switch (fb_info->var.bits_per_pixel) {
414 case 16:
415 dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n");
416 ctrl |= CTRL_SET_WORD_LENGTH(0);
417 writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1);
418 break;
419 case 32:
420 dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n");
421 ctrl |= CTRL_SET_WORD_LENGTH(3);
422 switch (host->ld_intf_width) {
423 case STMLCDIF_8BIT:
424 dev_dbg(&host->pdev->dev,
425 "Unsupported LCD bus width mapping\n");
426 return -EINVAL;
427 case STMLCDIF_16BIT:
428 case STMLCDIF_18BIT:
429 /* 24 bit to 18 bit mapping */
430 ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
431 * each colour component
432 */
433 break;
434 case STMLCDIF_24BIT:
435 /* real 24 bit */
436 break;
437 }
438 /* do not use packed pixels = one pixel per word instead */
439 writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
440 break;
441 default:
442 dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n",
443 fb_info->var.bits_per_pixel);
444 return -EINVAL;
445 }
446
447 writel(ctrl, host->base + LCDC_CTRL);
448
449 writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) |
450 TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres),
451 host->base + host->devdata->transfer_count);
452
453 vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* always in DOTCLOCK mode */
454 VDCTRL0_VSYNC_PERIOD_UNIT |
455 VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
456 VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len);
457 if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT)
458 vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
459 if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
460 vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
6a15075e 461 if (host->sync & MXSFB_SYNC_DATA_ENABLE_HIGH_ACT)
f0a523b5 462 vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
6a15075e 463 if (host->sync & MXSFB_SYNC_DOTCLK_FAILING_ACT)
f0a523b5
SH		 464 vdctrl0 |= VDCTRL0_DOTCLK_ACT_FAILING;
465
466 writel(vdctrl0, host->base + LCDC_VDCTRL0);
467
468 /* frame length in lines */
469 writel(fb_info->var.upper_margin + fb_info->var.vsync_len +
470 fb_info->var.lower_margin + fb_info->var.yres,
471 host->base + LCDC_VDCTRL1);
472
473 /* line length in units of clocks or pixels */
474 writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) |
475 VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin +
476 fb_info->var.hsync_len + fb_info->var.right_margin +
477 fb_info->var.xres),
478 host->base + LCDC_VDCTRL2);
479
480 writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin +
481 fb_info->var.hsync_len) |
482 SET_VERT_WAIT_CNT(fb_info->var.upper_margin +
483 fb_info->var.vsync_len),
484 host->base + LCDC_VDCTRL3);
485
486 vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres);
487 if (mxsfb_is_v4(host))
488 vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay);
489 writel(vdctrl4, host->base + LCDC_VDCTRL4);
490
491 writel(fb_info->fix.smem_start +
492 fb_info->fix.line_length * fb_info->var.yoffset,
493 host->base + host->devdata->next_buf);
494
495 if (reenable)
496 mxsfb_enable_controller(fb_info);
497
498 return 0;
499}
500
501static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
502 u_int transp, struct fb_info *fb_info)
503{
504 unsigned int val;
505 int ret = -EINVAL;
506
507 /*
508 * If greyscale is true, then we convert the RGB value
509 * to greyscale no matter what visual we are using.
510 */
511 if (fb_info->var.grayscale)
512 red = green = blue = (19595 * red + 38470 * green +
513 7471 * blue) >> 16;
514
515 switch (fb_info->fix.visual) {
516 case FB_VISUAL_TRUECOLOR:
517 /*
518 * 12 or 16-bit True Colour. We encode the RGB value
519 * according to the RGB bitfield information.
520 */
521 if (regno < 16) {
522 u32 *pal = fb_info->pseudo_palette;
523
524 val = chan_to_field(red, &fb_info->var.red);
525 val |= chan_to_field(green, &fb_info->var.green);
526 val |= chan_to_field(blue, &fb_info->var.blue);
527
528 pal[regno] = val;
529 ret = 0;
530 }
531 break;
532
533 case FB_VISUAL_STATIC_PSEUDOCOLOR:
534 case FB_VISUAL_PSEUDOCOLOR:
535 break;
536 }
537
538 return ret;
539}
540
541static int mxsfb_blank(int blank, struct fb_info *fb_info)
542{
543 struct mxsfb_info *host = to_imxfb_host(fb_info);
544
545 switch (blank) {
546 case FB_BLANK_POWERDOWN:
547 case FB_BLANK_VSYNC_SUSPEND:
548 case FB_BLANK_HSYNC_SUSPEND:
549 case FB_BLANK_NORMAL:
550 if (host->enabled)
551 mxsfb_disable_controller(fb_info);
552 break;
553
554 case FB_BLANK_UNBLANK:
555 if (!host->enabled)
556 mxsfb_enable_controller(fb_info);
557 break;
558 }
559 return 0;
560}
561
562static int mxsfb_pan_display(struct fb_var_screeninfo *var,
563 struct fb_info *fb_info)
564{
565 struct mxsfb_info *host = to_imxfb_host(fb_info);
566 unsigned offset;
567
568 if (var->xoffset != 0)
569 return -EINVAL;
570
571 offset = fb_info->fix.line_length * var->yoffset;
572
573 /* update on next VSYNC */
574 writel(fb_info->fix.smem_start + offset,
575 host->base + host->devdata->next_buf);
576
577 return 0;
578}
579
580static struct fb_ops mxsfb_ops = {
581 .owner = THIS_MODULE,
582 .fb_check_var = mxsfb_check_var,
583 .fb_set_par = mxsfb_set_par,
584 .fb_setcolreg = mxsfb_setcolreg,
585 .fb_blank = mxsfb_blank,
586 .fb_pan_display = mxsfb_pan_display,
587 .fb_fillrect = cfb_fillrect,
588 .fb_copyarea = cfb_copyarea,
589 .fb_imageblit = cfb_imageblit,
590};
591
48c68c4f 592static int mxsfb_restore_mode(struct mxsfb_info *host)
f0a523b5
SH		 593{
594 struct fb_info *fb_info = &host->fb_info;
595 unsigned line_count;
596 unsigned period;
597 unsigned long pa, fbsize;
598 int bits_per_pixel, ofs;
599 u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
600 struct fb_videomode vmode;
601
602 /* Only restore the mode when the controller is running */
603 ctrl = readl(host->base + LCDC_CTRL);
604 if (!(ctrl & CTRL_RUN))
605 return -EINVAL;
606
607 vdctrl0 = readl(host->base + LCDC_VDCTRL0);
608 vdctrl2 = readl(host->base + LCDC_VDCTRL2);
609 vdctrl3 = readl(host->base + LCDC_VDCTRL3);
610 vdctrl4 = readl(host->base + LCDC_VDCTRL4);
611
612 transfer_count = readl(host->base + host->devdata->transfer_count);
613
614 vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
615 vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
616
617 switch (CTRL_GET_WORD_LENGTH(ctrl)) {
618 case 0:
619 bits_per_pixel = 16;
620 break;
621 case 3:
622 bits_per_pixel = 32;
623 case 1:
624 default:
625 return -EINVAL;
626 }
627
628 fb_info->var.bits_per_pixel = bits_per_pixel;
629
630 vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
631 vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2);
632 vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len;
633 vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len -
634 vmode.left_margin - vmode.xres;
635 vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
636 period = readl(host->base + LCDC_VDCTRL1);
637 vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len;
638 vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres;
639
640 vmode.vmode = FB_VMODE_NONINTERLACED;
641
642 vmode.sync = 0;
643 if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
644 vmode.sync |= FB_SYNC_HOR_HIGH_ACT;
645 if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
646 vmode.sync |= FB_SYNC_VERT_HIGH_ACT;
647
648 pr_debug("Reconstructed video mode:\n");
649 pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
650 vmode.xres, vmode.yres,
651 vmode.hsync_len, vmode.left_margin, vmode.right_margin,
652 vmode.vsync_len, vmode.upper_margin, vmode.lower_margin);
653 pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock));
654
655 fb_add_videomode(&vmode, &fb_info->modelist);
656
657 host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
658 host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
659
660 fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3);
661
662 pa = readl(host->base + host->devdata->cur_buf);
663 fbsize = fb_info->fix.line_length * vmode.yres;
664 if (pa < fb_info->fix.smem_start)
665 return -EINVAL;
666 if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len)
667 return -EINVAL;
668 ofs = pa - fb_info->fix.smem_start;
669 if (ofs) {
670 memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize);
671 writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf);
672 }
673
674 line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
675 fb_info->fix.ypanstep = 1;
676
ca4c22d3 677 clk_prepare_enable(host->clk);
f0a523b5
SH		 678 host->enabled = 1;
679
680 return 0;
681}
682
66940653
SG		 683static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host)
684{
685 struct fb_info *fb_info = &host->fb_info;
686 struct fb_var_screeninfo *var = &fb_info->var;
687 struct device *dev = &host->pdev->dev;
688 struct device_node *np = host->pdev->dev.of_node;
689 struct device_node *display_np;
690 struct device_node *timings_np;
691 struct display_timings *timings;
692 u32 width;
693 int i;
694 int ret = 0;
695
696 display_np = of_parse_phandle(np, "display", 0);
697 if (!display_np) {
698 dev_err(dev, "failed to find display phandle\n");
699 return -ENOENT;
700 }
701
702 ret = of_property_read_u32(display_np, "bus-width", &width);
703 if (ret < 0) {
704 dev_err(dev, "failed to get property bus-width\n");
705 goto put_display_node;
706 }
707
708 switch (width) {
709 case 8:
710 host->ld_intf_width = STMLCDIF_8BIT;
711 break;
712 case 16:
713 host->ld_intf_width = STMLCDIF_16BIT;
714 break;
715 case 18:
716 host->ld_intf_width = STMLCDIF_18BIT;
717 break;
718 case 24:
719 host->ld_intf_width = STMLCDIF_24BIT;
720 break;
721 default:
722 dev_err(dev, "invalid bus-width value\n");
723 ret = -EINVAL;
724 goto put_display_node;
725 }
726
727 ret = of_property_read_u32(display_np, "bits-per-pixel",
728 &var->bits_per_pixel);
729 if (ret < 0) {
730 dev_err(dev, "failed to get property bits-per-pixel\n");
731 goto put_display_node;
732 }
733
734 timings = of_get_display_timings(display_np);
735 if (!timings) {
736 dev_err(dev, "failed to get display timings\n");
737 ret = -ENOENT;
738 goto put_display_node;
739 }
740
741 timings_np = of_find_node_by_name(display_np,
742 "display-timings");
743 if (!timings_np) {
744 dev_err(dev, "failed to find display-timings node\n");
745 ret = -ENOENT;
746 goto put_display_node;
747 }
748
749 for (i = 0; i < of_get_child_count(timings_np); i++) {
750 struct videomode vm;
751 struct fb_videomode fb_vm;
752
753 ret = videomode_from_timing(timings, &vm, i);
754 if (ret < 0)
755 goto put_timings_node;
756 ret = fb_videomode_from_videomode(&vm, &fb_vm);
757 if (ret < 0)
758 goto put_timings_node;
759
760 if (vm.data_flags & DISPLAY_FLAGS_DE_HIGH)
761 host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
762 if (vm.data_flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
763 host->sync |= MXSFB_SYNC_DOTCLK_FAILING_ACT;
764 fb_add_videomode(&fb_vm, &fb_info->modelist);
765 }
766
767put_timings_node:
768 of_node_put(timings_np);
769put_display_node:
770 of_node_put(display_np);
771 return ret;
772}
773
48c68c4f 774static int mxsfb_init_fbinfo(struct mxsfb_info *host)
f0a523b5
SH		 775{
776 struct fb_info *fb_info = &host->fb_info;
777 struct fb_var_screeninfo *var = &fb_info->var;
778 struct mxsfb_platform_data *pdata = host->pdev->dev.platform_data;
779 dma_addr_t fb_phys;
780 void *fb_virt;
4aa02c7c 781 unsigned fb_size;
66940653 782 int ret;
f0a523b5
SH		 783
784 fb_info->fbops = &mxsfb_ops;
785 fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
786 strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
787 fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
788 fb_info->fix.ypanstep = 1;
789 fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
790 fb_info->fix.accel = FB_ACCEL_NONE;
791
66940653
SG		 792 if (pdata) {
793 host->ld_intf_width = pdata->ld_intf_width;
794 var->bits_per_pixel =
795 pdata->default_bpp ? pdata->default_bpp : 16;
796 } else {
797 ret = mxsfb_init_fbinfo_dt(host);
798 if (ret)
799 return ret;
800 }
801
f0a523b5
SH		 802 var->nonstd = 0;
803 var->activate = FB_ACTIVATE_NOW;
804 var->accel_flags = 0;
805 var->vmode = FB_VMODE_NONINTERLACED;
806
f0a523b5 807 /* Memory allocation for framebuffer */
4aa02c7c
SG		 808 fb_size = SZ_2M;
809 fb_virt = alloc_pages_exact(fb_size, GFP_DMA);
810 if (!fb_virt)
811 return -ENOMEM;
f0a523b5 812
4aa02c7c 813 fb_phys = virt_to_phys(fb_virt);
f0a523b5
SH		 814
815 fb_info->fix.smem_start = fb_phys;
816 fb_info->screen_base = fb_virt;
817 fb_info->screen_size = fb_info->fix.smem_len = fb_size;
818
819 if (mxsfb_restore_mode(host))
820 memset(fb_virt, 0, fb_size);
821
822 return 0;
823}
824
48c68c4f 825static void mxsfb_free_videomem(struct mxsfb_info *host)
f0a523b5
SH		 826{
827 struct fb_info *fb_info = &host->fb_info;
828
4aa02c7c 829 free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len);
f0a523b5
SH		 830}
831
73fc610f
SG		 832static struct platform_device_id mxsfb_devtype[] = {
833 {
834 .name = "imx23-fb",
835 .driver_data = MXSFB_V3,
836 }, {
837 .name = "imx28-fb",
838 .driver_data = MXSFB_V4,
839 }, {
840 /* sentinel */
841 }
842};
843MODULE_DEVICE_TABLE(platform, mxsfb_devtype);
844
845static const struct of_device_id mxsfb_dt_ids[] = {
846 { .compatible = "fsl,imx23-lcdif", .data = &mxsfb_devtype[0], },
847 { .compatible = "fsl,imx28-lcdif", .data = &mxsfb_devtype[1], },
848 { /* sentinel */ }
849};
850MODULE_DEVICE_TABLE(of, mxsfb_dt_ids);
851
48c68c4f 852static int mxsfb_probe(struct platform_device *pdev)
f0a523b5 853{
73fc610f
SG		 854 const struct of_device_id *of_id =
855 of_match_device(mxsfb_dt_ids, &pdev->dev);
f0a523b5
SH		 856 struct mxsfb_platform_data *pdata = pdev->dev.platform_data;
857 struct resource *res;
858 struct mxsfb_info *host;
859 struct fb_info *fb_info;
860 struct fb_modelist *modelist;
fe233b9d 861 struct pinctrl *pinctrl;
73fc610f
SG		 862 int panel_enable;
863 enum of_gpio_flags flags;
f0a523b5
SH		 864 int i, ret;
865
73fc610f
SG		 866 if (of_id)
867 pdev->id_entry = of_id->data;
868
f0a523b5
SH		 869 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
870 if (!res) {
871 dev_err(&pdev->dev, "Cannot get memory IO resource\n");
872 return -ENODEV;
873 }
874
f0a523b5
SH		 875 fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
876 if (!fb_info) {
877 dev_err(&pdev->dev, "Failed to allocate fbdev\n");
9e548579 878 return -ENOMEM;
f0a523b5
SH		 879 }
880
881 host = to_imxfb_host(fb_info);
882
9e548579
SG		 883 host->base = devm_ioremap_resource(&pdev->dev, res);
884 if (IS_ERR(host->base)) {
f0a523b5 885 dev_err(&pdev->dev, "ioremap failed\n");
9e548579
SG		 886 ret = PTR_ERR(host->base);
887 goto fb_release;
f0a523b5
SH		 888 }
889
890 host->pdev = pdev;
891 platform_set_drvdata(pdev, host);
892
893 host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
894
fe233b9d
SG		 895 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
896 if (IS_ERR(pinctrl)) {
897 ret = PTR_ERR(pinctrl);
9e548579 898 goto fb_release;
fe233b9d
SG		 899 }
900
9e548579 901 host->clk = devm_clk_get(&host->pdev->dev, NULL);
f0a523b5
SH		 902 if (IS_ERR(host->clk)) {
903 ret = PTR_ERR(host->clk);
9e548579 904 goto fb_release;
f0a523b5
SH		 905 }
906
73fc610f
SG		 907 panel_enable = of_get_named_gpio_flags(pdev->dev.of_node,
908 "panel-enable-gpios", 0, &flags);
909 if (gpio_is_valid(panel_enable)) {
910 unsigned long f = GPIOF_OUT_INIT_HIGH;
911 if (flags == OF_GPIO_ACTIVE_LOW)
912 f = GPIOF_OUT_INIT_LOW;
913 ret = devm_gpio_request_one(&pdev->dev, panel_enable,
914 f, "panel-enable");
915 if (ret) {
916 dev_err(&pdev->dev,
917 "failed to request gpio %d: %d\n",
918 panel_enable, ret);
9e548579 919 goto fb_release;
73fc610f
SG		 920 }
921 }
922
9e548579
SG		 923 fb_info->pseudo_palette = devm_kzalloc(&pdev->dev, sizeof(u32) * 16,
924 GFP_KERNEL);
f0a523b5
SH		 925 if (!fb_info->pseudo_palette) {
926 ret = -ENOMEM;
9e548579 927 goto fb_release;
f0a523b5
SH		 928 }
929
930 INIT_LIST_HEAD(&fb_info->modelist);
931
932 ret = mxsfb_init_fbinfo(host);
933 if (ret != 0)
9e548579 934 goto fb_release;
f0a523b5 935
66940653
SG		 936 if (pdata) {
937 host->sync = pdata->sync;
938 for (i = 0; i < pdata->mode_count; i++)
939 fb_add_videomode(&pdata->mode_list[i],
940 &fb_info->modelist);
941 }
f0a523b5
SH		 942
943 modelist = list_first_entry(&fb_info->modelist,
944 struct fb_modelist, list);
945 fb_videomode_to_var(&fb_info->var, &modelist->mode);
946
947 /* init the color fields */
948 mxsfb_check_var(&fb_info->var, fb_info);
949
950 platform_set_drvdata(pdev, fb_info);
951
952 ret = register_framebuffer(fb_info);
953 if (ret != 0) {
954 dev_err(&pdev->dev,"Failed to register framebuffer\n");
9e548579 955 goto fb_destroy;
f0a523b5
SH		 956 }
957
958 if (!host->enabled) {
959 writel(0, host->base + LCDC_CTRL);
960 mxsfb_set_par(fb_info);
961 mxsfb_enable_controller(fb_info);
962 }
963
964 dev_info(&pdev->dev, "initialized\n");
965
966 return 0;
967
9e548579 968fb_destroy:
f0a523b5 969 if (host->enabled)
ca4c22d3 970 clk_disable_unprepare(host->clk);
f0a523b5 971 fb_destroy_modelist(&fb_info->modelist);
9e548579 972fb_release:
f0a523b5 973 framebuffer_release(fb_info);
f0a523b5
SH		 974
975 return ret;
976}
977
48c68c4f 978static int mxsfb_remove(struct platform_device *pdev)
f0a523b5
SH		 979{
980 struct fb_info *fb_info = platform_get_drvdata(pdev);
981 struct mxsfb_info *host = to_imxfb_host(fb_info);
f0a523b5
SH		 982
983 if (host->enabled)
984 mxsfb_disable_controller(fb_info);
985
986 unregister_framebuffer(fb_info);
f0a523b5 987 mxsfb_free_videomem(host);
f0a523b5
SH		 988
989 framebuffer_release(fb_info);
f0a523b5
SH		 990
991 platform_set_drvdata(pdev, NULL);
992
993 return 0;
994}
995
d313a86d
MV		 996static void mxsfb_shutdown(struct platform_device *pdev)
997{
998 struct fb_info *fb_info = platform_get_drvdata(pdev);
999 struct mxsfb_info *host = to_imxfb_host(fb_info);
1000
1001 /*
1002 * Force stop the LCD controller as keeping it running during reboot
1003 * might interfere with the BootROM's boot mode pads sampling.
1004 */
1005 writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR);
1006}
1007
f0a523b5
SH		 1008static struct platform_driver mxsfb_driver = {
1009 .probe = mxsfb_probe,
48c68c4f 1010 .remove = mxsfb_remove,
d313a86d 1011 .shutdown = mxsfb_shutdown,
f0a523b5
SH		 1012 .id_table = mxsfb_devtype,
1013 .driver = {
1014 .name = DRIVER_NAME,
73fc610f 1015 .of_match_table = mxsfb_dt_ids,
f0a523b5
SH		 1016 },
1017};
1018
396fa99e 1019module_platform_driver(mxsfb_driver);
f0a523b5
SH		 1020
1021MODULE_DESCRIPTION("Freescale mxs framebuffer driver");
1022MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1023MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)