[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / intelfb / intelfb.h

#ifndef _INTELFB_H
#define _INTELFB_H

/* $DHD: intelfb/intelfb.h,v 1.40 2003/06/27 15:06:25 dawes Exp $ */

#include <linux/agp_backend.h>
#include <linux/fb.h>

#ifdef CONFIG_FB_INTEL_I2C
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#endif

/*** Version/name ***/
#define INTELFB_VERSION			"0.9.6"
#define INTELFB_MODULE_NAME		"intelfb"
#define SUPPORTED_CHIPSETS		"830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM/945GME/965G/965GM"


/*** Debug/feature defines ***/

#ifndef DEBUG
#define DEBUG				0
#endif

#ifndef VERBOSE
#define VERBOSE				0
#endif

#ifndef REGDUMP
#define REGDUMP				0
#endif

#ifndef DETECT_VGA_CLASS_ONLY
#define DETECT_VGA_CLASS_ONLY		1
#endif

#ifndef ALLOCATE_FOR_PANNING
#define ALLOCATE_FOR_PANNING		1
#endif

#ifndef PREFERRED_MODE
#define PREFERRED_MODE			"1024x768-32@70"
#endif

/*** hw-related values ***/

/* Resource Allocation */
#define INTELFB_FB_ACQUIRED                 1
#define INTELFB_MMIO_ACQUIRED               2

/* PCI ids for supported devices */
#define PCI_DEVICE_ID_INTEL_830M	0x3577
#define PCI_DEVICE_ID_INTEL_845G	0x2562
#define PCI_DEVICE_ID_INTEL_85XGM	0x3582
#define PCI_DEVICE_ID_INTEL_854		0x358E
#define PCI_DEVICE_ID_INTEL_865G	0x2572
#define PCI_DEVICE_ID_INTEL_915G	0x2582
#define PCI_DEVICE_ID_INTEL_915GM	0x2592
#define PCI_DEVICE_ID_INTEL_945G	0x2772
#define PCI_DEVICE_ID_INTEL_945GM	0x27A2
#define PCI_DEVICE_ID_INTEL_945GME	0x27AE
#define PCI_DEVICE_ID_INTEL_965G	0x29A2
#define PCI_DEVICE_ID_INTEL_965GM	0x2A02

/* Size of MMIO region */
#define INTEL_REG_SIZE			0x80000

#define STRIDE_ALIGNMENT		16
#define STRIDE_ALIGNMENT_I9XX		64

#define PALETTE_8_ENTRIES		256


/*** Macros ***/

/* basic arithmetic */
#define KB(x)			((x) * 1024)
#define MB(x)			((x) * 1024 * 1024)
#define BtoKB(x)		((x) / 1024)
#define BtoMB(x)		((x) / 1024 / 1024)

#define GTT_PAGE_SIZE           KB(4)

#define ROUND_UP_TO(x, y)	(((x) + (y) - 1) / (y) * (y))
#define ROUND_DOWN_TO(x, y)	((x) / (y) * (y))
#define ROUND_UP_TO_PAGE(x)	ROUND_UP_TO((x), GTT_PAGE_SIZE)
#define ROUND_DOWN_TO_PAGE(x)	ROUND_DOWN_TO((x), GTT_PAGE_SIZE)

/* messages */
#define PFX			INTELFB_MODULE_NAME ": "

#define ERR_MSG(fmt, args...)	printk(KERN_ERR PFX fmt, ## args)
#define WRN_MSG(fmt, args...)	printk(KERN_WARNING PFX fmt, ## args)
#define NOT_MSG(fmt, args...)	printk(KERN_NOTICE PFX fmt, ## args)
#define INF_MSG(fmt, args...)	printk(KERN_INFO PFX fmt, ## args)
#if DEBUG
#define DBG_MSG(fmt, args...)	printk(KERN_DEBUG PFX fmt, ## args)
#else
#define DBG_MSG(fmt, args...)	while (0) printk(fmt, ## args)
#endif

/* get commonly used pointers */
#define GET_DINFO(info)		(info)->par

/* misc macros */
#define ACCEL(d, i)                                                     \
	((d)->accel && !(d)->ring_lockup &&                             \
	 ((i)->var.accel_flags & FB_ACCELF_TEXT))

/*#define NOACCEL_CHIPSET(d)						\
	((d)->chipset != INTEL_865G)*/
#define NOACCEL_CHIPSET(d)						\
	(0)

#define FIXED_MODE(d) ((d)->fixed_mode)

/*** Driver parameters ***/

#define RINGBUFFER_SIZE		KB(64)
#define HW_CURSOR_SIZE		KB(4)

/* Intel agpgart driver */
#define AGP_PHYSICAL_MEMORY     2

/* store information about an Ixxx DVO */
/* The i830->i865 use multiple DVOs with multiple i2cs */
/* the i915, i945 have a single sDVO i2c bus - which is different */
#define MAX_OUTPUTS 6

/* these are outputs from the chip - integrated only
   external chips are via DVO or SDVO output */
#define INTELFB_OUTPUT_UNUSED 0
#define INTELFB_OUTPUT_ANALOG 1
#define INTELFB_OUTPUT_DVO 2
#define INTELFB_OUTPUT_SDVO 3
#define INTELFB_OUTPUT_LVDS 4
#define INTELFB_OUTPUT_TVOUT 5

#define INTELFB_DVO_CHIP_NONE 0
#define INTELFB_DVO_CHIP_LVDS 1
#define INTELFB_DVO_CHIP_TMDS 2
#define INTELFB_DVO_CHIP_TVOUT 4

#define INTELFB_OUTPUT_PIPE_NC  0
#define INTELFB_OUTPUT_PIPE_A   1
#define INTELFB_OUTPUT_PIPE_B   2

/*** Data Types ***/

/* supported chipsets */
enum intel_chips {
	INTEL_830M,
	INTEL_845G,
	INTEL_85XGM,
	INTEL_852GM,
	INTEL_852GME,
	INTEL_854,
	INTEL_855GM,
	INTEL_855GME,
	INTEL_865G,
	INTEL_915G,
	INTEL_915GM,
	INTEL_945G,
	INTEL_945GM,
	INTEL_945GME,
	INTEL_965G,
	INTEL_965GM,
};

struct intelfb_hwstate {
	u32 vga0_divisor;
	u32 vga1_divisor;
	u32 vga_pd;
	u32 dpll_a;
	u32 dpll_b;
	u32 fpa0;
	u32 fpa1;
	u32 fpb0;
	u32 fpb1;
	u32 palette_a[PALETTE_8_ENTRIES];
	u32 palette_b[PALETTE_8_ENTRIES];
	u32 htotal_a;
	u32 hblank_a;
	u32 hsync_a;
	u32 vtotal_a;
	u32 vblank_a;
	u32 vsync_a;
	u32 src_size_a;
	u32 bclrpat_a;
	u32 htotal_b;
	u32 hblank_b;
	u32 hsync_b;
	u32 vtotal_b;
	u32 vblank_b;
	u32 vsync_b;
	u32 src_size_b;
	u32 bclrpat_b;
	u32 adpa;
	u32 dvoa;
	u32 dvob;
	u32 dvoc;
	u32 dvoa_srcdim;
	u32 dvob_srcdim;
	u32 dvoc_srcdim;
	u32 lvds;
	u32 pipe_a_conf;
	u32 pipe_b_conf;
	u32 disp_arb;
	u32 cursor_a_control;
	u32 cursor_b_control;
	u32 cursor_a_base;
	u32 cursor_b_base;
	u32 cursor_size;
	u32 disp_a_ctrl;
	u32 disp_b_ctrl;
	u32 disp_a_base;
	u32 disp_b_base;
	u32 cursor_a_palette[4];
	u32 cursor_b_palette[4];
	u32 disp_a_stride;
	u32 disp_b_stride;
	u32 vgacntrl;
	u32 add_id;
	u32 swf0x[7];
	u32 swf1x[7];
	u32 swf3x[3];
	u32 fence[8];
	u32 instpm;
	u32 mem_mode;
	u32 fw_blc_0;
	u32 fw_blc_1;
	u16 hwstam;
	u16 ier;
	u16 iir;
	u16 imr;
};

struct intelfb_heap_data {
	u32 physical;
	u8 __iomem *virtual;
	u32 offset;		/* in GATT pages */
	u32 size;		/* in bytes */
};

#ifdef CONFIG_FB_INTEL_I2C
struct intelfb_i2c_chan {
    struct intelfb_info *dinfo;
    u32 reg;
    struct i2c_adapter adapter;
    struct i2c_algo_bit_data algo;
};
#endif

struct intelfb_output_rec {
    int type;
    int pipe;
    int flags;

#ifdef CONFIG_FB_INTEL_I2C
    struct intelfb_i2c_chan i2c_bus;
    struct intelfb_i2c_chan ddc_bus;
#endif
};

struct intelfb_vsync {
	wait_queue_head_t wait;
	unsigned int count;
	int pan_display;
	u32 pan_offset;
};

struct intelfb_info {
	struct fb_info *info;
	struct fb_ops  *fbops;
	struct pci_dev *pdev;

	struct intelfb_hwstate save_state;

	/* agpgart structs */
	struct agp_memory *gtt_fb_mem;     /* use all stolen memory or vram */
	struct agp_memory *gtt_ring_mem;   /* ring buffer */
	struct agp_memory *gtt_cursor_mem; /* hw cursor */

	/* use a gart reserved fb mem */
	u8 fbmem_gart;

	/* mtrr support */
	int mtrr_reg;
	u32 has_mtrr;

	/* heap data */
	struct intelfb_heap_data aperture;
	struct intelfb_heap_data fb;
	struct intelfb_heap_data ring;
	struct intelfb_heap_data cursor;

	/* mmio regs */
	u32 mmio_base_phys;
	u8 __iomem *mmio_base;

	/* fb start offset (in bytes) */
	u32 fb_start;

	/* ring buffer */
	u32 ring_head;
	u32 ring_tail;
	u32 ring_tail_mask;
	u32 ring_space;
	u32 ring_lockup;

	/* palette */
	u32 pseudo_palette[16];

	/* chip info */
	int pci_chipset;
	int chipset;
	const char *name;
	int mobile;

	/* current mode */
	int bpp, depth;
	u32 visual;
	int xres, yres, pitch;
	int pixclock;

	/* current pipe */
	int pipe;

	/* some flags */
	int accel;
	int hwcursor;
	int fixed_mode;
	int ring_active;
	int flag;
	unsigned long irq_flags;
	int open;

	/* vsync */
	struct intelfb_vsync vsync;
	spinlock_t int_lock;

	/* hw cursor */
	int cursor_on;
	int cursor_blanked;
	u8  cursor_src[64];

	/* initial parameters */
	int initial_vga;
	struct fb_var_screeninfo initial_var;
	u32 initial_fb_base;
	u32 initial_video_ram;
	u32 initial_pitch;

	/* driver registered */
	int registered;

	/* index into plls */
	int pll_index;

	/* outputs */
	int num_outputs;
	struct intelfb_output_rec output[MAX_OUTPUTS];
};

#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G) ||	\
			((dinfo)->chipset == INTEL_915GM) ||	\
			((dinfo)->chipset == INTEL_945G) ||	\
			((dinfo)->chipset == INTEL_945GM) ||	\
			((dinfo)->chipset == INTEL_945GME) ||	\
			((dinfo)->chipset == INTEL_965G) ||	\
			((dinfo)->chipset == INTEL_965GM))

/*** function prototypes ***/

extern int intelfb_var_to_depth(const struct fb_var_screeninfo *var);

#ifdef CONFIG_FB_INTEL_I2C
extern void intelfb_create_i2c_busses(struct intelfb_info *dinfo);
extern void intelfb_delete_i2c_busses(struct intelfb_info *dinfo);
#endif

#endif /* _INTELFB_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _INTELFB_H
	2	#define _INTELFB_H
	3
	4	/* $DHD: intelfb/intelfb.h,v 1.40 2003/06/27 15:06:25 dawes Exp $ */
	5
	6	#include <linux/agp_backend.h>
	7	#include <linux/fb.h>
	8
183b1214 DM	9	#ifdef CONFIG_FB_INTEL_I2C
	10	#include <linux/i2c.h>
	11	#include <linux/i2c-algo-bit.h>
	12	#endif
1da177e4 LT	13
1da177e4 LT	14	/* Version/name */
3f7a26b4	15	#define INTELFB_VERSION "0.9.6"
1da177e4	16	#define INTELFB_MODULE_NAME "intelfb"
3f7a26b4	17	#define SUPPORTED_CHIPSETS "830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM/945GME/965G/965GM"
1da177e4 LT	18
	19
	20	/* Debug/feature defines */
	21
	22	#ifndef DEBUG
	23	#define DEBUG 0
	24	#endif
	25
	26	#ifndef VERBOSE
	27	#define VERBOSE 0
	28	#endif
	29
	30	#ifndef REGDUMP
	31	#define REGDUMP 0
	32	#endif
	33
	34	#ifndef DETECT_VGA_CLASS_ONLY
	35	#define DETECT_VGA_CLASS_ONLY 1
	36	#endif
	37
	38	#ifndef ALLOCATE_FOR_PANNING
	39	#define ALLOCATE_FOR_PANNING 1
	40	#endif
	41
	42	#ifndef PREFERRED_MODE
	43	#define PREFERRED_MODE "1024x768-32@70"
	44	#endif
	45
	46	/* hw-related values */
	47
4b3760ce AD	48	/* Resource Allocation */
	49	#define INTELFB_FB_ACQUIRED 1
	50	#define INTELFB_MMIO_ACQUIRED 2
	51
1da177e4 LT	52	/* PCI ids for supported devices */
	53	#define PCI_DEVICE_ID_INTEL_830M 0x3577
	54	#define PCI_DEVICE_ID_INTEL_845G 0x2562
	55	#define PCI_DEVICE_ID_INTEL_85XGM 0x3582
347486bb	56	#define PCI_DEVICE_ID_INTEL_854 0x358E
1da177e4 LT	57	#define PCI_DEVICE_ID_INTEL_865G 0x2572
1da177e4 LT	58	#define PCI_DEVICE_ID_INTEL_915G 0x2582
3a59026b	59	#define PCI_DEVICE_ID_INTEL_915GM 0x2592
9639d5ec	60	#define PCI_DEVICE_ID_INTEL_945G 0x2772
9a90603f	61	#define PCI_DEVICE_ID_INTEL_945GM 0x27A2
3f7a26b4	62	#define PCI_DEVICE_ID_INTEL_945GME 0x27AE
0e170c72 MB	63	#define PCI_DEVICE_ID_INTEL_965G 0x29A2
0e170c72 MB	64	#define PCI_DEVICE_ID_INTEL_965GM 0x2A02
1da177e4 LT	65
	66	/* Size of MMIO region */
	67	#define INTEL_REG_SIZE 0x80000
	68
	69	#define STRIDE_ALIGNMENT 16
df7df8ab	70	#define STRIDE_ALIGNMENT_I9XX 64
1da177e4 LT	71
	72	#define PALETTE_8_ENTRIES 256
	73
	74
	75	/* Macros */
	76
	77	/* basic arithmetic */
	78	#define KB(x) ((x) * 1024)
	79	#define MB(x) ((x) * 1024 * 1024)
	80	#define BtoKB(x) ((x) / 1024)
	81	#define BtoMB(x) ((x) / 1024 / 1024)
	82
	83	#define GTT_PAGE_SIZE KB(4)
	84
	85	#define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y))
	86	#define ROUND_DOWN_TO(x, y) ((x) / (y) * (y))
	87	#define ROUND_UP_TO_PAGE(x) ROUND_UP_TO((x), GTT_PAGE_SIZE)
	88	#define ROUND_DOWN_TO_PAGE(x) ROUND_DOWN_TO((x), GTT_PAGE_SIZE)
	89
	90	/* messages */
	91	#define PFX INTELFB_MODULE_NAME ": "
	92
	93	#define ERR_MSG(fmt, args...) printk(KERN_ERR PFX fmt, ## args)
	94	#define WRN_MSG(fmt, args...) printk(KERN_WARNING PFX fmt, ## args)
	95	#define NOT_MSG(fmt, args...) printk(KERN_NOTICE PFX fmt, ## args)
	96	#define INF_MSG(fmt, args...) printk(KERN_INFO PFX fmt, ## args)
	97	#if DEBUG
	98	#define DBG_MSG(fmt, args...) printk(KERN_DEBUG PFX fmt, ## args)
	99	#else
	100	#define DBG_MSG(fmt, args...) while (0) printk(fmt, ## args)
	101	#endif
	102
	103	/* get commonly used pointers */
	104	#define GET_DINFO(info) (info)->par
	105
	106	/* misc macros */
	107	#define ACCEL(d, i) \
	108	((d)->accel && !(d)->ring_lockup && \
	109	((i)->var.accel_flags & FB_ACCELF_TEXT))
	110
	111	/*#define NOACCEL_CHIPSET(d) \
	112	((d)->chipset != INTEL_865G)*/
	113	#define NOACCEL_CHIPSET(d) \
	114	(0)
	115
	116	#define FIXED_MODE(d) ((d)->fixed_mode)
	117
44363f14	118	/* Driver parameters */
1da177e4 LT	119
	120	#define RINGBUFFER_SIZE KB(64)
	121	#define HW_CURSOR_SIZE KB(4)
	122
	123	/* Intel agpgart driver */
	124	#define AGP_PHYSICAL_MEMORY 2
	125
dd696ec8 DM	126	/* store information about an Ixxx DVO */
	127	/* The i830->i865 use multiple DVOs with multiple i2cs */
	128	/* the i915, i945 have a single sDVO i2c bus - which is different */
	129	#define MAX_OUTPUTS 6
	130
399fb431 DM	131	/* these are outputs from the chip - integrated only
	132	external chips are via DVO or SDVO output */
	133	#define INTELFB_OUTPUT_UNUSED 0
	134	#define INTELFB_OUTPUT_ANALOG 1
	135	#define INTELFB_OUTPUT_DVO 2
	136	#define INTELFB_OUTPUT_SDVO 3
	137	#define INTELFB_OUTPUT_LVDS 4
	138	#define INTELFB_OUTPUT_TVOUT 5
	139
	140	#define INTELFB_DVO_CHIP_NONE 0
	141	#define INTELFB_DVO_CHIP_LVDS 1
	142	#define INTELFB_DVO_CHIP_TMDS 2
	143	#define INTELFB_DVO_CHIP_TVOUT 4
	144
	145	#define INTELFB_OUTPUT_PIPE_NC 0
	146	#define INTELFB_OUTPUT_PIPE_A 1
	147	#define INTELFB_OUTPUT_PIPE_B 2
	148
1da177e4 LT	149	/* Data Types */
	150
	151	/* supported chipsets */
	152	enum intel_chips {
	153	INTEL_830M,
	154	INTEL_845G,
	155	INTEL_85XGM,
	156	INTEL_852GM,
	157	INTEL_852GME,
347486bb	158	INTEL_854,
1da177e4 LT	159	INTEL_855GM,
	160	INTEL_855GME,
	161	INTEL_865G,
3a59026b	162	INTEL_915G,
9639d5ec	163	INTEL_915GM,
9a90603f DA	164	INTEL_945G,
9a90603f DA	165	INTEL_945GM,
3f7a26b4	166	INTEL_945GME,
0e170c72 MB	167	INTEL_965G,
0e170c72 MB	168	INTEL_965GM,
1da177e4 LT	169	};
	170
	171	struct intelfb_hwstate {
	172	u32 vga0_divisor;
	173	u32 vga1_divisor;
	174	u32 vga_pd;
	175	u32 dpll_a;
	176	u32 dpll_b;
	177	u32 fpa0;
	178	u32 fpa1;
	179	u32 fpb0;
	180	u32 fpb1;
	181	u32 palette_a[PALETTE_8_ENTRIES];
	182	u32 palette_b[PALETTE_8_ENTRIES];
	183	u32 htotal_a;
	184	u32 hblank_a;
	185	u32 hsync_a;
	186	u32 vtotal_a;
	187	u32 vblank_a;
	188	u32 vsync_a;
	189	u32 src_size_a;
	190	u32 bclrpat_a;
	191	u32 htotal_b;
	192	u32 hblank_b;
	193	u32 hsync_b;
	194	u32 vtotal_b;
	195	u32 vblank_b;
	196	u32 vsync_b;
	197	u32 src_size_b;
	198	u32 bclrpat_b;
	199	u32 adpa;
	200	u32 dvoa;
	201	u32 dvob;
	202	u32 dvoc;
	203	u32 dvoa_srcdim;
	204	u32 dvob_srcdim;
	205	u32 dvoc_srcdim;
	206	u32 lvds;
	207	u32 pipe_a_conf;
	208	u32 pipe_b_conf;
	209	u32 disp_arb;
	210	u32 cursor_a_control;
	211	u32 cursor_b_control;
	212	u32 cursor_a_base;
	213	u32 cursor_b_base;
	214	u32 cursor_size;
	215	u32 disp_a_ctrl;
	216	u32 disp_b_ctrl;
	217	u32 disp_a_base;
	218	u32 disp_b_base;
	219	u32 cursor_a_palette[4];
	220	u32 cursor_b_palette[4];
	221	u32 disp_a_stride;
	222	u32 disp_b_stride;
	223	u32 vgacntrl;
	224	u32 add_id;
	225	u32 swf0x[7];
	226	u32 swf1x[7];
	227	u32 swf3x[3];
	228	u32 fence[8];
	229	u32 instpm;
	230	u32 mem_mode;
	231	u32 fw_blc_0;
	232	u32 fw_blc_1;
9a5f019b EH	233	u16 hwstam;
	234	u16 ier;
	235	u16 iir;
	236	u16 imr;
1da177e4 LT	237	};
	238
	239	struct intelfb_heap_data {
	240	u32 physical;
	241	u8 __iomem *virtual;
689c9568 KH	242	u32 offset; /* in GATT pages */
689c9568 KH	243	u32 size; /* in bytes */
1da177e4 LT	244	};
1da177e4 LT	245
183b1214 DM	246	#ifdef CONFIG_FB_INTEL_I2C
	247	struct intelfb_i2c_chan {
	248	struct intelfb_info *dinfo;
	249	u32 reg;
	250	struct i2c_adapter adapter;
	251	struct i2c_algo_bit_data algo;
	252	};
	253	#endif
	254
399fb431 DM	255	struct intelfb_output_rec {
	256	int type;
	257	int pipe;
	258	int flags;
	259
	260	#ifdef CONFIG_FB_INTEL_I2C
	261	struct intelfb_i2c_chan i2c_bus;
	262	struct intelfb_i2c_chan ddc_bus;
	263	#endif
	264	};
	265
7649757b EH	266	struct intelfb_vsync {
	267	wait_queue_head_t wait;
	268	unsigned int count;
f80d0d23 EH	269	int pan_display;
f80d0d23 EH	270	u32 pan_offset;
7649757b EH	271	};
7649757b EH	272
1da177e4 LT	273	struct intelfb_info {
	274	struct fb_info *info;
	275	struct fb_ops *fbops;
	276	struct pci_dev *pdev;
	277
	278	struct intelfb_hwstate save_state;
	279
	280	/* agpgart structs */
689c9568 KH	281	struct agp_memory gtt_fb_mem; / use all stolen memory or vram */
	282	struct agp_memory gtt_ring_mem; / ring buffer */
	283	struct agp_memory gtt_cursor_mem; / hw cursor */
1da177e4 LT	284
	285	/* use a gart reserved fb mem */
	286	u8 fbmem_gart;
	287
	288	/* mtrr support */
d5afabce	289	int mtrr_reg;
1da177e4 LT	290	u32 has_mtrr;
	291
	292	/* heap data */
	293	struct intelfb_heap_data aperture;
	294	struct intelfb_heap_data fb;
	295	struct intelfb_heap_data ring;
	296	struct intelfb_heap_data cursor;
	297
	298	/* mmio regs */
	299	u32 mmio_base_phys;
	300	u8 __iomem *mmio_base;
	301
	302	/* fb start offset (in bytes) */
	303	u32 fb_start;
	304
	305	/* ring buffer */
0fe6e2d2	306	u32 ring_head;
1da177e4 LT	307	u32 ring_tail;
	308	u32 ring_tail_mask;
	309	u32 ring_space;
	310	u32 ring_lockup;
	311
	312	/* palette */
c312f97d	313	u32 pseudo_palette[16];
1da177e4 LT	314
	315	/* chip info */
	316	int pci_chipset;
	317	int chipset;
	318	const char *name;
	319	int mobile;
	320
	321	/* current mode */
	322	int bpp, depth;
	323	u32 visual;
	324	int xres, yres, pitch;
	325	int pixclock;
	326
	327	/* current pipe */
	328	int pipe;
	329
	330	/* some flags */
	331	int accel;
	332	int hwcursor;
	333	int fixed_mode;
	334	int ring_active;
4b3760ce	335	int flag;
7649757b EH	336	unsigned long irq_flags;
	337	int open;
	338
	339	/* vsync */
	340	struct intelfb_vsync vsync;
	341	spinlock_t int_lock;
1da177e4 LT	342
	343	/* hw cursor */
	344	int cursor_on;
	345	int cursor_blanked;
	346	u8 cursor_src[64];
	347
	348	/* initial parameters */
	349	int initial_vga;
	350	struct fb_var_screeninfo initial_var;
	351	u32 initial_fb_base;
	352	u32 initial_video_ram;
	353	u32 initial_pitch;
	354
	355	/* driver registered */
	356	int registered;
689c9568	357
d024960c DA	358	/* index into plls */
d024960c DA	359	int pll_index;
dd696ec8 DM	360
	361	/* outputs */
	362	int num_outputs;
	363	struct intelfb_output_rec output[MAX_OUTPUTS];
1da177e4 LT	364	};
1da177e4 LT	365
ee5618f4 KH	366	#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G) \|\| \
	367	((dinfo)->chipset == INTEL_915GM) \|\| \
	368	((dinfo)->chipset == INTEL_945G) \|\| \
0e170c72	369	((dinfo)->chipset == INTEL_945GM) \|\| \
3f7a26b4	370	((dinfo)->chipset == INTEL_945GME) \|\| \
0e170c72 MB	371	((dinfo)->chipset == INTEL_965G) \|\| \
0e170c72 MB	372	((dinfo)->chipset == INTEL_965GM))
8bb91f6a	373
1da177e4 LT	374	/* function prototypes */
	375
	376	extern int intelfb_var_to_depth(const struct fb_var_screeninfo *var);
	377
41c9480a DM	378	#ifdef CONFIG_FB_INTEL_I2C
41c9480a DM	379	extern void intelfb_create_i2c_busses(struct intelfb_info *dinfo);
7627899b	380	extern void intelfb_delete_i2c_busses(struct intelfb_info *dinfo);
41c9480a DM	381	#endif
41c9480a DM	382
1da177e4	383	#endif /* _INTELFB_H */