[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / geode / lxfb.h

/* Geode LX framebuffer driver
 *
 * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
 * Copyright (c) 2008  Andres Salomon <dilinger@debian.org>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */
#ifndef _LXFB_H_
#define _LXFB_H_

#include <linux/fb.h>

#define GP_REG_COUNT	(0x7c / 4)
#define DC_REG_COUNT	(0xf0 / 4)
#define VP_REG_COUNT	(0x158 / 8)
#define FP_REG_COUNT	(0x60 / 8)

#define DC_PAL_COUNT	0x104
#define DC_HFILT_COUNT	0x100
#define DC_VFILT_COUNT	0x100
#define VP_COEFF_SIZE	0x1000
#define VP_PAL_COUNT	0x100

#define OUTPUT_CRT   0x01
#define OUTPUT_PANEL 0x02

struct lxfb_par {
	int output;

	void __iomem *gp_regs;
	void __iomem *dc_regs;
	void __iomem *vp_regs;
#ifdef CONFIG_PM
	int powered_down;

	/* register state, for power mgmt functionality */
	struct {
		uint64_t padsel;
		uint64_t dotpll;
		uint64_t dfglcfg;
		uint64_t dcspare;
	} msr;

	uint32_t gp[GP_REG_COUNT];
	uint32_t dc[DC_REG_COUNT];
	uint64_t vp[VP_REG_COUNT];
	uint64_t fp[FP_REG_COUNT];

	uint32_t dc_pal[DC_PAL_COUNT];
	uint32_t vp_pal[VP_PAL_COUNT];
	uint32_t hcoeff[DC_HFILT_COUNT * 2];
	uint32_t vcoeff[DC_VFILT_COUNT];
	uint32_t vp_coeff[VP_COEFF_SIZE / 4];
#endif
};

static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
{
	return (((xres * (bpp >> 3)) + 7) & ~7);
}

void lx_set_mode(struct fb_info *);
unsigned int lx_framebuffer_size(void);
int lx_blank_display(struct fb_info *, int);
void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
			unsigned int, unsigned int);

#ifdef CONFIG_PM
int lx_powerdown(struct fb_info *info);
int lx_powerup(struct fb_info *info);
#endif


/* Graphics Processor registers (table 6-29 from the data book) */
enum gp_registers {
	GP_DST_OFFSET = 0,
	GP_SRC_OFFSET,
	GP_STRIDE,
	GP_WID_HEIGHT,

	GP_SRC_COLOR_FG,
	GP_SRC_COLOR_BG,
	GP_PAT_COLOR_0,
	GP_PAT_COLOR_1,

	GP_PAT_COLOR_2,
	GP_PAT_COLOR_3,
	GP_PAT_COLOR_4,
	GP_PAT_COLOR_5,

	GP_PAT_DATA_0,
	GP_PAT_DATA_1,
	GP_RASTER_MODE,
	GP_VECTOR_MODE,

	GP_BLT_MODE,
	GP_BLT_STATUS,
	GP_HST_SRC,
	GP_BASE_OFFSET,

	GP_CMD_TOP,
	GP_CMD_BOT,
	GP_CMD_READ,
	GP_CMD_WRITE,

	GP_CH3_OFFSET,
	GP_CH3_MODE_STR,
	GP_CH3_WIDHI,
	GP_CH3_HSRC,

	GP_LUT_INDEX,
	GP_LUT_DATA,
	GP_INT_CNTRL, /* 0x78 */
};

#define GP_BLT_STATUS_CE		(1 << 4)	/* cmd buf empty */
#define GP_BLT_STATUS_PB		(1 << 0)	/* primative busy */


/* Display Controller registers (table 6-47 from the data book) */
enum dc_registers {
	DC_UNLOCK = 0,
	DC_GENERAL_CFG,
	DC_DISPLAY_CFG,
	DC_ARB_CFG,

	DC_FB_ST_OFFSET,
	DC_CB_ST_OFFSET,
	DC_CURS_ST_OFFSET,
	DC_RSVD_0,

	DC_VID_Y_ST_OFFSET,
	DC_VID_U_ST_OFFSET,
	DC_VID_V_ST_OFFSET,
	DC_DV_TOP,

	DC_LINE_SIZE,
	DC_GFX_PITCH,
	DC_VID_YUV_PITCH,
	DC_RSVD_1,

	DC_H_ACTIVE_TIMING,
	DC_H_BLANK_TIMING,
	DC_H_SYNC_TIMING,
	DC_RSVD_2,

	DC_V_ACTIVE_TIMING,
	DC_V_BLANK_TIMING,
	DC_V_SYNC_TIMING,
	DC_FB_ACTIVE,

	DC_CURSOR_X,
	DC_CURSOR_Y,
	DC_RSVD_3,
	DC_LINE_CNT,

	DC_PAL_ADDRESS,
	DC_PAL_DATA,
	DC_DFIFO_DIAG,
	DC_CFIFO_DIAG,

	DC_VID_DS_DELTA,
	DC_GLIU0_MEM_OFFSET,
	DC_DV_CTL,
	DC_DV_ACCESS,

	DC_GFX_SCALE,
	DC_IRQ_FILT_CTL,
	DC_FILT_COEFF1,
	DC_FILT_COEFF2,

	DC_VBI_EVEN_CTL,
	DC_VBI_ODD_CTL,
	DC_VBI_HOR,
	DC_VBI_LN_ODD,

	DC_VBI_LN_EVEN,
	DC_VBI_PITCH,
	DC_CLR_KEY,
	DC_CLR_KEY_MASK,

	DC_CLR_KEY_X,
	DC_CLR_KEY_Y,
	DC_IRQ,
	DC_RSVD_4,

	DC_RSVD_5,
	DC_GENLK_CTL,
	DC_VID_EVEN_Y_ST_OFFSET,
	DC_VID_EVEN_U_ST_OFFSET,

	DC_VID_EVEN_V_ST_OFFSET,
	DC_V_ACTIVE_EVEN_TIMING,
	DC_V_BLANK_EVEN_TIMING,
	DC_V_SYNC_EVEN_TIMING,	/* 0xec */
};

#define DC_UNLOCK_LOCK			0x00000000
#define DC_UNLOCK_UNLOCK		0x00004758	/* magic value */

#define DC_GENERAL_CFG_FDTY		(1 << 17)
#define DC_GENERAL_CFG_DFHPEL_SHIFT	(12)
#define DC_GENERAL_CFG_DFHPSL_SHIFT	(8)
#define DC_GENERAL_CFG_VGAE		(1 << 7)
#define DC_GENERAL_CFG_DECE		(1 << 6)
#define DC_GENERAL_CFG_CMPE		(1 << 5)
#define DC_GENERAL_CFG_VIDE		(1 << 3)
#define DC_GENERAL_CFG_DFLE		(1 << 0)

#define DC_DISPLAY_CFG_VISL		(1 << 27)
#define DC_DISPLAY_CFG_PALB		(1 << 25)
#define DC_DISPLAY_CFG_DCEN		(1 << 24)
#define DC_DISPLAY_CFG_DISP_MODE_24BPP	(1 << 9)
#define DC_DISPLAY_CFG_DISP_MODE_16BPP	(1 << 8)
#define DC_DISPLAY_CFG_DISP_MODE_8BPP	(0)
#define DC_DISPLAY_CFG_TRUP		(1 << 6)
#define DC_DISPLAY_CFG_VDEN		(1 << 4)
#define DC_DISPLAY_CFG_GDEN		(1 << 3)
#define DC_DISPLAY_CFG_TGEN		(1 << 0)

#define DC_DV_TOP_DV_TOP_EN		(1 << 0)

#define DC_DV_CTL_DV_LINE_SIZE		((1 << 10) | (1 << 11))
#define DC_DV_CTL_DV_LINE_SIZE_1K	(0)
#define DC_DV_CTL_DV_LINE_SIZE_2K	(1 << 10)
#define DC_DV_CTL_DV_LINE_SIZE_4K	(1 << 11)
#define DC_DV_CTL_DV_LINE_SIZE_8K	((1 << 10) | (1 << 11))
#define DC_DV_CTL_CLEAR_DV_RAM		(1 << 0)

#define DC_IRQ_FILT_CTL_H_FILT_SEL	(1 << 10)

#define DC_CLR_KEY_CLR_KEY_EN		(1 << 24)

#define DC_IRQ_VIP_VSYNC_IRQ_STATUS	(1 << 21)	/* undocumented? */
#define DC_IRQ_STATUS			(1 << 20)	/* undocumented? */
#define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK	(1 << 1)
#define DC_IRQ_MASK			(1 << 0)

#define DC_GENLK_CTL_FLICK_SEL_MASK	(0x0F << 28)
#define DC_GENLK_CTL_ALPHA_FLICK_EN	(1 << 25)
#define DC_GENLK_CTL_FLICK_EN		(1 << 24)
#define DC_GENLK_CTL_GENLK_EN		(1 << 18)


/*
 * Video Processor registers (table 6-71).
 * There is space for 64 bit values, but we never use more than the
 * lower 32 bits.  The actual register save/restore code only bothers
 * to restore those 32 bits.
 */
enum vp_registers {
	VP_VCFG = 0,
	VP_DCFG,

	VP_VX,
	VP_VY,

	VP_SCL,
	VP_VCK,

	VP_VCM,
	VP_PAR,

	VP_PDR,
	VP_SLR,

	VP_MISC,
	VP_CCS,

	VP_VYS,
	VP_VXS,

	VP_RSVD_0,
	VP_VDC,

	VP_RSVD_1,
	VP_CRC,

	VP_CRC32,
	VP_VDE,

	VP_CCK,
	VP_CCM,

	VP_CC1,
	VP_CC2,

	VP_A1X,
	VP_A1Y,

	VP_A1C,
	VP_A1T,

	VP_A2X,
	VP_A2Y,

	VP_A2C,
	VP_A2T,

	VP_A3X,
	VP_A3Y,

	VP_A3C,
	VP_A3T,

	VP_VRR,
	VP_AWT,

	VP_VTM,
	VP_VYE,

	VP_A1YE,
	VP_A2YE,

	VP_A3YE,	/* 0x150 */

	VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
};

#define VP_VCFG_VID_EN			(1 << 0)

#define VP_DCFG_GV_GAM			(1 << 21)
#define VP_DCFG_PWR_SEQ_DELAY		((1 << 17) | (1 << 18) | (1 << 19))
#define VP_DCFG_PWR_SEQ_DELAY_DEFAULT	(1 << 19)	/* undocumented */
#define VP_DCFG_CRT_SYNC_SKW		((1 << 14) | (1 << 15) | (1 << 16))
#define VP_DCFG_CRT_SYNC_SKW_DEFAULT	(1 << 16)
#define VP_DCFG_CRT_VSYNC_POL		(1 << 9)
#define VP_DCFG_CRT_HSYNC_POL		(1 << 8)
#define VP_DCFG_DAC_BL_EN		(1 << 3)
#define VP_DCFG_VSYNC_EN		(1 << 2)
#define VP_DCFG_HSYNC_EN		(1 << 1)
#define VP_DCFG_CRT_EN			(1 << 0)

#define VP_MISC_APWRDN			(1 << 11)
#define VP_MISC_DACPWRDN		(1 << 10)
#define VP_MISC_BYP_BOTH		(1 << 0)


/*
 * Flat Panel registers (table 6-71).
 * Also 64 bit registers; see above note about 32-bit handling.
 */

/* we're actually in the VP register space, starting at address 0x400 */
#define VP_FP_START	0x400

enum fp_registers {
	FP_PT1 = 0,
	FP_PT2,

	FP_PM,
	FP_DFC,

	FP_RSVD_0,
	FP_RSVD_1,

	FP_RSVD_2,
	FP_RSVD_3,

	FP_RSVD_4,
	FP_DCA,

	FP_DMD,
	FP_CRC, /* 0x458 */
};

#define FP_PT2_HSP			(1 << 22)
#define FP_PT2_VSP			(1 << 23)
#define FP_PT2_SCRC			(1 << 27)	/* shfclk free */

#define FP_PM_P				(1 << 24)	/* panel power ctl */
#define FP_PM_PANEL_PWR_UP		(1 << 3)	/* r/o */
#define FP_PM_PANEL_PWR_DOWN		(1 << 2)	/* r/o */
#define FP_PM_PANEL_OFF			(1 << 1)	/* r/o */
#define FP_PM_PANEL_ON			(1 << 0)	/* r/o */

#define FP_DFC_BC			((1 << 4) | (1 << 5) | (1 << 6))


/* register access functions */

static inline uint32_t read_gp(struct lxfb_par *par, int reg)
{
	return readl(par->gp_regs + 4*reg);
}

static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
{
	writel(val, par->gp_regs + 4*reg);
}

static inline uint32_t read_dc(struct lxfb_par *par, int reg)
{
	return readl(par->dc_regs + 4*reg);
}

static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
{
	writel(val, par->dc_regs + 4*reg);
}

static inline uint32_t read_vp(struct lxfb_par *par, int reg)
{
	return readl(par->vp_regs + 8*reg);
}

static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
{
	writel(val, par->vp_regs + 8*reg);
}

static inline uint32_t read_fp(struct lxfb_par *par, int reg)
{
	return readl(par->vp_regs + 8*reg + VP_FP_START);
}

static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
{
	writel(val, par->vp_regs + 8*reg + VP_FP_START);
}


/* MSRs are defined in linux/cs5535.h; their bitfields are here */

#define MSR_GLCP_DOTPLL_LOCK		(1 << 25)	/* r/o */
#define MSR_GLCP_DOTPLL_HALFPIX		(1 << 24)
#define MSR_GLCP_DOTPLL_BYPASS		(1 << 15)
#define MSR_GLCP_DOTPLL_DOTRESET	(1 << 0)

/* note: this is actually the VP's GLD_MSR_CONFIG */
#define MSR_LX_GLD_MSR_CONFIG_FMT	((1 << 3) | (1 << 4) | (1 << 5))
#define MSR_LX_GLD_MSR_CONFIG_FMT_FP	(1 << 3)
#define MSR_LX_GLD_MSR_CONFIG_FMT_CRT	(0)
#define MSR_LX_GLD_MSR_CONFIG_FPC	(1 << 15)	/* FP *and* CRT */

#define MSR_LX_MSR_PADSEL_TFT_SEL_LOW	0xDFFFFFFF	/* ??? */
#define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH	0x0000003F	/* ??? */

#define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO	(1 << 11)	/* undocumented */
#define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL	(1 << 10)	/* undocumented */
#define MSR_LX_SPARE_MSR_WM_LPEN_OVRD	(1 << 9)	/* undocumented */
#define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M	(1 << 8)	/* undocumented */
#define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI	(1 << 7)	/* undocumented */
#define MSR_LX_SPARE_MSR_DIS_VIFO_WM	(1 << 6)
#define MSR_LX_SPARE_MSR_DIS_CWD_CHECK	(1 << 5)	/* undocumented */
#define MSR_LX_SPARE_MSR_PIX8_PAN_FIX	(1 << 4)	/* undocumented */
#define MSR_LX_SPARE_MSR_FIRST_REQ_MASK	(1 << 1)	/* undocumented */

#endif
Commit	Line	Data
8a8e6b9d AS	1	/* Geode LX framebuffer driver
	2	*
	3	* Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
	4	* Copyright (c) 2008 Andres Salomon <dilinger@debian.org>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
3968cb49 JC	11	#ifndef _LXFB_H_
	12	#define _LXFB_H_
	13
	14	#include <linux/fb.h>
	15
f694e53b AS	16	#define GP_REG_COUNT (0x7c / 4)
	17	#define DC_REG_COUNT (0xf0 / 4)
	18	#define VP_REG_COUNT (0x158 / 8)
	19	#define FP_REG_COUNT (0x60 / 8)
	20
	21	#define DC_PAL_COUNT 0x104
	22	#define DC_HFILT_COUNT 0x100
	23	#define DC_VFILT_COUNT 0x100
	24	#define VP_COEFF_SIZE 0x1000
16cdd433	25	#define VP_PAL_COUNT 0x100
f694e53b	26
3968cb49 JC	27	#define OUTPUT_CRT 0x01
	28	#define OUTPUT_PANEL 0x02
	29
	30	struct lxfb_par {
	31	int output;
3968cb49 JC	32
	33	void __iomem *gp_regs;
	34	void __iomem *dc_regs;
31f51fa8	35	void __iomem *vp_regs;
f694e53b AS	36	#ifdef CONFIG_PM
	37	int powered_down;
	38
	39	/* register state, for power mgmt functionality */
	40	struct {
	41	uint64_t padsel;
	42	uint64_t dotpll;
	43	uint64_t dfglcfg;
	44	uint64_t dcspare;
	45	} msr;
	46
	47	uint32_t gp[GP_REG_COUNT];
	48	uint32_t dc[DC_REG_COUNT];
	49	uint64_t vp[VP_REG_COUNT];
	50	uint64_t fp[FP_REG_COUNT];
	51
16cdd433 DD	52	uint32_t dc_pal[DC_PAL_COUNT];
16cdd433 DD	53	uint32_t vp_pal[VP_PAL_COUNT];
f694e53b AS	54	uint32_t hcoeff[DC_HFILT_COUNT * 2];
	55	uint32_t vcoeff[DC_VFILT_COUNT];
	56	uint32_t vp_coeff[VP_COEFF_SIZE / 4];
	57	#endif
3968cb49 JC	58	};
	59
	60	static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
	61	{
	62	return (((xres * (bpp >> 3)) + 7) & ~7);
	63	}
	64
	65	void lx_set_mode(struct fb_info *);
3968cb49 JC	66	unsigned int lx_framebuffer_size(void);
	67	int lx_blank_display(struct fb_info *, int);
	68	void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
	69	unsigned int, unsigned int);
	70
f694e53b AS	71	#ifdef CONFIG_PM
	72	int lx_powerdown(struct fb_info *info);
	73	int lx_powerup(struct fb_info *info);
	74	#endif
	75
3968cb49	76
f5c90e85 AS	77	/* Graphics Processor registers (table 6-29 from the data book) */
	78	enum gp_registers {
	79	GP_DST_OFFSET = 0,
	80	GP_SRC_OFFSET,
	81	GP_STRIDE,
	82	GP_WID_HEIGHT,
	83
	84	GP_SRC_COLOR_FG,
	85	GP_SRC_COLOR_BG,
	86	GP_PAT_COLOR_0,
	87	GP_PAT_COLOR_1,
	88
	89	GP_PAT_COLOR_2,
	90	GP_PAT_COLOR_3,
	91	GP_PAT_COLOR_4,
	92	GP_PAT_COLOR_5,
	93
	94	GP_PAT_DATA_0,
	95	GP_PAT_DATA_1,
	96	GP_RASTER_MODE,
	97	GP_VECTOR_MODE,
	98
	99	GP_BLT_MODE,
	100	GP_BLT_STATUS,
	101	GP_HST_SRC,
	102	GP_BASE_OFFSET,
	103
	104	GP_CMD_TOP,
	105	GP_CMD_BOT,
	106	GP_CMD_READ,
	107	GP_CMD_WRITE,
	108
	109	GP_CH3_OFFSET,
	110	GP_CH3_MODE_STR,
	111	GP_CH3_WIDHI,
	112	GP_CH3_HSRC,
	113
	114	GP_LUT_INDEX,
	115	GP_LUT_DATA,
	116	GP_INT_CNTRL, /* 0x78 */
	117	};
	118
	119	#define GP_BLT_STATUS_CE (1 << 4) /* cmd buf empty */
	120	#define GP_BLT_STATUS_PB (1 << 0) /* primative busy */
	121
	122
	123	/* Display Controller registers (table 6-47 from the data book) */
	124	enum dc_registers {
	125	DC_UNLOCK = 0,
	126	DC_GENERAL_CFG,
	127	DC_DISPLAY_CFG,
	128	DC_ARB_CFG,
	129
	130	DC_FB_ST_OFFSET,
	131	DC_CB_ST_OFFSET,
	132	DC_CURS_ST_OFFSET,
	133	DC_RSVD_0,
	134
	135	DC_VID_Y_ST_OFFSET,
	136	DC_VID_U_ST_OFFSET,
	137	DC_VID_V_ST_OFFSET,
	138	DC_DV_TOP,
	139
	140	DC_LINE_SIZE,
141	DC_GFX_PITCH,
142	DC_VID_YUV_PITCH,
143	DC_RSVD_1,
144
145	DC_H_ACTIVE_TIMING,
146	DC_H_BLANK_TIMING,
147	DC_H_SYNC_TIMING,
148	DC_RSVD_2,
149
150	DC_V_ACTIVE_TIMING,
151	DC_V_BLANK_TIMING,
152	DC_V_SYNC_TIMING,
153	DC_FB_ACTIVE,
154
155	DC_CURSOR_X,
156	DC_CURSOR_Y,
157	DC_RSVD_3,
158	DC_LINE_CNT,
159
160	DC_PAL_ADDRESS,
161	DC_PAL_DATA,
162	DC_DFIFO_DIAG,
163	DC_CFIFO_DIAG,
164
165	DC_VID_DS_DELTA,
166	DC_GLIU0_MEM_OFFSET,
167	DC_DV_CTL,
168	DC_DV_ACCESS,
169
170	DC_GFX_SCALE,
171	DC_IRQ_FILT_CTL,
172	DC_FILT_COEFF1,
173	DC_FILT_COEFF2,
174
175	DC_VBI_EVEN_CTL,
176	DC_VBI_ODD_CTL,
177	DC_VBI_HOR,
178	DC_VBI_LN_ODD,
179
180	DC_VBI_LN_EVEN,
181	DC_VBI_PITCH,
182	DC_CLR_KEY,
183	DC_CLR_KEY_MASK,
184
185	DC_CLR_KEY_X,
186	DC_CLR_KEY_Y,
187	DC_IRQ,
188	DC_RSVD_4,
189
190	DC_RSVD_5,
191	DC_GENLK_CTL,
192	DC_VID_EVEN_Y_ST_OFFSET,
193	DC_VID_EVEN_U_ST_OFFSET,
194
195	DC_VID_EVEN_V_ST_OFFSET,
196	DC_V_ACTIVE_EVEN_TIMING,
197	DC_V_BLANK_EVEN_TIMING,
198	DC_V_SYNC_EVEN_TIMING, /* 0xec */
199	};
200
201	#define DC_UNLOCK_LOCK 0x00000000
202	#define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
203
204	#define DC_GENERAL_CFG_FDTY (1 << 17)
205	#define DC_GENERAL_CFG_DFHPEL_SHIFT (12)
206	#define DC_GENERAL_CFG_DFHPSL_SHIFT (8)
207	#define DC_GENERAL_CFG_VGAE (1 << 7)
208	#define DC_GENERAL_CFG_DECE (1 << 6)
209	#define DC_GENERAL_CFG_CMPE (1 << 5)
210	#define DC_GENERAL_CFG_VIDE (1 << 3)
211	#define DC_GENERAL_CFG_DFLE (1 << 0)
3968cb49	212
f5c90e85 AS	213	#define DC_DISPLAY_CFG_VISL (1 << 27)
	214	#define DC_DISPLAY_CFG_PALB (1 << 25)
	215	#define DC_DISPLAY_CFG_DCEN (1 << 24)
	216	#define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
	217	#define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
	218	#define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
	219	#define DC_DISPLAY_CFG_TRUP (1 << 6)
	220	#define DC_DISPLAY_CFG_VDEN (1 << 4)
	221	#define DC_DISPLAY_CFG_GDEN (1 << 3)
	222	#define DC_DISPLAY_CFG_TGEN (1 << 0)
3968cb49	223
f5c90e85	224	#define DC_DV_TOP_DV_TOP_EN (1 << 0)
3968cb49	225
f5c90e85 AS	226	#define DC_DV_CTL_DV_LINE_SIZE ((1 << 10) \| (1 << 11))
	227	#define DC_DV_CTL_DV_LINE_SIZE_1K (0)
	228	#define DC_DV_CTL_DV_LINE_SIZE_2K (1 << 10)
	229	#define DC_DV_CTL_DV_LINE_SIZE_4K (1 << 11)
	230	#define DC_DV_CTL_DV_LINE_SIZE_8K ((1 << 10) \| (1 << 11))
f694e53b AS	231	#define DC_DV_CTL_CLEAR_DV_RAM (1 << 0)
	232
	233	#define DC_IRQ_FILT_CTL_H_FILT_SEL (1 << 10)
3968cb49	234
f5c90e85	235	#define DC_CLR_KEY_CLR_KEY_EN (1 << 24)
3968cb49	236
f5c90e85 AS	237	#define DC_IRQ_VIP_VSYNC_IRQ_STATUS (1 << 21) /* undocumented? */
	238	#define DC_IRQ_STATUS (1 << 20) /* undocumented? */
	239	#define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK (1 << 1)
	240	#define DC_IRQ_MASK (1 << 0)
3968cb49	241
f5c90e85 AS	242	#define DC_GENLK_CTL_FLICK_SEL_MASK (0x0F << 28)
	243	#define DC_GENLK_CTL_ALPHA_FLICK_EN (1 << 25)
	244	#define DC_GENLK_CTL_FLICK_EN (1 << 24)
	245	#define DC_GENLK_CTL_GENLK_EN (1 << 18)
3968cb49	246
3968cb49	247
f5c90e85 AS	248	/*
	249	* Video Processor registers (table 6-71).
	250	* There is space for 64 bit values, but we never use more than the
	251	* lower 32 bits. The actual register save/restore code only bothers
	252	* to restore those 32 bits.
	253	*/
	254	enum vp_registers {
	255	VP_VCFG = 0,
	256	VP_DCFG,
3968cb49	257
f5c90e85 AS	258	VP_VX,
f5c90e85 AS	259	VP_VY,
3968cb49	260
f5c90e85 AS	261	VP_SCL,
f5c90e85 AS	262	VP_VCK,
3968cb49	263
f5c90e85 AS	264	VP_VCM,
f5c90e85 AS	265	VP_PAR,
3968cb49	266
f5c90e85 AS	267	VP_PDR,
f5c90e85 AS	268	VP_SLR,
3968cb49	269
f5c90e85 AS	270	VP_MISC,
f5c90e85 AS	271	VP_CCS,
3968cb49	272
f5c90e85 AS	273	VP_VYS,
f5c90e85 AS	274	VP_VXS,
3968cb49	275
f5c90e85 AS	276	VP_RSVD_0,
f5c90e85 AS	277	VP_VDC,
3968cb49	278
f5c90e85 AS	279	VP_RSVD_1,
f5c90e85 AS	280	VP_CRC,
3968cb49	281
f5c90e85 AS	282	VP_CRC32,
f5c90e85 AS	283	VP_VDE,
3968cb49	284
f5c90e85 AS	285	VP_CCK,
f5c90e85 AS	286	VP_CCM,
3968cb49	287
f5c90e85 AS	288	VP_CC1,
f5c90e85 AS	289	VP_CC2,
3968cb49	290
f5c90e85 AS	291	VP_A1X,
f5c90e85 AS	292	VP_A1Y,
3968cb49	293
f5c90e85 AS	294	VP_A1C,
f5c90e85 AS	295	VP_A1T,
3968cb49	296
f5c90e85 AS	297	VP_A2X,
f5c90e85 AS	298	VP_A2Y,
3968cb49	299
f5c90e85 AS	300	VP_A2C,
f5c90e85 AS	301	VP_A2T,
3968cb49	302
f5c90e85 AS	303	VP_A3X,
f5c90e85 AS	304	VP_A3Y,
3968cb49	305
f5c90e85 AS	306	VP_A3C,
	307	VP_A3T,
	308
	309	VP_VRR,
	310	VP_AWT,
	311
	312	VP_VTM,
	313	VP_VYE,
	314
	315	VP_A1YE,
	316	VP_A2YE,
	317
	318	VP_A3YE, /* 0x150 */
f694e53b AS	319
f694e53b AS	320	VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
f5c90e85	321	};
3968cb49	322
f5c90e85	323	#define VP_VCFG_VID_EN (1 << 0)
3968cb49	324
f5c90e85 AS	325	#define VP_DCFG_GV_GAM (1 << 21)
	326	#define VP_DCFG_PWR_SEQ_DELAY ((1 << 17) \| (1 << 18) \| (1 << 19))
	327	#define VP_DCFG_PWR_SEQ_DELAY_DEFAULT (1 << 19) /* undocumented */
	328	#define VP_DCFG_CRT_SYNC_SKW ((1 << 14) \| (1 << 15) \| (1 << 16))
	329	#define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
	330	#define VP_DCFG_CRT_VSYNC_POL (1 << 9)
	331	#define VP_DCFG_CRT_HSYNC_POL (1 << 8)
	332	#define VP_DCFG_DAC_BL_EN (1 << 3)
	333	#define VP_DCFG_VSYNC_EN (1 << 2)
	334	#define VP_DCFG_HSYNC_EN (1 << 1)
	335	#define VP_DCFG_CRT_EN (1 << 0)
3968cb49	336
f5c90e85 AS	337	#define VP_MISC_APWRDN (1 << 11)
	338	#define VP_MISC_DACPWRDN (1 << 10)
	339	#define VP_MISC_BYP_BOTH (1 << 0)
3968cb49	340
3968cb49	341
f5c90e85 AS	342	/*
	343	* Flat Panel registers (table 6-71).
	344	* Also 64 bit registers; see above note about 32-bit handling.
	345	*/
	346
	347	/* we're actually in the VP register space, starting at address 0x400 */
	348	#define VP_FP_START 0x400
	349
	350	enum fp_registers {
	351	FP_PT1 = 0,
	352	FP_PT2,
	353
	354	FP_PM,
	355	FP_DFC,
	356
	357	FP_RSVD_0,
	358	FP_RSVD_1,
	359
	360	FP_RSVD_2,
	361	FP_RSVD_3,
	362
	363	FP_RSVD_4,
	364	FP_DCA,
	365
	366	FP_DMD,
	367	FP_CRC, /* 0x458 */
	368	};
	369
b5c26f97 MG	370	#define FP_PT2_HSP (1 << 22)
b5c26f97 MG	371	#define FP_PT2_VSP (1 << 23)
f5c90e85	372	#define FP_PT2_SCRC (1 << 27) /* shfclk free */
3968cb49	373
f5c90e85	374	#define FP_PM_P (1 << 24) /* panel power ctl */
f694e53b AS	375	#define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
	376	#define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
	377	#define FP_PM_PANEL_OFF (1 << 1) /* r/o */
	378	#define FP_PM_PANEL_ON (1 << 0) /* r/o */
3968cb49	379
f5c90e85	380	#define FP_DFC_BC ((1 << 4) \| (1 << 5) \| (1 << 6))
3968cb49	381
9286361b AS	382
	383	/* register access functions */
	384
	385	static inline uint32_t read_gp(struct lxfb_par *par, int reg)
	386	{
f5c90e85	387	return readl(par->gp_regs + 4*reg);
9286361b AS	388	}
	389
	390	static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
	391	{
f5c90e85	392	writel(val, par->gp_regs + 4*reg);
9286361b AS	393	}
	394
	395	static inline uint32_t read_dc(struct lxfb_par *par, int reg)
	396	{
f5c90e85	397	return readl(par->dc_regs + 4*reg);
9286361b AS	398	}
	399
	400	static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
	401	{
f5c90e85	402	writel(val, par->dc_regs + 4*reg);
9286361b AS	403	}
	404
	405	static inline uint32_t read_vp(struct lxfb_par *par, int reg)
	406	{
31f51fa8	407	return readl(par->vp_regs + 8*reg);
9286361b AS	408	}
	409
	410	static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
	411	{
31f51fa8	412	writel(val, par->vp_regs + 8*reg);
9286361b AS	413	}
	414
	415	static inline uint32_t read_fp(struct lxfb_par *par, int reg)
	416	{
31f51fa8	417	return readl(par->vp_regs + 8*reg + VP_FP_START);
9286361b AS	418	}
	419
	420	static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
	421	{
31f51fa8	422	writel(val, par->vp_regs + 8*reg + VP_FP_START);
9286361b AS	423	}
9286361b AS	424
aec40532	425
f3a57a60	426	/* MSRs are defined in linux/cs5535.h; their bitfields are here */
aec40532 AS	427
	428	#define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
	429	#define MSR_GLCP_DOTPLL_HALFPIX (1 << 24)
	430	#define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
	431	#define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
	432
	433	/* note: this is actually the VP's GLD_MSR_CONFIG */
	434	#define MSR_LX_GLD_MSR_CONFIG_FMT ((1 << 3) \| (1 << 4) \| (1 << 5))
	435	#define MSR_LX_GLD_MSR_CONFIG_FMT_FP (1 << 3)
	436	#define MSR_LX_GLD_MSR_CONFIG_FMT_CRT (0)
	437	#define MSR_LX_GLD_MSR_CONFIG_FPC (1 << 15) /* FP and CRT */
	438
	439	#define MSR_LX_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF /* ??? */
	440	#define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F /* ??? */
	441
	442	#define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO (1 << 11) /* undocumented */
	443	#define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL (1 << 10) /* undocumented */
	444	#define MSR_LX_SPARE_MSR_WM_LPEN_OVRD (1 << 9) /* undocumented */
	445	#define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8) /* undocumented */
	446	#define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7) /* undocumented */
	447	#define MSR_LX_SPARE_MSR_DIS_VIFO_WM (1 << 6)
	448	#define MSR_LX_SPARE_MSR_DIS_CWD_CHECK (1 << 5) /* undocumented */
	449	#define MSR_LX_SPARE_MSR_PIX8_PAN_FIX (1 << 4) /* undocumented */
	450	#define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1) /* undocumented */
	451
3968cb49	452	#endif