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drivers/video: fsl-diu-fb: add default platform ops functions
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / fsl-diu-fb.c
CommitLineData
9b53a9e2
YS		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Freescale DIU Frame Buffer device driver
5 *
6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
7 * Paul Widmer <paul.widmer@freescale.com>
8 * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
9 * York Sun <yorksun@freescale.com>
10 *
11 * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26#include <linux/init.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29#include <linux/interrupt.h>
30#include <linux/clk.h>
31#include <linux/uaccess.h>
32#include <linux/vmalloc.h>
b715f9f0 33#include <linux/spinlock.h>
9b53a9e2 34
9b53a9e2 35#include <sysdev/fsl_soc.h>
0814a979 36#include <linux/fsl-diu-fb.h>
8b856f04 37#include "edid.h"
9b53a9e2 38
ddd3d905 39#define NUM_AOIS 5 /* 1 for plane 0, 2 for planes 1 & 2 each */
b715f9f0
TT		 40
41/* HW cursor parameters */
42#define MAX_CURS 32
43
44/* INT_STATUS/INT_MASK field descriptions */
45#define INT_VSYNC 0x01 /* Vsync interrupt */
46#define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
47#define INT_UNDRUN 0x04 /* Under run exception interrupt */
48#define INT_PARERR 0x08 /* Display parameters error interrupt */
49#define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
50
9b53a9e2 51/*
63cf8df4
TT		 52 * List of supported video modes
53 *
760af8f8
TT		 54 * The first entry is the default video mode. The remain entries are in
55 * order if increasing resolution and frequency. The 320x240-60 mode is
56 * the initial AOI for the second and third planes.
9b53a9e2 57 */
9b53a9e2
YS		 58static struct fb_videomode __devinitdata fsl_diu_mode_db[] = {
59 {
9b53a9e2
YS		 60 .refresh = 60,
61 .xres = 1024,
62 .yres = 768,
63 .pixclock = 15385,
64 .left_margin = 160,
65 .right_margin = 24,
66 .upper_margin = 29,
67 .lower_margin = 3,
68 .hsync_len = 136,
69 .vsync_len = 6,
70 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
71 .vmode = FB_VMODE_NONINTERLACED
72 },
73 {
760af8f8
TT		 74 .refresh = 60,
75 .xres = 320,
76 .yres = 240,
77 .pixclock = 79440,
78 .left_margin = 16,
79 .right_margin = 16,
80 .upper_margin = 16,
81 .lower_margin = 5,
82 .hsync_len = 48,
83 .vsync_len = 1,
84 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
85 .vmode = FB_VMODE_NONINTERLACED
86 },
87 {
88 .refresh = 60,
89 .xres = 640,
90 .yres = 480,
91 .pixclock = 39722,
92 .left_margin = 48,
93 .right_margin = 16,
94 .upper_margin = 33,
95 .lower_margin = 10,
96 .hsync_len = 96,
97 .vsync_len = 2,
98 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
99 .vmode = FB_VMODE_NONINTERLACED
100 },
101 {
102 .refresh = 72,
103 .xres = 640,
104 .yres = 480,
105 .pixclock = 32052,
106 .left_margin = 128,
107 .right_margin = 24,
108 .upper_margin = 28,
109 .lower_margin = 9,
110 .hsync_len = 40,
111 .vsync_len = 3,
112 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
113 .vmode = FB_VMODE_NONINTERLACED
114 },
115 {
116 .refresh = 75,
117 .xres = 640,
118 .yres = 480,
119 .pixclock = 31747,
120 .left_margin = 120,
121 .right_margin = 16,
122 .upper_margin = 16,
123 .lower_margin = 1,
124 .hsync_len = 64,
125 .vsync_len = 3,
126 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
127 .vmode = FB_VMODE_NONINTERLACED
128 },
129 {
130 .refresh = 90,
131 .xres = 640,
132 .yres = 480,
133 .pixclock = 25057,
134 .left_margin = 120,
135 .right_margin = 32,
136 .upper_margin = 14,
137 .lower_margin = 25,
138 .hsync_len = 40,
139 .vsync_len = 14,
140 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
141 .vmode = FB_VMODE_NONINTERLACED
142 },
143 {
144 .refresh = 100,
145 .xres = 640,
146 .yres = 480,
147 .pixclock = 22272,
148 .left_margin = 48,
149 .right_margin = 32,
150 .upper_margin = 17,
151 .lower_margin = 22,
152 .hsync_len = 128,
153 .vsync_len = 12,
154 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
155 .vmode = FB_VMODE_NONINTERLACED
156 },
157 {
158 .refresh = 60,
159 .xres = 800,
160 .yres = 480,
161 .pixclock = 33805,
162 .left_margin = 96,
163 .right_margin = 24,
164 .upper_margin = 10,
165 .lower_margin = 3,
166 .hsync_len = 72,
167 .vsync_len = 7,
168 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
169 .vmode = FB_VMODE_NONINTERLACED
170 },
171 {
172 .refresh = 60,
173 .xres = 800,
174 .yres = 600,
175 .pixclock = 25000,
176 .left_margin = 88,
177 .right_margin = 40,
178 .upper_margin = 23,
179 .lower_margin = 1,
180 .hsync_len = 128,
181 .vsync_len = 4,
182 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
183 .vmode = FB_VMODE_NONINTERLACED
184 },
185 {
186 .refresh = 60,
187 .xres = 854,
188 .yres = 480,
189 .pixclock = 31518,
190 .left_margin = 104,
191 .right_margin = 16,
192 .upper_margin = 13,
193 .lower_margin = 1,
194 .hsync_len = 88,
195 .vsync_len = 3,
196 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
197 .vmode = FB_VMODE_NONINTERLACED
198 },
199 {
9b53a9e2
YS		 200 .refresh = 70,
201 .xres = 1024,
202 .yres = 768,
203 .pixclock = 16886,
204 .left_margin = 3,
205 .right_margin = 3,
206 .upper_margin = 2,
207 .lower_margin = 2,
208 .hsync_len = 40,
209 .vsync_len = 18,
210 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
211 .vmode = FB_VMODE_NONINTERLACED
212 },
213 {
9b53a9e2
YS		 214 .refresh = 75,
215 .xres = 1024,
216 .yres = 768,
217 .pixclock = 15009,
218 .left_margin = 3,
219 .right_margin = 3,
220 .upper_margin = 2,
221 .lower_margin = 2,
222 .hsync_len = 80,
223 .vsync_len = 32,
224 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
225 .vmode = FB_VMODE_NONINTERLACED
226 },
227 {
760af8f8
TT		 228 .refresh = 60,
229 .xres = 1280,
230 .yres = 480,
231 .pixclock = 18939,
232 .left_margin = 353,
233 .right_margin = 47,
234 .upper_margin = 39,
235 .lower_margin = 4,
236 .hsync_len = 8,
237 .vsync_len = 2,
238 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
239 .vmode = FB_VMODE_NONINTERLACED
240 },
241 {
242 .refresh = 60,
243 .xres = 1280,
244 .yres = 720,
245 .pixclock = 13426,
246 .left_margin = 192,
247 .right_margin = 64,
248 .upper_margin = 22,
249 .lower_margin = 1,
250 .hsync_len = 136,
251 .vsync_len = 3,
252 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
253 .vmode = FB_VMODE_NONINTERLACED
254 },
255 {
9b53a9e2
YS		 256 .refresh = 60,
257 .xres = 1280,
258 .yres = 1024,
259 .pixclock = 9375,
260 .left_margin = 38,
261 .right_margin = 128,
262 .upper_margin = 2,
263 .lower_margin = 7,
264 .hsync_len = 216,
265 .vsync_len = 37,
266 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
267 .vmode = FB_VMODE_NONINTERLACED
268 },
269 {
9b53a9e2
YS		 270 .refresh = 70,
271 .xres = 1280,
272 .yres = 1024,
273 .pixclock = 9380,
274 .left_margin = 6,
275 .right_margin = 6,
276 .upper_margin = 4,
277 .lower_margin = 4,
278 .hsync_len = 60,
279 .vsync_len = 94,
280 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
281 .vmode = FB_VMODE_NONINTERLACED
282 },
283 {
9b53a9e2
YS		 284 .refresh = 75,
285 .xres = 1280,
286 .yres = 1024,
287 .pixclock = 9380,
288 .left_margin = 6,
289 .right_margin = 6,
290 .upper_margin = 4,
291 .lower_margin = 4,
292 .hsync_len = 60,
293 .vsync_len = 15,
294 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
295 .vmode = FB_VMODE_NONINTERLACED
296 },
297 {
9b53a9e2 298 .refresh = 60,
760af8f8
TT		 299 .xres = 1920,
300 .yres = 1080,
301 .pixclock = 5787,
302 .left_margin = 328,
303 .right_margin = 120,
304 .upper_margin = 34,
305 .lower_margin = 1,
306 .hsync_len = 208,
307 .vsync_len = 3,
9b53a9e2
YS		 308 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
309 .vmode = FB_VMODE_NONINTERLACED
310 },
311};
312
760af8f8 313static char *fb_mode;
9b53a9e2 314static unsigned long default_bpp = 32;
7653aaab
TT		 315static enum fsl_diu_monitor_port monitor_port;
316static char *monitor_string;
9b53a9e2
YS		 317
318#if defined(CONFIG_NOT_COHERENT_CACHE)
319static u8 *coherence_data;
320static size_t coherence_data_size;
321static unsigned int d_cache_line_size;
322#endif
323
324static DEFINE_SPINLOCK(diu_lock);
325
2572df91
TT		 326enum mfb_index {
327 PLANE0 = 0, /* Plane 0, only one AOI that fills the screen */
328 PLANE1_AOI0, /* Plane 1, first AOI */
329 PLANE1_AOI1, /* Plane 1, second AOI */
330 PLANE2_AOI0, /* Plane 2, first AOI */
331 PLANE2_AOI1, /* Plane 2, second AOI */
332};
333
9b53a9e2 334struct mfb_info {
2572df91 335 enum mfb_index index;
9b53a9e2
YS		 336 char *id;
337 int registered;
9b53a9e2
YS		 338 unsigned long pseudo_palette[16];
339 struct diu_ad *ad;
340 int cursor_reset;
341 unsigned char g_alpha;
342 unsigned int count;
343 int x_aoi_d; /* aoi display x offset to physical screen */
344 int y_aoi_d; /* aoi display y offset to physical screen */
345 struct fsl_diu_data *parent;
8b856f04 346 u8 *edid_data;
9b53a9e2
YS		 347};
348
ddd3d905
TT		 349/**
350 * struct fsl_diu_data - per-DIU data structure
351 * @dma_addr: DMA address of this structure
352 * @fsl_diu_info: fb_info objects, one per AOI
353 * @dev_attr: sysfs structure
354 * @irq: IRQ
ddd3d905
TT		 355 * @monitor_port: the monitor port this DIU is connected to
356 * @diu_reg: pointer to the DIU hardware registers
357 * @reg_lock: spinlock for register access
358 * @dummy_aoi: video buffer for the 4x4 32-bit dummy AOI
359 * dummy_ad: DIU Area Descriptor for the dummy AOI
360 * @ad[]: Area Descriptors for each real AOI
361 * @gamma: gamma color table
362 * @cursor: hardware cursor data
363 *
364 * This data structure must be allocated with 32-byte alignment, so that the
365 * internal fields can be aligned properly.
366 */
367struct fsl_diu_data {
368 dma_addr_t dma_addr;
369 struct fb_info fsl_diu_info[NUM_AOIS];
370 struct mfb_info mfb[NUM_AOIS];
371 struct device_attribute dev_attr;
372 unsigned int irq;
ddd3d905
TT		 373 enum fsl_diu_monitor_port monitor_port;
374 struct diu __iomem *diu_reg;
375 spinlock_t reg_lock;
376 u8 dummy_aoi[4 * 4 * 4];
377 struct diu_ad dummy_ad __aligned(8);
378 struct diu_ad ad[NUM_AOIS] __aligned(8);
379 u8 gamma[256 * 3] __aligned(32);
380 u8 cursor[MAX_CURS * MAX_CURS * 2] __aligned(32);
381} __aligned(32);
382
383/* Determine the DMA address of a member of the fsl_diu_data structure */
384#define DMA_ADDR(p, f) ((p)->dma_addr + offsetof(struct fsl_diu_data, f))
9b53a9e2
YS		 385
386static struct mfb_info mfb_template[] = {
2572df91
TT		 387 {
388 .index = PLANE0,
4a85dc8b
TT		 389 .id = "Panel0",
390 .registered = 0,
391 .count = 0,
392 .x_aoi_d = 0,
393 .y_aoi_d = 0,
9b53a9e2 394 },
2572df91
TT		 395 {
396 .index = PLANE1_AOI0,
4a85dc8b
TT		 397 .id = "Panel1 AOI0",
398 .registered = 0,
399 .g_alpha = 0xff,
400 .count = 0,
401 .x_aoi_d = 0,
402 .y_aoi_d = 0,
9b53a9e2 403 },
2572df91
TT		 404 {
405 .index = PLANE1_AOI1,
4a85dc8b
TT		 406 .id = "Panel1 AOI1",
407 .registered = 0,
408 .g_alpha = 0xff,
409 .count = 0,
410 .x_aoi_d = 0,
411 .y_aoi_d = 480,
9b53a9e2 412 },
2572df91
TT		 413 {
414 .index = PLANE2_AOI0,
4a85dc8b
TT		 415 .id = "Panel2 AOI0",
416 .registered = 0,
417 .g_alpha = 0xff,
418 .count = 0,
419 .x_aoi_d = 640,
420 .y_aoi_d = 0,
9b53a9e2 421 },
2572df91
TT		 422 {
423 .index = PLANE2_AOI1,
4a85dc8b
TT		 424 .id = "Panel2 AOI1",
425 .registered = 0,
426 .g_alpha = 0xff,
427 .count = 0,
428 .x_aoi_d = 640,
429 .y_aoi_d = 480,
9b53a9e2
YS		 430 },
431};
432
7653aaab
TT		 433/**
434 * fsl_diu_name_to_port - convert a port name to a monitor port enum
435 *
436 * Takes the name of a monitor port ("dvi", "lvds", or "dlvds") and returns
437 * the enum fsl_diu_monitor_port that corresponds to that string.
438 *
439 * For compatibility with older versions, a number ("0", "1", or "2") is also
440 * supported.
441 *
442 * If the string is unknown, DVI is assumed.
443 *
444 * If the particular port is not supported by the platform, another port
445 * (platform-specific) is chosen instead.
446 */
447static enum fsl_diu_monitor_port fsl_diu_name_to_port(const char *s)
448{
449 enum fsl_diu_monitor_port port = FSL_DIU_PORT_DVI;
450 unsigned long val;
451
452 if (s) {
453 if (!strict_strtoul(s, 10, &val) && (val <= 2))
454 port = (enum fsl_diu_monitor_port) val;
455 else if (strncmp(s, "lvds", 4) == 0)
456 port = FSL_DIU_PORT_LVDS;
457 else if (strncmp(s, "dlvds", 5) == 0)
458 port = FSL_DIU_PORT_DLVDS;
459 }
460
461 return diu_ops.valid_monitor_port(port);
462}
463
6b51d51a
TT		 464/**
465 * fsl_diu_alloc - allocate memory for the DIU
466 * @size: number of bytes to allocate
467 * @param: returned physical address of memory
468 *
469 * This function allocates a physically-contiguous block of memory.
9b53a9e2 470 */
6b51d51a 471static void *fsl_diu_alloc(size_t size, phys_addr_t *phys)
9b53a9e2
YS		 472{
473 void *virt;
474
6b51d51a 475 virt = alloc_pages_exact(size, GFP_DMA | __GFP_ZERO);
154152ae 476 if (virt)
9b53a9e2 477 *phys = virt_to_phys(virt);
9b53a9e2 478
9b53a9e2
YS		 479 return virt;
480}
481
6b51d51a
TT		 482/**
483 * fsl_diu_free - release DIU memory
484 * @virt: pointer returned by fsl_diu_alloc()
485 * @size: number of bytes allocated by fsl_diu_alloc()
486 *
487 * This function releases memory allocated by fsl_diu_alloc().
488 */
489static void fsl_diu_free(void *virt, size_t size)
9b53a9e2 490{
6b51d51a
TT		 491 if (virt && size)
492 free_pages_exact(virt, size);
9b53a9e2
YS		 493}
494
0d9dab39
AG		 495/*
496 * Workaround for failed writing desc register of planes.
497 * Needed with MPC5121 DIU rev 2.0 silicon.
498 */
499void wr_reg_wa(u32 *reg, u32 val)
500{
501 do {
502 out_be32(reg, val);
503 } while (in_be32(reg) != val);
504}
505
7e47c211 506static void fsl_diu_enable_panel(struct fb_info *info)
9b53a9e2
YS		 507{
508 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
9b53a9e2 509 struct diu_ad *ad = mfbi->ad;
b7795052
TT		 510 struct fsl_diu_data *data = mfbi->parent;
511 struct diu __iomem *hw = data->diu_reg;
9b53a9e2 512
7e47c211
TT		 513 switch (mfbi->index) {
514 case PLANE0:
515 if (hw->desc[0] != ad->paddr)
516 wr_reg_wa(&hw->desc[0], ad->paddr);
517 break;
518 case PLANE1_AOI0:
b7795052 519 cmfbi = &data->mfb[2];
7e47c211
TT		 520 if (hw->desc[1] != ad->paddr) { /* AOI0 closed */
521 if (cmfbi->count > 0) /* AOI1 open */
522 ad->next_ad =
523 cpu_to_le32(cmfbi->ad->paddr);
524 else
525 ad->next_ad = 0;
526 wr_reg_wa(&hw->desc[1], ad->paddr);
9b53a9e2 527 }
7e47c211
TT		 528 break;
529 case PLANE2_AOI0:
b7795052 530 cmfbi = &data->mfb[4];
7e47c211
TT		 531 if (hw->desc[2] != ad->paddr) { /* AOI0 closed */
532 if (cmfbi->count > 0) /* AOI1 open */
533 ad->next_ad =
534 cpu_to_le32(cmfbi->ad->paddr);
535 else
536 ad->next_ad = 0;
537 wr_reg_wa(&hw->desc[2], ad->paddr);
538 }
539 break;
540 case PLANE1_AOI1:
b7795052 541 pmfbi = &data->mfb[1];
7e47c211 542 ad->next_ad = 0;
b7795052 543 if (hw->desc[1] == data->dummy_ad.paddr)
7e47c211
TT		 544 wr_reg_wa(&hw->desc[1], ad->paddr);
545 else /* AOI0 open */
546 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
547 break;
548 case PLANE2_AOI1:
b7795052 549 pmfbi = &data->mfb[3];
7e47c211 550 ad->next_ad = 0;
b7795052 551 if (hw->desc[2] == data->dummy_ad.paddr)
7e47c211
TT		 552 wr_reg_wa(&hw->desc[2], ad->paddr);
553 else /* AOI0 was open */
554 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
555 break;
556 }
9b53a9e2
YS		 557}
558
2572df91 559static void fsl_diu_disable_panel(struct fb_info *info)
9b53a9e2
YS		 560{
561 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
9b53a9e2 562 struct diu_ad *ad = mfbi->ad;
b7795052
TT		 563 struct fsl_diu_data *data = mfbi->parent;
564 struct diu __iomem *hw = data->diu_reg;
9b53a9e2
YS		 565
566 switch (mfbi->index) {
2572df91 567 case PLANE0:
b7795052
TT		 568 if (hw->desc[0] != data->dummy_ad.paddr)
569 wr_reg_wa(&hw->desc[0], data->dummy_ad.paddr);
9b53a9e2 570 break;
2572df91 571 case PLANE1_AOI0:
b7795052 572 cmfbi = &data->mfb[2];
9b53a9e2 573 if (cmfbi->count > 0) /* AOI1 is open */
0d9dab39 574 wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr);
9b53a9e2
YS		 575 /* move AOI1 to the first */
576 else /* AOI1 was closed */
b7795052 577 wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr);
9b53a9e2
YS		 578 /* close AOI 0 */
579 break;
2572df91 580 case PLANE2_AOI0:
b7795052 581 cmfbi = &data->mfb[4];
9b53a9e2 582 if (cmfbi->count > 0) /* AOI1 is open */
0d9dab39 583 wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr);
9b53a9e2
YS		 584 /* move AOI1 to the first */
585 else /* AOI1 was closed */
b7795052 586 wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr);
9b53a9e2
YS		 587 /* close AOI 0 */
588 break;
2572df91 589 case PLANE1_AOI1:
b7795052 590 pmfbi = &data->mfb[1];
9b53a9e2
YS		 591 if (hw->desc[1] != ad->paddr) {
592 /* AOI1 is not the first in the chain */
593 if (pmfbi->count > 0)
594 /* AOI0 is open, must be the first */
595 pmfbi->ad->next_ad = 0;
596 } else /* AOI1 is the first in the chain */
b7795052 597 wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr);
9b53a9e2
YS		 598 /* close AOI 1 */
599 break;
2572df91 600 case PLANE2_AOI1:
b7795052 601 pmfbi = &data->mfb[3];
9b53a9e2
YS		 602 if (hw->desc[2] != ad->paddr) {
603 /* AOI1 is not the first in the chain */
604 if (pmfbi->count > 0)
605 /* AOI0 is open, must be the first */
606 pmfbi->ad->next_ad = 0;
607 } else /* AOI1 is the first in the chain */
b7795052 608 wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr);
9b53a9e2
YS		 609 /* close AOI 1 */
610 break;
9b53a9e2 611 }
9b53a9e2
YS		 612}
613
614static void enable_lcdc(struct fb_info *info)
615{
9b53a9e2 616 struct mfb_info *mfbi = info->par;
b7795052
TT		 617 struct fsl_diu_data *data = mfbi->parent;
618 struct diu __iomem *hw = data->diu_reg;
9b53a9e2 619
d397e916 620 out_be32(&hw->diu_mode, MFB_MODE1);
9b53a9e2
YS		 621}
622
623static void disable_lcdc(struct fb_info *info)
624{
9b53a9e2 625 struct mfb_info *mfbi = info->par;
b7795052
TT		 626 struct fsl_diu_data *data = mfbi->parent;
627 struct diu __iomem *hw = data->diu_reg;
9b53a9e2 628
d397e916 629 out_be32(&hw->diu_mode, 0);
9b53a9e2
YS		 630}
631
632static void adjust_aoi_size_position(struct fb_var_screeninfo *var,
633 struct fb_info *info)
634{
635 struct mfb_info *lower_aoi_mfbi, *upper_aoi_mfbi, *mfbi = info->par;
b7795052 636 struct fsl_diu_data *data = mfbi->parent;
2572df91
TT		 637 int available_height, upper_aoi_bottom;
638 enum mfb_index index = mfbi->index;
9b53a9e2
YS		 639 int lower_aoi_is_open, upper_aoi_is_open;
640 __u32 base_plane_width, base_plane_height, upper_aoi_height;
641
b7795052
TT		 642 base_plane_width = data->fsl_diu_info[0].var.xres;
643 base_plane_height = data->fsl_diu_info[0].var.yres;
9b53a9e2 644
fdfaa483
YS		 645 if (mfbi->x_aoi_d < 0)
646 mfbi->x_aoi_d = 0;
647 if (mfbi->y_aoi_d < 0)
648 mfbi->y_aoi_d = 0;
9b53a9e2 649 switch (index) {
2572df91 650 case PLANE0:
9b53a9e2
YS		 651 if (mfbi->x_aoi_d != 0)
652 mfbi->x_aoi_d = 0;
653 if (mfbi->y_aoi_d != 0)
654 mfbi->y_aoi_d = 0;
655 break;
2572df91
TT		 656 case PLANE1_AOI0:
657 case PLANE2_AOI0:
b7795052 658 lower_aoi_mfbi = data->fsl_diu_info[index+1].par;
9b53a9e2
YS		 659 lower_aoi_is_open = lower_aoi_mfbi->count > 0 ? 1 : 0;
660 if (var->xres > base_plane_width)
661 var->xres = base_plane_width;
662 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
663 mfbi->x_aoi_d = base_plane_width - var->xres;
664
665 if (lower_aoi_is_open)
666 available_height = lower_aoi_mfbi->y_aoi_d;
667 else
668 available_height = base_plane_height;
669 if (var->yres > available_height)
670 var->yres = available_height;
671 if ((mfbi->y_aoi_d + var->yres) > available_height)
672 mfbi->y_aoi_d = available_height - var->yres;
673 break;
2572df91
TT		 674 case PLANE1_AOI1:
675 case PLANE2_AOI1:
b7795052
TT		 676 upper_aoi_mfbi = data->fsl_diu_info[index-1].par;
677 upper_aoi_height = data->fsl_diu_info[index-1].var.yres;
9b53a9e2
YS		 678 upper_aoi_bottom = upper_aoi_mfbi->y_aoi_d + upper_aoi_height;
679 upper_aoi_is_open = upper_aoi_mfbi->count > 0 ? 1 : 0;
680 if (var->xres > base_plane_width)
681 var->xres = base_plane_width;
682 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
683 mfbi->x_aoi_d = base_plane_width - var->xres;
684 if (mfbi->y_aoi_d < 0)
685 mfbi->y_aoi_d = 0;
686 if (upper_aoi_is_open) {
687 if (mfbi->y_aoi_d < upper_aoi_bottom)
688 mfbi->y_aoi_d = upper_aoi_bottom;
689 available_height = base_plane_height
690 - upper_aoi_bottom;
691 } else
692 available_height = base_plane_height;
693 if (var->yres > available_height)
694 var->yres = available_height;
695 if ((mfbi->y_aoi_d + var->yres) > base_plane_height)
696 mfbi->y_aoi_d = base_plane_height - var->yres;
697 break;
698 }
699}
700/*
701 * Checks to see if the hardware supports the state requested by var passed
702 * in. This function does not alter the hardware state! If the var passed in
703 * is slightly off by what the hardware can support then we alter the var
704 * PASSED in to what we can do. If the hardware doesn't support mode change
705 * a -EINVAL will be returned by the upper layers.
706 */
707static int fsl_diu_check_var(struct fb_var_screeninfo *var,
708 struct fb_info *info)
709{
9b53a9e2
YS		 710 if (var->xres_virtual < var->xres)
711 var->xres_virtual = var->xres;
712 if (var->yres_virtual < var->yres)
713 var->yres_virtual = var->yres;
714
715 if (var->xoffset < 0)
716 var->xoffset = 0;
717
718 if (var->yoffset < 0)
719 var->yoffset = 0;
720
721 if (var->xoffset + info->var.xres > info->var.xres_virtual)
722 var->xoffset = info->var.xres_virtual - info->var.xres;
723
724 if (var->yoffset + info->var.yres > info->var.yres_virtual)
725 var->yoffset = info->var.yres_virtual - info->var.yres;
726
727 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
728 (var->bits_per_pixel != 16))
729 var->bits_per_pixel = default_bpp;
730
731 switch (var->bits_per_pixel) {
732 case 16:
733 var->red.length = 5;
734 var->red.offset = 11;
735 var->red.msb_right = 0;
736
737 var->green.length = 6;
738 var->green.offset = 5;
739 var->green.msb_right = 0;
740
741 var->blue.length = 5;
742 var->blue.offset = 0;
743 var->blue.msb_right = 0;
744
745 var->transp.length = 0;
746 var->transp.offset = 0;
747 var->transp.msb_right = 0;
748 break;
749 case 24:
750 var->red.length = 8;
751 var->red.offset = 0;
752 var->red.msb_right = 0;
753
754 var->green.length = 8;
755 var->green.offset = 8;
756 var->green.msb_right = 0;
757
758 var->blue.length = 8;
759 var->blue.offset = 16;
760 var->blue.msb_right = 0;
761
762 var->transp.length = 0;
763 var->transp.offset = 0;
764 var->transp.msb_right = 0;
765 break;
766 case 32:
767 var->red.length = 8;
768 var->red.offset = 16;
769 var->red.msb_right = 0;
770
771 var->green.length = 8;
772 var->green.offset = 8;
773 var->green.msb_right = 0;
774
775 var->blue.length = 8;
776 var->blue.offset = 0;
777 var->blue.msb_right = 0;
778
779 var->transp.length = 8;
780 var->transp.offset = 24;
781 var->transp.msb_right = 0;
782
783 break;
784 }
9b53a9e2
YS		 785
786 var->height = -1;
787 var->width = -1;
788 var->grayscale = 0;
789
790 /* Copy nonstd field to/from sync for fbset usage */
791 var->sync |= var->nonstd;
792 var->nonstd |= var->sync;
793
794 adjust_aoi_size_position(var, info);
795 return 0;
796}
797
798static void set_fix(struct fb_info *info)
799{
800 struct fb_fix_screeninfo *fix = &info->fix;
801 struct fb_var_screeninfo *var = &info->var;
802 struct mfb_info *mfbi = info->par;
803
ec02dd23 804 strncpy(fix->id, mfbi->id, sizeof(fix->id));
9b53a9e2
YS		 805 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
806 fix->type = FB_TYPE_PACKED_PIXELS;
807 fix->accel = FB_ACCEL_NONE;
808 fix->visual = FB_VISUAL_TRUECOLOR;
809 fix->xpanstep = 1;
810 fix->ypanstep = 1;
811}
812
813static void update_lcdc(struct fb_info *info)
814{
815 struct fb_var_screeninfo *var = &info->var;
816 struct mfb_info *mfbi = info->par;
b7795052 817 struct fsl_diu_data *data = mfbi->parent;
3c755b7c 818 struct diu __iomem *hw;
9b53a9e2 819 int i, j;
ddd3d905 820 u8 *gamma_table_base;
9b53a9e2
YS		 821
822 u32 temp;
823
b7795052 824 hw = data->diu_reg;
9b53a9e2 825
b7795052
TT		 826 diu_ops.set_monitor_port(data->monitor_port);
827 gamma_table_base = data->gamma;
ddd3d905 828
9b53a9e2
YS		 829 /* Prep for DIU init - gamma table, cursor table */
830
831 for (i = 0; i <= 2; i++)
4a85dc8b
TT		 832 for (j = 0; j <= 255; j++)
833 *gamma_table_base++ = j;
9b53a9e2 834
e09a8c3a
TT		 835 if (diu_ops.set_gamma_table)
836 diu_ops.set_gamma_table(data->monitor_port, data->gamma);
9b53a9e2 837
9b53a9e2
YS		 838 disable_lcdc(info);
839
840 /* Program DIU registers */
841
b7795052
TT		 842 out_be32(&hw->gamma, DMA_ADDR(data, gamma));
843 out_be32(&hw->cursor, DMA_ADDR(data, cursor));
9b53a9e2
YS		 844
845 out_be32(&hw->bgnd, 0x007F7F7F); /* BGND */
846 out_be32(&hw->bgnd_wb, 0); /* BGND_WB */
847 out_be32(&hw->disp_size, (var->yres << 16 | var->xres));
848 /* DISP SIZE */
9b53a9e2
YS		 849 out_be32(&hw->wb_size, 0); /* WB SIZE */
850 out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */
851
852 /* Horizontal and vertical configuration register */
853 temp = var->left_margin << 22 | /* BP_H */
854 var->hsync_len << 11 | /* PW_H */
855 var->right_margin; /* FP_H */
856
857 out_be32(&hw->hsyn_para, temp);
858
859 temp = var->upper_margin << 22 | /* BP_V */
860 var->vsync_len << 11 | /* PW_V */
861 var->lower_margin; /* FP_V */
862
863 out_be32(&hw->vsyn_para, temp);
864
9b53a9e2
YS		 865 diu_ops.set_pixel_clock(var->pixclock);
866
867 out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */
868 out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */
869 out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */
870 out_be32(&hw->plut, 0x01F5F666);
871
872 /* Enable the DIU */
873 enable_lcdc(info);
874}
875
876static int map_video_memory(struct fb_info *info)
877{
878 phys_addr_t phys;
537a1bf0 879 u32 smem_len = info->fix.line_length * info->var.yres_virtual;
9b53a9e2 880
537a1bf0 881 info->screen_base = fsl_diu_alloc(smem_len, &phys);
05946bce 882 if (info->screen_base == NULL) {
154152ae 883 dev_err(info->dev, "unable to allocate fb memory\n");
9b53a9e2
YS		 884 return -ENOMEM;
885 }
537a1bf0 886 mutex_lock(&info->mm_lock);
9b53a9e2 887 info->fix.smem_start = (unsigned long) phys;
537a1bf0
KH		 888 info->fix.smem_len = smem_len;
889 mutex_unlock(&info->mm_lock);
9b53a9e2
YS		 890 info->screen_size = info->fix.smem_len;
891
9b53a9e2
YS		 892 return 0;
893}
894
895static void unmap_video_memory(struct fb_info *info)
896{
897 fsl_diu_free(info->screen_base, info->fix.smem_len);
537a1bf0 898 mutex_lock(&info->mm_lock);
05946bce 899 info->screen_base = NULL;
9b53a9e2
YS		 900 info->fix.smem_start = 0;
901 info->fix.smem_len = 0;
537a1bf0 902 mutex_unlock(&info->mm_lock);
9b53a9e2
YS		 903}
904
ae5591e3
YS		 905/*
906 * Using the fb_var_screeninfo in fb_info we set the aoi of this
907 * particular framebuffer. It is a light version of fsl_diu_set_par.
908 */
909static int fsl_diu_set_aoi(struct fb_info *info)
910{
911 struct fb_var_screeninfo *var = &info->var;
912 struct mfb_info *mfbi = info->par;
913 struct diu_ad *ad = mfbi->ad;
914
915 /* AOI should not be greater than display size */
916 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
917 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
918 return 0;
919}
920
e09a8c3a
TT		 921/**
922 * fsl_diu_get_pixel_format: return the pixel format for a given color depth
923 *
924 * The pixel format is a 32-bit value that determine which bits in each
925 * pixel are to be used for each color. This is the default function used
926 * if the platform does not define its own version.
927 */
928static u32 fsl_diu_get_pixel_format(unsigned int bits_per_pixel)
929{
930#define PF_BYTE_F 0x10000000
931#define PF_ALPHA_C_MASK 0x0E000000
932#define PF_ALPHA_C_SHIFT 25
933#define PF_BLUE_C_MASK 0x01800000
934#define PF_BLUE_C_SHIFT 23
935#define PF_GREEN_C_MASK 0x00600000
936#define PF_GREEN_C_SHIFT 21
937#define PF_RED_C_MASK 0x00180000
938#define PF_RED_C_SHIFT 19
939#define PF_PALETTE 0x00040000
940#define PF_PIXEL_S_MASK 0x00030000
941#define PF_PIXEL_S_SHIFT 16
942#define PF_COMP_3_MASK 0x0000F000
943#define PF_COMP_3_SHIFT 12
944#define PF_COMP_2_MASK 0x00000F00
945#define PF_COMP_2_SHIFT 8
946#define PF_COMP_1_MASK 0x000000F0
947#define PF_COMP_1_SHIFT 4
948#define PF_COMP_0_MASK 0x0000000F
949#define PF_COMP_0_SHIFT 0
950
951#define MAKE_PF(alpha, red, blue, green, size, c0, c1, c2, c3) \
952 cpu_to_le32(PF_BYTE_F | (alpha << PF_ALPHA_C_SHIFT) | \
953 (blue << PF_BLUE_C_SHIFT) | (green << PF_GREEN_C_SHIFT) | \
954 (red << PF_RED_C_SHIFT) | (c3 << PF_COMP_3_SHIFT) | \
955 (c2 << PF_COMP_2_SHIFT) | (c1 << PF_COMP_1_SHIFT) | \
956 (c0 << PF_COMP_0_SHIFT) | (size << PF_PIXEL_S_SHIFT))
957
958 switch (bits_per_pixel) {
959 case 32:
960 /* 0x88883316 */
961 return MAKE_PF(3, 2, 0, 1, 3, 8, 8, 8, 8);
962 case 24:
963 /* 0x88082219 */
964 return MAKE_PF(4, 0, 1, 2, 2, 0, 8, 8, 8);
965 case 16:
966 /* 0x65053118 */
967 return MAKE_PF(4, 2, 1, 0, 1, 5, 6, 5, 0);
968 default:
969 pr_err("fsl-diu: unsupported color depth %u\n", bits_per_pixel);
970 return 0;
971 }
972}
973
9b53a9e2
YS		 974/*
975 * Using the fb_var_screeninfo in fb_info we set the resolution of this
976 * particular framebuffer. This function alters the fb_fix_screeninfo stored
977 * in fb_info. It does not alter var in fb_info since we are using that
978 * data. This means we depend on the data in var inside fb_info to be
979 * supported by the hardware. fsl_diu_check_var is always called before
980 * fsl_diu_set_par to ensure this.
981 */
982static int fsl_diu_set_par(struct fb_info *info)
983{
984 unsigned long len;
985 struct fb_var_screeninfo *var = &info->var;
986 struct mfb_info *mfbi = info->par;
b7795052 987 struct fsl_diu_data *data = mfbi->parent;
9b53a9e2 988 struct diu_ad *ad = mfbi->ad;
3c755b7c 989 struct diu __iomem *hw;
9b53a9e2 990
b7795052 991 hw = data->diu_reg;
9b53a9e2
YS		 992
993 set_fix(info);
994 mfbi->cursor_reset = 1;
995
996 len = info->var.yres_virtual * info->fix.line_length;
997 /* Alloc & dealloc each time resolution/bpp change */
998 if (len != info->fix.smem_len) {
999 if (info->fix.smem_start)
1000 unmap_video_memory(info);
9b53a9e2
YS		 1001
1002 /* Memory allocation for framebuffer */
1003 if (map_video_memory(info)) {
154152ae 1004 dev_err(info->dev, "unable to allocate fb memory 1\n");
9b53a9e2
YS		 1005 return -ENOMEM;
1006 }
1007 }
1008
e09a8c3a
TT		 1009 if (diu_ops.get_pixel_format)
1010 ad->pix_fmt = diu_ops.get_pixel_format(data->monitor_port,
1011 var->bits_per_pixel);
1012 else
1013 ad->pix_fmt = fsl_diu_get_pixel_format(var->bits_per_pixel);
1014
9b53a9e2 1015 ad->addr = cpu_to_le32(info->fix.smem_start);
ae5591e3
YS		 1016 ad->src_size_g_alpha = cpu_to_le32((var->yres_virtual << 12) |
1017 var->xres_virtual) | mfbi->g_alpha;
1018 /* AOI should not be greater than display size */
9b53a9e2 1019 ad->aoi_size = cpu_to_le32((var->yres << 16) | var->xres);
ae5591e3 1020 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
9b53a9e2
YS		 1021 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
1022
1023 /* Disable chroma keying function */
1024 ad->ckmax_r = 0;
1025 ad->ckmax_g = 0;
1026 ad->ckmax_b = 0;
1027
1028 ad->ckmin_r = 255;
1029 ad->ckmin_g = 255;
1030 ad->ckmin_b = 255;
1031
2572df91 1032 if (mfbi->index == PLANE0)
9b53a9e2
YS		 1033 update_lcdc(info);
1034 return 0;
1035}
1036
1037static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
1038{
4a85dc8b 1039 return ((val << width) + 0x7FFF - val) >> 16;
9b53a9e2
YS		 1040}
1041
1042/*
1043 * Set a single color register. The values supplied have a 16 bit magnitude
1044 * which needs to be scaled in this function for the hardware. Things to take
1045 * into consideration are how many color registers, if any, are supported with
1046 * the current color visual. With truecolor mode no color palettes are
25985edc 1047 * supported. Here a pseudo palette is created which we store the value in
9b53a9e2
YS		 1048 * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited
1049 * color palette.
1050 */
4a85dc8b
TT		 1051static int fsl_diu_setcolreg(unsigned int regno, unsigned int red,
1052 unsigned int green, unsigned int blue,
1053 unsigned int transp, struct fb_info *info)
9b53a9e2
YS		 1054{
1055 int ret = 1;
1056
1057 /*
1058 * If greyscale is true, then we convert the RGB value
1059 * to greyscale no matter what visual we are using.
1060 */
1061 if (info->var.grayscale)
1062 red = green = blue = (19595 * red + 38470 * green +
1063 7471 * blue) >> 16;
1064 switch (info->fix.visual) {
1065 case FB_VISUAL_TRUECOLOR:
1066 /*
1067 * 16-bit True Colour. We encode the RGB value
1068 * according to the RGB bitfield information.
1069 */
1070 if (regno < 16) {
1071 u32 *pal = info->pseudo_palette;
1072 u32 v;
1073
1074 red = CNVT_TOHW(red, info->var.red.length);
1075 green = CNVT_TOHW(green, info->var.green.length);
1076 blue = CNVT_TOHW(blue, info->var.blue.length);
1077 transp = CNVT_TOHW(transp, info->var.transp.length);
1078
1079 v = (red << info->var.red.offset) |
1080 (green << info->var.green.offset) |
1081 (blue << info->var.blue.offset) |
1082 (transp << info->var.transp.offset);
1083
1084 pal[regno] = v;
1085 ret = 0;
1086 }
1087 break;
9b53a9e2
YS		 1088 }
1089
1090 return ret;
1091}
1092
1093/*
1094 * Pan (or wrap, depending on the `vmode' field) the display using the
1095 * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values
1096 * don't fit, return -EINVAL.
1097 */
1098static int fsl_diu_pan_display(struct fb_var_screeninfo *var,
1099 struct fb_info *info)
1100{
1101 if ((info->var.xoffset == var->xoffset) &&
1102 (info->var.yoffset == var->yoffset))
1103 return 0; /* No change, do nothing */
1104
1105 if (var->xoffset < 0 || var->yoffset < 0
1106 || var->xoffset + info->var.xres > info->var.xres_virtual
1107 || var->yoffset + info->var.yres > info->var.yres_virtual)
1108 return -EINVAL;
1109
1110 info->var.xoffset = var->xoffset;
1111 info->var.yoffset = var->yoffset;
1112
1113 if (var->vmode & FB_VMODE_YWRAP)
1114 info->var.vmode |= FB_VMODE_YWRAP;
1115 else
1116 info->var.vmode &= ~FB_VMODE_YWRAP;
1117
ae5591e3
YS		 1118 fsl_diu_set_aoi(info);
1119
9b53a9e2
YS		 1120 return 0;
1121}
1122
9b53a9e2
YS		 1123static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd,
1124 unsigned long arg)
1125{
1126 struct mfb_info *mfbi = info->par;
1127 struct diu_ad *ad = mfbi->ad;
1128 struct mfb_chroma_key ck;
1129 unsigned char global_alpha;
1130 struct aoi_display_offset aoi_d;
1131 __u32 pix_fmt;
1132 void __user *buf = (void __user *)arg;
1133
1134 if (!arg)
1135 return -EINVAL;
1136 switch (cmd) {
36b0b1d4
TT		 1137 case MFB_SET_PIXFMT_OLD:
1138 dev_warn(info->dev,
1139 "MFB_SET_PIXFMT value of 0x%08x is deprecated.\n",
1140 MFB_SET_PIXFMT_OLD);
9b53a9e2
YS		 1141 case MFB_SET_PIXFMT:
1142 if (copy_from_user(&pix_fmt, buf, sizeof(pix_fmt)))
1143 return -EFAULT;
1144 ad->pix_fmt = pix_fmt;
9b53a9e2 1145 break;
36b0b1d4
TT		 1146 case MFB_GET_PIXFMT_OLD:
1147 dev_warn(info->dev,
1148 "MFB_GET_PIXFMT value of 0x%08x is deprecated.\n",
1149 MFB_GET_PIXFMT_OLD);
9b53a9e2
YS		 1150 case MFB_GET_PIXFMT:
1151 pix_fmt = ad->pix_fmt;
1152 if (copy_to_user(buf, &pix_fmt, sizeof(pix_fmt)))
1153 return -EFAULT;
9b53a9e2
YS		 1154 break;
1155 case MFB_SET_AOID:
1156 if (copy_from_user(&aoi_d, buf, sizeof(aoi_d)))
1157 return -EFAULT;
1158 mfbi->x_aoi_d = aoi_d.x_aoi_d;
1159 mfbi->y_aoi_d = aoi_d.y_aoi_d;
9b53a9e2 1160 fsl_diu_check_var(&info->var, info);
ae5591e3 1161 fsl_diu_set_aoi(info);
9b53a9e2
YS		 1162 break;
1163 case MFB_GET_AOID:
1164 aoi_d.x_aoi_d = mfbi->x_aoi_d;
1165 aoi_d.y_aoi_d = mfbi->y_aoi_d;
1166 if (copy_to_user(buf, &aoi_d, sizeof(aoi_d)))
1167 return -EFAULT;
9b53a9e2
YS		 1168 break;
1169 case MFB_GET_ALPHA:
1170 global_alpha = mfbi->g_alpha;
1171 if (copy_to_user(buf, &global_alpha, sizeof(global_alpha)))
1172 return -EFAULT;
9b53a9e2
YS		 1173 break;
1174 case MFB_SET_ALPHA:
1175 /* set panel information */
1176 if (copy_from_user(&global_alpha, buf, sizeof(global_alpha)))
1177 return -EFAULT;
1178 ad->src_size_g_alpha = (ad->src_size_g_alpha & (~0xff)) |
1179 (global_alpha & 0xff);
1180 mfbi->g_alpha = global_alpha;
9b53a9e2
YS		 1181 break;
1182 case MFB_SET_CHROMA_KEY:
1183 /* set panel winformation */
1184 if (copy_from_user(&ck, buf, sizeof(ck)))
1185 return -EFAULT;
1186
1187 if (ck.enable &&
1188 (ck.red_max < ck.red_min ||
1189 ck.green_max < ck.green_min ||
1190 ck.blue_max < ck.blue_min))
1191 return -EINVAL;
1192
1193 if (!ck.enable) {
1194 ad->ckmax_r = 0;
1195 ad->ckmax_g = 0;
1196 ad->ckmax_b = 0;
1197 ad->ckmin_r = 255;
1198 ad->ckmin_g = 255;
1199 ad->ckmin_b = 255;
1200 } else {
1201 ad->ckmax_r = ck.red_max;
1202 ad->ckmax_g = ck.green_max;
1203 ad->ckmax_b = ck.blue_max;
1204 ad->ckmin_r = ck.red_min;
1205 ad->ckmin_g = ck.green_min;
1206 ad->ckmin_b = ck.blue_min;
1207 }
9b53a9e2 1208 break;
9b53a9e2 1209 default:
154152ae 1210 dev_err(info->dev, "unknown ioctl command (0x%08X)\n", cmd);
9b53a9e2
YS		 1211 return -ENOIOCTLCMD;
1212 }
1213
1214 return 0;
1215}
1216
1217/* turn on fb if count == 1
1218 */
1219static int fsl_diu_open(struct fb_info *info, int user)
1220{
1221 struct mfb_info *mfbi = info->par;
1222 int res = 0;
1223
4b5006ec 1224 /* free boot splash memory on first /dev/fb0 open */
2572df91 1225 if ((mfbi->index == PLANE0) && diu_ops.release_bootmem)
4b5006ec
AG		 1226 diu_ops.release_bootmem();
1227
9b53a9e2
YS		 1228 spin_lock(&diu_lock);
1229 mfbi->count++;
1230 if (mfbi->count == 1) {
9b53a9e2
YS		 1231 fsl_diu_check_var(&info->var, info);
1232 res = fsl_diu_set_par(info);
1233 if (res < 0)
1234 mfbi->count--;
7e47c211
TT		 1235 else
1236 fsl_diu_enable_panel(info);
9b53a9e2
YS		 1237 }
1238
1239 spin_unlock(&diu_lock);
1240 return res;
1241}
1242
1243/* turn off fb if count == 0
1244 */
1245static int fsl_diu_release(struct fb_info *info, int user)
1246{
1247 struct mfb_info *mfbi = info->par;
1248 int res = 0;
1249
1250 spin_lock(&diu_lock);
1251 mfbi->count--;
2572df91
TT		 1252 if (mfbi->count == 0)
1253 fsl_diu_disable_panel(info);
1254
9b53a9e2
YS		 1255 spin_unlock(&diu_lock);
1256 return res;
1257}
1258
1259static struct fb_ops fsl_diu_ops = {
1260 .owner = THIS_MODULE,
1261 .fb_check_var = fsl_diu_check_var,
1262 .fb_set_par = fsl_diu_set_par,
1263 .fb_setcolreg = fsl_diu_setcolreg,
9b53a9e2
YS		 1264 .fb_pan_display = fsl_diu_pan_display,
1265 .fb_fillrect = cfb_fillrect,
1266 .fb_copyarea = cfb_copyarea,
1267 .fb_imageblit = cfb_imageblit,
1268 .fb_ioctl = fsl_diu_ioctl,
1269 .fb_open = fsl_diu_open,
1270 .fb_release = fsl_diu_release,
1271};
1272
05946bce 1273static int __devinit install_fb(struct fb_info *info)
9b53a9e2
YS		 1274{
1275 int rc;
1276 struct mfb_info *mfbi = info->par;
1277 const char *aoi_mode, *init_aoi_mode = "320x240";
8b856f04
AG		 1278 struct fb_videomode *db = fsl_diu_mode_db;
1279 unsigned int dbsize = ARRAY_SIZE(fsl_diu_mode_db);
1280 int has_default_mode = 1;
9b53a9e2 1281
f934fbd6
TT		 1282 info->var.activate = FB_ACTIVATE_NOW;
1283 info->fbops = &fsl_diu_ops;
934dbeeb
TT		 1284 info->flags = FBINFO_DEFAULT | FBINFO_VIRTFB | FBINFO_PARTIAL_PAN_OK |
1285 FBINFO_READS_FAST;
f934fbd6
TT		 1286 info->pseudo_palette = mfbi->pseudo_palette;
1287
1288 rc = fb_alloc_cmap(&info->cmap, 16, 0);
1289 if (rc)
1290 return rc;
9b53a9e2 1291
2572df91 1292 if (mfbi->index == PLANE0) {
8b856f04
AG		 1293 if (mfbi->edid_data) {
1294 /* Now build modedb from EDID */
1295 fb_edid_to_monspecs(mfbi->edid_data, &info->monspecs);
1296 fb_videomode_to_modelist(info->monspecs.modedb,
1297 info->monspecs.modedb_len,
1298 &info->modelist);
1299 db = info->monspecs.modedb;
1300 dbsize = info->monspecs.modedb_len;
1301 }
9b53a9e2 1302 aoi_mode = fb_mode;
8b856f04 1303 } else {
9b53a9e2 1304 aoi_mode = init_aoi_mode;
8b856f04 1305 }
63cf8df4
TT		 1306 rc = fb_find_mode(&info->var, info, aoi_mode, db, dbsize, NULL,
1307 default_bpp);
154152ae 1308 if (!rc) {
8b856f04
AG		 1309 /*
1310 * For plane 0 we continue and look into
1311 * driver's internal modedb.
1312 */
2572df91 1313 if ((mfbi->index == PLANE0) && mfbi->edid_data)
8b856f04
AG		 1314 has_default_mode = 0;
1315 else
1316 return -EINVAL;
9b53a9e2
YS		 1317 }
1318
8b856f04
AG		 1319 if (!has_default_mode) {
1320 rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
63cf8df4
TT		 1321 ARRAY_SIZE(fsl_diu_mode_db), NULL, default_bpp);
1322 if (rc)
8b856f04
AG		 1323 has_default_mode = 1;
1324 }
1325
1326 /* Still not found, use preferred mode from database if any */
1327 if (!has_default_mode && info->monspecs.modedb) {
1328 struct fb_monspecs *specs = &info->monspecs;
1329 struct fb_videomode *modedb = &specs->modedb[0];
1330
1331 /*
1332 * Get preferred timing. If not found,
1333 * first mode in database will be used.
1334 */
1335 if (specs->misc & FB_MISC_1ST_DETAIL) {
1336 int i;
1337
1338 for (i = 0; i < specs->modedb_len; i++) {
1339 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1340 modedb = &specs->modedb[i];
1341 break;
1342 }
1343 }
1344 }
1345
1346 info->var.bits_per_pixel = default_bpp;
1347 fb_videomode_to_var(&info->var, modedb);
1348 }
1349
9b53a9e2 1350 if (fsl_diu_check_var(&info->var, info)) {
154152ae 1351 dev_err(info->dev, "fsl_diu_check_var failed\n");
589c7971 1352 unmap_video_memory(info);
9b53a9e2
YS		 1353 fb_dealloc_cmap(&info->cmap);
1354 return -EINVAL;
1355 }
1356
9b53a9e2 1357 if (register_framebuffer(info) < 0) {
154152ae 1358 dev_err(info->dev, "register_framebuffer failed\n");
9b53a9e2
YS		 1359 unmap_video_memory(info);
1360 fb_dealloc_cmap(&info->cmap);
1361 return -EINVAL;
1362 }
1363
1364 mfbi->registered = 1;
154152ae 1365 dev_info(info->dev, "%s registered successfully\n", mfbi->id);
9b53a9e2
YS		 1366
1367 return 0;
1368}
1369
05946bce 1370static void uninstall_fb(struct fb_info *info)
9b53a9e2
YS		 1371{
1372 struct mfb_info *mfbi = info->par;
1373
1374 if (!mfbi->registered)
1375 return;
1376
2572df91 1377 if (mfbi->index == PLANE0)
8b856f04
AG		 1378 kfree(mfbi->edid_data);
1379
9b53a9e2
YS		 1380 unregister_framebuffer(info);
1381 unmap_video_memory(info);
1382 if (&info->cmap)
1383 fb_dealloc_cmap(&info->cmap);
1384
1385 mfbi->registered = 0;
1386}
1387
1388static irqreturn_t fsl_diu_isr(int irq, void *dev_id)
1389{
3c755b7c 1390 struct diu __iomem *hw = dev_id;
9b53a9e2
YS		 1391 unsigned int status = in_be32(&hw->int_status);
1392
1393 if (status) {
1394 /* This is the workaround for underrun */
1395 if (status & INT_UNDRUN) {
1396 out_be32(&hw->diu_mode, 0);
9b53a9e2
YS		 1397 udelay(1);
1398 out_be32(&hw->diu_mode, 1);
1399 }
1400#if defined(CONFIG_NOT_COHERENT_CACHE)
1401 else if (status & INT_VSYNC) {
1402 unsigned int i;
4a85dc8b 1403
9b53a9e2
YS		 1404 for (i = 0; i < coherence_data_size;
1405 i += d_cache_line_size)
1406 __asm__ __volatile__ (
1407 "dcbz 0, %[input]"
1408 ::[input]"r"(&coherence_data[i]));
1409 }
1410#endif
1411 return IRQ_HANDLED;
1412 }
1413 return IRQ_NONE;
1414}
1415
b7795052 1416static int request_irq_local(struct fsl_diu_data *data)
9b53a9e2 1417{
b7795052 1418 struct diu __iomem *hw = data->diu_reg;
bada04fc 1419 u32 ints;
9b53a9e2
YS		 1420 int ret;
1421
9b53a9e2 1422 /* Read to clear the status */
bada04fc 1423 in_be32(&hw->int_status);
9b53a9e2 1424
b7795052 1425 ret = request_irq(data->irq, fsl_diu_isr, 0, "fsl-diu-fb", hw);
154152ae 1426 if (!ret) {
9b53a9e2
YS		 1427 ints = INT_PARERR | INT_LS_BF_VS;
1428#if !defined(CONFIG_NOT_COHERENT_CACHE)
1429 ints |= INT_VSYNC;
1430#endif
4a85dc8b 1431
9b53a9e2 1432 /* Read to clear the status */
bada04fc 1433 in_be32(&hw->int_status);
9b53a9e2
YS		 1434 out_be32(&hw->int_mask, ints);
1435 }
4a85dc8b 1436
9b53a9e2
YS		 1437 return ret;
1438}
1439
b7795052 1440static void free_irq_local(struct fsl_diu_data *data)
9b53a9e2 1441{
b7795052 1442 struct diu __iomem *hw = data->diu_reg;
9b53a9e2
YS		 1443
1444 /* Disable all LCDC interrupt */
1445 out_be32(&hw->int_mask, 0x1f);
1446
b7795052 1447 free_irq(data->irq, NULL);
9b53a9e2
YS		 1448}
1449
1450#ifdef CONFIG_PM
1451/*
1452 * Power management hooks. Note that we won't be called from IRQ context,
1453 * unlike the blank functions above, so we may sleep.
1454 */
2dc11581 1455static int fsl_diu_suspend(struct platform_device *ofdev, pm_message_t state)
9b53a9e2 1456{
b7795052 1457 struct fsl_diu_data *data;
9b53a9e2 1458
b7795052
TT		 1459 data = dev_get_drvdata(&ofdev->dev);
1460 disable_lcdc(data->fsl_diu_info[0]);
9b53a9e2
YS		 1461
1462 return 0;
1463}
1464
2dc11581 1465static int fsl_diu_resume(struct platform_device *ofdev)
9b53a9e2 1466{
b7795052 1467 struct fsl_diu_data *data;
9b53a9e2 1468
b7795052
TT		 1469 data = dev_get_drvdata(&ofdev->dev);
1470 enable_lcdc(data->fsl_diu_info[0]);
9b53a9e2
YS		 1471
1472 return 0;
1473}
1474
1475#else
1476#define fsl_diu_suspend NULL
1477#define fsl_diu_resume NULL
1478#endif /* CONFIG_PM */
1479
9b53a9e2
YS		 1480static ssize_t store_monitor(struct device *device,
1481 struct device_attribute *attr, const char *buf, size_t count)
1482{
7653aaab 1483 enum fsl_diu_monitor_port old_monitor_port;
b7795052 1484 struct fsl_diu_data *data =
9b53a9e2
YS		 1485 container_of(attr, struct fsl_diu_data, dev_attr);
1486
b7795052
TT		 1487 old_monitor_port = data->monitor_port;
1488 data->monitor_port = fsl_diu_name_to_port(buf);
9b53a9e2 1489
b7795052 1490 if (old_monitor_port != data->monitor_port) {
9b53a9e2
YS		 1491 /* All AOIs need adjust pixel format
1492 * fsl_diu_set_par only change the pixsel format here
1493 * unlikely to fail. */
ddd3d905
TT		 1494 unsigned int i;
1495
1496 for (i=0; i < NUM_AOIS; i++)
b7795052 1497 fsl_diu_set_par(&data->fsl_diu_info[i]);
9b53a9e2
YS		 1498 }
1499 return count;
1500}
1501
1502static ssize_t show_monitor(struct device *device,
1503 struct device_attribute *attr, char *buf)
1504{
b7795052 1505 struct fsl_diu_data *data =
9b53a9e2 1506 container_of(attr, struct fsl_diu_data, dev_attr);
7653aaab 1507
b7795052 1508 switch (data->monitor_port) {
7653aaab
TT		 1509 case FSL_DIU_PORT_DVI:
1510 return sprintf(buf, "DVI\n");
1511 case FSL_DIU_PORT_LVDS:
1512 return sprintf(buf, "Single-link LVDS\n");
1513 case FSL_DIU_PORT_DLVDS:
1514 return sprintf(buf, "Dual-link LVDS\n");
1515 }
1516
1517 return 0;
9b53a9e2
YS		 1518}
1519
9e52ba61 1520static int __devinit fsl_diu_probe(struct platform_device *pdev)
9b53a9e2 1521{
9e52ba61 1522 struct device_node *np = pdev->dev.of_node;
9b53a9e2 1523 struct mfb_info *mfbi;
b7795052 1524 struct fsl_diu_data *data;
4b5006ec 1525 int diu_mode;
b7795052 1526 dma_addr_t dma_addr; /* DMA addr of fsl_diu_data struct */
ddd3d905
TT		 1527 unsigned int i;
1528 int ret;
9b53a9e2 1529
b7795052
TT		 1530 data = dma_alloc_coherent(&pdev->dev, sizeof(struct fsl_diu_data),
1531 &dma_addr, GFP_DMA | __GFP_ZERO);
1532 if (!data)
9b53a9e2 1533 return -ENOMEM;
b7795052 1534 data->dma_addr = dma_addr;
ddd3d905
TT		 1535
1536 /*
1537 * dma_alloc_coherent() uses a page allocator, so the address is
1538 * always page-aligned. We need the memory to be 32-byte aligned,
1539 * so that's good. However, if one day the allocator changes, we
1540 * need to catch that. It's not worth the effort to handle unaligned
1541 * alloctions now because it's highly unlikely to ever be a problem.
1542 */
b7795052 1543 if ((unsigned long)data & 31) {
ddd3d905
TT		 1544 dev_err(&pdev->dev, "misaligned allocation");
1545 ret = -ENOMEM;
1546 goto error;
1547 }
9b53a9e2 1548
b7795052 1549 spin_lock_init(&data->reg_lock);
3c755b7c 1550
ddd3d905 1551 for (i = 0; i < NUM_AOIS; i++) {
b7795052 1552 struct fb_info *info = &data->fsl_diu_info[i];
ddd3d905
TT		 1553
1554 info->device = &pdev->dev;
b7795052 1555 info->par = &data->mfb[i];
ddd3d905
TT		 1556
1557 /*
1558 * We store the physical address of the AD in the reserved
1559 * 'paddr' field of the AD itself.
1560 */
b7795052 1561 data->ad[i].paddr = DMA_ADDR(data, ad[i]);
ddd3d905
TT		 1562
1563 info->fix.smem_start = 0;
1564
1565 /* Initialize the AOI data structure */
1566 mfbi = info->par;
9b53a9e2 1567 memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info));
b7795052
TT		 1568 mfbi->parent = data;
1569 mfbi->ad = &data->ad[i];
8b856f04 1570
2572df91 1571 if (mfbi->index == PLANE0) {
8b856f04
AG		 1572 const u8 *prop;
1573 int len;
1574
1575 /* Get EDID */
1576 prop = of_get_property(np, "edid", &len);
1577 if (prop && len == EDID_LENGTH)
1578 mfbi->edid_data = kmemdup(prop, EDID_LENGTH,
1579 GFP_KERNEL);
1580 }
9b53a9e2
YS		 1581 }
1582
b7795052
TT		 1583 data->diu_reg = of_iomap(np, 0);
1584 if (!data->diu_reg) {
9e52ba61 1585 dev_err(&pdev->dev, "cannot map DIU registers\n");
9b53a9e2 1586 ret = -EFAULT;
ddd3d905 1587 goto error;
9b53a9e2
YS		 1588 }
1589
b7795052 1590 diu_mode = in_be32(&data->diu_reg->diu_mode);
c4e5a023 1591 if (diu_mode == MFB_MODE0)
b7795052 1592 out_be32(&data->diu_reg->diu_mode, 0); /* disable DIU */
9b53a9e2
YS		 1593
1594 /* Get the IRQ of the DIU */
b7795052 1595 data->irq = irq_of_parse_and_map(np, 0);
9b53a9e2 1596
b7795052 1597 if (!data->irq) {
9e52ba61 1598 dev_err(&pdev->dev, "could not get DIU IRQ\n");
9b53a9e2
YS		 1599 ret = -EINVAL;
1600 goto error;
1601 }
b7795052 1602 data->monitor_port = monitor_port;
9b53a9e2 1603
ddd3d905 1604 /* Initialize the dummy Area Descriptor */
b7795052
TT		 1605 data->dummy_ad.addr = cpu_to_le32(DMA_ADDR(data, dummy_aoi));
1606 data->dummy_ad.pix_fmt = 0x88882317;
1607 data->dummy_ad.src_size_g_alpha = cpu_to_le32((4 << 12) | 4);
1608 data->dummy_ad.aoi_size = cpu_to_le32((4 << 16) | 2);
1609 data->dummy_ad.offset_xyi = 0;
1610 data->dummy_ad.offset_xyd = 0;
1611 data->dummy_ad.next_ad = 0;
1612 data->dummy_ad.paddr = DMA_ADDR(data, dummy_ad);
9b53a9e2 1613
4b5006ec
AG		 1614 /*
1615 * Let DIU display splash screen if it was pre-initialized
1616 * by the bootloader, set dummy area descriptor otherwise.
1617 */
c4e5a023 1618 if (diu_mode == MFB_MODE0)
b7795052 1619 out_be32(&data->diu_reg->desc[0], data->dummy_ad.paddr);
ddd3d905 1620
b7795052
TT		 1621 out_be32(&data->diu_reg->desc[1], data->dummy_ad.paddr);
1622 out_be32(&data->diu_reg->desc[2], data->dummy_ad.paddr);
ddd3d905
TT		 1623
1624 for (i = 0; i < NUM_AOIS; i++) {
b7795052 1625 ret = install_fb(&data->fsl_diu_info[i]);
9b53a9e2 1626 if (ret) {
9e52ba61 1627 dev_err(&pdev->dev, "could not register fb %d\n", i);
9b53a9e2
YS		 1628 goto error;
1629 }
1630 }
1631
b7795052 1632 if (request_irq_local(data)) {
9e52ba61 1633 dev_err(&pdev->dev, "could not claim irq\n");
9b53a9e2
YS		 1634 goto error;
1635 }
1636
b7795052
TT		 1637 sysfs_attr_init(&data->dev_attr.attr);
1638 data->dev_attr.attr.name = "monitor";
1639 data->dev_attr.attr.mode = S_IRUGO|S_IWUSR;
1640 data->dev_attr.show = show_monitor;
1641 data->dev_attr.store = store_monitor;
1642 ret = device_create_file(&pdev->dev, &data->dev_attr);
ddd3d905 1643 if (ret) {
9e52ba61 1644 dev_err(&pdev->dev, "could not create sysfs file %s\n",
b7795052 1645 data->dev_attr.attr.name);
9b53a9e2
YS		 1646 }
1647
b7795052 1648 dev_set_drvdata(&pdev->dev, data);
9b53a9e2
YS		 1649 return 0;
1650
1651error:
ddd3d905 1652 for (i = 0; i < NUM_AOIS; i++)
b7795052 1653 uninstall_fb(&data->fsl_diu_info[i]);
ddd3d905 1654
b7795052 1655 iounmap(data->diu_reg);
9b53a9e2 1656
b7795052
TT		 1657 dma_free_coherent(&pdev->dev, sizeof(struct fsl_diu_data), data,
1658 data->dma_addr);
9b53a9e2
YS		 1659
1660 return ret;
1661}
1662
9e52ba61 1663static int fsl_diu_remove(struct platform_device *pdev)
9b53a9e2 1664{
b7795052 1665 struct fsl_diu_data *data;
9b53a9e2
YS		 1666 int i;
1667
b7795052
TT		 1668 data = dev_get_drvdata(&pdev->dev);
1669 disable_lcdc(&data->fsl_diu_info[0]);
1670 free_irq_local(data);
ddd3d905
TT		 1671
1672 for (i = 0; i < NUM_AOIS; i++)
b7795052 1673 uninstall_fb(&data->fsl_diu_info[i]);
ddd3d905 1674
b7795052 1675 iounmap(data->diu_reg);
ddd3d905 1676
b7795052
TT		 1677 dma_free_coherent(&pdev->dev, sizeof(struct fsl_diu_data), data,
1678 data->dma_addr);
9b53a9e2
YS		 1679
1680 return 0;
1681}
1682
1683#ifndef MODULE
1684static int __init fsl_diu_setup(char *options)
1685{
1686 char *opt;
1687 unsigned long val;
1688
1689 if (!options || !*options)
1690 return 0;
1691
1692 while ((opt = strsep(&options, ",")) != NULL) {
1693 if (!*opt)
1694 continue;
1695 if (!strncmp(opt, "monitor=", 8)) {
7653aaab 1696 monitor_port = fsl_diu_name_to_port(opt + 8);
9b53a9e2
YS		 1697 } else if (!strncmp(opt, "bpp=", 4)) {
1698 if (!strict_strtoul(opt + 4, 10, &val))
1699 default_bpp = val;
1700 } else
1701 fb_mode = opt;
1702 }
1703
1704 return 0;
1705}
1706#endif
1707
1708static struct of_device_id fsl_diu_match[] = {
d24720a4
AG		 1709#ifdef CONFIG_PPC_MPC512x
1710 {
1711 .compatible = "fsl,mpc5121-diu",
1712 },
1713#endif
9b53a9e2
YS		 1714 {
1715 .compatible = "fsl,diu",
1716 },
1717 {}
1718};
1719MODULE_DEVICE_TABLE(of, fsl_diu_match);
1720
28541d0f 1721static struct platform_driver fsl_diu_driver = {
4018294b 1722 .driver = {
f8c6bf6a 1723 .name = "fsl-diu-fb",
4018294b
GL		 1724 .owner = THIS_MODULE,
1725 .of_match_table = fsl_diu_match,
1726 },
9b53a9e2
YS		 1727 .probe = fsl_diu_probe,
1728 .remove = fsl_diu_remove,
1729 .suspend = fsl_diu_suspend,
1730 .resume = fsl_diu_resume,
1731};
1732
1733static int __init fsl_diu_init(void)
1734{
1735#ifdef CONFIG_NOT_COHERENT_CACHE
1736 struct device_node *np;
1737 const u32 *prop;
1738#endif
1739 int ret;
1740#ifndef MODULE
1741 char *option;
1742
1743 /*
1744 * For kernel boot options (in 'video=xxxfb:<options>' format)
1745 */
1746 if (fb_get_options("fslfb", &option))
1747 return -ENODEV;
1748 fsl_diu_setup(option);
7653aaab
TT		 1749#else
1750 monitor_port = fsl_diu_name_to_port(monitor_string);
9b53a9e2 1751#endif
154152ae 1752 pr_info("Freescale Display Interface Unit (DIU) framebuffer driver\n");
9b53a9e2
YS		 1753
1754#ifdef CONFIG_NOT_COHERENT_CACHE
1755 np = of_find_node_by_type(NULL, "cpu");
1756 if (!np) {
154152ae 1757 pr_err("fsl-diu-fb: can't find 'cpu' device node\n");
9b53a9e2
YS		 1758 return -ENODEV;
1759 }
1760
1761 prop = of_get_property(np, "d-cache-size", NULL);
5394ba0f 1762 if (prop == NULL) {
154152ae
TT		 1763 pr_err("fsl-diu-fb: missing 'd-cache-size' property' "
1764 "in 'cpu' node\n");
5394ba0f 1765 of_node_put(np);
9b53a9e2 1766 return -ENODEV;
5394ba0f 1767 }
9b53a9e2 1768
4a85dc8b
TT		 1769 /*
1770 * Freescale PLRU requires 13/8 times the cache size to do a proper
1771 * displacement flush
9b53a9e2 1772 */
9e52ba61 1773 coherence_data_size = be32_to_cpup(prop) * 13;
9b53a9e2
YS		 1774 coherence_data_size /= 8;
1775
1776 prop = of_get_property(np, "d-cache-line-size", NULL);
5394ba0f 1777 if (prop == NULL) {
154152ae
TT		 1778 pr_err("fsl-diu-fb: missing 'd-cache-line-size' property' "
1779 "in 'cpu' node\n");
5394ba0f 1780 of_node_put(np);
9b53a9e2 1781 return -ENODEV;
5394ba0f 1782 }
9e52ba61 1783 d_cache_line_size = be32_to_cpup(prop);
9b53a9e2
YS		 1784
1785 of_node_put(np);
1786 coherence_data = vmalloc(coherence_data_size);
1787 if (!coherence_data)
1788 return -ENOMEM;
1789#endif
4a85dc8b 1790
28541d0f 1791 ret = platform_driver_register(&fsl_diu_driver);
9b53a9e2 1792 if (ret) {
154152ae 1793 pr_err("fsl-diu-fb: failed to register platform driver\n");
9b53a9e2
YS		 1794#if defined(CONFIG_NOT_COHERENT_CACHE)
1795 vfree(coherence_data);
1796#endif
9b53a9e2
YS		 1797 }
1798 return ret;
1799}
1800
1801static void __exit fsl_diu_exit(void)
1802{
28541d0f 1803 platform_driver_unregister(&fsl_diu_driver);
9b53a9e2
YS		 1804#if defined(CONFIG_NOT_COHERENT_CACHE)
1805 vfree(coherence_data);
1806#endif
1807}
1808
1809module_init(fsl_diu_init);
1810module_exit(fsl_diu_exit);
1811
1812MODULE_AUTHOR("York Sun <yorksun@freescale.com>");
1813MODULE_DESCRIPTION("Freescale DIU framebuffer driver");
1814MODULE_LICENSE("GPL");
1815
1816module_param_named(mode, fb_mode, charp, 0);
1817MODULE_PARM_DESC(mode,
1818 "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
1819module_param_named(bpp, default_bpp, ulong, 0);
154152ae 1820MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified in 'mode'");
7653aaab
TT		 1821module_param_named(monitor, monitor_string, charp, 0);
1822MODULE_PARM_DESC(monitor, "Specify the monitor port "
1823 "(\"dvi\", \"lvds\", or \"dlvds\") if supported by the platform");
9b53a9e2 1824
kernel source for telekom puls (alcatel/mediatek)