Commit | Line | Data |
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4ed824d9 SR |
1 | /* |
2 | * Copyright (C) 2008-2009 MontaVista Software Inc. | |
3 | * Copyright (C) 2008-2009 Texas Instruments Inc | |
4 | * | |
5 | * Based on the LCD driver for TI Avalanche processors written by | |
6 | * Ajay Singh and Shalom Hai. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option)any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #include <linux/module.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/fb.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/uaccess.h> | |
9dd44d5d | 29 | #include <linux/pm_runtime.h> |
4ed824d9 | 30 | #include <linux/interrupt.h> |
a481b37a | 31 | #include <linux/wait.h> |
4ed824d9 | 32 | #include <linux/clk.h> |
e04e5483 | 33 | #include <linux/cpufreq.h> |
1d3c6c7b | 34 | #include <linux/console.h> |
deb95c6c | 35 | #include <linux/spinlock.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
a0239073 | 37 | #include <linux/delay.h> |
3b9cc4ea | 38 | #include <linux/lcm.h> |
4ed824d9 | 39 | #include <video/da8xx-fb.h> |
12fa8350 | 40 | #include <asm/div64.h> |
4ed824d9 SR |
41 | |
42 | #define DRIVER_NAME "da8xx_lcdc" | |
43 | ||
c6daf05b MP |
44 | #define LCD_VERSION_1 1 |
45 | #define LCD_VERSION_2 2 | |
46 | ||
4ed824d9 | 47 | /* LCD Status Register */ |
1f9c3e1f | 48 | #define LCD_END_OF_FRAME1 BIT(9) |
4ed824d9 | 49 | #define LCD_END_OF_FRAME0 BIT(8) |
1f9c3e1f | 50 | #define LCD_PL_LOAD_DONE BIT(6) |
4ed824d9 SR |
51 | #define LCD_FIFO_UNDERFLOW BIT(5) |
52 | #define LCD_SYNC_LOST BIT(2) | |
a481b37a | 53 | #define LCD_FRAME_DONE BIT(0) |
4ed824d9 SR |
54 | |
55 | /* LCD DMA Control Register */ | |
56 | #define LCD_DMA_BURST_SIZE(x) ((x) << 4) | |
57 | #define LCD_DMA_BURST_1 0x0 | |
58 | #define LCD_DMA_BURST_2 0x1 | |
59 | #define LCD_DMA_BURST_4 0x2 | |
60 | #define LCD_DMA_BURST_8 0x3 | |
61 | #define LCD_DMA_BURST_16 0x4 | |
c6daf05b MP |
62 | #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) |
63 | #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) | |
64 | #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) | |
4ed824d9 SR |
65 | #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) |
66 | ||
67 | /* LCD Control Register */ | |
68 | #define LCD_CLK_DIVISOR(x) ((x) << 8) | |
69 | #define LCD_RASTER_MODE 0x01 | |
70 | ||
71 | /* LCD Raster Control Register */ | |
72 | #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) | |
73 | #define PALETTE_AND_DATA 0x00 | |
74 | #define PALETTE_ONLY 0x01 | |
1f9c3e1f | 75 | #define DATA_ONLY 0x02 |
4ed824d9 SR |
76 | |
77 | #define LCD_MONO_8BIT_MODE BIT(9) | |
78 | #define LCD_RASTER_ORDER BIT(8) | |
79 | #define LCD_TFT_MODE BIT(7) | |
c6daf05b MP |
80 | #define LCD_V1_UNDERFLOW_INT_ENA BIT(6) |
81 | #define LCD_V2_UNDERFLOW_INT_ENA BIT(5) | |
82 | #define LCD_V1_PL_INT_ENA BIT(4) | |
83 | #define LCD_V2_PL_INT_ENA BIT(6) | |
4ed824d9 SR |
84 | #define LCD_MONOCHROME_MODE BIT(1) |
85 | #define LCD_RASTER_ENABLE BIT(0) | |
86 | #define LCD_TFT_ALT_ENABLE BIT(23) | |
87 | #define LCD_STN_565_ENABLE BIT(24) | |
c6daf05b MP |
88 | #define LCD_V2_DMA_CLK_EN BIT(2) |
89 | #define LCD_V2_LIDD_CLK_EN BIT(1) | |
90 | #define LCD_V2_CORE_CLK_EN BIT(0) | |
91 | #define LCD_V2_LPP_B10 26 | |
1a2b750c MP |
92 | #define LCD_V2_TFT_24BPP_MODE BIT(25) |
93 | #define LCD_V2_TFT_24BPP_UNPACK BIT(26) | |
4ed824d9 SR |
94 | |
95 | /* LCD Raster Timing 2 Register */ | |
96 | #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) | |
97 | #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) | |
98 | #define LCD_SYNC_CTRL BIT(25) | |
99 | #define LCD_SYNC_EDGE BIT(24) | |
100 | #define LCD_INVERT_PIXEL_CLOCK BIT(22) | |
101 | #define LCD_INVERT_LINE_CLOCK BIT(21) | |
102 | #define LCD_INVERT_FRAME_CLOCK BIT(20) | |
103 | ||
104 | /* LCD Block */ | |
c6daf05b | 105 | #define LCD_PID_REG 0x0 |
4ed824d9 SR |
106 | #define LCD_CTRL_REG 0x4 |
107 | #define LCD_STAT_REG 0x8 | |
108 | #define LCD_RASTER_CTRL_REG 0x28 | |
109 | #define LCD_RASTER_TIMING_0_REG 0x2C | |
110 | #define LCD_RASTER_TIMING_1_REG 0x30 | |
111 | #define LCD_RASTER_TIMING_2_REG 0x34 | |
112 | #define LCD_DMA_CTRL_REG 0x40 | |
113 | #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44 | |
114 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48 | |
1f9c3e1f MA |
115 | #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C |
116 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50 | |
117 | ||
c6daf05b MP |
118 | /* Interrupt Registers available only in Version 2 */ |
119 | #define LCD_RAW_STAT_REG 0x58 | |
120 | #define LCD_MASKED_STAT_REG 0x5c | |
121 | #define LCD_INT_ENABLE_SET_REG 0x60 | |
122 | #define LCD_INT_ENABLE_CLR_REG 0x64 | |
123 | #define LCD_END_OF_INT_IND_REG 0x68 | |
124 | ||
125 | /* Clock registers available only on Version 2 */ | |
126 | #define LCD_CLK_ENABLE_REG 0x6c | |
127 | #define LCD_CLK_RESET_REG 0x70 | |
74a0efde | 128 | #define LCD_CLK_MAIN_RESET BIT(3) |
c6daf05b | 129 | |
1f9c3e1f | 130 | #define LCD_NUM_BUFFERS 2 |
4ed824d9 SR |
131 | |
132 | #define WSI_TIMEOUT 50 | |
133 | #define PALETTE_SIZE 256 | |
134 | #define LEFT_MARGIN 64 | |
135 | #define RIGHT_MARGIN 64 | |
136 | #define UPPER_MARGIN 32 | |
137 | #define LOWER_MARGIN 32 | |
138 | ||
34aef6eb | 139 | static void __iomem *da8xx_fb_reg_base; |
4ed824d9 | 140 | static struct resource *lcdc_regs; |
c6daf05b MP |
141 | static unsigned int lcd_revision; |
142 | static irq_handler_t lcdc_irq_handler; | |
a481b37a MP |
143 | static wait_queue_head_t frame_done_wq; |
144 | static int frame_done_flag; | |
4ed824d9 SR |
145 | |
146 | static inline unsigned int lcdc_read(unsigned int addr) | |
147 | { | |
148 | return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr)); | |
149 | } | |
150 | ||
151 | static inline void lcdc_write(unsigned int val, unsigned int addr) | |
152 | { | |
153 | __raw_writel(val, da8xx_fb_reg_base + (addr)); | |
154 | } | |
155 | ||
156 | struct da8xx_fb_par { | |
4ed824d9 SR |
157 | resource_size_t p_palette_base; |
158 | unsigned char *v_palette_base; | |
1f9c3e1f MA |
159 | dma_addr_t vram_phys; |
160 | unsigned long vram_size; | |
161 | void *vram_virt; | |
162 | unsigned int dma_start; | |
163 | unsigned int dma_end; | |
4ed824d9 SR |
164 | struct clk *lcdc_clk; |
165 | int irq; | |
4ed824d9 | 166 | unsigned int palette_sz; |
8097b174 | 167 | unsigned int pxl_clk; |
36113804 | 168 | int blank; |
1f9c3e1f MA |
169 | wait_queue_head_t vsync_wait; |
170 | int vsync_flag; | |
171 | int vsync_timeout; | |
deb95c6c MP |
172 | spinlock_t lock_for_chan_update; |
173 | ||
174 | /* | |
175 | * LCDC has 2 ping pong DMA channels, channel 0 | |
176 | * and channel 1. | |
177 | */ | |
178 | unsigned int which_dma_channel_done; | |
e04e5483 C |
179 | #ifdef CONFIG_CPU_FREQ |
180 | struct notifier_block freq_transition; | |
f820917a | 181 | unsigned int lcd_fck_rate; |
e04e5483 | 182 | #endif |
36113804 | 183 | void (*panel_power_ctrl)(int); |
1a2b750c | 184 | u32 pseudo_palette[16]; |
4ed824d9 SR |
185 | }; |
186 | ||
187 | /* Variable Screen Information */ | |
48c68c4f | 188 | static struct fb_var_screeninfo da8xx_fb_var = { |
4ed824d9 SR |
189 | .xoffset = 0, |
190 | .yoffset = 0, | |
191 | .transp = {0, 0, 0}, | |
192 | .nonstd = 0, | |
193 | .activate = 0, | |
194 | .height = -1, | |
195 | .width = -1, | |
4ed824d9 SR |
196 | .accel_flags = 0, |
197 | .left_margin = LEFT_MARGIN, | |
198 | .right_margin = RIGHT_MARGIN, | |
199 | .upper_margin = UPPER_MARGIN, | |
200 | .lower_margin = LOWER_MARGIN, | |
201 | .sync = 0, | |
202 | .vmode = FB_VMODE_NONINTERLACED | |
203 | }; | |
204 | ||
48c68c4f | 205 | static struct fb_fix_screeninfo da8xx_fb_fix = { |
4ed824d9 SR |
206 | .id = "DA8xx FB Drv", |
207 | .type = FB_TYPE_PACKED_PIXELS, | |
208 | .type_aux = 0, | |
209 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
1f9c3e1f | 210 | .xpanstep = 0, |
4ed824d9 | 211 | .ypanstep = 1, |
1f9c3e1f | 212 | .ywrapstep = 0, |
4ed824d9 SR |
213 | .accel = FB_ACCEL_NONE |
214 | }; | |
215 | ||
f772fabd | 216 | static struct fb_videomode known_lcd_panels[] = { |
4ed824d9 SR |
217 | /* Sharp LCD035Q3DG01 */ |
218 | [0] = { | |
f772fabd MP |
219 | .name = "Sharp_LCD035Q3DG01", |
220 | .xres = 320, | |
221 | .yres = 240, | |
222 | .pixclock = 4608000, | |
223 | .left_margin = 6, | |
224 | .right_margin = 8, | |
225 | .upper_margin = 2, | |
226 | .lower_margin = 2, | |
227 | .hsync_len = 0, | |
228 | .vsync_len = 0, | |
fe1ff215 | 229 | .sync = FB_SYNC_CLK_INVERT, |
4ed824d9 SR |
230 | }, |
231 | /* Sharp LK043T1DG01 */ | |
232 | [1] = { | |
f772fabd MP |
233 | .name = "Sharp_LK043T1DG01", |
234 | .xres = 480, | |
235 | .yres = 272, | |
236 | .pixclock = 7833600, | |
237 | .left_margin = 2, | |
238 | .right_margin = 2, | |
239 | .upper_margin = 2, | |
240 | .lower_margin = 2, | |
241 | .hsync_len = 41, | |
242 | .vsync_len = 10, | |
fe1ff215 | 243 | .sync = 0, |
f772fabd | 244 | .flag = 0, |
4ed824d9 | 245 | }, |
f413070e AG |
246 | [2] = { |
247 | /* Hitachi SP10Q010 */ | |
f772fabd MP |
248 | .name = "SP10Q010", |
249 | .xres = 320, | |
250 | .yres = 240, | |
251 | .pixclock = 7833600, | |
252 | .left_margin = 10, | |
253 | .right_margin = 10, | |
254 | .upper_margin = 10, | |
255 | .lower_margin = 10, | |
256 | .hsync_len = 10, | |
257 | .vsync_len = 10, | |
fe1ff215 | 258 | .sync = 0, |
f772fabd | 259 | .flag = 0, |
f413070e | 260 | }, |
4ed824d9 SR |
261 | }; |
262 | ||
36113804 C |
263 | /* Enable the Raster Engine of the LCD Controller */ |
264 | static inline void lcd_enable_raster(void) | |
265 | { | |
266 | u32 reg; | |
267 | ||
92b4e450 MP |
268 | /* Put LCDC in reset for several cycles */ |
269 | if (lcd_revision == LCD_VERSION_2) | |
270 | /* Write 1 to reset LCDC */ | |
271 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
272 | mdelay(1); | |
273 | ||
74a0efde MP |
274 | /* Bring LCDC out of reset */ |
275 | if (lcd_revision == LCD_VERSION_2) | |
276 | lcdc_write(0, LCD_CLK_RESET_REG); | |
92b4e450 | 277 | mdelay(1); |
74a0efde | 278 | |
92b4e450 | 279 | /* Above reset sequence doesnot reset register context */ |
36113804 C |
280 | reg = lcdc_read(LCD_RASTER_CTRL_REG); |
281 | if (!(reg & LCD_RASTER_ENABLE)) | |
282 | lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); | |
283 | } | |
284 | ||
4ed824d9 | 285 | /* Disable the Raster Engine of the LCD Controller */ |
a481b37a | 286 | static inline void lcd_disable_raster(bool wait_for_frame_done) |
4ed824d9 | 287 | { |
4ed824d9 | 288 | u32 reg; |
a481b37a | 289 | int ret; |
4ed824d9 SR |
290 | |
291 | reg = lcdc_read(LCD_RASTER_CTRL_REG); | |
2f93e8f4 | 292 | if (reg & LCD_RASTER_ENABLE) |
4ed824d9 | 293 | lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); |
a481b37a MP |
294 | else |
295 | /* return if already disabled */ | |
296 | return; | |
297 | ||
298 | if ((wait_for_frame_done == true) && (lcd_revision == LCD_VERSION_2)) { | |
299 | frame_done_flag = 0; | |
300 | ret = wait_event_interruptible_timeout(frame_done_wq, | |
301 | frame_done_flag != 0, | |
302 | msecs_to_jiffies(50)); | |
303 | if (ret == 0) | |
304 | pr_err("LCD Controller timed out\n"); | |
305 | } | |
4ed824d9 SR |
306 | } |
307 | ||
308 | static void lcd_blit(int load_mode, struct da8xx_fb_par *par) | |
309 | { | |
1f9c3e1f MA |
310 | u32 start; |
311 | u32 end; | |
312 | u32 reg_ras; | |
313 | u32 reg_dma; | |
c6daf05b | 314 | u32 reg_int; |
1f9c3e1f MA |
315 | |
316 | /* init reg to clear PLM (loading mode) fields */ | |
317 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
318 | reg_ras &= ~(3 << 20); | |
319 | ||
320 | reg_dma = lcdc_read(LCD_DMA_CTRL_REG); | |
321 | ||
322 | if (load_mode == LOAD_DATA) { | |
323 | start = par->dma_start; | |
324 | end = par->dma_end; | |
325 | ||
326 | reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); | |
c6daf05b MP |
327 | if (lcd_revision == LCD_VERSION_1) { |
328 | reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; | |
329 | } else { | |
330 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
331 | LCD_V2_END_OF_FRAME0_INT_ENA | | |
a481b37a MP |
332 | LCD_V2_END_OF_FRAME1_INT_ENA | |
333 | LCD_FRAME_DONE; | |
c6daf05b MP |
334 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); |
335 | } | |
1f9c3e1f MA |
336 | reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; |
337 | ||
338 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
339 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
340 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
341 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
342 | } else if (load_mode == LOAD_PALETTE) { | |
343 | start = par->p_palette_base; | |
344 | end = start + par->palette_sz - 1; | |
345 | ||
346 | reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); | |
c6daf05b MP |
347 | |
348 | if (lcd_revision == LCD_VERSION_1) { | |
349 | reg_ras |= LCD_V1_PL_INT_ENA; | |
350 | } else { | |
351 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
352 | LCD_V2_PL_INT_ENA; | |
353 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
354 | } | |
1f9c3e1f MA |
355 | |
356 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
357 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
358 | } | |
4ed824d9 | 359 | |
1f9c3e1f MA |
360 | lcdc_write(reg_dma, LCD_DMA_CTRL_REG); |
361 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); | |
4ed824d9 | 362 | |
1f9c3e1f MA |
363 | /* |
364 | * The Raster enable bit must be set after all other control fields are | |
365 | * set. | |
366 | */ | |
367 | lcd_enable_raster(); | |
4ed824d9 SR |
368 | } |
369 | ||
fb8fa943 MP |
370 | /* Configure the Burst Size and fifo threhold of DMA */ |
371 | static int lcd_cfg_dma(int burst_size, int fifo_th) | |
4ed824d9 SR |
372 | { |
373 | u32 reg; | |
374 | ||
375 | reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001; | |
376 | switch (burst_size) { | |
377 | case 1: | |
378 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); | |
379 | break; | |
380 | case 2: | |
381 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); | |
382 | break; | |
383 | case 4: | |
384 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); | |
385 | break; | |
386 | case 8: | |
387 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); | |
388 | break; | |
389 | case 16: | |
3b43ad20 | 390 | default: |
4ed824d9 SR |
391 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); |
392 | break; | |
4ed824d9 | 393 | } |
fb8fa943 MP |
394 | |
395 | reg |= (fifo_th << 8); | |
396 | ||
2f93e8f4 | 397 | lcdc_write(reg, LCD_DMA_CTRL_REG); |
4ed824d9 SR |
398 | |
399 | return 0; | |
400 | } | |
401 | ||
402 | static void lcd_cfg_ac_bias(int period, int transitions_per_int) | |
403 | { | |
404 | u32 reg; | |
405 | ||
406 | /* Set the AC Bias Period and Number of Transisitons per Interrupt */ | |
407 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000; | |
408 | reg |= LCD_AC_BIAS_FREQUENCY(period) | | |
409 | LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); | |
410 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
411 | } | |
412 | ||
413 | static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, | |
414 | int front_porch) | |
415 | { | |
416 | u32 reg; | |
417 | ||
418 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf; | |
419 | reg |= ((back_porch & 0xff) << 24) | |
420 | | ((front_porch & 0xff) << 16) | |
421 | | ((pulse_width & 0x3f) << 10); | |
422 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); | |
423 | } | |
424 | ||
425 | static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, | |
426 | int front_porch) | |
427 | { | |
428 | u32 reg; | |
429 | ||
430 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff; | |
431 | reg |= ((back_porch & 0xff) << 24) | |
432 | | ((front_porch & 0xff) << 16) | |
433 | | ((pulse_width & 0x3f) << 10); | |
434 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
435 | } | |
436 | ||
3b43ad20 MP |
437 | static int lcd_cfg_display(const struct lcd_ctrl_config *cfg, |
438 | struct fb_videomode *panel) | |
4ed824d9 SR |
439 | { |
440 | u32 reg; | |
c6daf05b | 441 | u32 reg_int; |
4ed824d9 SR |
442 | |
443 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE | | |
444 | LCD_MONO_8BIT_MODE | | |
445 | LCD_MONOCHROME_MODE); | |
446 | ||
3b43ad20 | 447 | switch (cfg->panel_shade) { |
4ed824d9 SR |
448 | case MONOCHROME: |
449 | reg |= LCD_MONOCHROME_MODE; | |
450 | if (cfg->mono_8bit_mode) | |
451 | reg |= LCD_MONO_8BIT_MODE; | |
452 | break; | |
453 | case COLOR_ACTIVE: | |
454 | reg |= LCD_TFT_MODE; | |
455 | if (cfg->tft_alt_mode) | |
456 | reg |= LCD_TFT_ALT_ENABLE; | |
457 | break; | |
458 | ||
459 | case COLOR_PASSIVE: | |
3b43ad20 MP |
460 | /* AC bias applicable only for Pasive panels */ |
461 | lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); | |
462 | if (cfg->bpp == 12 && cfg->stn_565_mode) | |
4ed824d9 SR |
463 | reg |= LCD_STN_565_ENABLE; |
464 | break; | |
465 | ||
466 | default: | |
467 | return -EINVAL; | |
468 | } | |
469 | ||
470 | /* enable additional interrupts here */ | |
c6daf05b MP |
471 | if (lcd_revision == LCD_VERSION_1) { |
472 | reg |= LCD_V1_UNDERFLOW_INT_ENA; | |
473 | } else { | |
474 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
475 | LCD_V2_UNDERFLOW_INT_ENA; | |
476 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
477 | } | |
4ed824d9 SR |
478 | |
479 | lcdc_write(reg, LCD_RASTER_CTRL_REG); | |
480 | ||
481 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
482 | ||
3b43ad20 | 483 | reg |= LCD_SYNC_CTRL; |
4ed824d9 SR |
484 | |
485 | if (cfg->sync_edge) | |
486 | reg |= LCD_SYNC_EDGE; | |
487 | else | |
488 | reg &= ~LCD_SYNC_EDGE; | |
489 | ||
3b43ad20 | 490 | if (panel->sync & FB_SYNC_HOR_HIGH_ACT) |
4ed824d9 SR |
491 | reg |= LCD_INVERT_LINE_CLOCK; |
492 | else | |
493 | reg &= ~LCD_INVERT_LINE_CLOCK; | |
494 | ||
3b43ad20 | 495 | if (panel->sync & FB_SYNC_VERT_HIGH_ACT) |
4ed824d9 SR |
496 | reg |= LCD_INVERT_FRAME_CLOCK; |
497 | else | |
498 | reg &= ~LCD_INVERT_FRAME_CLOCK; | |
499 | ||
500 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
501 | ||
502 | return 0; | |
503 | } | |
504 | ||
505 | static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, | |
506 | u32 bpp, u32 raster_order) | |
507 | { | |
1f9c3e1f | 508 | u32 reg; |
4ed824d9 | 509 | |
1a2b750c MP |
510 | if (bpp > 16 && lcd_revision == LCD_VERSION_1) |
511 | return -EINVAL; | |
512 | ||
4ed824d9 SR |
513 | /* Set the Panel Width */ |
514 | /* Pixels per line = (PPL + 1)*16 */ | |
4d740801 MP |
515 | if (lcd_revision == LCD_VERSION_1) { |
516 | /* | |
517 | * 0x3F in bits 4..9 gives max horizontal resolution = 1024 | |
518 | * pixels. | |
519 | */ | |
520 | width &= 0x3f0; | |
521 | } else { | |
522 | /* | |
523 | * 0x7F in bits 4..10 gives max horizontal resolution = 2048 | |
524 | * pixels. | |
525 | */ | |
526 | width &= 0x7f0; | |
527 | } | |
528 | ||
4ed824d9 SR |
529 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG); |
530 | reg &= 0xfffffc00; | |
4d740801 MP |
531 | if (lcd_revision == LCD_VERSION_1) { |
532 | reg |= ((width >> 4) - 1) << 4; | |
533 | } else { | |
534 | width = (width >> 4) - 1; | |
535 | reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); | |
536 | } | |
4ed824d9 SR |
537 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); |
538 | ||
539 | /* Set the Panel Height */ | |
4d740801 | 540 | /* Set bits 9:0 of Lines Per Pixel */ |
4ed824d9 SR |
541 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG); |
542 | reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); | |
543 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
544 | ||
4d740801 MP |
545 | /* Set bit 10 of Lines Per Pixel */ |
546 | if (lcd_revision == LCD_VERSION_2) { | |
547 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
548 | reg |= ((height - 1) & 0x400) << 16; | |
549 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
550 | } | |
551 | ||
4ed824d9 SR |
552 | /* Set the Raster Order of the Frame Buffer */ |
553 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8); | |
554 | if (raster_order) | |
555 | reg |= LCD_RASTER_ORDER; | |
1a2b750c MP |
556 | |
557 | par->palette_sz = 16 * 2; | |
4ed824d9 SR |
558 | |
559 | switch (bpp) { | |
560 | case 1: | |
561 | case 2: | |
562 | case 4: | |
563 | case 16: | |
1a2b750c MP |
564 | break; |
565 | case 24: | |
566 | reg |= LCD_V2_TFT_24BPP_MODE; | |
567 | case 32: | |
568 | reg |= LCD_V2_TFT_24BPP_UNPACK; | |
4ed824d9 SR |
569 | break; |
570 | ||
571 | case 8: | |
572 | par->palette_sz = 256 * 2; | |
573 | break; | |
574 | ||
575 | default: | |
576 | return -EINVAL; | |
577 | } | |
578 | ||
1a2b750c MP |
579 | lcdc_write(reg, LCD_RASTER_CTRL_REG); |
580 | ||
4ed824d9 SR |
581 | return 0; |
582 | } | |
583 | ||
1a2b750c | 584 | #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) |
4ed824d9 SR |
585 | static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, |
586 | unsigned blue, unsigned transp, | |
587 | struct fb_info *info) | |
588 | { | |
589 | struct da8xx_fb_par *par = info->par; | |
1f9c3e1f | 590 | unsigned short *palette = (unsigned short *) par->v_palette_base; |
4ed824d9 | 591 | u_short pal; |
1f9c3e1f | 592 | int update_hw = 0; |
4ed824d9 SR |
593 | |
594 | if (regno > 255) | |
595 | return 1; | |
596 | ||
597 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) | |
598 | return 1; | |
599 | ||
1a2b750c MP |
600 | if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
601 | return -EINVAL; | |
f413070e | 602 | |
1a2b750c MP |
603 | switch (info->fix.visual) { |
604 | case FB_VISUAL_TRUECOLOR: | |
605 | red = CNVT_TOHW(red, info->var.red.length); | |
606 | green = CNVT_TOHW(green, info->var.green.length); | |
607 | blue = CNVT_TOHW(blue, info->var.blue.length); | |
608 | break; | |
609 | case FB_VISUAL_PSEUDOCOLOR: | |
610 | switch (info->var.bits_per_pixel) { | |
611 | case 4: | |
612 | if (regno > 15) | |
613 | return -EINVAL; | |
614 | ||
615 | if (info->var.grayscale) { | |
616 | pal = regno; | |
617 | } else { | |
618 | red >>= 4; | |
619 | green >>= 8; | |
620 | blue >>= 12; | |
621 | ||
622 | pal = red & 0x0f00; | |
623 | pal |= green & 0x00f0; | |
624 | pal |= blue & 0x000f; | |
625 | } | |
626 | if (regno == 0) | |
627 | pal |= 0x2000; | |
628 | palette[regno] = pal; | |
629 | break; | |
630 | ||
631 | case 8: | |
f413070e AG |
632 | red >>= 4; |
633 | green >>= 8; | |
634 | blue >>= 12; | |
635 | ||
636 | pal = (red & 0x0f00); | |
637 | pal |= (green & 0x00f0); | |
638 | pal |= (blue & 0x000f); | |
4ed824d9 | 639 | |
1a2b750c MP |
640 | if (palette[regno] != pal) { |
641 | update_hw = 1; | |
642 | palette[regno] = pal; | |
643 | } | |
644 | break; | |
1f9c3e1f | 645 | } |
1a2b750c MP |
646 | break; |
647 | } | |
4ed824d9 | 648 | |
1a2b750c MP |
649 | /* Truecolor has hardware independent palette */ |
650 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { | |
651 | u32 v; | |
4ed824d9 | 652 | |
1a2b750c MP |
653 | if (regno > 15) |
654 | return -EINVAL; | |
4ed824d9 | 655 | |
1a2b750c MP |
656 | v = (red << info->var.red.offset) | |
657 | (green << info->var.green.offset) | | |
658 | (blue << info->var.blue.offset); | |
4ed824d9 | 659 | |
1a2b750c MP |
660 | switch (info->var.bits_per_pixel) { |
661 | case 16: | |
662 | ((u16 *) (info->pseudo_palette))[regno] = v; | |
663 | break; | |
664 | case 24: | |
665 | case 32: | |
666 | ((u32 *) (info->pseudo_palette))[regno] = v; | |
667 | break; | |
668 | } | |
1f9c3e1f MA |
669 | if (palette[0] != 0x4000) { |
670 | update_hw = 1; | |
671 | palette[0] = 0x4000; | |
672 | } | |
4ed824d9 SR |
673 | } |
674 | ||
1f9c3e1f MA |
675 | /* Update the palette in the h/w as needed. */ |
676 | if (update_hw) | |
677 | lcd_blit(LOAD_PALETTE, par); | |
678 | ||
4ed824d9 SR |
679 | return 0; |
680 | } | |
1a2b750c | 681 | #undef CNVT_TOHW |
4ed824d9 | 682 | |
2f93e8f4 | 683 | static void lcd_reset(struct da8xx_fb_par *par) |
4ed824d9 | 684 | { |
4ed824d9 | 685 | /* Disable the Raster if previously Enabled */ |
a481b37a | 686 | lcd_disable_raster(false); |
4ed824d9 SR |
687 | |
688 | /* DMA has to be disabled */ | |
689 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
690 | lcdc_write(0, LCD_RASTER_CTRL_REG); | |
c6daf05b | 691 | |
74a0efde | 692 | if (lcd_revision == LCD_VERSION_2) { |
c6daf05b | 693 | lcdc_write(0, LCD_INT_ENABLE_SET_REG); |
74a0efde MP |
694 | /* Write 1 to reset */ |
695 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
696 | lcdc_write(0, LCD_CLK_RESET_REG); | |
697 | } | |
4ed824d9 SR |
698 | } |
699 | ||
8097b174 C |
700 | static void lcd_calc_clk_divider(struct da8xx_fb_par *par) |
701 | { | |
702 | unsigned int lcd_clk, div; | |
703 | ||
704 | lcd_clk = clk_get_rate(par->lcdc_clk); | |
705 | div = lcd_clk / par->pxl_clk; | |
706 | ||
707 | /* Configure the LCD clock divisor. */ | |
708 | lcdc_write(LCD_CLK_DIVISOR(div) | | |
709 | (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG); | |
c6daf05b MP |
710 | |
711 | if (lcd_revision == LCD_VERSION_2) | |
712 | lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | | |
713 | LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG); | |
714 | ||
8097b174 C |
715 | } |
716 | ||
4ed824d9 | 717 | static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, |
f772fabd | 718 | struct fb_videomode *panel) |
4ed824d9 SR |
719 | { |
720 | u32 bpp; | |
721 | int ret = 0; | |
722 | ||
2f93e8f4 | 723 | lcd_reset(par); |
4ed824d9 | 724 | |
8097b174 C |
725 | /* Calculate the divider */ |
726 | lcd_calc_clk_divider(par); | |
4ed824d9 | 727 | |
f772fabd | 728 | if (panel->sync & FB_SYNC_CLK_INVERT) |
2f93e8f4 SR |
729 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) | |
730 | LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
731 | else | |
732 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) & | |
733 | ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
734 | ||
fb8fa943 MP |
735 | /* Configure the DMA burst size and fifo threshold. */ |
736 | ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th); | |
4ed824d9 SR |
737 | if (ret < 0) |
738 | return ret; | |
739 | ||
4ed824d9 | 740 | /* Configure the vertical and horizontal sync properties. */ |
f772fabd MP |
741 | lcd_cfg_vertical_sync(panel->lower_margin, panel->vsync_len, |
742 | panel->upper_margin); | |
743 | lcd_cfg_horizontal_sync(panel->right_margin, panel->hsync_len, | |
744 | panel->left_margin); | |
4ed824d9 SR |
745 | |
746 | /* Configure for disply */ | |
3b43ad20 | 747 | ret = lcd_cfg_display(cfg, panel); |
4ed824d9 SR |
748 | if (ret < 0) |
749 | return ret; | |
750 | ||
3b43ad20 | 751 | bpp = cfg->bpp; |
4ed824d9 | 752 | |
4ed824d9 SR |
753 | if (bpp == 12) |
754 | bpp = 16; | |
f772fabd MP |
755 | ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres, |
756 | (unsigned int)panel->yres, bpp, | |
4ed824d9 SR |
757 | cfg->raster_order); |
758 | if (ret < 0) | |
759 | return ret; | |
760 | ||
761 | /* Configure FDD */ | |
762 | lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) | | |
763 | (cfg->fdd << 12), LCD_RASTER_CTRL_REG); | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
c6daf05b MP |
768 | /* IRQ handler for version 2 of LCDC */ |
769 | static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) | |
770 | { | |
771 | struct da8xx_fb_par *par = arg; | |
772 | u32 stat = lcdc_read(LCD_MASKED_STAT_REG); | |
c6daf05b MP |
773 | |
774 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
a481b37a | 775 | lcd_disable_raster(false); |
c6daf05b MP |
776 | lcdc_write(stat, LCD_MASKED_STAT_REG); |
777 | lcd_enable_raster(); | |
778 | } else if (stat & LCD_PL_LOAD_DONE) { | |
779 | /* | |
780 | * Must disable raster before changing state of any control bit. | |
781 | * And also must be disabled before clearing the PL loading | |
782 | * interrupt via the following write to the status register. If | |
783 | * this is done after then one gets multiple PL done interrupts. | |
784 | */ | |
a481b37a | 785 | lcd_disable_raster(false); |
c6daf05b MP |
786 | |
787 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
788 | ||
8a81dccd MP |
789 | /* Disable PL completion interrupt */ |
790 | lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG); | |
c6daf05b MP |
791 | |
792 | /* Setup and start data loading mode */ | |
793 | lcd_blit(LOAD_DATA, par); | |
794 | } else { | |
795 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
796 | ||
797 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 798 | par->which_dma_channel_done = 0; |
c6daf05b MP |
799 | lcdc_write(par->dma_start, |
800 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
801 | lcdc_write(par->dma_end, | |
802 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
803 | par->vsync_flag = 1; | |
804 | wake_up_interruptible(&par->vsync_wait); | |
805 | } | |
806 | ||
807 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 808 | par->which_dma_channel_done = 1; |
c6daf05b MP |
809 | lcdc_write(par->dma_start, |
810 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
811 | lcdc_write(par->dma_end, | |
812 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
813 | par->vsync_flag = 1; | |
814 | wake_up_interruptible(&par->vsync_wait); | |
815 | } | |
a481b37a MP |
816 | |
817 | /* Set only when controller is disabled and at the end of | |
818 | * active frame | |
819 | */ | |
820 | if (stat & BIT(0)) { | |
821 | frame_done_flag = 1; | |
822 | wake_up_interruptible(&frame_done_wq); | |
823 | } | |
c6daf05b MP |
824 | } |
825 | ||
826 | lcdc_write(0, LCD_END_OF_INT_IND_REG); | |
827 | return IRQ_HANDLED; | |
828 | } | |
829 | ||
830 | /* IRQ handler for version 1 LCDC */ | |
831 | static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg) | |
4ed824d9 | 832 | { |
1f9c3e1f | 833 | struct da8xx_fb_par *par = arg; |
4ed824d9 | 834 | u32 stat = lcdc_read(LCD_STAT_REG); |
1f9c3e1f | 835 | u32 reg_ras; |
4ed824d9 SR |
836 | |
837 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
a481b37a | 838 | lcd_disable_raster(false); |
4ed824d9 | 839 | lcdc_write(stat, LCD_STAT_REG); |
36113804 | 840 | lcd_enable_raster(); |
1f9c3e1f MA |
841 | } else if (stat & LCD_PL_LOAD_DONE) { |
842 | /* | |
843 | * Must disable raster before changing state of any control bit. | |
844 | * And also must be disabled before clearing the PL loading | |
845 | * interrupt via the following write to the status register. If | |
846 | * this is done after then one gets multiple PL done interrupts. | |
847 | */ | |
a481b37a | 848 | lcd_disable_raster(false); |
1f9c3e1f | 849 | |
4ed824d9 SR |
850 | lcdc_write(stat, LCD_STAT_REG); |
851 | ||
1f9c3e1f MA |
852 | /* Disable PL completion inerrupt */ |
853 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
c6daf05b | 854 | reg_ras &= ~LCD_V1_PL_INT_ENA; |
1f9c3e1f MA |
855 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); |
856 | ||
857 | /* Setup and start data loading mode */ | |
858 | lcd_blit(LOAD_DATA, par); | |
859 | } else { | |
860 | lcdc_write(stat, LCD_STAT_REG); | |
861 | ||
862 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 863 | par->which_dma_channel_done = 0; |
1f9c3e1f MA |
864 | lcdc_write(par->dma_start, |
865 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
866 | lcdc_write(par->dma_end, | |
867 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
868 | par->vsync_flag = 1; | |
869 | wake_up_interruptible(&par->vsync_wait); | |
870 | } | |
871 | ||
872 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 873 | par->which_dma_channel_done = 1; |
1f9c3e1f MA |
874 | lcdc_write(par->dma_start, |
875 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
876 | lcdc_write(par->dma_end, | |
877 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
878 | par->vsync_flag = 1; | |
879 | wake_up_interruptible(&par->vsync_wait); | |
880 | } | |
881 | } | |
882 | ||
4ed824d9 SR |
883 | return IRQ_HANDLED; |
884 | } | |
885 | ||
886 | static int fb_check_var(struct fb_var_screeninfo *var, | |
887 | struct fb_info *info) | |
888 | { | |
889 | int err = 0; | |
890 | ||
1a2b750c MP |
891 | if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
892 | return -EINVAL; | |
893 | ||
4ed824d9 SR |
894 | switch (var->bits_per_pixel) { |
895 | case 1: | |
896 | case 8: | |
897 | var->red.offset = 0; | |
898 | var->red.length = 8; | |
899 | var->green.offset = 0; | |
900 | var->green.length = 8; | |
901 | var->blue.offset = 0; | |
902 | var->blue.length = 8; | |
903 | var->transp.offset = 0; | |
904 | var->transp.length = 0; | |
f413070e | 905 | var->nonstd = 0; |
4ed824d9 SR |
906 | break; |
907 | case 4: | |
908 | var->red.offset = 0; | |
909 | var->red.length = 4; | |
910 | var->green.offset = 0; | |
911 | var->green.length = 4; | |
912 | var->blue.offset = 0; | |
913 | var->blue.length = 4; | |
914 | var->transp.offset = 0; | |
915 | var->transp.length = 0; | |
f413070e | 916 | var->nonstd = FB_NONSTD_REV_PIX_IN_B; |
4ed824d9 SR |
917 | break; |
918 | case 16: /* RGB 565 */ | |
3510b8f7 | 919 | var->red.offset = 11; |
4ed824d9 SR |
920 | var->red.length = 5; |
921 | var->green.offset = 5; | |
922 | var->green.length = 6; | |
3510b8f7 | 923 | var->blue.offset = 0; |
4ed824d9 SR |
924 | var->blue.length = 5; |
925 | var->transp.offset = 0; | |
926 | var->transp.length = 0; | |
f413070e | 927 | var->nonstd = 0; |
4ed824d9 | 928 | break; |
1a2b750c MP |
929 | case 24: |
930 | var->red.offset = 16; | |
931 | var->red.length = 8; | |
932 | var->green.offset = 8; | |
933 | var->green.length = 8; | |
934 | var->blue.offset = 0; | |
935 | var->blue.length = 8; | |
936 | var->nonstd = 0; | |
937 | break; | |
938 | case 32: | |
939 | var->transp.offset = 24; | |
940 | var->transp.length = 8; | |
941 | var->red.offset = 16; | |
942 | var->red.length = 8; | |
943 | var->green.offset = 8; | |
944 | var->green.length = 8; | |
945 | var->blue.offset = 0; | |
946 | var->blue.length = 8; | |
947 | var->nonstd = 0; | |
948 | break; | |
4ed824d9 SR |
949 | default: |
950 | err = -EINVAL; | |
951 | } | |
952 | ||
953 | var->red.msb_right = 0; | |
954 | var->green.msb_right = 0; | |
955 | var->blue.msb_right = 0; | |
956 | var->transp.msb_right = 0; | |
957 | return err; | |
958 | } | |
959 | ||
e04e5483 C |
960 | #ifdef CONFIG_CPU_FREQ |
961 | static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb, | |
962 | unsigned long val, void *data) | |
963 | { | |
964 | struct da8xx_fb_par *par; | |
e04e5483 C |
965 | |
966 | par = container_of(nb, struct da8xx_fb_par, freq_transition); | |
f820917a MP |
967 | if (val == CPUFREQ_POSTCHANGE) { |
968 | if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) { | |
969 | par->lcd_fck_rate = clk_get_rate(par->lcdc_clk); | |
a481b37a | 970 | lcd_disable_raster(true); |
f820917a | 971 | lcd_calc_clk_divider(par); |
67900814 MP |
972 | if (par->blank == FB_BLANK_UNBLANK) |
973 | lcd_enable_raster(); | |
f820917a | 974 | } |
e04e5483 C |
975 | } |
976 | ||
977 | return 0; | |
978 | } | |
979 | ||
980 | static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par) | |
981 | { | |
982 | par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition; | |
983 | ||
984 | return cpufreq_register_notifier(&par->freq_transition, | |
985 | CPUFREQ_TRANSITION_NOTIFIER); | |
986 | } | |
987 | ||
988 | static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par) | |
989 | { | |
990 | cpufreq_unregister_notifier(&par->freq_transition, | |
991 | CPUFREQ_TRANSITION_NOTIFIER); | |
992 | } | |
993 | #endif | |
994 | ||
48c68c4f | 995 | static int fb_remove(struct platform_device *dev) |
4ed824d9 SR |
996 | { |
997 | struct fb_info *info = dev_get_drvdata(&dev->dev); | |
4ed824d9 SR |
998 | |
999 | if (info) { | |
1000 | struct da8xx_fb_par *par = info->par; | |
1001 | ||
e04e5483 C |
1002 | #ifdef CONFIG_CPU_FREQ |
1003 | lcd_da8xx_cpufreq_deregister(par); | |
1004 | #endif | |
36113804 C |
1005 | if (par->panel_power_ctrl) |
1006 | par->panel_power_ctrl(0); | |
1007 | ||
a481b37a | 1008 | lcd_disable_raster(true); |
4ed824d9 SR |
1009 | lcdc_write(0, LCD_RASTER_CTRL_REG); |
1010 | ||
1011 | /* disable DMA */ | |
1012 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
1013 | ||
1014 | unregister_framebuffer(info); | |
1015 | fb_dealloc_cmap(&info->cmap); | |
1f9c3e1f MA |
1016 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, |
1017 | par->p_palette_base); | |
1018 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, | |
1019 | par->vram_phys); | |
4ed824d9 | 1020 | free_irq(par->irq, par); |
9dd44d5d MP |
1021 | pm_runtime_put_sync(&dev->dev); |
1022 | pm_runtime_disable(&dev->dev); | |
4ed824d9 | 1023 | framebuffer_release(info); |
34aef6eb | 1024 | iounmap(da8xx_fb_reg_base); |
4ed824d9 SR |
1025 | release_mem_region(lcdc_regs->start, resource_size(lcdc_regs)); |
1026 | ||
1027 | } | |
2f93e8f4 | 1028 | return 0; |
4ed824d9 SR |
1029 | } |
1030 | ||
1f9c3e1f MA |
1031 | /* |
1032 | * Function to wait for vertical sync which for this LCD peripheral | |
1033 | * translates into waiting for the current raster frame to complete. | |
1034 | */ | |
1035 | static int fb_wait_for_vsync(struct fb_info *info) | |
1036 | { | |
1037 | struct da8xx_fb_par *par = info->par; | |
1038 | int ret; | |
1039 | ||
1040 | /* | |
1041 | * Set flag to 0 and wait for isr to set to 1. It would seem there is a | |
25985edc | 1042 | * race condition here where the ISR could have occurred just before or |
1f9c3e1f MA |
1043 | * just after this set. But since we are just coarsely waiting for |
1044 | * a frame to complete then that's OK. i.e. if the frame completed | |
1045 | * just before this code executed then we have to wait another full | |
1046 | * frame time but there is no way to avoid such a situation. On the | |
1047 | * other hand if the frame completed just after then we don't need | |
1048 | * to wait long at all. Either way we are guaranteed to return to the | |
1049 | * user immediately after a frame completion which is all that is | |
1050 | * required. | |
1051 | */ | |
1052 | par->vsync_flag = 0; | |
1053 | ret = wait_event_interruptible_timeout(par->vsync_wait, | |
1054 | par->vsync_flag != 0, | |
1055 | par->vsync_timeout); | |
1056 | if (ret < 0) | |
1057 | return ret; | |
1058 | if (ret == 0) | |
1059 | return -ETIMEDOUT; | |
1060 | ||
1061 | return 0; | |
1062 | } | |
1063 | ||
4ed824d9 SR |
1064 | static int fb_ioctl(struct fb_info *info, unsigned int cmd, |
1065 | unsigned long arg) | |
1066 | { | |
1067 | struct lcd_sync_arg sync_arg; | |
1068 | ||
1069 | switch (cmd) { | |
1070 | case FBIOGET_CONTRAST: | |
1071 | case FBIOPUT_CONTRAST: | |
1072 | case FBIGET_BRIGHTNESS: | |
1073 | case FBIPUT_BRIGHTNESS: | |
1074 | case FBIGET_COLOR: | |
1075 | case FBIPUT_COLOR: | |
2f93e8f4 | 1076 | return -ENOTTY; |
4ed824d9 SR |
1077 | case FBIPUT_HSYNC: |
1078 | if (copy_from_user(&sync_arg, (char *)arg, | |
1079 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1080 | return -EFAULT; |
4ed824d9 SR |
1081 | lcd_cfg_horizontal_sync(sync_arg.back_porch, |
1082 | sync_arg.pulse_width, | |
1083 | sync_arg.front_porch); | |
1084 | break; | |
1085 | case FBIPUT_VSYNC: | |
1086 | if (copy_from_user(&sync_arg, (char *)arg, | |
1087 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1088 | return -EFAULT; |
4ed824d9 SR |
1089 | lcd_cfg_vertical_sync(sync_arg.back_porch, |
1090 | sync_arg.pulse_width, | |
1091 | sync_arg.front_porch); | |
1092 | break; | |
1f9c3e1f MA |
1093 | case FBIO_WAITFORVSYNC: |
1094 | return fb_wait_for_vsync(info); | |
4ed824d9 SR |
1095 | default: |
1096 | return -EINVAL; | |
1097 | } | |
1098 | return 0; | |
1099 | } | |
1100 | ||
312d9715 C |
1101 | static int cfb_blank(int blank, struct fb_info *info) |
1102 | { | |
1103 | struct da8xx_fb_par *par = info->par; | |
1104 | int ret = 0; | |
1105 | ||
1106 | if (par->blank == blank) | |
1107 | return 0; | |
1108 | ||
1109 | par->blank = blank; | |
1110 | switch (blank) { | |
1111 | case FB_BLANK_UNBLANK: | |
f7c848b6 MP |
1112 | lcd_enable_raster(); |
1113 | ||
312d9715 C |
1114 | if (par->panel_power_ctrl) |
1115 | par->panel_power_ctrl(1); | |
312d9715 | 1116 | break; |
99a647d1 YY |
1117 | case FB_BLANK_NORMAL: |
1118 | case FB_BLANK_VSYNC_SUSPEND: | |
1119 | case FB_BLANK_HSYNC_SUSPEND: | |
312d9715 C |
1120 | case FB_BLANK_POWERDOWN: |
1121 | if (par->panel_power_ctrl) | |
1122 | par->panel_power_ctrl(0); | |
1123 | ||
a481b37a | 1124 | lcd_disable_raster(true); |
312d9715 C |
1125 | break; |
1126 | default: | |
1127 | ret = -EINVAL; | |
1128 | } | |
1129 | ||
1130 | return ret; | |
1131 | } | |
1132 | ||
1f9c3e1f MA |
1133 | /* |
1134 | * Set new x,y offsets in the virtual display for the visible area and switch | |
1135 | * to the new mode. | |
1136 | */ | |
1137 | static int da8xx_pan_display(struct fb_var_screeninfo *var, | |
1138 | struct fb_info *fbi) | |
1139 | { | |
1140 | int ret = 0; | |
1141 | struct fb_var_screeninfo new_var; | |
1142 | struct da8xx_fb_par *par = fbi->par; | |
1143 | struct fb_fix_screeninfo *fix = &fbi->fix; | |
1144 | unsigned int end; | |
1145 | unsigned int start; | |
deb95c6c | 1146 | unsigned long irq_flags; |
1f9c3e1f MA |
1147 | |
1148 | if (var->xoffset != fbi->var.xoffset || | |
1149 | var->yoffset != fbi->var.yoffset) { | |
1150 | memcpy(&new_var, &fbi->var, sizeof(new_var)); | |
1151 | new_var.xoffset = var->xoffset; | |
1152 | new_var.yoffset = var->yoffset; | |
1153 | if (fb_check_var(&new_var, fbi)) | |
1154 | ret = -EINVAL; | |
1155 | else { | |
1156 | memcpy(&fbi->var, &new_var, sizeof(new_var)); | |
1157 | ||
1158 | start = fix->smem_start + | |
1159 | new_var.yoffset * fix->line_length + | |
e6c4d3d4 LP |
1160 | new_var.xoffset * fbi->var.bits_per_pixel / 8; |
1161 | end = start + fbi->var.yres * fix->line_length - 1; | |
1f9c3e1f MA |
1162 | par->dma_start = start; |
1163 | par->dma_end = end; | |
deb95c6c MP |
1164 | spin_lock_irqsave(&par->lock_for_chan_update, |
1165 | irq_flags); | |
1166 | if (par->which_dma_channel_done == 0) { | |
1167 | lcdc_write(par->dma_start, | |
1168 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1169 | lcdc_write(par->dma_end, | |
1170 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1171 | } else if (par->which_dma_channel_done == 1) { | |
1172 | lcdc_write(par->dma_start, | |
1173 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1174 | lcdc_write(par->dma_end, | |
1175 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1176 | } | |
1177 | spin_unlock_irqrestore(&par->lock_for_chan_update, | |
1178 | irq_flags); | |
1f9c3e1f MA |
1179 | } |
1180 | } | |
1181 | ||
1182 | return ret; | |
1183 | } | |
1184 | ||
4ed824d9 SR |
1185 | static struct fb_ops da8xx_fb_ops = { |
1186 | .owner = THIS_MODULE, | |
1187 | .fb_check_var = fb_check_var, | |
1188 | .fb_setcolreg = fb_setcolreg, | |
1f9c3e1f | 1189 | .fb_pan_display = da8xx_pan_display, |
4ed824d9 SR |
1190 | .fb_ioctl = fb_ioctl, |
1191 | .fb_fillrect = cfb_fillrect, | |
1192 | .fb_copyarea = cfb_copyarea, | |
1193 | .fb_imageblit = cfb_imageblit, | |
312d9715 | 1194 | .fb_blank = cfb_blank, |
4ed824d9 SR |
1195 | }; |
1196 | ||
12fa8350 MP |
1197 | /* Calculate and return pixel clock period in pico seconds */ |
1198 | static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par) | |
1199 | { | |
1200 | unsigned int lcd_clk, div; | |
1201 | unsigned int configured_pix_clk; | |
1202 | unsigned long long pix_clk_period_picosec = 1000000000000ULL; | |
1203 | ||
1204 | lcd_clk = clk_get_rate(par->lcdc_clk); | |
1205 | div = lcd_clk / par->pxl_clk; | |
1206 | configured_pix_clk = (lcd_clk / div); | |
1207 | ||
1208 | do_div(pix_clk_period_picosec, configured_pix_clk); | |
1209 | ||
1210 | return pix_clk_period_picosec; | |
1211 | } | |
1212 | ||
48c68c4f | 1213 | static int fb_probe(struct platform_device *device) |
4ed824d9 SR |
1214 | { |
1215 | struct da8xx_lcdc_platform_data *fb_pdata = | |
1216 | device->dev.platform_data; | |
1217 | struct lcd_ctrl_config *lcd_cfg; | |
f772fabd | 1218 | struct fb_videomode *lcdc_info; |
4ed824d9 SR |
1219 | struct fb_info *da8xx_fb_info; |
1220 | struct clk *fb_clk = NULL; | |
1221 | struct da8xx_fb_par *par; | |
1222 | resource_size_t len; | |
1223 | int ret, i; | |
3b9cc4ea | 1224 | unsigned long ulcm; |
4ed824d9 SR |
1225 | |
1226 | if (fb_pdata == NULL) { | |
1227 | dev_err(&device->dev, "Can not get platform data\n"); | |
1228 | return -ENOENT; | |
1229 | } | |
1230 | ||
1231 | lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0); | |
1232 | if (!lcdc_regs) { | |
1233 | dev_err(&device->dev, | |
1234 | "Can not get memory resource for LCD controller\n"); | |
1235 | return -ENOENT; | |
1236 | } | |
1237 | ||
1238 | len = resource_size(lcdc_regs); | |
1239 | ||
1240 | lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name); | |
1241 | if (!lcdc_regs) | |
1242 | return -EBUSY; | |
1243 | ||
34aef6eb | 1244 | da8xx_fb_reg_base = ioremap(lcdc_regs->start, len); |
4ed824d9 SR |
1245 | if (!da8xx_fb_reg_base) { |
1246 | ret = -EBUSY; | |
1247 | goto err_request_mem; | |
1248 | } | |
1249 | ||
81cec3c7 | 1250 | fb_clk = clk_get(&device->dev, "fck"); |
4ed824d9 SR |
1251 | if (IS_ERR(fb_clk)) { |
1252 | dev_err(&device->dev, "Can not get device clock\n"); | |
1253 | ret = -ENODEV; | |
1254 | goto err_ioremap; | |
1255 | } | |
9dd44d5d MP |
1256 | |
1257 | pm_runtime_enable(&device->dev); | |
1258 | pm_runtime_get_sync(&device->dev); | |
4ed824d9 | 1259 | |
c6daf05b MP |
1260 | /* Determine LCD IP Version */ |
1261 | switch (lcdc_read(LCD_PID_REG)) { | |
1262 | case 0x4C100102: | |
1263 | lcd_revision = LCD_VERSION_1; | |
1264 | break; | |
1265 | case 0x4F200800: | |
8f22e8ea | 1266 | case 0x4F201000: |
c6daf05b MP |
1267 | lcd_revision = LCD_VERSION_2; |
1268 | break; | |
1269 | default: | |
1270 | dev_warn(&device->dev, "Unknown PID Reg value 0x%x, " | |
1271 | "defaulting to LCD revision 1\n", | |
1272 | lcdc_read(LCD_PID_REG)); | |
1273 | lcd_revision = LCD_VERSION_1; | |
1274 | break; | |
1275 | } | |
1276 | ||
4ed824d9 SR |
1277 | for (i = 0, lcdc_info = known_lcd_panels; |
1278 | i < ARRAY_SIZE(known_lcd_panels); | |
1279 | i++, lcdc_info++) { | |
1280 | if (strcmp(fb_pdata->type, lcdc_info->name) == 0) | |
1281 | break; | |
1282 | } | |
1283 | ||
1284 | if (i == ARRAY_SIZE(known_lcd_panels)) { | |
1285 | dev_err(&device->dev, "GLCD: No valid panel found\n"); | |
dd04a6b3 | 1286 | ret = -ENODEV; |
9dd44d5d | 1287 | goto err_pm_runtime_disable; |
4ed824d9 SR |
1288 | } else |
1289 | dev_info(&device->dev, "GLCD: Found %s panel\n", | |
1290 | fb_pdata->type); | |
1291 | ||
1292 | lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data; | |
1293 | ||
1294 | da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par), | |
1295 | &device->dev); | |
1296 | if (!da8xx_fb_info) { | |
1297 | dev_dbg(&device->dev, "Memory allocation failed for fb_info\n"); | |
1298 | ret = -ENOMEM; | |
9dd44d5d | 1299 | goto err_pm_runtime_disable; |
4ed824d9 SR |
1300 | } |
1301 | ||
1302 | par = da8xx_fb_info->par; | |
8097b174 | 1303 | par->lcdc_clk = fb_clk; |
f820917a MP |
1304 | #ifdef CONFIG_CPU_FREQ |
1305 | par->lcd_fck_rate = clk_get_rate(fb_clk); | |
1306 | #endif | |
f772fabd | 1307 | par->pxl_clk = lcdc_info->pixclock; |
36113804 C |
1308 | if (fb_pdata->panel_power_ctrl) { |
1309 | par->panel_power_ctrl = fb_pdata->panel_power_ctrl; | |
1310 | par->panel_power_ctrl(1); | |
1311 | } | |
4ed824d9 SR |
1312 | |
1313 | if (lcd_init(par, lcd_cfg, lcdc_info) < 0) { | |
1314 | dev_err(&device->dev, "lcd_init failed\n"); | |
1315 | ret = -EFAULT; | |
1316 | goto err_release_fb; | |
1317 | } | |
1318 | ||
1319 | /* allocate frame buffer */ | |
f772fabd MP |
1320 | par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp; |
1321 | ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE); | |
3b9cc4ea | 1322 | par->vram_size = roundup(par->vram_size/8, ulcm); |
1f9c3e1f MA |
1323 | par->vram_size = par->vram_size * LCD_NUM_BUFFERS; |
1324 | ||
1325 | par->vram_virt = dma_alloc_coherent(NULL, | |
1326 | par->vram_size, | |
1327 | (resource_size_t *) &par->vram_phys, | |
1328 | GFP_KERNEL | GFP_DMA); | |
1329 | if (!par->vram_virt) { | |
4ed824d9 SR |
1330 | dev_err(&device->dev, |
1331 | "GLCD: kmalloc for frame buffer failed\n"); | |
1332 | ret = -EINVAL; | |
1333 | goto err_release_fb; | |
1334 | } | |
1335 | ||
1f9c3e1f MA |
1336 | da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt; |
1337 | da8xx_fb_fix.smem_start = par->vram_phys; | |
1338 | da8xx_fb_fix.smem_len = par->vram_size; | |
f772fabd | 1339 | da8xx_fb_fix.line_length = (lcdc_info->xres * lcd_cfg->bpp) / 8; |
1f9c3e1f MA |
1340 | |
1341 | par->dma_start = par->vram_phys; | |
f772fabd | 1342 | par->dma_end = par->dma_start + lcdc_info->yres * |
1f9c3e1f MA |
1343 | da8xx_fb_fix.line_length - 1; |
1344 | ||
1345 | /* allocate palette buffer */ | |
1346 | par->v_palette_base = dma_alloc_coherent(NULL, | |
1347 | PALETTE_SIZE, | |
1348 | (resource_size_t *) | |
1349 | &par->p_palette_base, | |
1350 | GFP_KERNEL | GFP_DMA); | |
1351 | if (!par->v_palette_base) { | |
1352 | dev_err(&device->dev, | |
1353 | "GLCD: kmalloc for palette buffer failed\n"); | |
1354 | ret = -EINVAL; | |
1355 | goto err_release_fb_mem; | |
1356 | } | |
1357 | memset(par->v_palette_base, 0, PALETTE_SIZE); | |
4ed824d9 | 1358 | |
4ed824d9 SR |
1359 | par->irq = platform_get_irq(device, 0); |
1360 | if (par->irq < 0) { | |
1361 | ret = -ENOENT; | |
1f9c3e1f | 1362 | goto err_release_pl_mem; |
4ed824d9 SR |
1363 | } |
1364 | ||
4ed824d9 SR |
1365 | /* Initialize par */ |
1366 | da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp; | |
1367 | ||
f772fabd MP |
1368 | da8xx_fb_var.xres = lcdc_info->xres; |
1369 | da8xx_fb_var.xres_virtual = lcdc_info->xres; | |
4ed824d9 | 1370 | |
f772fabd MP |
1371 | da8xx_fb_var.yres = lcdc_info->yres; |
1372 | da8xx_fb_var.yres_virtual = lcdc_info->yres * LCD_NUM_BUFFERS; | |
4ed824d9 SR |
1373 | |
1374 | da8xx_fb_var.grayscale = | |
3b43ad20 | 1375 | lcd_cfg->panel_shade == MONOCHROME ? 1 : 0; |
4ed824d9 SR |
1376 | da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; |
1377 | ||
f772fabd MP |
1378 | da8xx_fb_var.hsync_len = lcdc_info->hsync_len; |
1379 | da8xx_fb_var.vsync_len = lcdc_info->vsync_len; | |
1380 | da8xx_fb_var.right_margin = lcdc_info->right_margin; | |
1381 | da8xx_fb_var.left_margin = lcdc_info->left_margin; | |
1382 | da8xx_fb_var.lower_margin = lcdc_info->lower_margin; | |
1383 | da8xx_fb_var.upper_margin = lcdc_info->upper_margin; | |
12fa8350 | 1384 | da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par); |
4ed824d9 SR |
1385 | |
1386 | /* Initialize fbinfo */ | |
1387 | da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; | |
1388 | da8xx_fb_info->fix = da8xx_fb_fix; | |
1389 | da8xx_fb_info->var = da8xx_fb_var; | |
1390 | da8xx_fb_info->fbops = &da8xx_fb_ops; | |
1391 | da8xx_fb_info->pseudo_palette = par->pseudo_palette; | |
3510b8f7 SR |
1392 | da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? |
1393 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
4ed824d9 SR |
1394 | |
1395 | ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0); | |
1396 | if (ret) | |
93c176f3 | 1397 | goto err_release_pl_mem; |
4ed824d9 SR |
1398 | da8xx_fb_info->cmap.len = par->palette_sz; |
1399 | ||
4ed824d9 SR |
1400 | /* initialize var_screeninfo */ |
1401 | da8xx_fb_var.activate = FB_ACTIVATE_FORCE; | |
1402 | fb_set_var(da8xx_fb_info, &da8xx_fb_var); | |
1403 | ||
1404 | dev_set_drvdata(&device->dev, da8xx_fb_info); | |
1f9c3e1f MA |
1405 | |
1406 | /* initialize the vsync wait queue */ | |
1407 | init_waitqueue_head(&par->vsync_wait); | |
1408 | par->vsync_timeout = HZ / 5; | |
deb95c6c MP |
1409 | par->which_dma_channel_done = -1; |
1410 | spin_lock_init(&par->lock_for_chan_update); | |
1f9c3e1f | 1411 | |
4ed824d9 SR |
1412 | /* Register the Frame Buffer */ |
1413 | if (register_framebuffer(da8xx_fb_info) < 0) { | |
1414 | dev_err(&device->dev, | |
1415 | "GLCD: Frame Buffer Registration Failed!\n"); | |
1416 | ret = -EINVAL; | |
1417 | goto err_dealloc_cmap; | |
1418 | } | |
1419 | ||
e04e5483 C |
1420 | #ifdef CONFIG_CPU_FREQ |
1421 | ret = lcd_da8xx_cpufreq_register(par); | |
1422 | if (ret) { | |
1423 | dev_err(&device->dev, "failed to register cpufreq\n"); | |
1424 | goto err_cpu_freq; | |
1425 | } | |
1426 | #endif | |
93c176f3 | 1427 | |
c6daf05b MP |
1428 | if (lcd_revision == LCD_VERSION_1) |
1429 | lcdc_irq_handler = lcdc_irq_handler_rev01; | |
a481b37a MP |
1430 | else { |
1431 | init_waitqueue_head(&frame_done_wq); | |
c6daf05b | 1432 | lcdc_irq_handler = lcdc_irq_handler_rev02; |
a481b37a | 1433 | } |
c6daf05b MP |
1434 | |
1435 | ret = request_irq(par->irq, lcdc_irq_handler, 0, | |
1436 | DRIVER_NAME, par); | |
93c176f3 CA |
1437 | if (ret) |
1438 | goto irq_freq; | |
4ed824d9 SR |
1439 | return 0; |
1440 | ||
93c176f3 | 1441 | irq_freq: |
e04e5483 | 1442 | #ifdef CONFIG_CPU_FREQ |
360c202b | 1443 | lcd_da8xx_cpufreq_deregister(par); |
e04e5483 | 1444 | err_cpu_freq: |
3a84409c | 1445 | #endif |
e04e5483 | 1446 | unregister_framebuffer(da8xx_fb_info); |
e04e5483 | 1447 | |
4ed824d9 SR |
1448 | err_dealloc_cmap: |
1449 | fb_dealloc_cmap(&da8xx_fb_info->cmap); | |
1450 | ||
1f9c3e1f MA |
1451 | err_release_pl_mem: |
1452 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, | |
1453 | par->p_palette_base); | |
1454 | ||
4ed824d9 | 1455 | err_release_fb_mem: |
1f9c3e1f | 1456 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys); |
4ed824d9 SR |
1457 | |
1458 | err_release_fb: | |
1459 | framebuffer_release(da8xx_fb_info); | |
1460 | ||
9dd44d5d MP |
1461 | err_pm_runtime_disable: |
1462 | pm_runtime_put_sync(&device->dev); | |
1463 | pm_runtime_disable(&device->dev); | |
4ed824d9 SR |
1464 | |
1465 | err_ioremap: | |
34aef6eb | 1466 | iounmap(da8xx_fb_reg_base); |
4ed824d9 SR |
1467 | |
1468 | err_request_mem: | |
1469 | release_mem_region(lcdc_regs->start, len); | |
1470 | ||
1471 | return ret; | |
1472 | } | |
1473 | ||
1474 | #ifdef CONFIG_PM | |
7a93cbbb MP |
1475 | struct lcdc_context { |
1476 | u32 clk_enable; | |
1477 | u32 ctrl; | |
1478 | u32 dma_ctrl; | |
1479 | u32 raster_timing_0; | |
1480 | u32 raster_timing_1; | |
1481 | u32 raster_timing_2; | |
1482 | u32 int_enable_set; | |
1483 | u32 dma_frm_buf_base_addr_0; | |
1484 | u32 dma_frm_buf_ceiling_addr_0; | |
1485 | u32 dma_frm_buf_base_addr_1; | |
1486 | u32 dma_frm_buf_ceiling_addr_1; | |
1487 | u32 raster_ctrl; | |
1488 | } reg_context; | |
1489 | ||
1490 | static void lcd_context_save(void) | |
1491 | { | |
1492 | if (lcd_revision == LCD_VERSION_2) { | |
1493 | reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG); | |
1494 | reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG); | |
1495 | } | |
1496 | ||
1497 | reg_context.ctrl = lcdc_read(LCD_CTRL_REG); | |
1498 | reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG); | |
1499 | reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG); | |
1500 | reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG); | |
1501 | reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
1502 | reg_context.dma_frm_buf_base_addr_0 = | |
1503 | lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1504 | reg_context.dma_frm_buf_ceiling_addr_0 = | |
1505 | lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1506 | reg_context.dma_frm_buf_base_addr_1 = | |
1507 | lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1508 | reg_context.dma_frm_buf_ceiling_addr_1 = | |
1509 | lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1510 | reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG); | |
1511 | return; | |
1512 | } | |
1513 | ||
1514 | static void lcd_context_restore(void) | |
1515 | { | |
1516 | if (lcd_revision == LCD_VERSION_2) { | |
1517 | lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG); | |
1518 | lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG); | |
1519 | } | |
1520 | ||
1521 | lcdc_write(reg_context.ctrl, LCD_CTRL_REG); | |
1522 | lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG); | |
1523 | lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG); | |
1524 | lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG); | |
1525 | lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG); | |
1526 | lcdc_write(reg_context.dma_frm_buf_base_addr_0, | |
1527 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1528 | lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0, | |
1529 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1530 | lcdc_write(reg_context.dma_frm_buf_base_addr_1, | |
1531 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1532 | lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1, | |
1533 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1534 | lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG); | |
1535 | return; | |
1536 | } | |
1537 | ||
4ed824d9 SR |
1538 | static int fb_suspend(struct platform_device *dev, pm_message_t state) |
1539 | { | |
1d3c6c7b C |
1540 | struct fb_info *info = platform_get_drvdata(dev); |
1541 | struct da8xx_fb_par *par = info->par; | |
1542 | ||
ac751efa | 1543 | console_lock(); |
1d3c6c7b C |
1544 | if (par->panel_power_ctrl) |
1545 | par->panel_power_ctrl(0); | |
1546 | ||
1547 | fb_set_suspend(info, 1); | |
a481b37a | 1548 | lcd_disable_raster(true); |
7a93cbbb | 1549 | lcd_context_save(); |
9dd44d5d | 1550 | pm_runtime_put_sync(&dev->dev); |
ac751efa | 1551 | console_unlock(); |
1d3c6c7b C |
1552 | |
1553 | return 0; | |
4ed824d9 SR |
1554 | } |
1555 | static int fb_resume(struct platform_device *dev) | |
1556 | { | |
1d3c6c7b C |
1557 | struct fb_info *info = platform_get_drvdata(dev); |
1558 | struct da8xx_fb_par *par = info->par; | |
1559 | ||
ac751efa | 1560 | console_lock(); |
9dd44d5d | 1561 | pm_runtime_get_sync(&dev->dev); |
7a93cbbb | 1562 | lcd_context_restore(); |
67900814 MP |
1563 | if (par->blank == FB_BLANK_UNBLANK) { |
1564 | lcd_enable_raster(); | |
f7c848b6 | 1565 | |
67900814 MP |
1566 | if (par->panel_power_ctrl) |
1567 | par->panel_power_ctrl(1); | |
1568 | } | |
1d3c6c7b | 1569 | |
1d3c6c7b | 1570 | fb_set_suspend(info, 0); |
ac751efa | 1571 | console_unlock(); |
1d3c6c7b C |
1572 | |
1573 | return 0; | |
4ed824d9 SR |
1574 | } |
1575 | #else | |
1576 | #define fb_suspend NULL | |
1577 | #define fb_resume NULL | |
1578 | #endif | |
1579 | ||
1580 | static struct platform_driver da8xx_fb_driver = { | |
1581 | .probe = fb_probe, | |
48c68c4f | 1582 | .remove = fb_remove, |
4ed824d9 SR |
1583 | .suspend = fb_suspend, |
1584 | .resume = fb_resume, | |
1585 | .driver = { | |
1586 | .name = DRIVER_NAME, | |
1587 | .owner = THIS_MODULE, | |
1588 | }, | |
1589 | }; | |
1590 | ||
1591 | static int __init da8xx_fb_init(void) | |
1592 | { | |
1593 | return platform_driver_register(&da8xx_fb_driver); | |
1594 | } | |
1595 | ||
1596 | static void __exit da8xx_fb_cleanup(void) | |
1597 | { | |
1598 | platform_driver_unregister(&da8xx_fb_driver); | |
1599 | } | |
1600 | ||
1601 | module_init(da8xx_fb_init); | |
1602 | module_exit(da8xx_fb_cleanup); | |
1603 | ||
1604 | MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx"); | |
1605 | MODULE_AUTHOR("Texas Instruments"); | |
1606 | MODULE_LICENSE("GPL"); |