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1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/cyber2000fb.c | |
3 | * | |
4 | * Copyright (C) 1998-2002 Russell King | |
5 | * | |
6 | * MIPS and 50xx clock support | |
7 | * Copyright (C) 2001 Bradley D. LaRonde <brad@ltc.com> | |
8 | * | |
9 | * 32 bit support, text color and panning fixes for modes != 8 bit | |
10 | * Copyright (C) 2002 Denis Oliver Kropp <dok@directfb.org> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * Integraphics CyberPro 2000, 2010 and 5000 frame buffer device | |
17 | * | |
18 | * Based on cyberfb.c. | |
19 | * | |
20 | * Note that we now use the new fbcon fix, var and cmap scheme. We do | |
21 | * still have to check which console is the currently displayed one | |
22 | * however, especially for the colourmap stuff. | |
23 | * | |
24 | * We also use the new hotplug PCI subsystem. I'm not sure if there | |
25 | * are any such cards, but I'm erring on the side of caution. We don't | |
26 | * want to go pop just because someone does have one. | |
27 | * | |
28 | * Note that this doesn't work fully in the case of multiple CyberPro | |
29 | * cards with grabbers. We currently can only attach to the first | |
30 | * CyberPro card found. | |
31 | * | |
32 | * When we're in truecolour mode, we power down the LUT RAM as a power | |
33 | * saving feature. Also, when we enter any of the powersaving modes | |
34 | * (except soft blanking) we power down the RAMDACs. This saves about | |
35 | * 1W, which is roughly 8% of the power consumption of a NetWinder | |
36 | * (which, incidentally, is about the same saving as a 2.5in hard disk | |
37 | * entering standby mode.) | |
38 | */ | |
1da177e4 LT |
39 | #include <linux/module.h> |
40 | #include <linux/kernel.h> | |
41 | #include <linux/errno.h> | |
42 | #include <linux/string.h> | |
43 | #include <linux/mm.h> | |
1da177e4 LT |
44 | #include <linux/slab.h> |
45 | #include <linux/delay.h> | |
46 | #include <linux/fb.h> | |
47 | #include <linux/pci.h> | |
48 | #include <linux/init.h> | |
49 | ||
50 | #include <asm/io.h> | |
1da177e4 LT |
51 | #include <asm/pgtable.h> |
52 | #include <asm/system.h> | |
53 | #include <asm/uaccess.h> | |
54 | ||
55 | #ifdef __arm__ | |
56 | #include <asm/mach-types.h> | |
57 | #endif | |
58 | ||
59 | #include "cyber2000fb.h" | |
60 | ||
61 | struct cfb_info { | |
62 | struct fb_info fb; | |
63 | struct display_switch *dispsw; | |
64 | struct display *display; | |
65 | struct pci_dev *dev; | |
66 | unsigned char __iomem *region; | |
67 | unsigned char __iomem *regs; | |
68 | u_int id; | |
69 | int func_use_count; | |
70 | u_long ref_ps; | |
71 | ||
72 | /* | |
73 | * Clock divisors | |
74 | */ | |
75 | u_int divisors[4]; | |
76 | ||
77 | struct { | |
78 | u8 red, green, blue; | |
79 | } palette[NR_PALETTE]; | |
80 | ||
81 | u_char mem_ctl1; | |
82 | u_char mem_ctl2; | |
83 | u_char mclk_mult; | |
84 | u_char mclk_div; | |
85 | /* | |
86 | * RAMDAC control register is both of these or'ed together | |
87 | */ | |
88 | u_char ramdac_ctrl; | |
89 | u_char ramdac_powerdown; | |
eca02b0c RK |
90 | |
91 | u32 pseudo_palette[16]; | |
1da177e4 LT |
92 | }; |
93 | ||
94 | static char *default_font = "Acorn8x8"; | |
95 | module_param(default_font, charp, 0); | |
96 | MODULE_PARM_DESC(default_font, "Default font name"); | |
97 | ||
98 | /* | |
99 | * Our access methods. | |
100 | */ | |
101 | #define cyber2000fb_writel(val,reg,cfb) writel(val, (cfb)->regs + (reg)) | |
102 | #define cyber2000fb_writew(val,reg,cfb) writew(val, (cfb)->regs + (reg)) | |
103 | #define cyber2000fb_writeb(val,reg,cfb) writeb(val, (cfb)->regs + (reg)) | |
104 | ||
105 | #define cyber2000fb_readb(reg,cfb) readb((cfb)->regs + (reg)) | |
106 | ||
107 | static inline void | |
108 | cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb) | |
109 | { | |
110 | cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb); | |
111 | } | |
112 | ||
113 | static inline void | |
114 | cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb) | |
115 | { | |
116 | cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb); | |
117 | } | |
118 | ||
119 | static inline unsigned int | |
120 | cyber2000_grphr(unsigned int reg, struct cfb_info *cfb) | |
121 | { | |
122 | cyber2000fb_writeb(reg, 0x3ce, cfb); | |
123 | return cyber2000fb_readb(0x3cf, cfb); | |
124 | } | |
125 | ||
126 | static inline void | |
127 | cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb) | |
128 | { | |
129 | cyber2000fb_readb(0x3da, cfb); | |
130 | cyber2000fb_writeb(reg, 0x3c0, cfb); | |
131 | cyber2000fb_readb(0x3c1, cfb); | |
132 | cyber2000fb_writeb(val, 0x3c0, cfb); | |
133 | } | |
134 | ||
135 | static inline void | |
136 | cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb) | |
137 | { | |
138 | cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb); | |
139 | } | |
140 | ||
141 | /* -------------------- Hardware specific routines ------------------------- */ | |
142 | ||
143 | /* | |
144 | * Hardware Cyber2000 Acceleration | |
145 | */ | |
146 | static void | |
147 | cyber2000fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
148 | { | |
149 | struct cfb_info *cfb = (struct cfb_info *)info; | |
150 | unsigned long dst, col; | |
151 | ||
152 | if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { | |
153 | cfb_fillrect(info, rect); | |
154 | return; | |
155 | } | |
156 | ||
157 | cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); | |
158 | cyber2000fb_writew(rect->width - 1, CO_REG_PIXWIDTH, cfb); | |
159 | cyber2000fb_writew(rect->height - 1, CO_REG_PIXHEIGHT, cfb); | |
160 | ||
161 | col = rect->color; | |
162 | if (cfb->fb.var.bits_per_pixel > 8) | |
163 | col = ((u32 *)cfb->fb.pseudo_palette)[col]; | |
164 | cyber2000fb_writel(col, CO_REG_FGCOLOUR, cfb); | |
165 | ||
166 | dst = rect->dx + rect->dy * cfb->fb.var.xres_virtual; | |
167 | if (cfb->fb.var.bits_per_pixel == 24) { | |
168 | cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb); | |
169 | dst *= 3; | |
170 | } | |
171 | ||
172 | cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb); | |
173 | cyber2000fb_writeb(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb); | |
174 | cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L, cfb); | |
175 | cyber2000fb_writew(CO_CMD_H_BLITTER, CO_REG_CMD_H, cfb); | |
176 | } | |
177 | ||
178 | static void | |
179 | cyber2000fb_copyarea(struct fb_info *info, const struct fb_copyarea *region) | |
180 | { | |
181 | struct cfb_info *cfb = (struct cfb_info *)info; | |
182 | unsigned int cmd = CO_CMD_L_PATTERN_FGCOL; | |
183 | unsigned long src, dst; | |
184 | ||
185 | if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { | |
186 | cfb_copyarea(info, region); | |
187 | return; | |
188 | } | |
189 | ||
190 | cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); | |
191 | cyber2000fb_writew(region->width - 1, CO_REG_PIXWIDTH, cfb); | |
192 | cyber2000fb_writew(region->height - 1, CO_REG_PIXHEIGHT, cfb); | |
193 | ||
194 | src = region->sx + region->sy * cfb->fb.var.xres_virtual; | |
195 | dst = region->dx + region->dy * cfb->fb.var.xres_virtual; | |
196 | ||
197 | if (region->sx < region->dx) { | |
198 | src += region->width - 1; | |
199 | dst += region->width - 1; | |
200 | cmd |= CO_CMD_L_INC_LEFT; | |
201 | } | |
202 | ||
203 | if (region->sy < region->dy) { | |
204 | src += (region->height - 1) * cfb->fb.var.xres_virtual; | |
205 | dst += (region->height - 1) * cfb->fb.var.xres_virtual; | |
206 | cmd |= CO_CMD_L_INC_UP; | |
207 | } | |
208 | ||
209 | if (cfb->fb.var.bits_per_pixel == 24) { | |
210 | cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb); | |
211 | src *= 3; | |
212 | dst *= 3; | |
213 | } | |
214 | cyber2000fb_writel(src, CO_REG_SRC1_PTR, cfb); | |
215 | cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb); | |
216 | cyber2000fb_writew(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb); | |
217 | cyber2000fb_writew(cmd, CO_REG_CMD_L, cfb); | |
218 | cyber2000fb_writew(CO_CMD_H_FGSRCMAP | CO_CMD_H_BLITTER, | |
219 | CO_REG_CMD_H, cfb); | |
220 | } | |
221 | ||
222 | static void | |
223 | cyber2000fb_imageblit(struct fb_info *info, const struct fb_image *image) | |
224 | { | |
225 | // struct cfb_info *cfb = (struct cfb_info *)info; | |
226 | ||
227 | // if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { | |
228 | cfb_imageblit(info, image); | |
229 | return; | |
230 | // } | |
231 | } | |
232 | ||
233 | static int cyber2000fb_sync(struct fb_info *info) | |
234 | { | |
235 | struct cfb_info *cfb = (struct cfb_info *)info; | |
236 | int count = 100000; | |
237 | ||
238 | if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) | |
239 | return 0; | |
240 | ||
241 | while (cyber2000fb_readb(CO_REG_CONTROL, cfb) & CO_CTRL_BUSY) { | |
242 | if (!count--) { | |
243 | debug_printf("accel_wait timed out\n"); | |
244 | cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); | |
245 | break; | |
246 | } | |
247 | udelay(1); | |
248 | } | |
249 | return 0; | |
250 | } | |
251 | ||
252 | /* | |
253 | * =========================================================================== | |
254 | */ | |
255 | ||
256 | static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf) | |
257 | { | |
258 | u_int mask = (1 << bf->length) - 1; | |
259 | ||
260 | return (val >> (16 - bf->length) & mask) << bf->offset; | |
261 | } | |
262 | ||
263 | /* | |
264 | * Set a single color register. Return != 0 for invalid regno. | |
265 | */ | |
266 | static int | |
267 | cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
268 | u_int transp, struct fb_info *info) | |
269 | { | |
270 | struct cfb_info *cfb = (struct cfb_info *)info; | |
271 | struct fb_var_screeninfo *var = &cfb->fb.var; | |
272 | u32 pseudo_val; | |
273 | int ret = 1; | |
274 | ||
275 | switch (cfb->fb.fix.visual) { | |
276 | default: | |
277 | return 1; | |
278 | ||
279 | /* | |
280 | * Pseudocolour: | |
281 | * 8 8 | |
282 | * pixel --/--+--/--> red lut --> red dac | |
283 | * | 8 | |
284 | * +--/--> green lut --> green dac | |
285 | * | 8 | |
286 | * +--/--> blue lut --> blue dac | |
287 | */ | |
288 | case FB_VISUAL_PSEUDOCOLOR: | |
289 | if (regno >= NR_PALETTE) | |
290 | return 1; | |
291 | ||
292 | red >>= 8; | |
293 | green >>= 8; | |
294 | blue >>= 8; | |
295 | ||
296 | cfb->palette[regno].red = red; | |
297 | cfb->palette[regno].green = green; | |
298 | cfb->palette[regno].blue = blue; | |
299 | ||
300 | cyber2000fb_writeb(regno, 0x3c8, cfb); | |
301 | cyber2000fb_writeb(red, 0x3c9, cfb); | |
302 | cyber2000fb_writeb(green, 0x3c9, cfb); | |
303 | cyber2000fb_writeb(blue, 0x3c9, cfb); | |
304 | return 0; | |
305 | ||
306 | /* | |
307 | * Direct colour: | |
308 | * n rl | |
309 | * pixel --/--+--/--> red lut --> red dac | |
310 | * | gl | |
311 | * +--/--> green lut --> green dac | |
312 | * | bl | |
313 | * +--/--> blue lut --> blue dac | |
314 | * n = bpp, rl = red length, gl = green length, bl = blue length | |
315 | */ | |
316 | case FB_VISUAL_DIRECTCOLOR: | |
317 | red >>= 8; | |
318 | green >>= 8; | |
319 | blue >>= 8; | |
320 | ||
321 | if (var->green.length == 6 && regno < 64) { | |
322 | cfb->palette[regno << 2].green = green; | |
323 | ||
324 | /* | |
325 | * The 6 bits of the green component are applied | |
326 | * to the high 6 bits of the LUT. | |
327 | */ | |
328 | cyber2000fb_writeb(regno << 2, 0x3c8, cfb); | |
329 | cyber2000fb_writeb(cfb->palette[regno >> 1].red, 0x3c9, cfb); | |
330 | cyber2000fb_writeb(green, 0x3c9, cfb); | |
331 | cyber2000fb_writeb(cfb->palette[regno >> 1].blue, 0x3c9, cfb); | |
332 | ||
333 | green = cfb->palette[regno << 3].green; | |
334 | ||
335 | ret = 0; | |
336 | } | |
337 | ||
338 | if (var->green.length >= 5 && regno < 32) { | |
339 | cfb->palette[regno << 3].red = red; | |
340 | cfb->palette[regno << 3].green = green; | |
341 | cfb->palette[regno << 3].blue = blue; | |
342 | ||
343 | /* | |
344 | * The 5 bits of each colour component are | |
345 | * applied to the high 5 bits of the LUT. | |
346 | */ | |
347 | cyber2000fb_writeb(regno << 3, 0x3c8, cfb); | |
348 | cyber2000fb_writeb(red, 0x3c9, cfb); | |
349 | cyber2000fb_writeb(green, 0x3c9, cfb); | |
350 | cyber2000fb_writeb(blue, 0x3c9, cfb); | |
351 | ret = 0; | |
352 | } | |
353 | ||
354 | if (var->green.length == 4 && regno < 16) { | |
355 | cfb->palette[regno << 4].red = red; | |
356 | cfb->palette[regno << 4].green = green; | |
357 | cfb->palette[regno << 4].blue = blue; | |
358 | ||
359 | /* | |
360 | * The 5 bits of each colour component are | |
361 | * applied to the high 5 bits of the LUT. | |
362 | */ | |
363 | cyber2000fb_writeb(regno << 4, 0x3c8, cfb); | |
364 | cyber2000fb_writeb(red, 0x3c9, cfb); | |
365 | cyber2000fb_writeb(green, 0x3c9, cfb); | |
366 | cyber2000fb_writeb(blue, 0x3c9, cfb); | |
367 | ret = 0; | |
368 | } | |
369 | ||
370 | /* | |
371 | * Since this is only used for the first 16 colours, we | |
372 | * don't have to care about overflowing for regno >= 32 | |
373 | */ | |
374 | pseudo_val = regno << var->red.offset | | |
375 | regno << var->green.offset | | |
376 | regno << var->blue.offset; | |
377 | break; | |
378 | ||
379 | /* | |
380 | * True colour: | |
381 | * n rl | |
382 | * pixel --/--+--/--> red dac | |
383 | * | gl | |
384 | * +--/--> green dac | |
385 | * | bl | |
386 | * +--/--> blue dac | |
387 | * n = bpp, rl = red length, gl = green length, bl = blue length | |
388 | */ | |
389 | case FB_VISUAL_TRUECOLOR: | |
390 | pseudo_val = convert_bitfield(transp ^ 0xffff, &var->transp); | |
391 | pseudo_val |= convert_bitfield(red, &var->red); | |
392 | pseudo_val |= convert_bitfield(green, &var->green); | |
393 | pseudo_val |= convert_bitfield(blue, &var->blue); | |
394 | break; | |
395 | } | |
396 | ||
397 | /* | |
398 | * Now set our pseudo palette for the CFB16/24/32 drivers. | |
399 | */ | |
400 | if (regno < 16) | |
401 | ((u32 *)cfb->fb.pseudo_palette)[regno] = pseudo_val; | |
402 | ||
403 | return ret; | |
404 | } | |
405 | ||
406 | struct par_info { | |
407 | /* | |
408 | * Hardware | |
409 | */ | |
410 | u_char clock_mult; | |
411 | u_char clock_div; | |
412 | u_char extseqmisc; | |
413 | u_char co_pixfmt; | |
414 | u_char crtc_ofl; | |
415 | u_char crtc[19]; | |
416 | u_int width; | |
417 | u_int pitch; | |
418 | u_int fetch; | |
419 | ||
420 | /* | |
421 | * Other | |
422 | */ | |
423 | u_char ramdac; | |
424 | }; | |
425 | ||
426 | static const u_char crtc_idx[] = { | |
427 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, | |
428 | 0x08, 0x09, | |
429 | 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18 | |
430 | }; | |
431 | ||
432 | static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb) | |
433 | { | |
434 | unsigned int i; | |
435 | unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown; | |
436 | ||
437 | cyber2000fb_writeb(0x56, 0x3ce, cfb); | |
438 | i = cyber2000fb_readb(0x3cf, cfb); | |
439 | cyber2000fb_writeb(i | 4, 0x3cf, cfb); | |
440 | cyber2000fb_writeb(val, 0x3c6, cfb); | |
441 | cyber2000fb_writeb(i, 0x3cf, cfb); | |
442 | } | |
443 | ||
444 | static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw) | |
445 | { | |
446 | u_int i; | |
447 | ||
448 | /* | |
449 | * Blank palette | |
450 | */ | |
451 | for (i = 0; i < NR_PALETTE; i++) { | |
452 | cyber2000fb_writeb(i, 0x3c8, cfb); | |
453 | cyber2000fb_writeb(0, 0x3c9, cfb); | |
454 | cyber2000fb_writeb(0, 0x3c9, cfb); | |
455 | cyber2000fb_writeb(0, 0x3c9, cfb); | |
456 | } | |
457 | ||
458 | cyber2000fb_writeb(0xef, 0x3c2, cfb); | |
459 | cyber2000_crtcw(0x11, 0x0b, cfb); | |
460 | cyber2000_attrw(0x11, 0x00, cfb); | |
461 | ||
462 | cyber2000_seqw(0x00, 0x01, cfb); | |
463 | cyber2000_seqw(0x01, 0x01, cfb); | |
464 | cyber2000_seqw(0x02, 0x0f, cfb); | |
465 | cyber2000_seqw(0x03, 0x00, cfb); | |
466 | cyber2000_seqw(0x04, 0x0e, cfb); | |
467 | cyber2000_seqw(0x00, 0x03, cfb); | |
468 | ||
469 | for (i = 0; i < sizeof(crtc_idx); i++) | |
470 | cyber2000_crtcw(crtc_idx[i], hw->crtc[i], cfb); | |
471 | ||
472 | for (i = 0x0a; i < 0x10; i++) | |
473 | cyber2000_crtcw(i, 0, cfb); | |
474 | ||
475 | cyber2000_grphw(EXT_CRT_VRTOFL, hw->crtc_ofl, cfb); | |
476 | cyber2000_grphw(0x00, 0x00, cfb); | |
477 | cyber2000_grphw(0x01, 0x00, cfb); | |
478 | cyber2000_grphw(0x02, 0x00, cfb); | |
479 | cyber2000_grphw(0x03, 0x00, cfb); | |
480 | cyber2000_grphw(0x04, 0x00, cfb); | |
481 | cyber2000_grphw(0x05, 0x60, cfb); | |
482 | cyber2000_grphw(0x06, 0x05, cfb); | |
483 | cyber2000_grphw(0x07, 0x0f, cfb); | |
484 | cyber2000_grphw(0x08, 0xff, cfb); | |
485 | ||
486 | /* Attribute controller registers */ | |
487 | for (i = 0; i < 16; i++) | |
488 | cyber2000_attrw(i, i, cfb); | |
489 | ||
490 | cyber2000_attrw(0x10, 0x01, cfb); | |
491 | cyber2000_attrw(0x11, 0x00, cfb); | |
492 | cyber2000_attrw(0x12, 0x0f, cfb); | |
493 | cyber2000_attrw(0x13, 0x00, cfb); | |
494 | cyber2000_attrw(0x14, 0x00, cfb); | |
495 | ||
496 | /* PLL registers */ | |
497 | cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb); | |
498 | cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb); | |
499 | cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb); | |
500 | cyber2000_grphw(EXT_MCLK_DIV, cfb->mclk_div, cfb); | |
501 | cyber2000_grphw(0x90, 0x01, cfb); | |
502 | cyber2000_grphw(0xb9, 0x80, cfb); | |
503 | cyber2000_grphw(0xb9, 0x00, cfb); | |
504 | ||
505 | cfb->ramdac_ctrl = hw->ramdac; | |
506 | cyber2000fb_write_ramdac_ctrl(cfb); | |
507 | ||
508 | cyber2000fb_writeb(0x20, 0x3c0, cfb); | |
509 | cyber2000fb_writeb(0xff, 0x3c6, cfb); | |
510 | ||
511 | cyber2000_grphw(0x14, hw->fetch, cfb); | |
512 | cyber2000_grphw(0x15, ((hw->fetch >> 8) & 0x03) | | |
513 | ((hw->pitch >> 4) & 0x30), cfb); | |
514 | cyber2000_grphw(EXT_SEQ_MISC, hw->extseqmisc, cfb); | |
515 | ||
516 | /* | |
517 | * Set up accelerator registers | |
518 | */ | |
519 | cyber2000fb_writew(hw->width, CO_REG_SRC_WIDTH, cfb); | |
520 | cyber2000fb_writew(hw->width, CO_REG_DEST_WIDTH, cfb); | |
521 | cyber2000fb_writeb(hw->co_pixfmt, CO_REG_PIXFMT, cfb); | |
522 | } | |
523 | ||
524 | static inline int | |
525 | cyber2000fb_update_start(struct cfb_info *cfb, struct fb_var_screeninfo *var) | |
526 | { | |
527 | u_int base = var->yoffset * var->xres_virtual + var->xoffset; | |
528 | ||
529 | base *= var->bits_per_pixel; | |
530 | ||
531 | /* | |
532 | * Convert to bytes and shift two extra bits because DAC | |
533 | * can only start on 4 byte aligned data. | |
534 | */ | |
535 | base >>= 5; | |
536 | ||
537 | if (base >= 1 << 20) | |
538 | return -EINVAL; | |
539 | ||
540 | cyber2000_grphw(0x10, base >> 16 | 0x10, cfb); | |
541 | cyber2000_crtcw(0x0c, base >> 8, cfb); | |
542 | cyber2000_crtcw(0x0d, base, cfb); | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
547 | static int | |
548 | cyber2000fb_decode_crtc(struct par_info *hw, struct cfb_info *cfb, | |
549 | struct fb_var_screeninfo *var) | |
550 | { | |
551 | u_int Htotal, Hblankend, Hsyncend; | |
552 | u_int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend; | |
553 | #define BIT(v,b1,m,b2) (((v >> b1) & m) << b2) | |
554 | ||
555 | hw->crtc[13] = hw->pitch; | |
556 | hw->crtc[17] = 0xe3; | |
557 | hw->crtc[14] = 0; | |
558 | hw->crtc[8] = 0; | |
559 | ||
560 | Htotal = var->xres + var->right_margin + | |
561 | var->hsync_len + var->left_margin; | |
562 | ||
563 | if (Htotal > 2080) | |
564 | return -EINVAL; | |
565 | ||
566 | hw->crtc[0] = (Htotal >> 3) - 5; | |
567 | hw->crtc[1] = (var->xres >> 3) - 1; | |
568 | hw->crtc[2] = var->xres >> 3; | |
569 | hw->crtc[4] = (var->xres + var->right_margin) >> 3; | |
570 | ||
571 | Hblankend = (Htotal - 4*8) >> 3; | |
572 | ||
573 | hw->crtc[3] = BIT(Hblankend, 0, 0x1f, 0) | | |
574 | BIT(1, 0, 0x01, 7); | |
575 | ||
576 | Hsyncend = (var->xres + var->right_margin + var->hsync_len) >> 3; | |
577 | ||
578 | hw->crtc[5] = BIT(Hsyncend, 0, 0x1f, 0) | | |
579 | BIT(Hblankend, 5, 0x01, 7); | |
580 | ||
581 | Vdispend = var->yres - 1; | |
582 | Vsyncstart = var->yres + var->lower_margin; | |
583 | Vsyncend = var->yres + var->lower_margin + var->vsync_len; | |
584 | Vtotal = var->yres + var->lower_margin + var->vsync_len + | |
585 | var->upper_margin - 2; | |
586 | ||
587 | if (Vtotal > 2047) | |
588 | return -EINVAL; | |
589 | ||
590 | Vblankstart = var->yres + 6; | |
591 | Vblankend = Vtotal - 10; | |
592 | ||
593 | hw->crtc[6] = Vtotal; | |
594 | hw->crtc[7] = BIT(Vtotal, 8, 0x01, 0) | | |
595 | BIT(Vdispend, 8, 0x01, 1) | | |
596 | BIT(Vsyncstart, 8, 0x01, 2) | | |
597 | BIT(Vblankstart,8, 0x01, 3) | | |
598 | BIT(1, 0, 0x01, 4) | | |
599 | BIT(Vtotal, 9, 0x01, 5) | | |
600 | BIT(Vdispend, 9, 0x01, 6) | | |
601 | BIT(Vsyncstart, 9, 0x01, 7); | |
602 | hw->crtc[9] = BIT(0, 0, 0x1f, 0) | | |
603 | BIT(Vblankstart,9, 0x01, 5) | | |
604 | BIT(1, 0, 0x01, 6); | |
605 | hw->crtc[10] = Vsyncstart; | |
606 | hw->crtc[11] = BIT(Vsyncend, 0, 0x0f, 0) | | |
607 | BIT(1, 0, 0x01, 7); | |
608 | hw->crtc[12] = Vdispend; | |
609 | hw->crtc[15] = Vblankstart; | |
610 | hw->crtc[16] = Vblankend; | |
611 | hw->crtc[18] = 0xff; | |
612 | ||
613 | /* | |
614 | * overflow - graphics reg 0x11 | |
615 | * 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10 | |
616 | * 4=LINECOMP:10 5-IVIDEO 6=FIXCNT | |
617 | */ | |
618 | hw->crtc_ofl = | |
619 | BIT(Vtotal, 10, 0x01, 0) | | |
620 | BIT(Vdispend, 10, 0x01, 1) | | |
621 | BIT(Vsyncstart, 10, 0x01, 2) | | |
622 | BIT(Vblankstart,10, 0x01, 3) | | |
623 | EXT_CRT_VRTOFL_LINECOMP10; | |
624 | ||
625 | /* woody: set the interlaced bit... */ | |
626 | /* FIXME: what about doublescan? */ | |
627 | if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) | |
628 | hw->crtc_ofl |= EXT_CRT_VRTOFL_INTERLACE; | |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
633 | /* | |
634 | * The following was discovered by a good monitor, bit twiddling, theorising | |
635 | * and but mostly luck. Strangely, it looks like everyone elses' PLL! | |
636 | * | |
637 | * Clock registers: | |
638 | * fclock = fpll / div2 | |
639 | * fpll = fref * mult / div1 | |
640 | * where: | |
641 | * fref = 14.318MHz (69842ps) | |
642 | * mult = reg0xb0.7:0 | |
643 | * div1 = (reg0xb1.5:0 + 1) | |
644 | * div2 = 2^(reg0xb1.7:6) | |
645 | * fpll should be between 115 and 260 MHz | |
646 | * (8696ps and 3846ps) | |
647 | */ | |
648 | static int | |
649 | cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb, | |
650 | struct fb_var_screeninfo *var) | |
651 | { | |
652 | u_long pll_ps = var->pixclock; | |
653 | const u_long ref_ps = cfb->ref_ps; | |
654 | u_int div2, t_div1, best_div1, best_mult; | |
655 | int best_diff; | |
656 | int vco; | |
657 | ||
658 | /* | |
659 | * Step 1: | |
660 | * find div2 such that 115MHz < fpll < 260MHz | |
661 | * and 0 <= div2 < 4 | |
662 | */ | |
663 | for (div2 = 0; div2 < 4; div2++) { | |
664 | u_long new_pll; | |
665 | ||
666 | new_pll = pll_ps / cfb->divisors[div2]; | |
667 | if (8696 > new_pll && new_pll > 3846) { | |
668 | pll_ps = new_pll; | |
669 | break; | |
670 | } | |
671 | } | |
672 | ||
673 | if (div2 == 4) | |
674 | return -EINVAL; | |
675 | ||
676 | /* | |
677 | * Step 2: | |
678 | * Given pll_ps and ref_ps, find: | |
679 | * pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005 | |
680 | * where { 1 < best_div1 < 32, 1 < best_mult < 256 } | |
681 | * pll_ps_calc = best_div1 / (ref_ps * best_mult) | |
682 | */ | |
683 | best_diff = 0x7fffffff; | |
684 | best_mult = 32; | |
685 | best_div1 = 255; | |
686 | for (t_div1 = 32; t_div1 > 1; t_div1 -= 1) { | |
687 | u_int rr, t_mult, t_pll_ps; | |
688 | int diff; | |
689 | ||
690 | /* | |
691 | * Find the multiplier for this divisor | |
692 | */ | |
693 | rr = ref_ps * t_div1; | |
694 | t_mult = (rr + pll_ps / 2) / pll_ps; | |
695 | ||
696 | /* | |
697 | * Is the multiplier within the correct range? | |
698 | */ | |
699 | if (t_mult > 256 || t_mult < 2) | |
700 | continue; | |
701 | ||
702 | /* | |
703 | * Calculate the actual clock period from this multiplier | |
704 | * and divisor, and estimate the error. | |
705 | */ | |
706 | t_pll_ps = (rr + t_mult / 2) / t_mult; | |
707 | diff = pll_ps - t_pll_ps; | |
708 | if (diff < 0) | |
709 | diff = -diff; | |
710 | ||
711 | if (diff < best_diff) { | |
712 | best_diff = diff; | |
713 | best_mult = t_mult; | |
714 | best_div1 = t_div1; | |
715 | } | |
716 | ||
717 | /* | |
718 | * If we hit an exact value, there is no point in continuing. | |
719 | */ | |
720 | if (diff == 0) | |
721 | break; | |
722 | } | |
723 | ||
724 | /* | |
725 | * Step 3: | |
726 | * combine values | |
727 | */ | |
728 | hw->clock_mult = best_mult - 1; | |
729 | hw->clock_div = div2 << 6 | (best_div1 - 1); | |
730 | ||
731 | vco = ref_ps * best_div1 / best_mult; | |
732 | if ((ref_ps == 40690) && (vco < 5556)) | |
733 | /* Set VFSEL when VCO > 180MHz (5.556 ps). */ | |
734 | hw->clock_div |= EXT_DCLK_DIV_VFSEL; | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
739 | /* | |
740 | * Set the User Defined Part of the Display | |
741 | */ | |
742 | static int | |
743 | cyber2000fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
744 | { | |
745 | struct cfb_info *cfb = (struct cfb_info *)info; | |
746 | struct par_info hw; | |
747 | unsigned int mem; | |
748 | int err; | |
749 | ||
750 | var->transp.msb_right = 0; | |
751 | var->red.msb_right = 0; | |
752 | var->green.msb_right = 0; | |
753 | var->blue.msb_right = 0; | |
754 | ||
755 | switch (var->bits_per_pixel) { | |
756 | case 8: /* PSEUDOCOLOUR, 256 */ | |
757 | var->transp.offset = 0; | |
758 | var->transp.length = 0; | |
759 | var->red.offset = 0; | |
760 | var->red.length = 8; | |
761 | var->green.offset = 0; | |
762 | var->green.length = 8; | |
763 | var->blue.offset = 0; | |
764 | var->blue.length = 8; | |
765 | break; | |
766 | ||
767 | case 16:/* DIRECTCOLOUR, 64k or 32k */ | |
768 | switch (var->green.length) { | |
769 | case 6: /* RGB565, 64k */ | |
770 | var->transp.offset = 0; | |
771 | var->transp.length = 0; | |
772 | var->red.offset = 11; | |
773 | var->red.length = 5; | |
774 | var->green.offset = 5; | |
775 | var->green.length = 6; | |
776 | var->blue.offset = 0; | |
777 | var->blue.length = 5; | |
778 | break; | |
779 | ||
780 | default: | |
781 | case 5: /* RGB555, 32k */ | |
782 | var->transp.offset = 0; | |
783 | var->transp.length = 0; | |
784 | var->red.offset = 10; | |
785 | var->red.length = 5; | |
786 | var->green.offset = 5; | |
787 | var->green.length = 5; | |
788 | var->blue.offset = 0; | |
789 | var->blue.length = 5; | |
790 | break; | |
791 | ||
792 | case 4: /* RGB444, 4k + transparency? */ | |
793 | var->transp.offset = 12; | |
794 | var->transp.length = 4; | |
795 | var->red.offset = 8; | |
796 | var->red.length = 4; | |
797 | var->green.offset = 4; | |
798 | var->green.length = 4; | |
799 | var->blue.offset = 0; | |
800 | var->blue.length = 4; | |
801 | break; | |
802 | } | |
803 | break; | |
804 | ||
805 | case 24:/* TRUECOLOUR, 16m */ | |
806 | var->transp.offset = 0; | |
807 | var->transp.length = 0; | |
808 | var->red.offset = 16; | |
809 | var->red.length = 8; | |
810 | var->green.offset = 8; | |
811 | var->green.length = 8; | |
812 | var->blue.offset = 0; | |
813 | var->blue.length = 8; | |
814 | break; | |
815 | ||
816 | case 32:/* TRUECOLOUR, 16m */ | |
817 | var->transp.offset = 24; | |
818 | var->transp.length = 8; | |
819 | var->red.offset = 16; | |
820 | var->red.length = 8; | |
821 | var->green.offset = 8; | |
822 | var->green.length = 8; | |
823 | var->blue.offset = 0; | |
824 | var->blue.length = 8; | |
825 | break; | |
826 | ||
827 | default: | |
828 | return -EINVAL; | |
829 | } | |
830 | ||
831 | mem = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8); | |
832 | if (mem > cfb->fb.fix.smem_len) | |
833 | var->yres_virtual = cfb->fb.fix.smem_len * 8 / | |
834 | (var->bits_per_pixel * var->xres_virtual); | |
835 | ||
836 | if (var->yres > var->yres_virtual) | |
837 | var->yres = var->yres_virtual; | |
838 | if (var->xres > var->xres_virtual) | |
839 | var->xres = var->xres_virtual; | |
840 | ||
841 | err = cyber2000fb_decode_clock(&hw, cfb, var); | |
842 | if (err) | |
843 | return err; | |
844 | ||
845 | err = cyber2000fb_decode_crtc(&hw, cfb, var); | |
846 | if (err) | |
847 | return err; | |
848 | ||
849 | return 0; | |
850 | } | |
851 | ||
852 | static int cyber2000fb_set_par(struct fb_info *info) | |
853 | { | |
854 | struct cfb_info *cfb = (struct cfb_info *)info; | |
855 | struct fb_var_screeninfo *var = &cfb->fb.var; | |
856 | struct par_info hw; | |
857 | unsigned int mem; | |
858 | ||
859 | hw.width = var->xres_virtual; | |
860 | hw.ramdac = RAMDAC_VREFEN | RAMDAC_DAC8BIT; | |
861 | ||
862 | switch (var->bits_per_pixel) { | |
863 | case 8: | |
864 | hw.co_pixfmt = CO_PIXFMT_8BPP; | |
865 | hw.pitch = hw.width >> 3; | |
866 | hw.extseqmisc = EXT_SEQ_MISC_8; | |
867 | break; | |
868 | ||
869 | case 16: | |
870 | hw.co_pixfmt = CO_PIXFMT_16BPP; | |
871 | hw.pitch = hw.width >> 2; | |
872 | ||
873 | switch (var->green.length) { | |
874 | case 6: /* RGB565, 64k */ | |
875 | hw.extseqmisc = EXT_SEQ_MISC_16_RGB565; | |
876 | break; | |
877 | case 5: /* RGB555, 32k */ | |
878 | hw.extseqmisc = EXT_SEQ_MISC_16_RGB555; | |
879 | break; | |
880 | case 4: /* RGB444, 4k + transparency? */ | |
881 | hw.extseqmisc = EXT_SEQ_MISC_16_RGB444; | |
882 | break; | |
883 | default: | |
884 | BUG(); | |
885 | } | |
886 | case 24:/* TRUECOLOUR, 16m */ | |
887 | hw.co_pixfmt = CO_PIXFMT_24BPP; | |
888 | hw.width *= 3; | |
889 | hw.pitch = hw.width >> 3; | |
890 | hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN); | |
891 | hw.extseqmisc = EXT_SEQ_MISC_24_RGB888; | |
892 | break; | |
893 | ||
894 | case 32:/* TRUECOLOUR, 16m */ | |
895 | hw.co_pixfmt = CO_PIXFMT_32BPP; | |
896 | hw.pitch = hw.width >> 1; | |
897 | hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN); | |
898 | hw.extseqmisc = EXT_SEQ_MISC_32; | |
899 | break; | |
900 | ||
901 | default: | |
902 | BUG(); | |
903 | } | |
904 | ||
905 | /* | |
906 | * Sigh, this is absolutely disgusting, but caused by | |
907 | * the way the fbcon developers want to separate out | |
908 | * the "checking" and the "setting" of the video mode. | |
909 | * | |
910 | * If the mode is not suitable for the hardware here, | |
911 | * we can't prevent it being set by returning an error. | |
912 | * | |
913 | * In theory, since NetWinders contain just one VGA card, | |
914 | * we should never end up hitting this problem. | |
915 | */ | |
916 | BUG_ON(cyber2000fb_decode_clock(&hw, cfb, var) != 0); | |
917 | BUG_ON(cyber2000fb_decode_crtc(&hw, cfb, var) != 0); | |
918 | ||
919 | hw.width -= 1; | |
920 | hw.fetch = hw.pitch; | |
921 | if (!(cfb->mem_ctl2 & MEM_CTL2_64BIT)) | |
922 | hw.fetch <<= 1; | |
923 | hw.fetch += 1; | |
924 | ||
925 | cfb->fb.fix.line_length = var->xres_virtual * var->bits_per_pixel / 8; | |
926 | ||
927 | /* | |
928 | * Same here - if the size of the video mode exceeds the | |
929 | * available RAM, we can't prevent this mode being set. | |
930 | * | |
931 | * In theory, since NetWinders contain just one VGA card, | |
932 | * we should never end up hitting this problem. | |
933 | */ | |
934 | mem = cfb->fb.fix.line_length * var->yres_virtual; | |
935 | BUG_ON(mem > cfb->fb.fix.smem_len); | |
936 | ||
937 | /* | |
938 | * 8bpp displays are always pseudo colour. 16bpp and above | |
939 | * are direct colour or true colour, depending on whether | |
940 | * the RAMDAC palettes are bypassed. (Direct colour has | |
941 | * palettes, true colour does not.) | |
942 | */ | |
943 | if (var->bits_per_pixel == 8) | |
944 | cfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
945 | else if (hw.ramdac & RAMDAC_BYPASS) | |
946 | cfb->fb.fix.visual = FB_VISUAL_TRUECOLOR; | |
947 | else | |
948 | cfb->fb.fix.visual = FB_VISUAL_DIRECTCOLOR; | |
949 | ||
950 | cyber2000fb_set_timing(cfb, &hw); | |
951 | cyber2000fb_update_start(cfb, var); | |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
956 | ||
957 | /* | |
958 | * Pan or Wrap the Display | |
959 | */ | |
960 | static int | |
961 | cyber2000fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) | |
962 | { | |
963 | struct cfb_info *cfb = (struct cfb_info *)info; | |
964 | ||
965 | if (cyber2000fb_update_start(cfb, var)) | |
966 | return -EINVAL; | |
967 | ||
968 | cfb->fb.var.xoffset = var->xoffset; | |
969 | cfb->fb.var.yoffset = var->yoffset; | |
970 | ||
971 | if (var->vmode & FB_VMODE_YWRAP) { | |
972 | cfb->fb.var.vmode |= FB_VMODE_YWRAP; | |
973 | } else { | |
974 | cfb->fb.var.vmode &= ~FB_VMODE_YWRAP; | |
975 | } | |
976 | ||
977 | return 0; | |
978 | } | |
979 | ||
980 | /* | |
981 | * (Un)Blank the display. | |
982 | * | |
983 | * Blank the screen if blank_mode != 0, else unblank. If | |
984 | * blank == NULL then the caller blanks by setting the CLUT | |
985 | * (Color Look Up Table) to all black. Return 0 if blanking | |
986 | * succeeded, != 0 if un-/blanking failed due to e.g. a | |
987 | * video mode which doesn't support it. Implements VESA | |
988 | * suspend and powerdown modes on hardware that supports | |
989 | * disabling hsync/vsync: | |
990 | * blank_mode == 2: suspend vsync | |
991 | * blank_mode == 3: suspend hsync | |
992 | * blank_mode == 4: powerdown | |
993 | * | |
994 | * wms...Enable VESA DMPS compatible powerdown mode | |
995 | * run "setterm -powersave powerdown" to take advantage | |
996 | */ | |
997 | static int cyber2000fb_blank(int blank, struct fb_info *info) | |
998 | { | |
999 | struct cfb_info *cfb = (struct cfb_info *)info; | |
1000 | unsigned int sync = 0; | |
1001 | int i; | |
1002 | ||
1003 | switch (blank) { | |
1004 | case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */ | |
1005 | sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_0; | |
1006 | break; | |
1007 | case FB_BLANK_HSYNC_SUSPEND: /* hsync off */ | |
1008 | sync = EXT_SYNC_CTL_VS_NORMAL | EXT_SYNC_CTL_HS_0; | |
1009 | break; | |
1010 | case FB_BLANK_VSYNC_SUSPEND: /* vsync off */ | |
1011 | sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_NORMAL; | |
1012 | break; | |
1013 | case FB_BLANK_NORMAL: /* soft blank */ | |
1014 | default: /* unblank */ | |
1015 | break; | |
1016 | } | |
1017 | ||
1018 | cyber2000_grphw(EXT_SYNC_CTL, sync, cfb); | |
1019 | ||
1020 | if (blank <= 1) { | |
1021 | /* turn on ramdacs */ | |
1022 | cfb->ramdac_powerdown &= ~(RAMDAC_DACPWRDN | RAMDAC_BYPASS | RAMDAC_RAMPWRDN); | |
1023 | cyber2000fb_write_ramdac_ctrl(cfb); | |
1024 | } | |
1025 | ||
1026 | /* | |
1027 | * Soft blank/unblank the display. | |
1028 | */ | |
1029 | if (blank) { /* soft blank */ | |
1030 | for (i = 0; i < NR_PALETTE; i++) { | |
1031 | cyber2000fb_writeb(i, 0x3c8, cfb); | |
1032 | cyber2000fb_writeb(0, 0x3c9, cfb); | |
1033 | cyber2000fb_writeb(0, 0x3c9, cfb); | |
1034 | cyber2000fb_writeb(0, 0x3c9, cfb); | |
1035 | } | |
1036 | } else { /* unblank */ | |
1037 | for (i = 0; i < NR_PALETTE; i++) { | |
1038 | cyber2000fb_writeb(i, 0x3c8, cfb); | |
1039 | cyber2000fb_writeb(cfb->palette[i].red, 0x3c9, cfb); | |
1040 | cyber2000fb_writeb(cfb->palette[i].green, 0x3c9, cfb); | |
1041 | cyber2000fb_writeb(cfb->palette[i].blue, 0x3c9, cfb); | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | if (blank >= 2) { | |
1046 | /* turn off ramdacs */ | |
1047 | cfb->ramdac_powerdown |= RAMDAC_DACPWRDN | RAMDAC_BYPASS | RAMDAC_RAMPWRDN; | |
1048 | cyber2000fb_write_ramdac_ctrl(cfb); | |
1049 | } | |
1050 | ||
1051 | return 0; | |
1052 | } | |
1053 | ||
1054 | static struct fb_ops cyber2000fb_ops = { | |
1055 | .owner = THIS_MODULE, | |
1056 | .fb_check_var = cyber2000fb_check_var, | |
1057 | .fb_set_par = cyber2000fb_set_par, | |
1058 | .fb_setcolreg = cyber2000fb_setcolreg, | |
1059 | .fb_blank = cyber2000fb_blank, | |
1060 | .fb_pan_display = cyber2000fb_pan_display, | |
1061 | .fb_fillrect = cyber2000fb_fillrect, | |
1062 | .fb_copyarea = cyber2000fb_copyarea, | |
1063 | .fb_imageblit = cyber2000fb_imageblit, | |
1da177e4 LT |
1064 | .fb_sync = cyber2000fb_sync, |
1065 | }; | |
1066 | ||
1067 | /* | |
1068 | * This is the only "static" reference to the internal data structures | |
1069 | * of this driver. It is here solely at the moment to support the other | |
1070 | * CyberPro modules external to this driver. | |
1071 | */ | |
1072 | static struct cfb_info *int_cfb_info; | |
1073 | ||
1074 | /* | |
1075 | * Enable access to the extended registers | |
1076 | */ | |
1077 | void cyber2000fb_enable_extregs(struct cfb_info *cfb) | |
1078 | { | |
1079 | cfb->func_use_count += 1; | |
1080 | ||
1081 | if (cfb->func_use_count == 1) { | |
1082 | int old; | |
1083 | ||
1084 | old = cyber2000_grphr(EXT_FUNC_CTL, cfb); | |
1085 | old |= EXT_FUNC_CTL_EXTREGENBL; | |
1086 | cyber2000_grphw(EXT_FUNC_CTL, old, cfb); | |
1087 | } | |
1088 | } | |
1089 | ||
1090 | /* | |
1091 | * Disable access to the extended registers | |
1092 | */ | |
1093 | void cyber2000fb_disable_extregs(struct cfb_info *cfb) | |
1094 | { | |
1095 | if (cfb->func_use_count == 1) { | |
1096 | int old; | |
1097 | ||
1098 | old = cyber2000_grphr(EXT_FUNC_CTL, cfb); | |
1099 | old &= ~EXT_FUNC_CTL_EXTREGENBL; | |
1100 | cyber2000_grphw(EXT_FUNC_CTL, old, cfb); | |
1101 | } | |
1102 | ||
1103 | if (cfb->func_use_count == 0) | |
1104 | printk(KERN_ERR "disable_extregs: count = 0\n"); | |
1105 | else | |
1106 | cfb->func_use_count -= 1; | |
1107 | } | |
1108 | ||
1109 | void cyber2000fb_get_fb_var(struct cfb_info *cfb, struct fb_var_screeninfo *var) | |
1110 | { | |
1111 | memcpy(var, &cfb->fb.var, sizeof(struct fb_var_screeninfo)); | |
1112 | } | |
1113 | ||
1114 | /* | |
1115 | * Attach a capture/tv driver to the core CyberX0X0 driver. | |
1116 | */ | |
1117 | int cyber2000fb_attach(struct cyberpro_info *info, int idx) | |
1118 | { | |
1119 | if (int_cfb_info != NULL) { | |
1120 | info->dev = int_cfb_info->dev; | |
1121 | info->regs = int_cfb_info->regs; | |
1122 | info->fb = int_cfb_info->fb.screen_base; | |
1123 | info->fb_size = int_cfb_info->fb.fix.smem_len; | |
1124 | info->enable_extregs = cyber2000fb_enable_extregs; | |
1125 | info->disable_extregs = cyber2000fb_disable_extregs; | |
1126 | info->info = int_cfb_info; | |
1127 | ||
1128 | strlcpy(info->dev_name, int_cfb_info->fb.fix.id, sizeof(info->dev_name)); | |
1129 | } | |
1130 | ||
1131 | return int_cfb_info != NULL; | |
1132 | } | |
1133 | ||
1134 | /* | |
1135 | * Detach a capture/tv driver from the core CyberX0X0 driver. | |
1136 | */ | |
1137 | void cyber2000fb_detach(int idx) | |
1138 | { | |
1139 | } | |
1140 | ||
1141 | EXPORT_SYMBOL(cyber2000fb_attach); | |
1142 | EXPORT_SYMBOL(cyber2000fb_detach); | |
1143 | EXPORT_SYMBOL(cyber2000fb_enable_extregs); | |
1144 | EXPORT_SYMBOL(cyber2000fb_disable_extregs); | |
1145 | EXPORT_SYMBOL(cyber2000fb_get_fb_var); | |
1146 | ||
1147 | /* | |
1148 | * These parameters give | |
1149 | * 640x480, hsync 31.5kHz, vsync 60Hz | |
1150 | */ | |
1151 | static struct fb_videomode __devinitdata cyber2000fb_default_mode = { | |
1152 | .refresh = 60, | |
1153 | .xres = 640, | |
1154 | .yres = 480, | |
1155 | .pixclock = 39722, | |
1156 | .left_margin = 56, | |
1157 | .right_margin = 16, | |
1158 | .upper_margin = 34, | |
1159 | .lower_margin = 9, | |
1160 | .hsync_len = 88, | |
1161 | .vsync_len = 2, | |
1162 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
1163 | .vmode = FB_VMODE_NONINTERLACED | |
1164 | }; | |
1165 | ||
1166 | static char igs_regs[] = { | |
1167 | EXT_CRT_IRQ, 0, | |
1168 | EXT_CRT_TEST, 0, | |
1169 | EXT_SYNC_CTL, 0, | |
1170 | EXT_SEG_WRITE_PTR, 0, | |
1171 | EXT_SEG_READ_PTR, 0, | |
1172 | EXT_BIU_MISC, EXT_BIU_MISC_LIN_ENABLE | | |
1173 | EXT_BIU_MISC_COP_ENABLE | | |
1174 | EXT_BIU_MISC_COP_BFC, | |
1175 | EXT_FUNC_CTL, 0, | |
1176 | CURS_H_START, 0, | |
1177 | CURS_H_START + 1, 0, | |
1178 | CURS_H_PRESET, 0, | |
1179 | CURS_V_START, 0, | |
1180 | CURS_V_START + 1, 0, | |
1181 | CURS_V_PRESET, 0, | |
1182 | CURS_CTL, 0, | |
1183 | EXT_ATTRIB_CTL, EXT_ATTRIB_CTL_EXT, | |
1184 | EXT_OVERSCAN_RED, 0, | |
1185 | EXT_OVERSCAN_GREEN, 0, | |
1186 | EXT_OVERSCAN_BLUE, 0, | |
1187 | ||
1188 | /* some of these are questionable when we have a BIOS */ | |
1189 | EXT_MEM_CTL0, EXT_MEM_CTL0_7CLK | | |
1190 | EXT_MEM_CTL0_RAS_1 | | |
1191 | EXT_MEM_CTL0_MULTCAS, | |
1192 | EXT_HIDDEN_CTL1, 0x30, | |
1193 | EXT_FIFO_CTL, 0x0b, | |
1194 | EXT_FIFO_CTL + 1, 0x17, | |
1195 | 0x76, 0x00, | |
1196 | EXT_HIDDEN_CTL4, 0xc8 | |
1197 | }; | |
1198 | ||
1199 | /* | |
1200 | * Initialise the CyberPro hardware. On the CyberPro5XXXX, | |
1201 | * ensure that we're using the correct PLL (5XXX's may be | |
1202 | * programmed to use an additional set of PLLs.) | |
1203 | */ | |
1204 | static void cyberpro_init_hw(struct cfb_info *cfb) | |
1205 | { | |
1206 | int i; | |
1207 | ||
1208 | for (i = 0; i < sizeof(igs_regs); i += 2) | |
1209 | cyber2000_grphw(igs_regs[i], igs_regs[i+1], cfb); | |
1210 | ||
1211 | if (cfb->id == ID_CYBERPRO_5000) { | |
1212 | unsigned char val; | |
1213 | cyber2000fb_writeb(0xba, 0x3ce, cfb); | |
1214 | val = cyber2000fb_readb(0x3cf, cfb) & 0x80; | |
1215 | cyber2000fb_writeb(val, 0x3cf, cfb); | |
1216 | } | |
1217 | } | |
1218 | ||
1219 | static struct cfb_info * __devinit | |
1220 | cyberpro_alloc_fb_info(unsigned int id, char *name) | |
1221 | { | |
1222 | struct cfb_info *cfb; | |
1223 | ||
dd00cc48 | 1224 | cfb = kzalloc(sizeof(struct cfb_info), GFP_KERNEL); |
1da177e4 LT |
1225 | if (!cfb) |
1226 | return NULL; | |
1227 | ||
1da177e4 LT |
1228 | |
1229 | cfb->id = id; | |
1230 | ||
1231 | if (id == ID_CYBERPRO_5000) | |
1232 | cfb->ref_ps = 40690; // 24.576 MHz | |
1233 | else | |
1234 | cfb->ref_ps = 69842; // 14.31818 MHz (69841?) | |
1235 | ||
1236 | cfb->divisors[0] = 1; | |
1237 | cfb->divisors[1] = 2; | |
1238 | cfb->divisors[2] = 4; | |
1239 | ||
1240 | if (id == ID_CYBERPRO_2000) | |
1241 | cfb->divisors[3] = 8; | |
1242 | else | |
1243 | cfb->divisors[3] = 6; | |
1244 | ||
1245 | strcpy(cfb->fb.fix.id, name); | |
1246 | ||
1247 | cfb->fb.fix.type = FB_TYPE_PACKED_PIXELS; | |
1248 | cfb->fb.fix.type_aux = 0; | |
1249 | cfb->fb.fix.xpanstep = 0; | |
1250 | cfb->fb.fix.ypanstep = 1; | |
1251 | cfb->fb.fix.ywrapstep = 0; | |
1252 | ||
1253 | switch (id) { | |
1254 | case ID_IGA_1682: | |
1255 | cfb->fb.fix.accel = 0; | |
1256 | break; | |
1257 | ||
1258 | case ID_CYBERPRO_2000: | |
1259 | cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2000; | |
1260 | break; | |
1261 | ||
1262 | case ID_CYBERPRO_2010: | |
1263 | cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2010; | |
1264 | break; | |
1265 | ||
1266 | case ID_CYBERPRO_5000: | |
1267 | cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER5000; | |
1268 | break; | |
1269 | } | |
1270 | ||
1271 | cfb->fb.var.nonstd = 0; | |
1272 | cfb->fb.var.activate = FB_ACTIVATE_NOW; | |
1273 | cfb->fb.var.height = -1; | |
1274 | cfb->fb.var.width = -1; | |
1275 | cfb->fb.var.accel_flags = FB_ACCELF_TEXT; | |
1276 | ||
1277 | cfb->fb.fbops = &cyber2000fb_ops; | |
1278 | cfb->fb.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; | |
eca02b0c | 1279 | cfb->fb.pseudo_palette = cfb->pseudo_palette; |
1da177e4 LT |
1280 | |
1281 | fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0); | |
1282 | ||
1283 | return cfb; | |
1284 | } | |
1285 | ||
1286 | static void | |
1287 | cyberpro_free_fb_info(struct cfb_info *cfb) | |
1288 | { | |
1289 | if (cfb) { | |
1290 | /* | |
1291 | * Free the colourmap | |
1292 | */ | |
1293 | fb_alloc_cmap(&cfb->fb.cmap, 0, 0); | |
1294 | ||
1295 | kfree(cfb); | |
1296 | } | |
1297 | } | |
1298 | ||
1299 | /* | |
1300 | * Parse Cyber2000fb options. Usage: | |
1301 | * video=cyber2000:font:fontname | |
1302 | */ | |
1303 | #ifndef MODULE | |
1304 | static int | |
1305 | cyber2000fb_setup(char *options) | |
1306 | { | |
1307 | char *opt; | |
1308 | ||
1309 | if (!options || !*options) | |
1310 | return 0; | |
1311 | ||
1312 | while ((opt = strsep(&options, ",")) != NULL) { | |
1313 | if (!*opt) | |
1314 | continue; | |
1315 | ||
1316 | if (strncmp(opt, "font:", 5) == 0) { | |
1317 | static char default_font_storage[40]; | |
1318 | ||
1319 | strlcpy(default_font_storage, opt + 5, sizeof(default_font_storage)); | |
1320 | default_font = default_font_storage; | |
1321 | continue; | |
1322 | } | |
1323 | ||
1324 | printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", opt); | |
1325 | } | |
1326 | return 0; | |
1327 | } | |
1328 | #endif /* MODULE */ | |
1329 | ||
1330 | /* | |
1331 | * The CyberPro chips can be placed on many different bus types. | |
1332 | * This probe function is common to all bus types. The bus-specific | |
1333 | * probe function is expected to have: | |
1334 | * - enabled access to the linear memory region | |
1335 | * - memory mapped access to the registers | |
1336 | * - initialised mem_ctl1 and mem_ctl2 appropriately. | |
1337 | */ | |
1338 | static int __devinit cyberpro_common_probe(struct cfb_info *cfb) | |
1339 | { | |
1340 | u_long smem_size; | |
1341 | u_int h_sync, v_sync; | |
1342 | int err; | |
1343 | ||
1344 | cyberpro_init_hw(cfb); | |
1345 | ||
1346 | /* | |
1347 | * Get the video RAM size and width from the VGA register. | |
1348 | * This should have been already initialised by the BIOS, | |
1349 | * but if it's garbage, claim default 1MB VRAM (woody) | |
1350 | */ | |
1351 | cfb->mem_ctl1 = cyber2000_grphr(EXT_MEM_CTL1, cfb); | |
1352 | cfb->mem_ctl2 = cyber2000_grphr(EXT_MEM_CTL2, cfb); | |
1353 | ||
1354 | /* | |
1355 | * Determine the size of the memory. | |
1356 | */ | |
1357 | switch (cfb->mem_ctl2 & MEM_CTL2_SIZE_MASK) { | |
1358 | case MEM_CTL2_SIZE_4MB: smem_size = 0x00400000; break; | |
1359 | case MEM_CTL2_SIZE_2MB: smem_size = 0x00200000; break; | |
1360 | case MEM_CTL2_SIZE_1MB: smem_size = 0x00100000; break; | |
1361 | default: smem_size = 0x00100000; break; | |
1362 | } | |
1363 | ||
1364 | cfb->fb.fix.smem_len = smem_size; | |
1365 | cfb->fb.fix.mmio_len = MMIO_SIZE; | |
1366 | cfb->fb.screen_base = cfb->region; | |
1367 | ||
1368 | err = -EINVAL; | |
1369 | if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0, | |
1370 | &cyber2000fb_default_mode, 8)) { | |
1371 | printk("%s: no valid mode found\n", cfb->fb.fix.id); | |
1372 | goto failed; | |
1373 | } | |
1374 | ||
1375 | cfb->fb.var.yres_virtual = cfb->fb.fix.smem_len * 8 / | |
1376 | (cfb->fb.var.bits_per_pixel * cfb->fb.var.xres_virtual); | |
1377 | ||
1378 | if (cfb->fb.var.yres_virtual < cfb->fb.var.yres) | |
1379 | cfb->fb.var.yres_virtual = cfb->fb.var.yres; | |
1380 | ||
1381 | // fb_set_var(&cfb->fb.var, -1, &cfb->fb); | |
1382 | ||
1383 | /* | |
1384 | * Calculate the hsync and vsync frequencies. Note that | |
1385 | * we split the 1e12 constant up so that we can preserve | |
1386 | * the precision and fit the results into 32-bit registers. | |
1387 | * (1953125000 * 512 = 1e12) | |
1388 | */ | |
1389 | h_sync = 1953125000 / cfb->fb.var.pixclock; | |
1390 | h_sync = h_sync * 512 / (cfb->fb.var.xres + cfb->fb.var.left_margin + | |
1391 | cfb->fb.var.right_margin + cfb->fb.var.hsync_len); | |
1392 | v_sync = h_sync / (cfb->fb.var.yres + cfb->fb.var.upper_margin + | |
1393 | cfb->fb.var.lower_margin + cfb->fb.var.vsync_len); | |
1394 | ||
1395 | printk(KERN_INFO "%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n", | |
1396 | cfb->fb.fix.id, cfb->fb.fix.smem_len >> 10, | |
1397 | cfb->fb.var.xres, cfb->fb.var.yres, | |
1398 | h_sync / 1000, h_sync % 1000, v_sync); | |
1399 | ||
1400 | if (cfb->dev) | |
1401 | cfb->fb.device = &cfb->dev->dev; | |
1402 | err = register_framebuffer(&cfb->fb); | |
1403 | ||
1404 | failed: | |
1405 | return err; | |
1406 | } | |
1407 | ||
1408 | static void cyberpro_common_resume(struct cfb_info *cfb) | |
1409 | { | |
1410 | cyberpro_init_hw(cfb); | |
1411 | ||
1412 | /* | |
1413 | * Reprogram the MEM_CTL1 and MEM_CTL2 registers | |
1414 | */ | |
1415 | cyber2000_grphw(EXT_MEM_CTL1, cfb->mem_ctl1, cfb); | |
1416 | cyber2000_grphw(EXT_MEM_CTL2, cfb->mem_ctl2, cfb); | |
1417 | ||
1418 | /* | |
1419 | * Restore the old video mode and the palette. | |
1420 | * We also need to tell fbcon to redraw the console. | |
1421 | */ | |
1422 | cyber2000fb_set_par(&cfb->fb); | |
1423 | } | |
1424 | ||
1425 | #ifdef CONFIG_ARCH_SHARK | |
1426 | ||
1427 | #include <asm/arch/hardware.h> | |
1428 | ||
1429 | static int __devinit | |
1430 | cyberpro_vl_probe(void) | |
1431 | { | |
1432 | struct cfb_info *cfb; | |
1433 | int err = -ENOMEM; | |
1434 | ||
1435 | if (!request_mem_region(FB_START,FB_SIZE,"CyberPro2010")) return err; | |
1436 | ||
1437 | cfb = cyberpro_alloc_fb_info(ID_CYBERPRO_2010, "CyberPro2010"); | |
1438 | if (!cfb) | |
1439 | goto failed_release; | |
1440 | ||
1441 | cfb->dev = NULL; | |
1442 | cfb->region = ioremap(FB_START,FB_SIZE); | |
1443 | if (!cfb->region) | |
1444 | goto failed_ioremap; | |
1445 | ||
1446 | cfb->regs = cfb->region + MMIO_OFFSET; | |
1447 | cfb->fb.fix.mmio_start = FB_START + MMIO_OFFSET; | |
1448 | cfb->fb.fix.smem_start = FB_START; | |
1449 | ||
1450 | /* | |
1451 | * Bring up the hardware. This is expected to enable access | |
1452 | * to the linear memory region, and allow access to the memory | |
1453 | * mapped registers. Also, mem_ctl1 and mem_ctl2 must be | |
1454 | * initialised. | |
1455 | */ | |
1456 | cyber2000fb_writeb(0x18, 0x46e8, cfb); | |
1457 | cyber2000fb_writeb(0x01, 0x102, cfb); | |
1458 | cyber2000fb_writeb(0x08, 0x46e8, cfb); | |
1459 | cyber2000fb_writeb(EXT_BIU_MISC, 0x3ce, cfb); | |
1460 | cyber2000fb_writeb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf, cfb); | |
1461 | ||
1462 | cfb->mclk_mult = 0xdb; | |
1463 | cfb->mclk_div = 0x54; | |
1464 | ||
1465 | err = cyberpro_common_probe(cfb); | |
1466 | if (err) | |
1467 | goto failed; | |
1468 | ||
1469 | if (int_cfb_info == NULL) | |
1470 | int_cfb_info = cfb; | |
1471 | ||
1472 | return 0; | |
1473 | ||
1474 | failed: | |
1475 | iounmap(cfb->region); | |
1476 | failed_ioremap: | |
1477 | cyberpro_free_fb_info(cfb); | |
1478 | failed_release: | |
1479 | release_mem_region(FB_START,FB_SIZE); | |
1480 | ||
1481 | return err; | |
1482 | } | |
1483 | #endif /* CONFIG_ARCH_SHARK */ | |
1484 | ||
1485 | /* | |
1486 | * PCI specific support. | |
1487 | */ | |
1488 | #ifdef CONFIG_PCI | |
1489 | /* | |
1490 | * We need to wake up the CyberPro, and make sure its in linear memory | |
1491 | * mode. Unfortunately, this is specific to the platform and card that | |
1492 | * we are running on. | |
1493 | * | |
1494 | * On x86 and ARM, should we be initialising the CyberPro first via the | |
1495 | * IO registers, and then the MMIO registers to catch all cases? Can we | |
1496 | * end up in the situation where the chip is in MMIO mode, but not awake | |
1497 | * on an x86 system? | |
1498 | */ | |
1499 | static int cyberpro_pci_enable_mmio(struct cfb_info *cfb) | |
1500 | { | |
1501 | unsigned char val; | |
1502 | ||
1503 | #if defined(__sparc_v9__) | |
1504 | #error "You lose, consult DaveM." | |
1505 | #elif defined(__sparc__) | |
1506 | /* | |
1507 | * SPARC does not have an "outb" instruction, so we generate | |
1508 | * I/O cycles storing into a reserved memory space at | |
1509 | * physical address 0x3000000 | |
1510 | */ | |
cd030665 | 1511 | unsigned char __iomem *iop; |
1da177e4 LT |
1512 | |
1513 | iop = ioremap(0x3000000, 0x5000); | |
1514 | if (iop == NULL) { | |
1515 | prom_printf("iga5000: cannot map I/O\n"); | |
1516 | return -ENOMEM; | |
1517 | } | |
1518 | ||
1519 | writeb(0x18, iop + 0x46e8); | |
1520 | writeb(0x01, iop + 0x102); | |
1521 | writeb(0x08, iop + 0x46e8); | |
1522 | writeb(EXT_BIU_MISC, iop + 0x3ce); | |
1523 | writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf); | |
1524 | ||
cd030665 | 1525 | iounmap(iop); |
1da177e4 LT |
1526 | #else |
1527 | /* | |
1528 | * Most other machine types are "normal", so | |
1529 | * we use the standard IO-based wakeup. | |
1530 | */ | |
1531 | outb(0x18, 0x46e8); | |
1532 | outb(0x01, 0x102); | |
1533 | outb(0x08, 0x46e8); | |
1534 | outb(EXT_BIU_MISC, 0x3ce); | |
1535 | outb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf); | |
1536 | #endif | |
1537 | ||
1538 | /* | |
1539 | * Allow the CyberPro to accept PCI burst accesses | |
1540 | */ | |
cd792aa8 WS |
1541 | if (cfb->id == ID_CYBERPRO_2010) { |
1542 | printk(KERN_INFO "%s: NOT enabling PCI bursts\n", cfb->fb.fix.id); | |
1543 | } else { | |
1544 | val = cyber2000_grphr(EXT_BUS_CTL, cfb); | |
1545 | if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) { | |
1546 | printk(KERN_INFO "%s: enabling PCI bursts\n", | |
1547 | cfb->fb.fix.id); | |
1da177e4 | 1548 | |
cd792aa8 | 1549 | val |= EXT_BUS_CTL_PCIBURST_WRITE; |
1da177e4 | 1550 | |
cd792aa8 WS |
1551 | if (cfb->id == ID_CYBERPRO_5000) |
1552 | val |= EXT_BUS_CTL_PCIBURST_READ; | |
1da177e4 | 1553 | |
cd792aa8 WS |
1554 | cyber2000_grphw(EXT_BUS_CTL, val, cfb); |
1555 | } | |
1da177e4 LT |
1556 | } |
1557 | ||
1558 | return 0; | |
1559 | } | |
1560 | ||
1561 | static int __devinit | |
1562 | cyberpro_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
1563 | { | |
1564 | struct cfb_info *cfb; | |
1565 | char name[16]; | |
1566 | int err; | |
1567 | ||
1568 | sprintf(name, "CyberPro%4X", id->device); | |
1569 | ||
1570 | err = pci_enable_device(dev); | |
1571 | if (err) | |
1572 | return err; | |
1573 | ||
1574 | err = pci_request_regions(dev, name); | |
1575 | if (err) | |
1576 | return err; | |
1577 | ||
1578 | err = -ENOMEM; | |
1579 | cfb = cyberpro_alloc_fb_info(id->driver_data, name); | |
1580 | if (!cfb) | |
1581 | goto failed_release; | |
1582 | ||
1583 | cfb->dev = dev; | |
1584 | cfb->region = ioremap(pci_resource_start(dev, 0), | |
1585 | pci_resource_len(dev, 0)); | |
1586 | if (!cfb->region) | |
1587 | goto failed_ioremap; | |
1588 | ||
1589 | cfb->regs = cfb->region + MMIO_OFFSET; | |
1590 | cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET; | |
1591 | cfb->fb.fix.smem_start = pci_resource_start(dev, 0); | |
1592 | ||
1593 | /* | |
1594 | * Bring up the hardware. This is expected to enable access | |
1595 | * to the linear memory region, and allow access to the memory | |
1596 | * mapped registers. Also, mem_ctl1 and mem_ctl2 must be | |
1597 | * initialised. | |
1598 | */ | |
1599 | err = cyberpro_pci_enable_mmio(cfb); | |
1600 | if (err) | |
1601 | goto failed; | |
1602 | ||
1603 | /* | |
1604 | * Use MCLK from BIOS. FIXME: what about hotplug? | |
1605 | */ | |
1606 | cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb); | |
1607 | cfb->mclk_div = cyber2000_grphr(EXT_MCLK_DIV, cfb); | |
1608 | ||
1609 | #ifdef __arm__ | |
1610 | /* | |
1611 | * MCLK on the NetWinder and the Shark is fixed at 75MHz | |
1612 | */ | |
1613 | if (machine_is_netwinder()) { | |
1614 | cfb->mclk_mult = 0xdb; | |
1615 | cfb->mclk_div = 0x54; | |
1616 | } | |
1617 | #endif | |
1618 | ||
1619 | err = cyberpro_common_probe(cfb); | |
1620 | if (err) | |
1621 | goto failed; | |
1622 | ||
1623 | /* | |
1624 | * Our driver data | |
1625 | */ | |
1626 | pci_set_drvdata(dev, cfb); | |
1627 | if (int_cfb_info == NULL) | |
1628 | int_cfb_info = cfb; | |
1629 | ||
1630 | return 0; | |
1631 | ||
1632 | failed: | |
1633 | iounmap(cfb->region); | |
1634 | failed_ioremap: | |
1635 | cyberpro_free_fb_info(cfb); | |
1636 | failed_release: | |
1637 | pci_release_regions(dev); | |
1638 | ||
1639 | return err; | |
1640 | } | |
1641 | ||
1642 | static void __devexit cyberpro_pci_remove(struct pci_dev *dev) | |
1643 | { | |
1644 | struct cfb_info *cfb = pci_get_drvdata(dev); | |
1645 | ||
1646 | if (cfb) { | |
1647 | /* | |
1648 | * If unregister_framebuffer fails, then | |
1649 | * we will be leaving hooks that could cause | |
1650 | * oopsen laying around. | |
1651 | */ | |
1652 | if (unregister_framebuffer(&cfb->fb)) | |
1653 | printk(KERN_WARNING "%s: danger Will Robinson, " | |
1654 | "danger danger! Oopsen imminent!\n", | |
1655 | cfb->fb.fix.id); | |
1656 | iounmap(cfb->region); | |
1657 | cyberpro_free_fb_info(cfb); | |
1658 | ||
1659 | /* | |
1660 | * Ensure that the driver data is no longer | |
1661 | * valid. | |
1662 | */ | |
1663 | pci_set_drvdata(dev, NULL); | |
1664 | if (cfb == int_cfb_info) | |
1665 | int_cfb_info = NULL; | |
1666 | ||
1667 | pci_release_regions(dev); | |
1668 | } | |
1669 | } | |
1670 | ||
1671 | static int cyberpro_pci_suspend(struct pci_dev *dev, pm_message_t state) | |
1672 | { | |
1673 | return 0; | |
1674 | } | |
1675 | ||
1676 | /* | |
1677 | * Re-initialise the CyberPro hardware | |
1678 | */ | |
1679 | static int cyberpro_pci_resume(struct pci_dev *dev) | |
1680 | { | |
1681 | struct cfb_info *cfb = pci_get_drvdata(dev); | |
1682 | ||
1683 | if (cfb) { | |
1684 | cyberpro_pci_enable_mmio(cfb); | |
1685 | cyberpro_common_resume(cfb); | |
1686 | } | |
1687 | ||
1688 | return 0; | |
1689 | } | |
1690 | ||
1691 | static struct pci_device_id cyberpro_pci_table[] = { | |
1692 | // Not yet | |
1693 | // { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682, | |
1694 | // PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 }, | |
1695 | { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000, | |
1696 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2000 }, | |
1697 | { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010, | |
1698 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2010 }, | |
1699 | { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000, | |
1700 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_5000 }, | |
1701 | { 0, } | |
1702 | }; | |
1703 | ||
1704 | MODULE_DEVICE_TABLE(pci,cyberpro_pci_table); | |
1705 | ||
1706 | static struct pci_driver cyberpro_driver = { | |
1707 | .name = "CyberPro", | |
1708 | .probe = cyberpro_pci_probe, | |
1709 | .remove = __devexit_p(cyberpro_pci_remove), | |
1710 | .suspend = cyberpro_pci_suspend, | |
1711 | .resume = cyberpro_pci_resume, | |
1712 | .id_table = cyberpro_pci_table | |
1713 | }; | |
1714 | #endif | |
1715 | ||
1716 | /* | |
1717 | * I don't think we can use the "module_init" stuff here because | |
1718 | * the fbcon stuff may not be initialised yet. Hence the #ifdef | |
1719 | * around module_init. | |
1720 | * | |
1721 | * Tony: "module_init" is now required | |
1722 | */ | |
1723 | static int __init cyber2000fb_init(void) | |
1724 | { | |
1725 | int ret = -1, err; | |
1726 | ||
1727 | #ifndef MODULE | |
1728 | char *option = NULL; | |
1729 | ||
1730 | if (fb_get_options("cyber2000fb", &option)) | |
1731 | return -ENODEV; | |
1732 | cyber2000fb_setup(option); | |
1733 | #endif | |
1734 | ||
1735 | #ifdef CONFIG_ARCH_SHARK | |
1736 | err = cyberpro_vl_probe(); | |
1737 | if (!err) { | |
1738 | ret = 0; | |
1739 | __module_get(THIS_MODULE); | |
1740 | } | |
1741 | #endif | |
1742 | #ifdef CONFIG_PCI | |
1743 | err = pci_register_driver(&cyberpro_driver); | |
1744 | if (!err) | |
1745 | ret = 0; | |
1746 | #endif | |
1747 | ||
1748 | return ret ? err : 0; | |
1749 | } | |
1750 | ||
1751 | static void __exit cyberpro_exit(void) | |
1752 | { | |
1753 | pci_unregister_driver(&cyberpro_driver); | |
1754 | } | |
1755 | ||
1756 | module_init(cyber2000fb_init); | |
1757 | module_exit(cyberpro_exit); | |
1758 | ||
1759 | MODULE_AUTHOR("Russell King"); | |
1760 | MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver"); | |
1761 | MODULE_LICENSE("GPL"); |