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1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/cyber2000fb.c | |
3 | * | |
4 | * Copyright (C) 1998-2002 Russell King | |
5 | * | |
6 | * MIPS and 50xx clock support | |
7 | * Copyright (C) 2001 Bradley D. LaRonde <brad@ltc.com> | |
8 | * | |
9 | * 32 bit support, text color and panning fixes for modes != 8 bit | |
10 | * Copyright (C) 2002 Denis Oliver Kropp <dok@directfb.org> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * Integraphics CyberPro 2000, 2010 and 5000 frame buffer device | |
17 | * | |
18 | * Based on cyberfb.c. | |
19 | * | |
20 | * Note that we now use the new fbcon fix, var and cmap scheme. We do | |
21 | * still have to check which console is the currently displayed one | |
22 | * however, especially for the colourmap stuff. | |
23 | * | |
24 | * We also use the new hotplug PCI subsystem. I'm not sure if there | |
25 | * are any such cards, but I'm erring on the side of caution. We don't | |
26 | * want to go pop just because someone does have one. | |
27 | * | |
28 | * Note that this doesn't work fully in the case of multiple CyberPro | |
29 | * cards with grabbers. We currently can only attach to the first | |
30 | * CyberPro card found. | |
31 | * | |
32 | * When we're in truecolour mode, we power down the LUT RAM as a power | |
33 | * saving feature. Also, when we enter any of the powersaving modes | |
34 | * (except soft blanking) we power down the RAMDACs. This saves about | |
35 | * 1W, which is roughly 8% of the power consumption of a NetWinder | |
36 | * (which, incidentally, is about the same saving as a 2.5in hard disk | |
37 | * entering standby mode.) | |
38 | */ | |
1da177e4 LT |
39 | #include <linux/module.h> |
40 | #include <linux/kernel.h> | |
41 | #include <linux/errno.h> | |
42 | #include <linux/string.h> | |
43 | #include <linux/mm.h> | |
1da177e4 LT |
44 | #include <linux/slab.h> |
45 | #include <linux/delay.h> | |
46 | #include <linux/fb.h> | |
47 | #include <linux/pci.h> | |
48 | #include <linux/init.h> | |
99730225 | 49 | #include <linux/io.h> |
1da177e4 | 50 | |
e5dedf8d OZ |
51 | #include <linux/i2c.h> |
52 | #include <linux/i2c-algo-bit.h> | |
53 | ||
1da177e4 LT |
54 | #include <asm/pgtable.h> |
55 | #include <asm/system.h> | |
1da177e4 LT |
56 | |
57 | #ifdef __arm__ | |
58 | #include <asm/mach-types.h> | |
59 | #endif | |
60 | ||
61 | #include "cyber2000fb.h" | |
62 | ||
63 | struct cfb_info { | |
64 | struct fb_info fb; | |
65 | struct display_switch *dispsw; | |
66 | struct display *display; | |
67 | struct pci_dev *dev; | |
532237ef | 68 | unsigned char __iomem *region; |
1da177e4 LT |
69 | unsigned char __iomem *regs; |
70 | u_int id; | |
71 | int func_use_count; | |
72 | u_long ref_ps; | |
73 | ||
74 | /* | |
75 | * Clock divisors | |
76 | */ | |
77 | u_int divisors[4]; | |
78 | ||
79 | struct { | |
80 | u8 red, green, blue; | |
81 | } palette[NR_PALETTE]; | |
82 | ||
83 | u_char mem_ctl1; | |
84 | u_char mem_ctl2; | |
85 | u_char mclk_mult; | |
86 | u_char mclk_div; | |
87 | /* | |
88 | * RAMDAC control register is both of these or'ed together | |
89 | */ | |
90 | u_char ramdac_ctrl; | |
91 | u_char ramdac_powerdown; | |
eca02b0c RK |
92 | |
93 | u32 pseudo_palette[16]; | |
052a7f5c RK |
94 | |
95 | spinlock_t reg_b0_lock; | |
96 | ||
e5dedf8d OZ |
97 | #ifdef CONFIG_FB_CYBER2000_DDC |
98 | bool ddc_registered; | |
99 | struct i2c_adapter ddc_adapter; | |
100 | struct i2c_algo_bit_data ddc_algo; | |
e5dedf8d | 101 | #endif |
1da177e4 LT |
102 | }; |
103 | ||
104 | static char *default_font = "Acorn8x8"; | |
105 | module_param(default_font, charp, 0); | |
106 | MODULE_PARM_DESC(default_font, "Default font name"); | |
107 | ||
108 | /* | |
109 | * Our access methods. | |
110 | */ | |
532237ef KH |
111 | #define cyber2000fb_writel(val, reg, cfb) writel(val, (cfb)->regs + (reg)) |
112 | #define cyber2000fb_writew(val, reg, cfb) writew(val, (cfb)->regs + (reg)) | |
113 | #define cyber2000fb_writeb(val, reg, cfb) writeb(val, (cfb)->regs + (reg)) | |
1da177e4 | 114 | |
532237ef | 115 | #define cyber2000fb_readb(reg, cfb) readb((cfb)->regs + (reg)) |
1da177e4 LT |
116 | |
117 | static inline void | |
118 | cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb) | |
119 | { | |
120 | cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb); | |
121 | } | |
122 | ||
123 | static inline void | |
124 | cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb) | |
125 | { | |
126 | cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb); | |
127 | } | |
128 | ||
129 | static inline unsigned int | |
130 | cyber2000_grphr(unsigned int reg, struct cfb_info *cfb) | |
131 | { | |
132 | cyber2000fb_writeb(reg, 0x3ce, cfb); | |
133 | return cyber2000fb_readb(0x3cf, cfb); | |
134 | } | |
135 | ||
136 | static inline void | |
137 | cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb) | |
138 | { | |
139 | cyber2000fb_readb(0x3da, cfb); | |
140 | cyber2000fb_writeb(reg, 0x3c0, cfb); | |
141 | cyber2000fb_readb(0x3c1, cfb); | |
142 | cyber2000fb_writeb(val, 0x3c0, cfb); | |
143 | } | |
144 | ||
145 | static inline void | |
146 | cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb) | |
147 | { | |
148 | cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb); | |
149 | } | |
150 | ||
151 | /* -------------------- Hardware specific routines ------------------------- */ | |
152 | ||
153 | /* | |
154 | * Hardware Cyber2000 Acceleration | |
155 | */ | |
156 | static void | |
157 | cyber2000fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
158 | { | |
159 | struct cfb_info *cfb = (struct cfb_info *)info; | |
160 | unsigned long dst, col; | |
161 | ||
162 | if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { | |
163 | cfb_fillrect(info, rect); | |
164 | return; | |
165 | } | |
166 | ||
167 | cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); | |
168 | cyber2000fb_writew(rect->width - 1, CO_REG_PIXWIDTH, cfb); | |
169 | cyber2000fb_writew(rect->height - 1, CO_REG_PIXHEIGHT, cfb); | |
170 | ||
171 | col = rect->color; | |
172 | if (cfb->fb.var.bits_per_pixel > 8) | |
173 | col = ((u32 *)cfb->fb.pseudo_palette)[col]; | |
174 | cyber2000fb_writel(col, CO_REG_FGCOLOUR, cfb); | |
175 | ||
176 | dst = rect->dx + rect->dy * cfb->fb.var.xres_virtual; | |
177 | if (cfb->fb.var.bits_per_pixel == 24) { | |
178 | cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb); | |
179 | dst *= 3; | |
180 | } | |
181 | ||
182 | cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb); | |
183 | cyber2000fb_writeb(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb); | |
184 | cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L, cfb); | |
185 | cyber2000fb_writew(CO_CMD_H_BLITTER, CO_REG_CMD_H, cfb); | |
186 | } | |
187 | ||
188 | static void | |
189 | cyber2000fb_copyarea(struct fb_info *info, const struct fb_copyarea *region) | |
190 | { | |
191 | struct cfb_info *cfb = (struct cfb_info *)info; | |
192 | unsigned int cmd = CO_CMD_L_PATTERN_FGCOL; | |
193 | unsigned long src, dst; | |
194 | ||
195 | if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { | |
196 | cfb_copyarea(info, region); | |
197 | return; | |
198 | } | |
199 | ||
200 | cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); | |
201 | cyber2000fb_writew(region->width - 1, CO_REG_PIXWIDTH, cfb); | |
202 | cyber2000fb_writew(region->height - 1, CO_REG_PIXHEIGHT, cfb); | |
203 | ||
204 | src = region->sx + region->sy * cfb->fb.var.xres_virtual; | |
205 | dst = region->dx + region->dy * cfb->fb.var.xres_virtual; | |
206 | ||
207 | if (region->sx < region->dx) { | |
208 | src += region->width - 1; | |
209 | dst += region->width - 1; | |
210 | cmd |= CO_CMD_L_INC_LEFT; | |
211 | } | |
212 | ||
213 | if (region->sy < region->dy) { | |
214 | src += (region->height - 1) * cfb->fb.var.xres_virtual; | |
215 | dst += (region->height - 1) * cfb->fb.var.xres_virtual; | |
216 | cmd |= CO_CMD_L_INC_UP; | |
217 | } | |
218 | ||
219 | if (cfb->fb.var.bits_per_pixel == 24) { | |
220 | cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb); | |
221 | src *= 3; | |
222 | dst *= 3; | |
223 | } | |
224 | cyber2000fb_writel(src, CO_REG_SRC1_PTR, cfb); | |
225 | cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb); | |
226 | cyber2000fb_writew(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb); | |
227 | cyber2000fb_writew(cmd, CO_REG_CMD_L, cfb); | |
228 | cyber2000fb_writew(CO_CMD_H_FGSRCMAP | CO_CMD_H_BLITTER, | |
229 | CO_REG_CMD_H, cfb); | |
230 | } | |
231 | ||
232 | static void | |
233 | cyber2000fb_imageblit(struct fb_info *info, const struct fb_image *image) | |
234 | { | |
532237ef KH |
235 | cfb_imageblit(info, image); |
236 | return; | |
1da177e4 LT |
237 | } |
238 | ||
239 | static int cyber2000fb_sync(struct fb_info *info) | |
240 | { | |
241 | struct cfb_info *cfb = (struct cfb_info *)info; | |
242 | int count = 100000; | |
243 | ||
244 | if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) | |
245 | return 0; | |
246 | ||
247 | while (cyber2000fb_readb(CO_REG_CONTROL, cfb) & CO_CTRL_BUSY) { | |
248 | if (!count--) { | |
249 | debug_printf("accel_wait timed out\n"); | |
250 | cyber2000fb_writeb(0, CO_REG_CONTROL, cfb); | |
251 | break; | |
252 | } | |
253 | udelay(1); | |
254 | } | |
255 | return 0; | |
256 | } | |
257 | ||
258 | /* | |
259 | * =========================================================================== | |
260 | */ | |
261 | ||
262 | static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf) | |
263 | { | |
264 | u_int mask = (1 << bf->length) - 1; | |
265 | ||
266 | return (val >> (16 - bf->length) & mask) << bf->offset; | |
267 | } | |
268 | ||
269 | /* | |
270 | * Set a single color register. Return != 0 for invalid regno. | |
271 | */ | |
272 | static int | |
273 | cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
274 | u_int transp, struct fb_info *info) | |
275 | { | |
276 | struct cfb_info *cfb = (struct cfb_info *)info; | |
277 | struct fb_var_screeninfo *var = &cfb->fb.var; | |
278 | u32 pseudo_val; | |
279 | int ret = 1; | |
280 | ||
281 | switch (cfb->fb.fix.visual) { | |
282 | default: | |
283 | return 1; | |
284 | ||
285 | /* | |
286 | * Pseudocolour: | |
532237ef | 287 | * 8 8 |
1da177e4 | 288 | * pixel --/--+--/--> red lut --> red dac |
532237ef KH |
289 | * | 8 |
290 | * +--/--> green lut --> green dac | |
291 | * | 8 | |
292 | * +--/--> blue lut --> blue dac | |
1da177e4 LT |
293 | */ |
294 | case FB_VISUAL_PSEUDOCOLOR: | |
295 | if (regno >= NR_PALETTE) | |
296 | return 1; | |
297 | ||
298 | red >>= 8; | |
299 | green >>= 8; | |
300 | blue >>= 8; | |
301 | ||
532237ef | 302 | cfb->palette[regno].red = red; |
1da177e4 | 303 | cfb->palette[regno].green = green; |
532237ef | 304 | cfb->palette[regno].blue = blue; |
1da177e4 LT |
305 | |
306 | cyber2000fb_writeb(regno, 0x3c8, cfb); | |
307 | cyber2000fb_writeb(red, 0x3c9, cfb); | |
308 | cyber2000fb_writeb(green, 0x3c9, cfb); | |
309 | cyber2000fb_writeb(blue, 0x3c9, cfb); | |
310 | return 0; | |
311 | ||
312 | /* | |
313 | * Direct colour: | |
532237ef KH |
314 | * n rl |
315 | * pixel --/--+--/--> red lut --> red dac | |
316 | * | gl | |
317 | * +--/--> green lut --> green dac | |
318 | * | bl | |
319 | * +--/--> blue lut --> blue dac | |
1da177e4 LT |
320 | * n = bpp, rl = red length, gl = green length, bl = blue length |
321 | */ | |
322 | case FB_VISUAL_DIRECTCOLOR: | |
323 | red >>= 8; | |
324 | green >>= 8; | |
325 | blue >>= 8; | |
326 | ||
327 | if (var->green.length == 6 && regno < 64) { | |
328 | cfb->palette[regno << 2].green = green; | |
329 | ||
330 | /* | |
331 | * The 6 bits of the green component are applied | |
332 | * to the high 6 bits of the LUT. | |
333 | */ | |
334 | cyber2000fb_writeb(regno << 2, 0x3c8, cfb); | |
532237ef KH |
335 | cyber2000fb_writeb(cfb->palette[regno >> 1].red, |
336 | 0x3c9, cfb); | |
1da177e4 | 337 | cyber2000fb_writeb(green, 0x3c9, cfb); |
532237ef KH |
338 | cyber2000fb_writeb(cfb->palette[regno >> 1].blue, |
339 | 0x3c9, cfb); | |
1da177e4 LT |
340 | |
341 | green = cfb->palette[regno << 3].green; | |
342 | ||
343 | ret = 0; | |
344 | } | |
345 | ||
346 | if (var->green.length >= 5 && regno < 32) { | |
532237ef | 347 | cfb->palette[regno << 3].red = red; |
1da177e4 | 348 | cfb->palette[regno << 3].green = green; |
532237ef | 349 | cfb->palette[regno << 3].blue = blue; |
1da177e4 LT |
350 | |
351 | /* | |
352 | * The 5 bits of each colour component are | |
353 | * applied to the high 5 bits of the LUT. | |
354 | */ | |
355 | cyber2000fb_writeb(regno << 3, 0x3c8, cfb); | |
356 | cyber2000fb_writeb(red, 0x3c9, cfb); | |
357 | cyber2000fb_writeb(green, 0x3c9, cfb); | |
358 | cyber2000fb_writeb(blue, 0x3c9, cfb); | |
359 | ret = 0; | |
360 | } | |
361 | ||
362 | if (var->green.length == 4 && regno < 16) { | |
532237ef | 363 | cfb->palette[regno << 4].red = red; |
1da177e4 | 364 | cfb->palette[regno << 4].green = green; |
532237ef | 365 | cfb->palette[regno << 4].blue = blue; |
1da177e4 LT |
366 | |
367 | /* | |
368 | * The 5 bits of each colour component are | |
369 | * applied to the high 5 bits of the LUT. | |
370 | */ | |
371 | cyber2000fb_writeb(regno << 4, 0x3c8, cfb); | |
372 | cyber2000fb_writeb(red, 0x3c9, cfb); | |
373 | cyber2000fb_writeb(green, 0x3c9, cfb); | |
374 | cyber2000fb_writeb(blue, 0x3c9, cfb); | |
375 | ret = 0; | |
376 | } | |
377 | ||
378 | /* | |
379 | * Since this is only used for the first 16 colours, we | |
380 | * don't have to care about overflowing for regno >= 32 | |
381 | */ | |
382 | pseudo_val = regno << var->red.offset | | |
383 | regno << var->green.offset | | |
384 | regno << var->blue.offset; | |
385 | break; | |
386 | ||
387 | /* | |
388 | * True colour: | |
532237ef KH |
389 | * n rl |
390 | * pixel --/--+--/--> red dac | |
391 | * | gl | |
392 | * +--/--> green dac | |
393 | * | bl | |
394 | * +--/--> blue dac | |
1da177e4 LT |
395 | * n = bpp, rl = red length, gl = green length, bl = blue length |
396 | */ | |
397 | case FB_VISUAL_TRUECOLOR: | |
398 | pseudo_val = convert_bitfield(transp ^ 0xffff, &var->transp); | |
399 | pseudo_val |= convert_bitfield(red, &var->red); | |
400 | pseudo_val |= convert_bitfield(green, &var->green); | |
401 | pseudo_val |= convert_bitfield(blue, &var->blue); | |
e76df4d3 | 402 | ret = 0; |
1da177e4 LT |
403 | break; |
404 | } | |
405 | ||
406 | /* | |
407 | * Now set our pseudo palette for the CFB16/24/32 drivers. | |
408 | */ | |
409 | if (regno < 16) | |
410 | ((u32 *)cfb->fb.pseudo_palette)[regno] = pseudo_val; | |
411 | ||
412 | return ret; | |
413 | } | |
414 | ||
415 | struct par_info { | |
416 | /* | |
417 | * Hardware | |
418 | */ | |
419 | u_char clock_mult; | |
420 | u_char clock_div; | |
421 | u_char extseqmisc; | |
422 | u_char co_pixfmt; | |
423 | u_char crtc_ofl; | |
424 | u_char crtc[19]; | |
425 | u_int width; | |
426 | u_int pitch; | |
427 | u_int fetch; | |
428 | ||
429 | /* | |
430 | * Other | |
431 | */ | |
432 | u_char ramdac; | |
433 | }; | |
434 | ||
435 | static const u_char crtc_idx[] = { | |
436 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, | |
437 | 0x08, 0x09, | |
438 | 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18 | |
439 | }; | |
440 | ||
441 | static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb) | |
442 | { | |
443 | unsigned int i; | |
444 | unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown; | |
445 | ||
446 | cyber2000fb_writeb(0x56, 0x3ce, cfb); | |
447 | i = cyber2000fb_readb(0x3cf, cfb); | |
448 | cyber2000fb_writeb(i | 4, 0x3cf, cfb); | |
449 | cyber2000fb_writeb(val, 0x3c6, cfb); | |
450 | cyber2000fb_writeb(i, 0x3cf, cfb); | |
00b4703f OZ |
451 | /* prevent card lock-up observed on x86 with CyberPro 2000 */ |
452 | cyber2000fb_readb(0x3cf, cfb); | |
1da177e4 LT |
453 | } |
454 | ||
455 | static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw) | |
456 | { | |
457 | u_int i; | |
458 | ||
459 | /* | |
460 | * Blank palette | |
461 | */ | |
462 | for (i = 0; i < NR_PALETTE; i++) { | |
463 | cyber2000fb_writeb(i, 0x3c8, cfb); | |
464 | cyber2000fb_writeb(0, 0x3c9, cfb); | |
465 | cyber2000fb_writeb(0, 0x3c9, cfb); | |
466 | cyber2000fb_writeb(0, 0x3c9, cfb); | |
467 | } | |
468 | ||
469 | cyber2000fb_writeb(0xef, 0x3c2, cfb); | |
470 | cyber2000_crtcw(0x11, 0x0b, cfb); | |
471 | cyber2000_attrw(0x11, 0x00, cfb); | |
472 | ||
473 | cyber2000_seqw(0x00, 0x01, cfb); | |
474 | cyber2000_seqw(0x01, 0x01, cfb); | |
475 | cyber2000_seqw(0x02, 0x0f, cfb); | |
476 | cyber2000_seqw(0x03, 0x00, cfb); | |
477 | cyber2000_seqw(0x04, 0x0e, cfb); | |
478 | cyber2000_seqw(0x00, 0x03, cfb); | |
479 | ||
480 | for (i = 0; i < sizeof(crtc_idx); i++) | |
481 | cyber2000_crtcw(crtc_idx[i], hw->crtc[i], cfb); | |
482 | ||
483 | for (i = 0x0a; i < 0x10; i++) | |
484 | cyber2000_crtcw(i, 0, cfb); | |
485 | ||
486 | cyber2000_grphw(EXT_CRT_VRTOFL, hw->crtc_ofl, cfb); | |
487 | cyber2000_grphw(0x00, 0x00, cfb); | |
488 | cyber2000_grphw(0x01, 0x00, cfb); | |
489 | cyber2000_grphw(0x02, 0x00, cfb); | |
490 | cyber2000_grphw(0x03, 0x00, cfb); | |
491 | cyber2000_grphw(0x04, 0x00, cfb); | |
492 | cyber2000_grphw(0x05, 0x60, cfb); | |
493 | cyber2000_grphw(0x06, 0x05, cfb); | |
494 | cyber2000_grphw(0x07, 0x0f, cfb); | |
495 | cyber2000_grphw(0x08, 0xff, cfb); | |
496 | ||
497 | /* Attribute controller registers */ | |
498 | for (i = 0; i < 16; i++) | |
499 | cyber2000_attrw(i, i, cfb); | |
500 | ||
501 | cyber2000_attrw(0x10, 0x01, cfb); | |
502 | cyber2000_attrw(0x11, 0x00, cfb); | |
503 | cyber2000_attrw(0x12, 0x0f, cfb); | |
504 | cyber2000_attrw(0x13, 0x00, cfb); | |
505 | cyber2000_attrw(0x14, 0x00, cfb); | |
506 | ||
507 | /* PLL registers */ | |
e5dedf8d | 508 | spin_lock(&cfb->reg_b0_lock); |
1da177e4 | 509 | cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb); |
532237ef | 510 | cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb); |
1da177e4 | 511 | cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb); |
532237ef | 512 | cyber2000_grphw(EXT_MCLK_DIV, cfb->mclk_div, cfb); |
1da177e4 LT |
513 | cyber2000_grphw(0x90, 0x01, cfb); |
514 | cyber2000_grphw(0xb9, 0x80, cfb); | |
515 | cyber2000_grphw(0xb9, 0x00, cfb); | |
e5dedf8d | 516 | spin_unlock(&cfb->reg_b0_lock); |
1da177e4 LT |
517 | |
518 | cfb->ramdac_ctrl = hw->ramdac; | |
519 | cyber2000fb_write_ramdac_ctrl(cfb); | |
520 | ||
521 | cyber2000fb_writeb(0x20, 0x3c0, cfb); | |
522 | cyber2000fb_writeb(0xff, 0x3c6, cfb); | |
523 | ||
524 | cyber2000_grphw(0x14, hw->fetch, cfb); | |
525 | cyber2000_grphw(0x15, ((hw->fetch >> 8) & 0x03) | | |
526 | ((hw->pitch >> 4) & 0x30), cfb); | |
527 | cyber2000_grphw(EXT_SEQ_MISC, hw->extseqmisc, cfb); | |
528 | ||
529 | /* | |
530 | * Set up accelerator registers | |
531 | */ | |
532237ef KH |
532 | cyber2000fb_writew(hw->width, CO_REG_SRC_WIDTH, cfb); |
533 | cyber2000fb_writew(hw->width, CO_REG_DEST_WIDTH, cfb); | |
1da177e4 LT |
534 | cyber2000fb_writeb(hw->co_pixfmt, CO_REG_PIXFMT, cfb); |
535 | } | |
536 | ||
537 | static inline int | |
538 | cyber2000fb_update_start(struct cfb_info *cfb, struct fb_var_screeninfo *var) | |
539 | { | |
540 | u_int base = var->yoffset * var->xres_virtual + var->xoffset; | |
541 | ||
542 | base *= var->bits_per_pixel; | |
543 | ||
544 | /* | |
545 | * Convert to bytes and shift two extra bits because DAC | |
546 | * can only start on 4 byte aligned data. | |
547 | */ | |
548 | base >>= 5; | |
549 | ||
550 | if (base >= 1 << 20) | |
551 | return -EINVAL; | |
552 | ||
553 | cyber2000_grphw(0x10, base >> 16 | 0x10, cfb); | |
554 | cyber2000_crtcw(0x0c, base >> 8, cfb); | |
555 | cyber2000_crtcw(0x0d, base, cfb); | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
560 | static int | |
561 | cyber2000fb_decode_crtc(struct par_info *hw, struct cfb_info *cfb, | |
562 | struct fb_var_screeninfo *var) | |
563 | { | |
564 | u_int Htotal, Hblankend, Hsyncend; | |
565 | u_int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend; | |
532237ef | 566 | #define ENCODE_BIT(v, b1, m, b2) ((((v) >> (b1)) & (m)) << (b2)) |
1da177e4 LT |
567 | |
568 | hw->crtc[13] = hw->pitch; | |
569 | hw->crtc[17] = 0xe3; | |
570 | hw->crtc[14] = 0; | |
571 | hw->crtc[8] = 0; | |
572 | ||
532237ef KH |
573 | Htotal = var->xres + var->right_margin + |
574 | var->hsync_len + var->left_margin; | |
1da177e4 LT |
575 | |
576 | if (Htotal > 2080) | |
577 | return -EINVAL; | |
578 | ||
579 | hw->crtc[0] = (Htotal >> 3) - 5; | |
580 | hw->crtc[1] = (var->xres >> 3) - 1; | |
581 | hw->crtc[2] = var->xres >> 3; | |
582 | hw->crtc[4] = (var->xres + var->right_margin) >> 3; | |
583 | ||
532237ef | 584 | Hblankend = (Htotal - 4 * 8) >> 3; |
1da177e4 | 585 | |
87d06131 JS |
586 | hw->crtc[3] = ENCODE_BIT(Hblankend, 0, 0x1f, 0) | |
587 | ENCODE_BIT(1, 0, 0x01, 7); | |
1da177e4 LT |
588 | |
589 | Hsyncend = (var->xres + var->right_margin + var->hsync_len) >> 3; | |
590 | ||
87d06131 JS |
591 | hw->crtc[5] = ENCODE_BIT(Hsyncend, 0, 0x1f, 0) | |
592 | ENCODE_BIT(Hblankend, 5, 0x01, 7); | |
1da177e4 LT |
593 | |
594 | Vdispend = var->yres - 1; | |
595 | Vsyncstart = var->yres + var->lower_margin; | |
596 | Vsyncend = var->yres + var->lower_margin + var->vsync_len; | |
597 | Vtotal = var->yres + var->lower_margin + var->vsync_len + | |
598 | var->upper_margin - 2; | |
599 | ||
600 | if (Vtotal > 2047) | |
601 | return -EINVAL; | |
602 | ||
603 | Vblankstart = var->yres + 6; | |
604 | Vblankend = Vtotal - 10; | |
605 | ||
606 | hw->crtc[6] = Vtotal; | |
87d06131 JS |
607 | hw->crtc[7] = ENCODE_BIT(Vtotal, 8, 0x01, 0) | |
608 | ENCODE_BIT(Vdispend, 8, 0x01, 1) | | |
609 | ENCODE_BIT(Vsyncstart, 8, 0x01, 2) | | |
532237ef | 610 | ENCODE_BIT(Vblankstart, 8, 0x01, 3) | |
87d06131 | 611 | ENCODE_BIT(1, 0, 0x01, 4) | |
532237ef | 612 | ENCODE_BIT(Vtotal, 9, 0x01, 5) | |
87d06131 JS |
613 | ENCODE_BIT(Vdispend, 9, 0x01, 6) | |
614 | ENCODE_BIT(Vsyncstart, 9, 0x01, 7); | |
615 | hw->crtc[9] = ENCODE_BIT(0, 0, 0x1f, 0) | | |
532237ef | 616 | ENCODE_BIT(Vblankstart, 9, 0x01, 5) | |
87d06131 | 617 | ENCODE_BIT(1, 0, 0x01, 6); |
1da177e4 | 618 | hw->crtc[10] = Vsyncstart; |
87d06131 JS |
619 | hw->crtc[11] = ENCODE_BIT(Vsyncend, 0, 0x0f, 0) | |
620 | ENCODE_BIT(1, 0, 0x01, 7); | |
1da177e4 LT |
621 | hw->crtc[12] = Vdispend; |
622 | hw->crtc[15] = Vblankstart; | |
623 | hw->crtc[16] = Vblankend; | |
624 | hw->crtc[18] = 0xff; | |
625 | ||
626 | /* | |
627 | * overflow - graphics reg 0x11 | |
628 | * 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10 | |
629 | * 4=LINECOMP:10 5-IVIDEO 6=FIXCNT | |
630 | */ | |
631 | hw->crtc_ofl = | |
532237ef KH |
632 | ENCODE_BIT(Vtotal, 10, 0x01, 0) | |
633 | ENCODE_BIT(Vdispend, 10, 0x01, 1) | | |
634 | ENCODE_BIT(Vsyncstart, 10, 0x01, 2) | | |
635 | ENCODE_BIT(Vblankstart, 10, 0x01, 3) | | |
1da177e4 LT |
636 | EXT_CRT_VRTOFL_LINECOMP10; |
637 | ||
638 | /* woody: set the interlaced bit... */ | |
639 | /* FIXME: what about doublescan? */ | |
640 | if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) | |
641 | hw->crtc_ofl |= EXT_CRT_VRTOFL_INTERLACE; | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
646 | /* | |
647 | * The following was discovered by a good monitor, bit twiddling, theorising | |
648 | * and but mostly luck. Strangely, it looks like everyone elses' PLL! | |
649 | * | |
650 | * Clock registers: | |
651 | * fclock = fpll / div2 | |
652 | * fpll = fref * mult / div1 | |
653 | * where: | |
654 | * fref = 14.318MHz (69842ps) | |
655 | * mult = reg0xb0.7:0 | |
656 | * div1 = (reg0xb1.5:0 + 1) | |
657 | * div2 = 2^(reg0xb1.7:6) | |
658 | * fpll should be between 115 and 260 MHz | |
659 | * (8696ps and 3846ps) | |
660 | */ | |
661 | static int | |
662 | cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb, | |
663 | struct fb_var_screeninfo *var) | |
664 | { | |
665 | u_long pll_ps = var->pixclock; | |
666 | const u_long ref_ps = cfb->ref_ps; | |
667 | u_int div2, t_div1, best_div1, best_mult; | |
668 | int best_diff; | |
669 | int vco; | |
670 | ||
671 | /* | |
672 | * Step 1: | |
673 | * find div2 such that 115MHz < fpll < 260MHz | |
674 | * and 0 <= div2 < 4 | |
675 | */ | |
676 | for (div2 = 0; div2 < 4; div2++) { | |
677 | u_long new_pll; | |
678 | ||
679 | new_pll = pll_ps / cfb->divisors[div2]; | |
680 | if (8696 > new_pll && new_pll > 3846) { | |
681 | pll_ps = new_pll; | |
682 | break; | |
683 | } | |
684 | } | |
685 | ||
686 | if (div2 == 4) | |
687 | return -EINVAL; | |
688 | ||
689 | /* | |
690 | * Step 2: | |
691 | * Given pll_ps and ref_ps, find: | |
692 | * pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005 | |
693 | * where { 1 < best_div1 < 32, 1 < best_mult < 256 } | |
694 | * pll_ps_calc = best_div1 / (ref_ps * best_mult) | |
695 | */ | |
696 | best_diff = 0x7fffffff; | |
fcd3c779 RK |
697 | best_mult = 2; |
698 | best_div1 = 32; | |
699 | for (t_div1 = 2; t_div1 < 32; t_div1 += 1) { | |
1da177e4 LT |
700 | u_int rr, t_mult, t_pll_ps; |
701 | int diff; | |
702 | ||
703 | /* | |
704 | * Find the multiplier for this divisor | |
705 | */ | |
706 | rr = ref_ps * t_div1; | |
707 | t_mult = (rr + pll_ps / 2) / pll_ps; | |
708 | ||
709 | /* | |
710 | * Is the multiplier within the correct range? | |
711 | */ | |
712 | if (t_mult > 256 || t_mult < 2) | |
713 | continue; | |
714 | ||
715 | /* | |
716 | * Calculate the actual clock period from this multiplier | |
717 | * and divisor, and estimate the error. | |
718 | */ | |
719 | t_pll_ps = (rr + t_mult / 2) / t_mult; | |
720 | diff = pll_ps - t_pll_ps; | |
721 | if (diff < 0) | |
722 | diff = -diff; | |
723 | ||
724 | if (diff < best_diff) { | |
725 | best_diff = diff; | |
726 | best_mult = t_mult; | |
727 | best_div1 = t_div1; | |
728 | } | |
729 | ||
730 | /* | |
731 | * If we hit an exact value, there is no point in continuing. | |
732 | */ | |
733 | if (diff == 0) | |
734 | break; | |
735 | } | |
736 | ||
737 | /* | |
738 | * Step 3: | |
739 | * combine values | |
740 | */ | |
741 | hw->clock_mult = best_mult - 1; | |
742 | hw->clock_div = div2 << 6 | (best_div1 - 1); | |
743 | ||
744 | vco = ref_ps * best_div1 / best_mult; | |
745 | if ((ref_ps == 40690) && (vco < 5556)) | |
746 | /* Set VFSEL when VCO > 180MHz (5.556 ps). */ | |
747 | hw->clock_div |= EXT_DCLK_DIV_VFSEL; | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
752 | /* | |
753 | * Set the User Defined Part of the Display | |
754 | */ | |
755 | static int | |
756 | cyber2000fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
757 | { | |
758 | struct cfb_info *cfb = (struct cfb_info *)info; | |
759 | struct par_info hw; | |
760 | unsigned int mem; | |
761 | int err; | |
762 | ||
763 | var->transp.msb_right = 0; | |
764 | var->red.msb_right = 0; | |
765 | var->green.msb_right = 0; | |
766 | var->blue.msb_right = 0; | |
532237ef KH |
767 | var->transp.offset = 0; |
768 | var->transp.length = 0; | |
1da177e4 LT |
769 | |
770 | switch (var->bits_per_pixel) { | |
771 | case 8: /* PSEUDOCOLOUR, 256 */ | |
1da177e4 LT |
772 | var->red.offset = 0; |
773 | var->red.length = 8; | |
774 | var->green.offset = 0; | |
775 | var->green.length = 8; | |
776 | var->blue.offset = 0; | |
777 | var->blue.length = 8; | |
778 | break; | |
779 | ||
780 | case 16:/* DIRECTCOLOUR, 64k or 32k */ | |
781 | switch (var->green.length) { | |
782 | case 6: /* RGB565, 64k */ | |
1da177e4 LT |
783 | var->red.offset = 11; |
784 | var->red.length = 5; | |
785 | var->green.offset = 5; | |
786 | var->green.length = 6; | |
787 | var->blue.offset = 0; | |
788 | var->blue.length = 5; | |
789 | break; | |
790 | ||
791 | default: | |
792 | case 5: /* RGB555, 32k */ | |
1da177e4 LT |
793 | var->red.offset = 10; |
794 | var->red.length = 5; | |
795 | var->green.offset = 5; | |
796 | var->green.length = 5; | |
797 | var->blue.offset = 0; | |
798 | var->blue.length = 5; | |
799 | break; | |
800 | ||
801 | case 4: /* RGB444, 4k + transparency? */ | |
802 | var->transp.offset = 12; | |
803 | var->transp.length = 4; | |
804 | var->red.offset = 8; | |
805 | var->red.length = 4; | |
806 | var->green.offset = 4; | |
807 | var->green.length = 4; | |
808 | var->blue.offset = 0; | |
809 | var->blue.length = 4; | |
810 | break; | |
811 | } | |
812 | break; | |
813 | ||
814 | case 24:/* TRUECOLOUR, 16m */ | |
1da177e4 LT |
815 | var->red.offset = 16; |
816 | var->red.length = 8; | |
817 | var->green.offset = 8; | |
818 | var->green.length = 8; | |
819 | var->blue.offset = 0; | |
820 | var->blue.length = 8; | |
821 | break; | |
822 | ||
823 | case 32:/* TRUECOLOUR, 16m */ | |
824 | var->transp.offset = 24; | |
825 | var->transp.length = 8; | |
826 | var->red.offset = 16; | |
827 | var->red.length = 8; | |
828 | var->green.offset = 8; | |
829 | var->green.length = 8; | |
830 | var->blue.offset = 0; | |
831 | var->blue.length = 8; | |
832 | break; | |
833 | ||
834 | default: | |
835 | return -EINVAL; | |
836 | } | |
837 | ||
838 | mem = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8); | |
839 | if (mem > cfb->fb.fix.smem_len) | |
840 | var->yres_virtual = cfb->fb.fix.smem_len * 8 / | |
532237ef | 841 | (var->bits_per_pixel * var->xres_virtual); |
1da177e4 LT |
842 | |
843 | if (var->yres > var->yres_virtual) | |
844 | var->yres = var->yres_virtual; | |
845 | if (var->xres > var->xres_virtual) | |
846 | var->xres = var->xres_virtual; | |
847 | ||
848 | err = cyber2000fb_decode_clock(&hw, cfb, var); | |
849 | if (err) | |
850 | return err; | |
851 | ||
852 | err = cyber2000fb_decode_crtc(&hw, cfb, var); | |
853 | if (err) | |
854 | return err; | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
859 | static int cyber2000fb_set_par(struct fb_info *info) | |
860 | { | |
861 | struct cfb_info *cfb = (struct cfb_info *)info; | |
862 | struct fb_var_screeninfo *var = &cfb->fb.var; | |
863 | struct par_info hw; | |
864 | unsigned int mem; | |
865 | ||
866 | hw.width = var->xres_virtual; | |
867 | hw.ramdac = RAMDAC_VREFEN | RAMDAC_DAC8BIT; | |
868 | ||
869 | switch (var->bits_per_pixel) { | |
870 | case 8: | |
871 | hw.co_pixfmt = CO_PIXFMT_8BPP; | |
872 | hw.pitch = hw.width >> 3; | |
873 | hw.extseqmisc = EXT_SEQ_MISC_8; | |
874 | break; | |
875 | ||
876 | case 16: | |
877 | hw.co_pixfmt = CO_PIXFMT_16BPP; | |
878 | hw.pitch = hw.width >> 2; | |
879 | ||
880 | switch (var->green.length) { | |
881 | case 6: /* RGB565, 64k */ | |
882 | hw.extseqmisc = EXT_SEQ_MISC_16_RGB565; | |
883 | break; | |
884 | case 5: /* RGB555, 32k */ | |
885 | hw.extseqmisc = EXT_SEQ_MISC_16_RGB555; | |
886 | break; | |
887 | case 4: /* RGB444, 4k + transparency? */ | |
888 | hw.extseqmisc = EXT_SEQ_MISC_16_RGB444; | |
889 | break; | |
890 | default: | |
891 | BUG(); | |
892 | } | |
c2ec21c5 JR |
893 | break; |
894 | ||
1da177e4 LT |
895 | case 24:/* TRUECOLOUR, 16m */ |
896 | hw.co_pixfmt = CO_PIXFMT_24BPP; | |
897 | hw.width *= 3; | |
898 | hw.pitch = hw.width >> 3; | |
899 | hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN); | |
900 | hw.extseqmisc = EXT_SEQ_MISC_24_RGB888; | |
901 | break; | |
902 | ||
903 | case 32:/* TRUECOLOUR, 16m */ | |
904 | hw.co_pixfmt = CO_PIXFMT_32BPP; | |
905 | hw.pitch = hw.width >> 1; | |
906 | hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN); | |
907 | hw.extseqmisc = EXT_SEQ_MISC_32; | |
908 | break; | |
909 | ||
910 | default: | |
911 | BUG(); | |
912 | } | |
913 | ||
914 | /* | |
915 | * Sigh, this is absolutely disgusting, but caused by | |
916 | * the way the fbcon developers want to separate out | |
917 | * the "checking" and the "setting" of the video mode. | |
918 | * | |
919 | * If the mode is not suitable for the hardware here, | |
920 | * we can't prevent it being set by returning an error. | |
921 | * | |
922 | * In theory, since NetWinders contain just one VGA card, | |
923 | * we should never end up hitting this problem. | |
924 | */ | |
925 | BUG_ON(cyber2000fb_decode_clock(&hw, cfb, var) != 0); | |
926 | BUG_ON(cyber2000fb_decode_crtc(&hw, cfb, var) != 0); | |
927 | ||
928 | hw.width -= 1; | |
929 | hw.fetch = hw.pitch; | |
930 | if (!(cfb->mem_ctl2 & MEM_CTL2_64BIT)) | |
931 | hw.fetch <<= 1; | |
932 | hw.fetch += 1; | |
933 | ||
532237ef | 934 | cfb->fb.fix.line_length = var->xres_virtual * var->bits_per_pixel / 8; |
1da177e4 LT |
935 | |
936 | /* | |
937 | * Same here - if the size of the video mode exceeds the | |
938 | * available RAM, we can't prevent this mode being set. | |
939 | * | |
940 | * In theory, since NetWinders contain just one VGA card, | |
941 | * we should never end up hitting this problem. | |
942 | */ | |
943 | mem = cfb->fb.fix.line_length * var->yres_virtual; | |
944 | BUG_ON(mem > cfb->fb.fix.smem_len); | |
945 | ||
946 | /* | |
947 | * 8bpp displays are always pseudo colour. 16bpp and above | |
948 | * are direct colour or true colour, depending on whether | |
949 | * the RAMDAC palettes are bypassed. (Direct colour has | |
950 | * palettes, true colour does not.) | |
951 | */ | |
952 | if (var->bits_per_pixel == 8) | |
953 | cfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
954 | else if (hw.ramdac & RAMDAC_BYPASS) | |
955 | cfb->fb.fix.visual = FB_VISUAL_TRUECOLOR; | |
956 | else | |
957 | cfb->fb.fix.visual = FB_VISUAL_DIRECTCOLOR; | |
958 | ||
959 | cyber2000fb_set_timing(cfb, &hw); | |
960 | cyber2000fb_update_start(cfb, var); | |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
1da177e4 LT |
965 | /* |
966 | * Pan or Wrap the Display | |
967 | */ | |
968 | static int | |
969 | cyber2000fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) | |
970 | { | |
971 | struct cfb_info *cfb = (struct cfb_info *)info; | |
972 | ||
973 | if (cyber2000fb_update_start(cfb, var)) | |
974 | return -EINVAL; | |
975 | ||
976 | cfb->fb.var.xoffset = var->xoffset; | |
977 | cfb->fb.var.yoffset = var->yoffset; | |
978 | ||
979 | if (var->vmode & FB_VMODE_YWRAP) { | |
980 | cfb->fb.var.vmode |= FB_VMODE_YWRAP; | |
981 | } else { | |
982 | cfb->fb.var.vmode &= ~FB_VMODE_YWRAP; | |
983 | } | |
984 | ||
985 | return 0; | |
986 | } | |
987 | ||
988 | /* | |
989 | * (Un)Blank the display. | |
990 | * | |
991 | * Blank the screen if blank_mode != 0, else unblank. If | |
992 | * blank == NULL then the caller blanks by setting the CLUT | |
993 | * (Color Look Up Table) to all black. Return 0 if blanking | |
994 | * succeeded, != 0 if un-/blanking failed due to e.g. a | |
995 | * video mode which doesn't support it. Implements VESA | |
996 | * suspend and powerdown modes on hardware that supports | |
997 | * disabling hsync/vsync: | |
998 | * blank_mode == 2: suspend vsync | |
999 | * blank_mode == 3: suspend hsync | |
1000 | * blank_mode == 4: powerdown | |
1001 | * | |
1002 | * wms...Enable VESA DMPS compatible powerdown mode | |
1003 | * run "setterm -powersave powerdown" to take advantage | |
1004 | */ | |
1005 | static int cyber2000fb_blank(int blank, struct fb_info *info) | |
1006 | { | |
1007 | struct cfb_info *cfb = (struct cfb_info *)info; | |
1008 | unsigned int sync = 0; | |
1009 | int i; | |
1010 | ||
1011 | switch (blank) { | |
1012 | case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */ | |
1013 | sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_0; | |
532237ef | 1014 | break; |
1da177e4 LT |
1015 | case FB_BLANK_HSYNC_SUSPEND: /* hsync off */ |
1016 | sync = EXT_SYNC_CTL_VS_NORMAL | EXT_SYNC_CTL_HS_0; | |
532237ef | 1017 | break; |
1da177e4 LT |
1018 | case FB_BLANK_VSYNC_SUSPEND: /* vsync off */ |
1019 | sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_NORMAL; | |
1020 | break; | |
532237ef KH |
1021 | case FB_BLANK_NORMAL: /* soft blank */ |
1022 | default: /* unblank */ | |
1da177e4 LT |
1023 | break; |
1024 | } | |
1025 | ||
1026 | cyber2000_grphw(EXT_SYNC_CTL, sync, cfb); | |
1027 | ||
1028 | if (blank <= 1) { | |
1029 | /* turn on ramdacs */ | |
532237ef KH |
1030 | cfb->ramdac_powerdown &= ~(RAMDAC_DACPWRDN | RAMDAC_BYPASS | |
1031 | RAMDAC_RAMPWRDN); | |
1da177e4 LT |
1032 | cyber2000fb_write_ramdac_ctrl(cfb); |
1033 | } | |
1034 | ||
1035 | /* | |
1036 | * Soft blank/unblank the display. | |
1037 | */ | |
1038 | if (blank) { /* soft blank */ | |
1039 | for (i = 0; i < NR_PALETTE; i++) { | |
1040 | cyber2000fb_writeb(i, 0x3c8, cfb); | |
1041 | cyber2000fb_writeb(0, 0x3c9, cfb); | |
1042 | cyber2000fb_writeb(0, 0x3c9, cfb); | |
1043 | cyber2000fb_writeb(0, 0x3c9, cfb); | |
1044 | } | |
1045 | } else { /* unblank */ | |
1046 | for (i = 0; i < NR_PALETTE; i++) { | |
1047 | cyber2000fb_writeb(i, 0x3c8, cfb); | |
1048 | cyber2000fb_writeb(cfb->palette[i].red, 0x3c9, cfb); | |
1049 | cyber2000fb_writeb(cfb->palette[i].green, 0x3c9, cfb); | |
1050 | cyber2000fb_writeb(cfb->palette[i].blue, 0x3c9, cfb); | |
1051 | } | |
1052 | } | |
1053 | ||
1054 | if (blank >= 2) { | |
1055 | /* turn off ramdacs */ | |
532237ef KH |
1056 | cfb->ramdac_powerdown |= RAMDAC_DACPWRDN | RAMDAC_BYPASS | |
1057 | RAMDAC_RAMPWRDN; | |
1da177e4 LT |
1058 | cyber2000fb_write_ramdac_ctrl(cfb); |
1059 | } | |
1060 | ||
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | static struct fb_ops cyber2000fb_ops = { | |
1065 | .owner = THIS_MODULE, | |
1066 | .fb_check_var = cyber2000fb_check_var, | |
1067 | .fb_set_par = cyber2000fb_set_par, | |
1068 | .fb_setcolreg = cyber2000fb_setcolreg, | |
1069 | .fb_blank = cyber2000fb_blank, | |
1070 | .fb_pan_display = cyber2000fb_pan_display, | |
1071 | .fb_fillrect = cyber2000fb_fillrect, | |
1072 | .fb_copyarea = cyber2000fb_copyarea, | |
1073 | .fb_imageblit = cyber2000fb_imageblit, | |
1da177e4 LT |
1074 | .fb_sync = cyber2000fb_sync, |
1075 | }; | |
1076 | ||
1077 | /* | |
1078 | * This is the only "static" reference to the internal data structures | |
1079 | * of this driver. It is here solely at the moment to support the other | |
1080 | * CyberPro modules external to this driver. | |
1081 | */ | |
532237ef | 1082 | static struct cfb_info *int_cfb_info; |
1da177e4 LT |
1083 | |
1084 | /* | |
1085 | * Enable access to the extended registers | |
1086 | */ | |
1087 | void cyber2000fb_enable_extregs(struct cfb_info *cfb) | |
1088 | { | |
1089 | cfb->func_use_count += 1; | |
1090 | ||
1091 | if (cfb->func_use_count == 1) { | |
1092 | int old; | |
1093 | ||
1094 | old = cyber2000_grphr(EXT_FUNC_CTL, cfb); | |
1095 | old |= EXT_FUNC_CTL_EXTREGENBL; | |
1096 | cyber2000_grphw(EXT_FUNC_CTL, old, cfb); | |
1097 | } | |
1098 | } | |
532237ef | 1099 | EXPORT_SYMBOL(cyber2000fb_enable_extregs); |
1da177e4 LT |
1100 | |
1101 | /* | |
1102 | * Disable access to the extended registers | |
1103 | */ | |
1104 | void cyber2000fb_disable_extregs(struct cfb_info *cfb) | |
1105 | { | |
1106 | if (cfb->func_use_count == 1) { | |
1107 | int old; | |
1108 | ||
1109 | old = cyber2000_grphr(EXT_FUNC_CTL, cfb); | |
1110 | old &= ~EXT_FUNC_CTL_EXTREGENBL; | |
1111 | cyber2000_grphw(EXT_FUNC_CTL, old, cfb); | |
1112 | } | |
1113 | ||
1114 | if (cfb->func_use_count == 0) | |
1115 | printk(KERN_ERR "disable_extregs: count = 0\n"); | |
1116 | else | |
1117 | cfb->func_use_count -= 1; | |
1118 | } | |
532237ef | 1119 | EXPORT_SYMBOL(cyber2000fb_disable_extregs); |
1da177e4 LT |
1120 | |
1121 | void cyber2000fb_get_fb_var(struct cfb_info *cfb, struct fb_var_screeninfo *var) | |
1122 | { | |
1123 | memcpy(var, &cfb->fb.var, sizeof(struct fb_var_screeninfo)); | |
1124 | } | |
532237ef | 1125 | EXPORT_SYMBOL(cyber2000fb_get_fb_var); |
1da177e4 LT |
1126 | |
1127 | /* | |
1128 | * Attach a capture/tv driver to the core CyberX0X0 driver. | |
1129 | */ | |
1130 | int cyber2000fb_attach(struct cyberpro_info *info, int idx) | |
1131 | { | |
1132 | if (int_cfb_info != NULL) { | |
1133 | info->dev = int_cfb_info->dev; | |
1134 | info->regs = int_cfb_info->regs; | |
1135 | info->fb = int_cfb_info->fb.screen_base; | |
1136 | info->fb_size = int_cfb_info->fb.fix.smem_len; | |
1137 | info->enable_extregs = cyber2000fb_enable_extregs; | |
1138 | info->disable_extregs = cyber2000fb_disable_extregs; | |
532237ef | 1139 | info->info = int_cfb_info; |
1da177e4 | 1140 | |
532237ef KH |
1141 | strlcpy(info->dev_name, int_cfb_info->fb.fix.id, |
1142 | sizeof(info->dev_name)); | |
1da177e4 LT |
1143 | } |
1144 | ||
1145 | return int_cfb_info != NULL; | |
1146 | } | |
532237ef | 1147 | EXPORT_SYMBOL(cyber2000fb_attach); |
1da177e4 LT |
1148 | |
1149 | /* | |
1150 | * Detach a capture/tv driver from the core CyberX0X0 driver. | |
1151 | */ | |
1152 | void cyber2000fb_detach(int idx) | |
1153 | { | |
1154 | } | |
1da177e4 | 1155 | EXPORT_SYMBOL(cyber2000fb_detach); |
1da177e4 | 1156 | |
e5dedf8d OZ |
1157 | #ifdef CONFIG_FB_CYBER2000_DDC |
1158 | ||
1159 | #define DDC_REG 0xb0 | |
1160 | #define DDC_SCL_OUT (1 << 0) | |
1161 | #define DDC_SDA_OUT (1 << 4) | |
1162 | #define DDC_SCL_IN (1 << 2) | |
1163 | #define DDC_SDA_IN (1 << 6) | |
1164 | ||
1165 | static void cyber2000fb_enable_ddc(struct cfb_info *cfb) | |
1166 | { | |
1167 | spin_lock(&cfb->reg_b0_lock); | |
1168 | cyber2000fb_writew(0x1bf, 0x3ce, cfb); | |
1169 | } | |
1170 | ||
1171 | static void cyber2000fb_disable_ddc(struct cfb_info *cfb) | |
1172 | { | |
1173 | cyber2000fb_writew(0x0bf, 0x3ce, cfb); | |
1174 | spin_unlock(&cfb->reg_b0_lock); | |
1175 | } | |
1176 | ||
1177 | ||
1178 | static void cyber2000fb_ddc_setscl(void *data, int val) | |
1179 | { | |
1180 | struct cfb_info *cfb = data; | |
1181 | unsigned char reg; | |
1182 | ||
1183 | cyber2000fb_enable_ddc(cfb); | |
1184 | reg = cyber2000_grphr(DDC_REG, cfb); | |
1185 | if (!val) /* bit is inverted */ | |
1186 | reg |= DDC_SCL_OUT; | |
1187 | else | |
1188 | reg &= ~DDC_SCL_OUT; | |
1189 | cyber2000_grphw(DDC_REG, reg, cfb); | |
1190 | cyber2000fb_disable_ddc(cfb); | |
1191 | } | |
1192 | ||
1193 | static void cyber2000fb_ddc_setsda(void *data, int val) | |
1194 | { | |
1195 | struct cfb_info *cfb = data; | |
1196 | unsigned char reg; | |
1197 | ||
1198 | cyber2000fb_enable_ddc(cfb); | |
1199 | reg = cyber2000_grphr(DDC_REG, cfb); | |
1200 | if (!val) /* bit is inverted */ | |
1201 | reg |= DDC_SDA_OUT; | |
1202 | else | |
1203 | reg &= ~DDC_SDA_OUT; | |
1204 | cyber2000_grphw(DDC_REG, reg, cfb); | |
1205 | cyber2000fb_disable_ddc(cfb); | |
1206 | } | |
1207 | ||
1208 | static int cyber2000fb_ddc_getscl(void *data) | |
1209 | { | |
1210 | struct cfb_info *cfb = data; | |
1211 | int retval; | |
1212 | ||
1213 | cyber2000fb_enable_ddc(cfb); | |
1214 | retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SCL_IN); | |
1215 | cyber2000fb_disable_ddc(cfb); | |
1216 | ||
1217 | return retval; | |
1218 | } | |
1219 | ||
1220 | static int cyber2000fb_ddc_getsda(void *data) | |
1221 | { | |
1222 | struct cfb_info *cfb = data; | |
1223 | int retval; | |
1224 | ||
1225 | cyber2000fb_enable_ddc(cfb); | |
1226 | retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SDA_IN); | |
1227 | cyber2000fb_disable_ddc(cfb); | |
1228 | ||
1229 | return retval; | |
1230 | } | |
1231 | ||
1232 | static int __devinit cyber2000fb_setup_ddc_bus(struct cfb_info *cfb) | |
1233 | { | |
e5dedf8d OZ |
1234 | strlcpy(cfb->ddc_adapter.name, cfb->fb.fix.id, |
1235 | sizeof(cfb->ddc_adapter.name)); | |
1236 | cfb->ddc_adapter.owner = THIS_MODULE; | |
1237 | cfb->ddc_adapter.class = I2C_CLASS_DDC; | |
1238 | cfb->ddc_adapter.algo_data = &cfb->ddc_algo; | |
1239 | cfb->ddc_adapter.dev.parent = &cfb->dev->dev; | |
1240 | cfb->ddc_algo.setsda = cyber2000fb_ddc_setsda; | |
1241 | cfb->ddc_algo.setscl = cyber2000fb_ddc_setscl; | |
1242 | cfb->ddc_algo.getsda = cyber2000fb_ddc_getsda; | |
1243 | cfb->ddc_algo.getscl = cyber2000fb_ddc_getscl; | |
1244 | cfb->ddc_algo.udelay = 10; | |
1245 | cfb->ddc_algo.timeout = 20; | |
1246 | cfb->ddc_algo.data = cfb; | |
1247 | ||
1248 | i2c_set_adapdata(&cfb->ddc_adapter, cfb); | |
1249 | ||
1250 | return i2c_bit_add_bus(&cfb->ddc_adapter); | |
1251 | } | |
1252 | #endif /* CONFIG_FB_CYBER2000_DDC */ | |
1253 | ||
1da177e4 LT |
1254 | /* |
1255 | * These parameters give | |
1256 | * 640x480, hsync 31.5kHz, vsync 60Hz | |
1257 | */ | |
1258 | static struct fb_videomode __devinitdata cyber2000fb_default_mode = { | |
1259 | .refresh = 60, | |
1260 | .xres = 640, | |
1261 | .yres = 480, | |
1262 | .pixclock = 39722, | |
1263 | .left_margin = 56, | |
1264 | .right_margin = 16, | |
1265 | .upper_margin = 34, | |
1266 | .lower_margin = 9, | |
1267 | .hsync_len = 88, | |
1268 | .vsync_len = 2, | |
1269 | .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
1270 | .vmode = FB_VMODE_NONINTERLACED | |
1271 | }; | |
1272 | ||
1273 | static char igs_regs[] = { | |
1274 | EXT_CRT_IRQ, 0, | |
1275 | EXT_CRT_TEST, 0, | |
1276 | EXT_SYNC_CTL, 0, | |
1277 | EXT_SEG_WRITE_PTR, 0, | |
1278 | EXT_SEG_READ_PTR, 0, | |
1279 | EXT_BIU_MISC, EXT_BIU_MISC_LIN_ENABLE | | |
1280 | EXT_BIU_MISC_COP_ENABLE | | |
1281 | EXT_BIU_MISC_COP_BFC, | |
1282 | EXT_FUNC_CTL, 0, | |
1283 | CURS_H_START, 0, | |
1284 | CURS_H_START + 1, 0, | |
1285 | CURS_H_PRESET, 0, | |
1286 | CURS_V_START, 0, | |
1287 | CURS_V_START + 1, 0, | |
1288 | CURS_V_PRESET, 0, | |
1289 | CURS_CTL, 0, | |
1290 | EXT_ATTRIB_CTL, EXT_ATTRIB_CTL_EXT, | |
1291 | EXT_OVERSCAN_RED, 0, | |
1292 | EXT_OVERSCAN_GREEN, 0, | |
1293 | EXT_OVERSCAN_BLUE, 0, | |
1294 | ||
1295 | /* some of these are questionable when we have a BIOS */ | |
1296 | EXT_MEM_CTL0, EXT_MEM_CTL0_7CLK | | |
1297 | EXT_MEM_CTL0_RAS_1 | | |
1298 | EXT_MEM_CTL0_MULTCAS, | |
1299 | EXT_HIDDEN_CTL1, 0x30, | |
1300 | EXT_FIFO_CTL, 0x0b, | |
1301 | EXT_FIFO_CTL + 1, 0x17, | |
1302 | 0x76, 0x00, | |
1303 | EXT_HIDDEN_CTL4, 0xc8 | |
1304 | }; | |
1305 | ||
1306 | /* | |
1307 | * Initialise the CyberPro hardware. On the CyberPro5XXXX, | |
1308 | * ensure that we're using the correct PLL (5XXX's may be | |
1309 | * programmed to use an additional set of PLLs.) | |
1310 | */ | |
1311 | static void cyberpro_init_hw(struct cfb_info *cfb) | |
1312 | { | |
1313 | int i; | |
1314 | ||
1315 | for (i = 0; i < sizeof(igs_regs); i += 2) | |
532237ef | 1316 | cyber2000_grphw(igs_regs[i], igs_regs[i + 1], cfb); |
1da177e4 LT |
1317 | |
1318 | if (cfb->id == ID_CYBERPRO_5000) { | |
1319 | unsigned char val; | |
1320 | cyber2000fb_writeb(0xba, 0x3ce, cfb); | |
1321 | val = cyber2000fb_readb(0x3cf, cfb) & 0x80; | |
1322 | cyber2000fb_writeb(val, 0x3cf, cfb); | |
1323 | } | |
1324 | } | |
1325 | ||
532237ef KH |
1326 | static struct cfb_info __devinit *cyberpro_alloc_fb_info(unsigned int id, |
1327 | char *name) | |
1da177e4 LT |
1328 | { |
1329 | struct cfb_info *cfb; | |
1330 | ||
dd00cc48 | 1331 | cfb = kzalloc(sizeof(struct cfb_info), GFP_KERNEL); |
1da177e4 LT |
1332 | if (!cfb) |
1333 | return NULL; | |
1334 | ||
1da177e4 LT |
1335 | |
1336 | cfb->id = id; | |
1337 | ||
1338 | if (id == ID_CYBERPRO_5000) | |
532237ef | 1339 | cfb->ref_ps = 40690; /* 24.576 MHz */ |
1da177e4 | 1340 | else |
532237ef | 1341 | cfb->ref_ps = 69842; /* 14.31818 MHz (69841?) */ |
1da177e4 LT |
1342 | |
1343 | cfb->divisors[0] = 1; | |
1344 | cfb->divisors[1] = 2; | |
1345 | cfb->divisors[2] = 4; | |
1346 | ||
1347 | if (id == ID_CYBERPRO_2000) | |
1348 | cfb->divisors[3] = 8; | |
1349 | else | |
1350 | cfb->divisors[3] = 6; | |
1351 | ||
1352 | strcpy(cfb->fb.fix.id, name); | |
1353 | ||
1354 | cfb->fb.fix.type = FB_TYPE_PACKED_PIXELS; | |
1355 | cfb->fb.fix.type_aux = 0; | |
1356 | cfb->fb.fix.xpanstep = 0; | |
1357 | cfb->fb.fix.ypanstep = 1; | |
1358 | cfb->fb.fix.ywrapstep = 0; | |
1359 | ||
1360 | switch (id) { | |
1361 | case ID_IGA_1682: | |
1362 | cfb->fb.fix.accel = 0; | |
1363 | break; | |
1364 | ||
1365 | case ID_CYBERPRO_2000: | |
1366 | cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2000; | |
1367 | break; | |
1368 | ||
1369 | case ID_CYBERPRO_2010: | |
1370 | cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2010; | |
1371 | break; | |
1372 | ||
1373 | case ID_CYBERPRO_5000: | |
1374 | cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER5000; | |
1375 | break; | |
1376 | } | |
1377 | ||
1378 | cfb->fb.var.nonstd = 0; | |
1379 | cfb->fb.var.activate = FB_ACTIVATE_NOW; | |
1380 | cfb->fb.var.height = -1; | |
1381 | cfb->fb.var.width = -1; | |
1382 | cfb->fb.var.accel_flags = FB_ACCELF_TEXT; | |
1383 | ||
1384 | cfb->fb.fbops = &cyber2000fb_ops; | |
1385 | cfb->fb.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; | |
eca02b0c | 1386 | cfb->fb.pseudo_palette = cfb->pseudo_palette; |
1da177e4 | 1387 | |
052a7f5c RK |
1388 | spin_lock_init(&cfb->reg_b0_lock); |
1389 | ||
1da177e4 LT |
1390 | fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0); |
1391 | ||
1392 | return cfb; | |
1393 | } | |
1394 | ||
532237ef | 1395 | static void cyberpro_free_fb_info(struct cfb_info *cfb) |
1da177e4 LT |
1396 | { |
1397 | if (cfb) { | |
1398 | /* | |
1399 | * Free the colourmap | |
1400 | */ | |
1401 | fb_alloc_cmap(&cfb->fb.cmap, 0, 0); | |
1402 | ||
1403 | kfree(cfb); | |
1404 | } | |
1405 | } | |
1406 | ||
1407 | /* | |
1408 | * Parse Cyber2000fb options. Usage: | |
1409 | * video=cyber2000:font:fontname | |
1410 | */ | |
1411 | #ifndef MODULE | |
532237ef | 1412 | static int cyber2000fb_setup(char *options) |
1da177e4 LT |
1413 | { |
1414 | char *opt; | |
1415 | ||
1416 | if (!options || !*options) | |
1417 | return 0; | |
1418 | ||
1419 | while ((opt = strsep(&options, ",")) != NULL) { | |
1420 | if (!*opt) | |
1421 | continue; | |
1422 | ||
1423 | if (strncmp(opt, "font:", 5) == 0) { | |
1424 | static char default_font_storage[40]; | |
1425 | ||
532237ef KH |
1426 | strlcpy(default_font_storage, opt + 5, |
1427 | sizeof(default_font_storage)); | |
1da177e4 LT |
1428 | default_font = default_font_storage; |
1429 | continue; | |
1430 | } | |
1431 | ||
1432 | printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", opt); | |
1433 | } | |
1434 | return 0; | |
1435 | } | |
1436 | #endif /* MODULE */ | |
1437 | ||
1438 | /* | |
1439 | * The CyberPro chips can be placed on many different bus types. | |
1440 | * This probe function is common to all bus types. The bus-specific | |
1441 | * probe function is expected to have: | |
1442 | * - enabled access to the linear memory region | |
1443 | * - memory mapped access to the registers | |
1444 | * - initialised mem_ctl1 and mem_ctl2 appropriately. | |
1445 | */ | |
1446 | static int __devinit cyberpro_common_probe(struct cfb_info *cfb) | |
1447 | { | |
1448 | u_long smem_size; | |
1449 | u_int h_sync, v_sync; | |
1450 | int err; | |
1451 | ||
1452 | cyberpro_init_hw(cfb); | |
1453 | ||
1454 | /* | |
1455 | * Get the video RAM size and width from the VGA register. | |
1456 | * This should have been already initialised by the BIOS, | |
1457 | * but if it's garbage, claim default 1MB VRAM (woody) | |
1458 | */ | |
1459 | cfb->mem_ctl1 = cyber2000_grphr(EXT_MEM_CTL1, cfb); | |
1460 | cfb->mem_ctl2 = cyber2000_grphr(EXT_MEM_CTL2, cfb); | |
1461 | ||
1462 | /* | |
1463 | * Determine the size of the memory. | |
1464 | */ | |
1465 | switch (cfb->mem_ctl2 & MEM_CTL2_SIZE_MASK) { | |
532237ef KH |
1466 | case MEM_CTL2_SIZE_4MB: |
1467 | smem_size = 0x00400000; | |
1468 | break; | |
1469 | case MEM_CTL2_SIZE_2MB: | |
1470 | smem_size = 0x00200000; | |
1471 | break; | |
1472 | case MEM_CTL2_SIZE_1MB: | |
1473 | smem_size = 0x00100000; | |
1474 | break; | |
1475 | default: | |
1476 | smem_size = 0x00100000; | |
1477 | break; | |
1da177e4 LT |
1478 | } |
1479 | ||
1480 | cfb->fb.fix.smem_len = smem_size; | |
1481 | cfb->fb.fix.mmio_len = MMIO_SIZE; | |
1482 | cfb->fb.screen_base = cfb->region; | |
1483 | ||
e5dedf8d OZ |
1484 | #ifdef CONFIG_FB_CYBER2000_DDC |
1485 | if (cyber2000fb_setup_ddc_bus(cfb) == 0) | |
1486 | cfb->ddc_registered = true; | |
1487 | #endif | |
1488 | ||
1da177e4 LT |
1489 | err = -EINVAL; |
1490 | if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0, | |
532237ef KH |
1491 | &cyber2000fb_default_mode, 8)) { |
1492 | printk(KERN_ERR "%s: no valid mode found\n", cfb->fb.fix.id); | |
1da177e4 LT |
1493 | goto failed; |
1494 | } | |
1495 | ||
1496 | cfb->fb.var.yres_virtual = cfb->fb.fix.smem_len * 8 / | |
1497 | (cfb->fb.var.bits_per_pixel * cfb->fb.var.xres_virtual); | |
1498 | ||
1499 | if (cfb->fb.var.yres_virtual < cfb->fb.var.yres) | |
1500 | cfb->fb.var.yres_virtual = cfb->fb.var.yres; | |
1501 | ||
532237ef | 1502 | /* fb_set_var(&cfb->fb.var, -1, &cfb->fb); */ |
1da177e4 LT |
1503 | |
1504 | /* | |
1505 | * Calculate the hsync and vsync frequencies. Note that | |
1506 | * we split the 1e12 constant up so that we can preserve | |
1507 | * the precision and fit the results into 32-bit registers. | |
1508 | * (1953125000 * 512 = 1e12) | |
1509 | */ | |
1510 | h_sync = 1953125000 / cfb->fb.var.pixclock; | |
1511 | h_sync = h_sync * 512 / (cfb->fb.var.xres + cfb->fb.var.left_margin + | |
1512 | cfb->fb.var.right_margin + cfb->fb.var.hsync_len); | |
1513 | v_sync = h_sync / (cfb->fb.var.yres + cfb->fb.var.upper_margin + | |
1514 | cfb->fb.var.lower_margin + cfb->fb.var.vsync_len); | |
1515 | ||
1516 | printk(KERN_INFO "%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n", | |
1517 | cfb->fb.fix.id, cfb->fb.fix.smem_len >> 10, | |
1518 | cfb->fb.var.xres, cfb->fb.var.yres, | |
1519 | h_sync / 1000, h_sync % 1000, v_sync); | |
1520 | ||
1521 | if (cfb->dev) | |
1522 | cfb->fb.device = &cfb->dev->dev; | |
1523 | err = register_framebuffer(&cfb->fb); | |
1524 | ||
1525 | failed: | |
e5dedf8d OZ |
1526 | #ifdef CONFIG_FB_CYBER2000_DDC |
1527 | if (err && cfb->ddc_registered) | |
1528 | i2c_del_adapter(&cfb->ddc_adapter); | |
1529 | #endif | |
1da177e4 LT |
1530 | return err; |
1531 | } | |
1532 | ||
1533 | static void cyberpro_common_resume(struct cfb_info *cfb) | |
1534 | { | |
1535 | cyberpro_init_hw(cfb); | |
1536 | ||
1537 | /* | |
1538 | * Reprogram the MEM_CTL1 and MEM_CTL2 registers | |
1539 | */ | |
1540 | cyber2000_grphw(EXT_MEM_CTL1, cfb->mem_ctl1, cfb); | |
1541 | cyber2000_grphw(EXT_MEM_CTL2, cfb->mem_ctl2, cfb); | |
1542 | ||
1543 | /* | |
1544 | * Restore the old video mode and the palette. | |
1545 | * We also need to tell fbcon to redraw the console. | |
1546 | */ | |
1547 | cyber2000fb_set_par(&cfb->fb); | |
1548 | } | |
1549 | ||
1550 | #ifdef CONFIG_ARCH_SHARK | |
1551 | ||
eab184c2 | 1552 | #include <mach/framebuffer.h> |
1da177e4 | 1553 | |
532237ef | 1554 | static int __devinit cyberpro_vl_probe(void) |
1da177e4 LT |
1555 | { |
1556 | struct cfb_info *cfb; | |
1557 | int err = -ENOMEM; | |
1558 | ||
532237ef KH |
1559 | if (!request_mem_region(FB_START, FB_SIZE, "CyberPro2010")) |
1560 | return err; | |
1da177e4 LT |
1561 | |
1562 | cfb = cyberpro_alloc_fb_info(ID_CYBERPRO_2010, "CyberPro2010"); | |
1563 | if (!cfb) | |
1564 | goto failed_release; | |
1565 | ||
1566 | cfb->dev = NULL; | |
532237ef | 1567 | cfb->region = ioremap(FB_START, FB_SIZE); |
1da177e4 LT |
1568 | if (!cfb->region) |
1569 | goto failed_ioremap; | |
1570 | ||
1571 | cfb->regs = cfb->region + MMIO_OFFSET; | |
1572 | cfb->fb.fix.mmio_start = FB_START + MMIO_OFFSET; | |
1573 | cfb->fb.fix.smem_start = FB_START; | |
1574 | ||
1575 | /* | |
1576 | * Bring up the hardware. This is expected to enable access | |
1577 | * to the linear memory region, and allow access to the memory | |
1578 | * mapped registers. Also, mem_ctl1 and mem_ctl2 must be | |
1579 | * initialised. | |
1580 | */ | |
1581 | cyber2000fb_writeb(0x18, 0x46e8, cfb); | |
1582 | cyber2000fb_writeb(0x01, 0x102, cfb); | |
1583 | cyber2000fb_writeb(0x08, 0x46e8, cfb); | |
1584 | cyber2000fb_writeb(EXT_BIU_MISC, 0x3ce, cfb); | |
1585 | cyber2000fb_writeb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf, cfb); | |
1586 | ||
1587 | cfb->mclk_mult = 0xdb; | |
1588 | cfb->mclk_div = 0x54; | |
1589 | ||
1590 | err = cyberpro_common_probe(cfb); | |
1591 | if (err) | |
1592 | goto failed; | |
1593 | ||
1594 | if (int_cfb_info == NULL) | |
1595 | int_cfb_info = cfb; | |
1596 | ||
1597 | return 0; | |
1598 | ||
1599 | failed: | |
1600 | iounmap(cfb->region); | |
1601 | failed_ioremap: | |
1602 | cyberpro_free_fb_info(cfb); | |
1603 | failed_release: | |
532237ef | 1604 | release_mem_region(FB_START, FB_SIZE); |
1da177e4 LT |
1605 | |
1606 | return err; | |
1607 | } | |
1608 | #endif /* CONFIG_ARCH_SHARK */ | |
1609 | ||
1610 | /* | |
1611 | * PCI specific support. | |
1612 | */ | |
1613 | #ifdef CONFIG_PCI | |
1614 | /* | |
1615 | * We need to wake up the CyberPro, and make sure its in linear memory | |
1616 | * mode. Unfortunately, this is specific to the platform and card that | |
1617 | * we are running on. | |
1618 | * | |
1619 | * On x86 and ARM, should we be initialising the CyberPro first via the | |
1620 | * IO registers, and then the MMIO registers to catch all cases? Can we | |
1621 | * end up in the situation where the chip is in MMIO mode, but not awake | |
1622 | * on an x86 system? | |
1623 | */ | |
1624 | static int cyberpro_pci_enable_mmio(struct cfb_info *cfb) | |
1625 | { | |
1626 | unsigned char val; | |
1627 | ||
1628 | #if defined(__sparc_v9__) | |
1629 | #error "You lose, consult DaveM." | |
1630 | #elif defined(__sparc__) | |
1631 | /* | |
1632 | * SPARC does not have an "outb" instruction, so we generate | |
1633 | * I/O cycles storing into a reserved memory space at | |
1634 | * physical address 0x3000000 | |
1635 | */ | |
cd030665 | 1636 | unsigned char __iomem *iop; |
1da177e4 LT |
1637 | |
1638 | iop = ioremap(0x3000000, 0x5000); | |
1639 | if (iop == NULL) { | |
89b409f7 | 1640 | printk(KERN_ERR "iga5000: cannot map I/O\n"); |
1da177e4 LT |
1641 | return -ENOMEM; |
1642 | } | |
1643 | ||
1644 | writeb(0x18, iop + 0x46e8); | |
1645 | writeb(0x01, iop + 0x102); | |
1646 | writeb(0x08, iop + 0x46e8); | |
1647 | writeb(EXT_BIU_MISC, iop + 0x3ce); | |
1648 | writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf); | |
1649 | ||
cd030665 | 1650 | iounmap(iop); |
1da177e4 LT |
1651 | #else |
1652 | /* | |
1653 | * Most other machine types are "normal", so | |
1654 | * we use the standard IO-based wakeup. | |
1655 | */ | |
1656 | outb(0x18, 0x46e8); | |
1657 | outb(0x01, 0x102); | |
1658 | outb(0x08, 0x46e8); | |
1659 | outb(EXT_BIU_MISC, 0x3ce); | |
1660 | outb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf); | |
1661 | #endif | |
1662 | ||
1663 | /* | |
1664 | * Allow the CyberPro to accept PCI burst accesses | |
1665 | */ | |
cd792aa8 | 1666 | if (cfb->id == ID_CYBERPRO_2010) { |
532237ef KH |
1667 | printk(KERN_INFO "%s: NOT enabling PCI bursts\n", |
1668 | cfb->fb.fix.id); | |
cd792aa8 WS |
1669 | } else { |
1670 | val = cyber2000_grphr(EXT_BUS_CTL, cfb); | |
1671 | if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) { | |
1672 | printk(KERN_INFO "%s: enabling PCI bursts\n", | |
1673 | cfb->fb.fix.id); | |
1da177e4 | 1674 | |
cd792aa8 | 1675 | val |= EXT_BUS_CTL_PCIBURST_WRITE; |
1da177e4 | 1676 | |
cd792aa8 WS |
1677 | if (cfb->id == ID_CYBERPRO_5000) |
1678 | val |= EXT_BUS_CTL_PCIBURST_READ; | |
1da177e4 | 1679 | |
cd792aa8 WS |
1680 | cyber2000_grphw(EXT_BUS_CTL, val, cfb); |
1681 | } | |
1da177e4 LT |
1682 | } |
1683 | ||
1684 | return 0; | |
1685 | } | |
1686 | ||
1687 | static int __devinit | |
1688 | cyberpro_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
1689 | { | |
1690 | struct cfb_info *cfb; | |
1691 | char name[16]; | |
1692 | int err; | |
1693 | ||
1694 | sprintf(name, "CyberPro%4X", id->device); | |
1695 | ||
1696 | err = pci_enable_device(dev); | |
1697 | if (err) | |
1698 | return err; | |
1699 | ||
1da177e4 LT |
1700 | err = -ENOMEM; |
1701 | cfb = cyberpro_alloc_fb_info(id->driver_data, name); | |
1702 | if (!cfb) | |
1703 | goto failed_release; | |
1704 | ||
ed5a35ac RK |
1705 | err = pci_request_regions(dev, cfb->fb.fix.id); |
1706 | if (err) | |
1707 | goto failed_regions; | |
1708 | ||
1da177e4 | 1709 | cfb->dev = dev; |
3c36aa5c | 1710 | cfb->region = pci_ioremap_bar(dev, 0); |
1da177e4 LT |
1711 | if (!cfb->region) |
1712 | goto failed_ioremap; | |
1713 | ||
1714 | cfb->regs = cfb->region + MMIO_OFFSET; | |
1715 | cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET; | |
1716 | cfb->fb.fix.smem_start = pci_resource_start(dev, 0); | |
1717 | ||
1718 | /* | |
1719 | * Bring up the hardware. This is expected to enable access | |
1720 | * to the linear memory region, and allow access to the memory | |
1721 | * mapped registers. Also, mem_ctl1 and mem_ctl2 must be | |
1722 | * initialised. | |
1723 | */ | |
1724 | err = cyberpro_pci_enable_mmio(cfb); | |
1725 | if (err) | |
1726 | goto failed; | |
1727 | ||
1728 | /* | |
1729 | * Use MCLK from BIOS. FIXME: what about hotplug? | |
1730 | */ | |
1731 | cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb); | |
1732 | cfb->mclk_div = cyber2000_grphr(EXT_MCLK_DIV, cfb); | |
1733 | ||
1734 | #ifdef __arm__ | |
1735 | /* | |
1736 | * MCLK on the NetWinder and the Shark is fixed at 75MHz | |
1737 | */ | |
1738 | if (machine_is_netwinder()) { | |
1739 | cfb->mclk_mult = 0xdb; | |
1740 | cfb->mclk_div = 0x54; | |
1741 | } | |
1742 | #endif | |
1743 | ||
1744 | err = cyberpro_common_probe(cfb); | |
1745 | if (err) | |
1746 | goto failed; | |
1747 | ||
1748 | /* | |
1749 | * Our driver data | |
1750 | */ | |
1751 | pci_set_drvdata(dev, cfb); | |
1752 | if (int_cfb_info == NULL) | |
1753 | int_cfb_info = cfb; | |
1754 | ||
1755 | return 0; | |
1756 | ||
1757 | failed: | |
1758 | iounmap(cfb->region); | |
1759 | failed_ioremap: | |
ed5a35ac RK |
1760 | pci_release_regions(dev); |
1761 | failed_regions: | |
1da177e4 LT |
1762 | cyberpro_free_fb_info(cfb); |
1763 | failed_release: | |
1da177e4 LT |
1764 | return err; |
1765 | } | |
1766 | ||
1767 | static void __devexit cyberpro_pci_remove(struct pci_dev *dev) | |
1768 | { | |
1769 | struct cfb_info *cfb = pci_get_drvdata(dev); | |
1770 | ||
1771 | if (cfb) { | |
1772 | /* | |
1773 | * If unregister_framebuffer fails, then | |
1774 | * we will be leaving hooks that could cause | |
1775 | * oopsen laying around. | |
1776 | */ | |
1777 | if (unregister_framebuffer(&cfb->fb)) | |
1778 | printk(KERN_WARNING "%s: danger Will Robinson, " | |
1779 | "danger danger! Oopsen imminent!\n", | |
1780 | cfb->fb.fix.id); | |
e5dedf8d OZ |
1781 | #ifdef CONFIG_FB_CYBER2000_DDC |
1782 | if (cfb->ddc_registered) | |
1783 | i2c_del_adapter(&cfb->ddc_adapter); | |
1784 | #endif | |
1da177e4 LT |
1785 | iounmap(cfb->region); |
1786 | cyberpro_free_fb_info(cfb); | |
1787 | ||
1788 | /* | |
1789 | * Ensure that the driver data is no longer | |
1790 | * valid. | |
1791 | */ | |
1792 | pci_set_drvdata(dev, NULL); | |
1793 | if (cfb == int_cfb_info) | |
1794 | int_cfb_info = NULL; | |
1795 | ||
1796 | pci_release_regions(dev); | |
1797 | } | |
1798 | } | |
1799 | ||
1800 | static int cyberpro_pci_suspend(struct pci_dev *dev, pm_message_t state) | |
1801 | { | |
1802 | return 0; | |
1803 | } | |
1804 | ||
1805 | /* | |
1806 | * Re-initialise the CyberPro hardware | |
1807 | */ | |
1808 | static int cyberpro_pci_resume(struct pci_dev *dev) | |
1809 | { | |
1810 | struct cfb_info *cfb = pci_get_drvdata(dev); | |
1811 | ||
1812 | if (cfb) { | |
1813 | cyberpro_pci_enable_mmio(cfb); | |
1814 | cyberpro_common_resume(cfb); | |
1815 | } | |
1816 | ||
1817 | return 0; | |
1818 | } | |
1819 | ||
1820 | static struct pci_device_id cyberpro_pci_table[] = { | |
532237ef KH |
1821 | /* Not yet |
1822 | * { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682, | |
1823 | * PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 }, | |
1824 | */ | |
1da177e4 LT |
1825 | { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000, |
1826 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2000 }, | |
1827 | { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010, | |
1828 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2010 }, | |
1829 | { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000, | |
1830 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_5000 }, | |
1831 | { 0, } | |
1832 | }; | |
1833 | ||
532237ef | 1834 | MODULE_DEVICE_TABLE(pci, cyberpro_pci_table); |
1da177e4 LT |
1835 | |
1836 | static struct pci_driver cyberpro_driver = { | |
1837 | .name = "CyberPro", | |
1838 | .probe = cyberpro_pci_probe, | |
1839 | .remove = __devexit_p(cyberpro_pci_remove), | |
1840 | .suspend = cyberpro_pci_suspend, | |
1841 | .resume = cyberpro_pci_resume, | |
1842 | .id_table = cyberpro_pci_table | |
1843 | }; | |
1844 | #endif | |
1845 | ||
1846 | /* | |
1847 | * I don't think we can use the "module_init" stuff here because | |
1848 | * the fbcon stuff may not be initialised yet. Hence the #ifdef | |
1849 | * around module_init. | |
1850 | * | |
1851 | * Tony: "module_init" is now required | |
1852 | */ | |
1853 | static int __init cyber2000fb_init(void) | |
1854 | { | |
1855 | int ret = -1, err; | |
1856 | ||
1857 | #ifndef MODULE | |
1858 | char *option = NULL; | |
1859 | ||
1860 | if (fb_get_options("cyber2000fb", &option)) | |
1861 | return -ENODEV; | |
1862 | cyber2000fb_setup(option); | |
1863 | #endif | |
1864 | ||
1865 | #ifdef CONFIG_ARCH_SHARK | |
1866 | err = cyberpro_vl_probe(); | |
ab8e2eb7 | 1867 | if (!err) |
1da177e4 | 1868 | ret = 0; |
1da177e4 LT |
1869 | #endif |
1870 | #ifdef CONFIG_PCI | |
1871 | err = pci_register_driver(&cyberpro_driver); | |
1872 | if (!err) | |
1873 | ret = 0; | |
1874 | #endif | |
1875 | ||
1876 | return ret ? err : 0; | |
1877 | } | |
ab8e2eb7 | 1878 | module_init(cyber2000fb_init); |
1da177e4 | 1879 | |
ab8e2eb7 | 1880 | #ifndef CONFIG_ARCH_SHARK |
1da177e4 LT |
1881 | static void __exit cyberpro_exit(void) |
1882 | { | |
1883 | pci_unregister_driver(&cyberpro_driver); | |
1884 | } | |
1da177e4 | 1885 | module_exit(cyberpro_exit); |
ab8e2eb7 | 1886 | #endif |
1da177e4 LT |
1887 | |
1888 | MODULE_AUTHOR("Russell King"); | |
1889 | MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver"); | |
1890 | MODULE_LICENSE("GPL"); |