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[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / video / amba-clcd.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/amba-clcd.c
3 *
4 * Copyright (C) 2001 ARM Limited, by David A Rusling
5 * Updated to 2.5, Deep Blue Solutions Ltd.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
9 * for more details.
10 *
11 * ARM PrimeCell PL110 Color LCD Controller
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/string.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
3c2a0909
S		 19#include <linux/dma-mapping.h>
20#include <linux/memblock.h>
1da177e4 21#include <linux/mm.h>
3c2a0909 22#include <linux/of.h>
1da177e4
LT		 23#include <linux/fb.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/list.h>
a62c80e5
RK		 27#include <linux/amba/bus.h>
28#include <linux/amba/clcd.h>
f8ce2547 29#include <linux/clk.h>
934848da 30#include <linux/hardirq.h>
1da177e4 31
c6b8fdad 32#include <asm/sizes.h>
1da177e4 33
1da177e4
LT		 34#define to_clcd(info) container_of(info, struct clcd_fb, fb)
35
3c2a0909
S		 36#ifdef CONFIG_ARM
37#define clcdfb_dma_alloc dma_alloc_writecombine
38#define clcdfb_dma_free dma_free_writecombine
39#define clcdfb_dma_mmap dma_mmap_writecombine
40#else
41#define clcdfb_dma_alloc dma_alloc_coherent
42#define clcdfb_dma_free dma_free_coherent
43#define clcdfb_dma_mmap dma_mmap_coherent
44#endif
45
1da177e4
LT		 46/* This is limited to 16 characters when displayed by X startup */
47static const char *clcd_name = "CLCD FB";
3c2a0909
S		 48static char *def_mode;
49module_param_named(mode, def_mode, charp, 0);
1da177e4
LT		 50
51/*
52 * Unfortunately, the enable/disable functions may be called either from
53 * process or IRQ context, and we _need_ to delay. This is _not_ good.
54 */
55static inline void clcdfb_sleep(unsigned int ms)
56{
57 if (in_atomic()) {
58 mdelay(ms);
59 } else {
60 msleep(ms);
61 }
62}
63
64static inline void clcdfb_set_start(struct clcd_fb *fb)
65{
66 unsigned long ustart = fb->fb.fix.smem_start;
67 unsigned long lstart;
68
69 ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
70 lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
71
72 writel(ustart, fb->regs + CLCD_UBAS);
73 writel(lstart, fb->regs + CLCD_LBAS);
74}
75
76static void clcdfb_disable(struct clcd_fb *fb)
77{
78 u32 val;
79
80 if (fb->board->disable)
81 fb->board->disable(fb);
82
3f17522c 83 val = readl(fb->regs + fb->off_cntl);
1da177e4
LT		 84 if (val & CNTL_LCDPWR) {
85 val &= ~CNTL_LCDPWR;
3f17522c 86 writel(val, fb->regs + fb->off_cntl);
1da177e4
LT		 87
88 clcdfb_sleep(20);
89 }
90 if (val & CNTL_LCDEN) {
91 val &= ~CNTL_LCDEN;
3f17522c 92 writel(val, fb->regs + fb->off_cntl);
1da177e4
LT		 93 }
94
95 /*
96 * Disable CLCD clock source.
97 */
99c796df
RK		 98 if (fb->clk_enabled) {
99 fb->clk_enabled = false;
100 clk_disable(fb->clk);
101 }
1da177e4
LT		 102}
103
104static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
105{
106 /*
107 * Enable the CLCD clock source.
108 */
99c796df
RK		 109 if (!fb->clk_enabled) {
110 fb->clk_enabled = true;
111 clk_enable(fb->clk);
112 }
1da177e4
LT		 113
114 /*
115 * Bring up by first enabling..
116 */
117 cntl |= CNTL_LCDEN;
3f17522c 118 writel(cntl, fb->regs + fb->off_cntl);
1da177e4
LT		 119
120 clcdfb_sleep(20);
121
122 /*
123 * and now apply power.
124 */
125 cntl |= CNTL_LCDPWR;
3f17522c 126 writel(cntl, fb->regs + fb->off_cntl);
1da177e4
LT		 127
128 /*
129 * finally, enable the interface.
130 */
131 if (fb->board->enable)
132 fb->board->enable(fb);
133}
134
135static int
136clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
137{
7b4e9ced 138 u32 caps;
1da177e4
LT		 139 int ret = 0;
140
7b4e9ced
RK		 141 if (fb->panel->caps && fb->board->caps)
142 caps = fb->panel->caps & fb->board->caps;
143 else {
144 /* Old way of specifying what can be used */
145 caps = fb->panel->cntl & CNTL_BGR ?
146 CLCD_CAP_BGR : CLCD_CAP_RGB;
147 /* But mask out 444 modes as they weren't supported */
148 caps &= ~CLCD_CAP_444;
149 }
150
151 /* Only TFT panels can do RGB888/BGR888 */
152 if (!(fb->panel->cntl & CNTL_LCDTFT))
153 caps &= ~CLCD_CAP_888;
154
1da177e4 155 memset(&var->transp, 0, sizeof(var->transp));
c43e6f02
RK		 156
157 var->red.msb_right = 0;
158 var->green.msb_right = 0;
159 var->blue.msb_right = 0;
1da177e4
LT		 160
161 switch (var->bits_per_pixel) {
162 case 1:
163 case 2:
164 case 4:
165 case 8:
7b4e9ced
RK		 166 /* If we can't do 5551, reject */
167 caps &= CLCD_CAP_5551;
168 if (!caps) {
169 ret = -EINVAL;
170 break;
171 }
172
c4d12b98 173 var->red.length = var->bits_per_pixel;
1da177e4 174 var->red.offset = 0;
c4d12b98 175 var->green.length = var->bits_per_pixel;
1da177e4 176 var->green.offset = 0;
c4d12b98 177 var->blue.length = var->bits_per_pixel;
1da177e4
LT		 178 var->blue.offset = 0;
179 break;
7b4e9ced 180
1da177e4 181 case 16:
7b4e9ced
RK		 182 /* If we can't do 444, 5551 or 565, reject */
183 if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) {
184 ret = -EINVAL;
185 break;
186 }
187
c43e6f02 188 /*
7b4e9ced
RK		 189 * Green length can be 4, 5 or 6 depending whether
190 * we're operating in 444, 5551 or 565 mode.
c43e6f02 191 */
7b4e9ced
RK		 192 if (var->green.length == 4 && caps & CLCD_CAP_444)
193 caps &= CLCD_CAP_444;
194 if (var->green.length == 5 && caps & CLCD_CAP_5551)
195 caps &= CLCD_CAP_5551;
196 else if (var->green.length == 6 && caps & CLCD_CAP_565)
197 caps &= CLCD_CAP_565;
198 else {
199 /*
200 * PL110 officially only supports RGB555,
201 * but may be wired up to allow RGB565.
202 */
203 if (caps & CLCD_CAP_565) {
204 var->green.length = 6;
205 caps &= CLCD_CAP_565;
206 } else if (caps & CLCD_CAP_5551) {
207 var->green.length = 5;
208 caps &= CLCD_CAP_5551;
209 } else {
210 var->green.length = 4;
211 caps &= CLCD_CAP_444;
212 }
213 }
214
215 if (var->green.length >= 5) {
216 var->red.length = 5;
217 var->blue.length = 5;
218 } else {
219 var->red.length = 4;
220 var->blue.length = 4;
221 }
1da177e4 222 break;
82235e91 223 case 32:
7b4e9ced
RK		 224 /* If we can't do 888, reject */
225 caps &= CLCD_CAP_888;
226 if (!caps) {
227 ret = -EINVAL;
1da177e4
LT		 228 break;
229 }
7b4e9ced
RK		 230
231 var->red.length = 8;
232 var->green.length = 8;
233 var->blue.length = 8;
234 break;
1da177e4
LT		 235 default:
236 ret = -EINVAL;
237 break;
238 }
239
c43e6f02
RK		 240 /*
241 * >= 16bpp displays have separate colour component bitfields
242 * encoded in the pixel data. Calculate their position from
243 * the bitfield length defined above.
244 */
245 if (ret == 0 && var->bits_per_pixel >= 16) {
7b4e9ced
RK		 246 bool bgr, rgb;
247
248 bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0;
249 rgb = caps & CLCD_CAP_RGB && var->red.offset == 0;
250
251 if (!bgr && !rgb)
252 /*
253 * The requested format was not possible, try just
254 * our capabilities. One of BGR or RGB must be
255 * supported.
256 */
257 bgr = caps & CLCD_CAP_BGR;
258
259 if (bgr) {
c43e6f02
RK		 260 var->blue.offset = 0;
261 var->green.offset = var->blue.offset + var->blue.length;
262 var->red.offset = var->green.offset + var->green.length;
263 } else {
264 var->red.offset = 0;
265 var->green.offset = var->red.offset + var->red.length;
266 var->blue.offset = var->green.offset + var->green.length;
267 }
268 }
269
1da177e4
LT		 270 return ret;
271}
272
273static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
274{
275 struct clcd_fb *fb = to_clcd(info);
276 int ret = -EINVAL;
277
278 if (fb->board->check)
279 ret = fb->board->check(fb, var);
82235e91
RK		 280
281 if (ret == 0 &&
282 var->xres_virtual * var->bits_per_pixel / 8 *
283 var->yres_virtual > fb->fb.fix.smem_len)
284 ret = -EINVAL;
285
1da177e4
LT		 286 if (ret == 0)
287 ret = clcdfb_set_bitfields(fb, var);
288
289 return ret;
290}
291
292static int clcdfb_set_par(struct fb_info *info)
293{
294 struct clcd_fb *fb = to_clcd(info);
295 struct clcd_regs regs;
296
297 fb->fb.fix.line_length = fb->fb.var.xres_virtual *
298 fb->fb.var.bits_per_pixel / 8;
299
300 if (fb->fb.var.bits_per_pixel <= 8)
301 fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
302 else
303 fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
304
305 fb->board->decode(fb, &regs);
306
307 clcdfb_disable(fb);
308
309 writel(regs.tim0, fb->regs + CLCD_TIM0);
310 writel(regs.tim1, fb->regs + CLCD_TIM1);
311 writel(regs.tim2, fb->regs + CLCD_TIM2);
312 writel(regs.tim3, fb->regs + CLCD_TIM3);
313
314 clcdfb_set_start(fb);
315
316 clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
317
318 fb->clcd_cntl = regs.cntl;
319
320 clcdfb_enable(fb, regs.cntl);
321
322#ifdef DEBUG
ad361c98
JP		 323 printk(KERN_INFO
324 "CLCD: Registers set to\n"
325 " %08x %08x %08x %08x\n"
326 " %08x %08x %08x %08x\n",
1da177e4
LT		 327 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
328 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
329 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
3f17522c 330 readl(fb->regs + fb->off_ienb), readl(fb->regs + fb->off_cntl));
1da177e4
LT		 331#endif
332
333 return 0;
334}
335
336static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
337{
338 unsigned int mask = (1 << bf->length) - 1;
339
340 return (val >> (16 - bf->length) & mask) << bf->offset;
341}
342
343/*
344 * Set a single color register. The values supplied have a 16 bit
345 * magnitude. Return != 0 for invalid regno.
346 */
347static int
348clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
349 unsigned int blue, unsigned int transp, struct fb_info *info)
350{
351 struct clcd_fb *fb = to_clcd(info);
352
353 if (regno < 16)
354 fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
355 convert_bitfield(blue, &fb->fb.var.blue) |
356 convert_bitfield(green, &fb->fb.var.green) |
357 convert_bitfield(red, &fb->fb.var.red);
358
1ddb8a16 359 if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
1da177e4
LT		 360 int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
361 u32 val, mask, newval;
362
363 newval = (red >> 11) & 0x001f;
364 newval |= (green >> 6) & 0x03e0;
365 newval |= (blue >> 1) & 0x7c00;
366
367 /*
368 * 3.2.11: if we're configured for big endian
369 * byte order, the palette entries are swapped.
370 */
371 if (fb->clcd_cntl & CNTL_BEBO)
372 regno ^= 1;
373
374 if (regno & 1) {
375 newval <<= 16;
376 mask = 0x0000ffff;
377 } else {
378 mask = 0xffff0000;
379 }
380
381 val = readl(fb->regs + hw_reg) & mask;
382 writel(val | newval, fb->regs + hw_reg);
383 }
384
385 return regno > 255;
386}
387
388/*
389 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
390 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
391 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
392 * to e.g. a video mode which doesn't support it. Implements VESA suspend
393 * and powerdown modes on hardware that supports disabling hsync/vsync:
394 * blank_mode == 2: suspend vsync
395 * blank_mode == 3: suspend hsync
396 * blank_mode == 4: powerdown
397 */
398static int clcdfb_blank(int blank_mode, struct fb_info *info)
399{
400 struct clcd_fb *fb = to_clcd(info);
401
402 if (blank_mode != 0) {
403 clcdfb_disable(fb);
404 } else {
405 clcdfb_enable(fb, fb->clcd_cntl);
406 }
407 return 0;
408}
409
3c2a0909
S		 410int clcdfb_mmap_dma(struct clcd_fb *fb, struct vm_area_struct *vma)
411{
412 return clcdfb_dma_mmap(&fb->dev->dev, vma,
413 fb->fb.screen_base,
414 fb->fb.fix.smem_start,
415 fb->fb.fix.smem_len);
416}
417
418int clcdfb_mmap_io(struct clcd_fb *fb, struct vm_area_struct *vma)
419{
420 unsigned long user_count, count, pfn, off;
421
422 user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
423 count = PAGE_ALIGN(fb->fb.fix.smem_len) >> PAGE_SHIFT;
424 pfn = fb->fb.fix.smem_start >> PAGE_SHIFT;
425 off = vma->vm_pgoff;
426
427 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
428
429 if (off < count && user_count <= (count - off))
430 return remap_pfn_range(vma, vma->vm_start, pfn + off,
431 user_count << PAGE_SHIFT,
432 vma->vm_page_prot);
433
434 return -ENXIO;
435}
436
437void clcdfb_remove_dma(struct clcd_fb *fb)
438{
439 clcdfb_dma_free(&fb->dev->dev, fb->fb.fix.smem_len,
440 fb->fb.screen_base, fb->fb.fix.smem_start);
441}
442
443void clcdfb_remove_io(struct clcd_fb *fb)
444{
445 iounmap(fb->fb.screen_base);
446}
447
216d526c 448static int clcdfb_mmap(struct fb_info *info,
1da177e4
LT		 449 struct vm_area_struct *vma)
450{
451 struct clcd_fb *fb = to_clcd(info);
452 unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
453 int ret = -EINVAL;
454
455 len = info->fix.smem_len;
456
457 if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
458 fb->board->mmap)
459 ret = fb->board->mmap(fb, vma);
460
461 return ret;
462}
463
464static struct fb_ops clcdfb_ops = {
465 .owner = THIS_MODULE,
466 .fb_check_var = clcdfb_check_var,
467 .fb_set_par = clcdfb_set_par,
468 .fb_setcolreg = clcdfb_setcolreg,
469 .fb_blank = clcdfb_blank,
470 .fb_fillrect = cfb_fillrect,
471 .fb_copyarea = cfb_copyarea,
472 .fb_imageblit = cfb_imageblit,
1da177e4
LT		 473 .fb_mmap = clcdfb_mmap,
474};
475
476static int clcdfb_register(struct clcd_fb *fb)
477{
478 int ret;
479
3f17522c
RK		 480 /*
481 * ARM PL111 always has IENB at 0x1c; it's only PL110
482 * which is reversed on some platforms.
483 */
484 if (amba_manf(fb->dev) == 0x41 && amba_part(fb->dev) == 0x111) {
485 fb->off_ienb = CLCD_PL111_IENB;
486 fb->off_cntl = CLCD_PL111_CNTL;
487 } else {
488#ifdef CONFIG_ARCH_VERSATILE
489 fb->off_ienb = CLCD_PL111_IENB;
490 fb->off_cntl = CLCD_PL111_CNTL;
491#else
492 fb->off_ienb = CLCD_PL110_IENB;
493 fb->off_cntl = CLCD_PL110_CNTL;
494#endif
495 }
496
ee569c43 497 fb->clk = clk_get(&fb->dev->dev, NULL);
1da177e4
LT		 498 if (IS_ERR(fb->clk)) {
499 ret = PTR_ERR(fb->clk);
500 goto out;
501 }
502
99df4ee1
RK		 503 ret = clk_prepare(fb->clk);
504 if (ret)
505 goto free_clk;
506
17e8c4e1
LM		 507 fb->fb.device = &fb->dev->dev;
508
1da177e4 509 fb->fb.fix.mmio_start = fb->dev->res.start;
dc890c2d 510 fb->fb.fix.mmio_len = resource_size(&fb->dev->res);
1da177e4
LT		 511
512 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
513 if (!fb->regs) {
514 printk(KERN_ERR "CLCD: unable to remap registers\n");
515 ret = -ENOMEM;
99df4ee1 516 goto clk_unprep;
1da177e4
LT		 517 }
518
519 fb->fb.fbops = &clcdfb_ops;
520 fb->fb.flags = FBINFO_FLAG_DEFAULT;
521 fb->fb.pseudo_palette = fb->cmap;
522
523 strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
524 fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
525 fb->fb.fix.type_aux = 0;
526 fb->fb.fix.xpanstep = 0;
527 fb->fb.fix.ypanstep = 0;
528 fb->fb.fix.ywrapstep = 0;
529 fb->fb.fix.accel = FB_ACCEL_NONE;
530
531 fb->fb.var.xres = fb->panel->mode.xres;
532 fb->fb.var.yres = fb->panel->mode.yres;
533 fb->fb.var.xres_virtual = fb->panel->mode.xres;
534 fb->fb.var.yres_virtual = fb->panel->mode.yres;
535 fb->fb.var.bits_per_pixel = fb->panel->bpp;
536 fb->fb.var.grayscale = fb->panel->grayscale;
537 fb->fb.var.pixclock = fb->panel->mode.pixclock;
538 fb->fb.var.left_margin = fb->panel->mode.left_margin;
539 fb->fb.var.right_margin = fb->panel->mode.right_margin;
540 fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
541 fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
542 fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
543 fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
544 fb->fb.var.sync = fb->panel->mode.sync;
545 fb->fb.var.vmode = fb->panel->mode.vmode;
546 fb->fb.var.activate = FB_ACTIVATE_NOW;
547 fb->fb.var.nonstd = 0;
548 fb->fb.var.height = fb->panel->height;
549 fb->fb.var.width = fb->panel->width;
550 fb->fb.var.accel_flags = 0;
551
552 fb->fb.monspecs.hfmin = 0;
553 fb->fb.monspecs.hfmax = 100000;
554 fb->fb.monspecs.vfmin = 0;
555 fb->fb.monspecs.vfmax = 400;
556 fb->fb.monspecs.dclkmin = 1000000;
557 fb->fb.monspecs.dclkmax = 100000000;
558
559 /*
560 * Make sure that the bitfields are set appropriately.
561 */
562 clcdfb_set_bitfields(fb, &fb->fb.var);
563
564 /*
565 * Allocate colourmap.
566 */
909baf00
AS		 567 ret = fb_alloc_cmap(&fb->fb.cmap, 256, 0);
568 if (ret)
569 goto unmap;
1da177e4
LT		 570
571 /*
572 * Ensure interrupts are disabled.
573 */
3f17522c 574 writel(0, fb->regs + fb->off_ienb);
1da177e4
LT		 575
576 fb_set_var(&fb->fb, &fb->fb.var);
577
ff643322
RK		 578 dev_info(&fb->dev->dev, "%s hardware, %s display\n",
579 fb->board->name, fb->panel->mode.name);
1da177e4
LT		 580
581 ret = register_framebuffer(&fb->fb);
582 if (ret == 0)
583 goto out;
584
585 printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
586
909baf00
AS		 587 fb_dealloc_cmap(&fb->fb.cmap);
588 unmap:
1da177e4 589 iounmap(fb->regs);
99df4ee1
RK		 590 clk_unprep:
591 clk_unprepare(fb->clk);
1da177e4
LT		 592 free_clk:
593 clk_put(fb->clk);
594 out:
595 return ret;
596}
597
3c2a0909
S		 598struct string_lookup {
599 const char *string;
600 const u32 val;
601};
602
603static struct string_lookup vmode_lookups[] = {
604 { "FB_VMODE_NONINTERLACED", FB_VMODE_NONINTERLACED},
605 { "FB_VMODE_INTERLACED", FB_VMODE_INTERLACED},
606 { "FB_VMODE_DOUBLE", FB_VMODE_DOUBLE},
607 { "FB_VMODE_ODD_FLD_FIRST", FB_VMODE_ODD_FLD_FIRST},
608 { NULL, 0 },
609};
610
611static struct string_lookup tim2_lookups[] = {
612 { "TIM2_CLKSEL", TIM2_CLKSEL},
613 { "TIM2_IVS", TIM2_IVS},
614 { "TIM2_IHS", TIM2_IHS},
615 { "TIM2_IPC", TIM2_IPC},
616 { "TIM2_IOE", TIM2_IOE},
617 { "TIM2_BCD", TIM2_BCD},
618 { NULL, 0},
619};
620static struct string_lookup cntl_lookups[] = {
621 {"CNTL_LCDEN", CNTL_LCDEN},
622 {"CNTL_LCDBPP1", CNTL_LCDBPP1},
623 {"CNTL_LCDBPP2", CNTL_LCDBPP2},
624 {"CNTL_LCDBPP4", CNTL_LCDBPP4},
625 {"CNTL_LCDBPP8", CNTL_LCDBPP8},
626 {"CNTL_LCDBPP16", CNTL_LCDBPP16},
627 {"CNTL_LCDBPP16_565", CNTL_LCDBPP16_565},
628 {"CNTL_LCDBPP16_444", CNTL_LCDBPP16_444},
629 {"CNTL_LCDBPP24", CNTL_LCDBPP24},
630 {"CNTL_LCDBW", CNTL_LCDBW},
631 {"CNTL_LCDTFT", CNTL_LCDTFT},
632 {"CNTL_LCDMONO8", CNTL_LCDMONO8},
633 {"CNTL_LCDDUAL", CNTL_LCDDUAL},
634 {"CNTL_BGR", CNTL_BGR},
635 {"CNTL_BEBO", CNTL_BEBO},
636 {"CNTL_BEPO", CNTL_BEPO},
637 {"CNTL_LCDPWR", CNTL_LCDPWR},
638 {"CNTL_LCDVCOMP(1)", CNTL_LCDVCOMP(1)},
639 {"CNTL_LCDVCOMP(2)", CNTL_LCDVCOMP(2)},
640 {"CNTL_LCDVCOMP(3)", CNTL_LCDVCOMP(3)},
641 {"CNTL_LCDVCOMP(4)", CNTL_LCDVCOMP(4)},
642 {"CNTL_LCDVCOMP(5)", CNTL_LCDVCOMP(5)},
643 {"CNTL_LCDVCOMP(6)", CNTL_LCDVCOMP(6)},
644 {"CNTL_LCDVCOMP(7)", CNTL_LCDVCOMP(7)},
645 {"CNTL_LDMAFIFOTIME", CNTL_LDMAFIFOTIME},
646 {"CNTL_WATERMARK", CNTL_WATERMARK},
647 { NULL, 0},
648};
649static struct string_lookup caps_lookups[] = {
650 {"CLCD_CAP_RGB444", CLCD_CAP_RGB444},
651 {"CLCD_CAP_RGB5551", CLCD_CAP_RGB5551},
652 {"CLCD_CAP_RGB565", CLCD_CAP_RGB565},
653 {"CLCD_CAP_RGB888", CLCD_CAP_RGB888},
654 {"CLCD_CAP_BGR444", CLCD_CAP_BGR444},
655 {"CLCD_CAP_BGR5551", CLCD_CAP_BGR5551},
656 {"CLCD_CAP_BGR565", CLCD_CAP_BGR565},
657 {"CLCD_CAP_BGR888", CLCD_CAP_BGR888},
658 {"CLCD_CAP_444", CLCD_CAP_444},
659 {"CLCD_CAP_5551", CLCD_CAP_5551},
660 {"CLCD_CAP_565", CLCD_CAP_565},
661 {"CLCD_CAP_888", CLCD_CAP_888},
662 {"CLCD_CAP_RGB", CLCD_CAP_RGB},
663 {"CLCD_CAP_BGR", CLCD_CAP_BGR},
664 {"CLCD_CAP_ALL", CLCD_CAP_ALL},
665 { NULL, 0},
666};
667
668u32 parse_setting(struct string_lookup *lookup, const char *name)
669{
670 int i = 0;
671 while (lookup[i].string != NULL) {
672 if (strcmp(lookup[i].string, name) == 0)
673 return lookup[i].val;
674 ++i;
675 }
676 return -EINVAL;
677}
678
679u32 get_string_lookup(struct device_node *node, const char *name,
680 struct string_lookup *lookup)
681{
682 const char *string;
683 int count, i, ret = 0;
684
685 count = of_property_count_strings(node, name);
686 if (count >= 0)
687 for (i = 0; i < count; i++)
688 if (of_property_read_string_index(node, name, i,
689 &string) == 0)
690 ret |= parse_setting(lookup, string);
691 return ret;
692}
693
694int get_val(struct device_node *node, const char *string)
695{
696 u32 ret = 0;
697
698 if (of_property_read_u32(node, string, &ret))
699 ret = -1;
700 return ret;
701}
702
703struct clcd_panel *getPanel(struct device_node *node)
704{
705 static struct clcd_panel panel;
706
707 panel.mode.refresh = get_val(node, "refresh");
708 panel.mode.xres = get_val(node, "xres");
709 panel.mode.yres = get_val(node, "yres");
710 panel.mode.pixclock = get_val(node, "pixclock");
711 panel.mode.left_margin = get_val(node, "left_margin");
712 panel.mode.right_margin = get_val(node, "right_margin");
713 panel.mode.upper_margin = get_val(node, "upper_margin");
714 panel.mode.lower_margin = get_val(node, "lower_margin");
715 panel.mode.hsync_len = get_val(node, "hsync_len");
716 panel.mode.vsync_len = get_val(node, "vsync_len");
717 panel.mode.sync = get_val(node, "sync");
718 panel.bpp = get_val(node, "bpp");
719 panel.width = (signed short) get_val(node, "width");
720 panel.height = (signed short) get_val(node, "height");
721
722 panel.mode.vmode = get_string_lookup(node, "vmode", vmode_lookups);
723 panel.tim2 = get_string_lookup(node, "tim2", tim2_lookups);
724 panel.cntl = get_string_lookup(node, "cntl", cntl_lookups);
725 panel.caps = get_string_lookup(node, "caps", caps_lookups);
726
727 return &panel;
728}
729
730struct clcd_panel *clcdfb_get_panel(const char *name)
731{
732 struct device_node *node = NULL;
733 const char *mode;
734 struct clcd_panel *panel = NULL;
735
736 do {
737 node = of_find_compatible_node(node, NULL, "panel");
738 if (node)
739 if (of_property_read_string(node, "mode", &mode) == 0)
740 if (strcmp(mode, name) == 0) {
741 panel = getPanel(node);
742 panel->mode.name = name;
743 }
744 } while (node != NULL);
745
746 return panel;
747}
748
749#ifdef CONFIG_OF
750static int clcdfb_dt_init(struct clcd_fb *fb)
751{
752 int err = 0;
753 struct device_node *node;
754 const char *mode;
755 dma_addr_t dma;
756 u32 use_dma;
757 const __be32 *prop;
758 int len, na, ns;
759 phys_addr_t fb_base, fb_size;
760
761 node = fb->dev->dev.of_node;
762 if (!node)
763 return -ENODEV;
764
765 na = of_n_addr_cells(node);
766 ns = of_n_size_cells(node);
767
768 if (def_mode && strlen(def_mode) > 0) {
769 fb->panel = clcdfb_get_panel(def_mode);
770 if (!fb->panel)
771 printk(KERN_ERR "CLCD: invalid mode specified on the command line (%s)\n", def_mode);
772 }
773
774 if (!fb->panel) {
775 if (WARN_ON(of_property_read_string(node, "mode", &mode)))
776 return -ENODEV;
777 fb->panel = clcdfb_get_panel(mode);
778 }
779
780 if (!fb->panel)
781 return -EINVAL;
782 fb->fb.fix.smem_len = fb->panel->mode.xres * fb->panel->mode.yres * 2;
783
784 fb->board->name = "Device Tree CLCD PL111";
785 fb->board->caps = CLCD_CAP_5551 | CLCD_CAP_565;
786 fb->board->check = clcdfb_check;
787 fb->board->decode = clcdfb_decode;
788
789 if (of_property_read_u32(node, "use_dma", &use_dma))
790 use_dma = 0;
791
792 if (use_dma) {
793 fb->fb.screen_base = clcdfb_dma_alloc(&fb->dev->dev,
794 fb->fb.fix.smem_len,
795 &dma, GFP_KERNEL);
796 if (!fb->fb.screen_base) {
797 pr_err("CLCD: unable to map framebuffer\n");
798 return -ENOMEM;
799 }
800
801 fb->fb.fix.smem_start = dma;
802 fb->board->mmap = clcdfb_mmap_dma;
803 fb->board->remove = clcdfb_remove_dma;
804 } else {
805 prop = of_get_property(node, "framebuffer", &len);
806 if (WARN_ON(!prop || len < (na + ns) * sizeof(*prop)))
807 return -EINVAL;
808
809 fb_base = of_read_number(prop, na);
810 fb_size = of_read_number(prop + na, ns);
811
812 fb->fb.fix.smem_start = fb_base;
813 fb->fb.screen_base = ioremap_wc(fb_base, fb_size);
814 fb->board->mmap = clcdfb_mmap_io;
815 fb->board->remove = clcdfb_remove_io;
816 }
817
818 return err;
819}
820#endif /* CONFIG_OF */
821
aa25afad 822static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id)
1da177e4
LT		 823{
824 struct clcd_board *board = dev->dev.platform_data;
825 struct clcd_fb *fb;
826 int ret;
827
3c2a0909
S		 828 if (!board) {
829#ifdef CONFIG_OF
830 if (dev->dev.of_node) {
831 board = kzalloc(sizeof(struct clcd_board), GFP_KERNEL);
832 if (!board)
833 return -ENOMEM;
834 board->setup = clcdfb_dt_init;
835 } else
836#endif
837 return -EINVAL;
838 }
1da177e4
LT		 839
840 ret = amba_request_regions(dev, NULL);
841 if (ret) {
842 printk(KERN_ERR "CLCD: unable to reserve regs region\n");
843 goto out;
844 }
845
dd00cc48 846 fb = kzalloc(sizeof(struct clcd_fb), GFP_KERNEL);
1da177e4
LT		 847 if (!fb) {
848 printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n");
849 ret = -ENOMEM;
850 goto free_region;
851 }
1da177e4
LT		 852
853 fb->dev = dev;
854 fb->board = board;
855
ff643322
RK		 856 dev_info(&fb->dev->dev, "PL%03x rev%u at 0x%08llx\n",
857 amba_part(dev), amba_rev(dev),
858 (unsigned long long)dev->res.start);
859
1da177e4
LT		 860 ret = fb->board->setup(fb);
861 if (ret)
862 goto free_fb;
863
864 ret = clcdfb_register(fb);
865 if (ret == 0) {
866 amba_set_drvdata(dev, fb);
867 goto out;
868 }
869
870 fb->board->remove(fb);
871 free_fb:
872 kfree(fb);
873 free_region:
874 amba_release_regions(dev);
875 out:
876 return ret;
877}
878
879static int clcdfb_remove(struct amba_device *dev)
880{
881 struct clcd_fb *fb = amba_get_drvdata(dev);
882
883 amba_set_drvdata(dev, NULL);
884
885 clcdfb_disable(fb);
886 unregister_framebuffer(&fb->fb);
909baf00
AS		 887 if (fb->fb.cmap.len)
888 fb_dealloc_cmap(&fb->fb.cmap);
1da177e4 889 iounmap(fb->regs);
99df4ee1 890 clk_unprepare(fb->clk);
1da177e4
LT		 891 clk_put(fb->clk);
892
893 fb->board->remove(fb);
894
895 kfree(fb);
896
897 amba_release_regions(dev);
898
899 return 0;
900}
901
902static struct amba_id clcdfb_id_table[] = {
903 {
904 .id = 0x00041110,
e831556f 905 .mask = 0x000ffffe,
1da177e4
LT		 906 },
907 { 0, 0 },
908};
909
6054f9b8
DM		 910MODULE_DEVICE_TABLE(amba, clcdfb_id_table);
911
1da177e4
LT		 912static struct amba_driver clcd_driver = {
913 .drv = {
e831556f 914 .name = "clcd-pl11x",
1da177e4
LT		 915 },
916 .probe = clcdfb_probe,
917 .remove = clcdfb_remove,
918 .id_table = clcdfb_id_table,
919};
920
2c250134 921static int __init amba_clcdfb_init(void)
1da177e4
LT		 922{
923 if (fb_get_options("ambafb", NULL))
924 return -ENODEV;
925
926 return amba_driver_register(&clcd_driver);
927}
928
929module_init(amba_clcdfb_init);
930
931static void __exit amba_clcdfb_exit(void)
932{
933 amba_driver_unregister(&clcd_driver);
934}
935
936module_exit(amba_clcdfb_exit);
937
938MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
939MODULE_LICENSE("GPL");