[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / serial / io_ti.h

/*****************************************************************************
 *
 *	Copyright (C) 1997-2002 Inside Out Networks, Inc.
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *
 *	Feb-16-2001	DMI	Added I2C structure definitions
 *	May-29-2002	gkh	Ported to Linux
 *
 *
 ******************************************************************************/

#ifndef _IO_TI_H_
#define _IO_TI_H_

/* Address Space */
#define DTK_ADDR_SPACE_XDATA		0x03	/* Addr is placed in XDATA space */
#define DTK_ADDR_SPACE_I2C_TYPE_II	0x82	/* Addr is placed in I2C area */
#define DTK_ADDR_SPACE_I2C_TYPE_III	0x83	/* Addr is placed in I2C area */

/* UART Defines */
#define UMPMEM_BASE_UART1		0xFFA0	/* UMP UART1 base address */
#define UMPMEM_BASE_UART2		0xFFB0	/* UMP UART2 base address */
#define UMPMEM_OFFS_UART_LSR		0x05	/* UMP UART LSR register offset */

/* Bits per character */
#define UMP_UART_CHAR5BITS		0x00
#define UMP_UART_CHAR6BITS		0x01
#define UMP_UART_CHAR7BITS		0x02
#define UMP_UART_CHAR8BITS		0x03

/* Parity */
#define UMP_UART_NOPARITY		0x00
#define UMP_UART_ODDPARITY		0x01
#define UMP_UART_EVENPARITY		0x02
#define UMP_UART_MARKPARITY		0x03
#define UMP_UART_SPACEPARITY		0x04

/* Stop bits */
#define UMP_UART_STOPBIT1		0x00
#define UMP_UART_STOPBIT15		0x01
#define UMP_UART_STOPBIT2		0x02

/* Line status register masks */
#define UMP_UART_LSR_OV_MASK		0x01
#define UMP_UART_LSR_PE_MASK		0x02
#define UMP_UART_LSR_FE_MASK		0x04
#define UMP_UART_LSR_BR_MASK		0x08
#define UMP_UART_LSR_ER_MASK		0x0F
#define UMP_UART_LSR_RX_MASK		0x10
#define UMP_UART_LSR_TX_MASK		0x20

#define UMP_UART_LSR_DATA_MASK		(LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK)

/* Port Settings Constants) */
#define UMP_MASK_UART_FLAGS_RTS_FLOW		0x0001
#define UMP_MASK_UART_FLAGS_RTS_DISABLE		0x0002
#define UMP_MASK_UART_FLAGS_PARITY		0x0008
#define UMP_MASK_UART_FLAGS_OUT_X_DSR_FLOW	0x0010
#define UMP_MASK_UART_FLAGS_OUT_X_CTS_FLOW	0x0020
#define UMP_MASK_UART_FLAGS_OUT_X		0x0040
#define UMP_MASK_UART_FLAGS_OUT_XA		0x0080
#define UMP_MASK_UART_FLAGS_IN_X		0x0100
#define UMP_MASK_UART_FLAGS_DTR_FLOW		0x0800
#define UMP_MASK_UART_FLAGS_DTR_DISABLE		0x1000
#define UMP_MASK_UART_FLAGS_RECEIVE_MS_INT	0x2000
#define UMP_MASK_UART_FLAGS_AUTO_START_ON_ERR	0x4000

#define UMP_DMA_MODE_CONTINOUS			0x01
#define UMP_PIPE_TRANS_TIMEOUT_ENA		0x80
#define UMP_PIPE_TRANSFER_MODE_MASK		0x03
#define UMP_PIPE_TRANS_TIMEOUT_MASK		0x7C

/* Purge port Direction Mask Bits */
#define UMP_PORT_DIR_OUT			0x01
#define UMP_PORT_DIR_IN				0x02

/* Address of Port 0 */
#define UMPM_UART1_PORT				0x03

/* Commands */
#define	UMPC_SET_CONFIG			0x05
#define	UMPC_OPEN_PORT			0x06
#define	UMPC_CLOSE_PORT			0x07
#define	UMPC_START_PORT			0x08
#define	UMPC_STOP_PORT			0x09
#define	UMPC_TEST_PORT			0x0A
#define	UMPC_PURGE_PORT			0x0B

/* Force the Firmware to complete the current Read */
#define	UMPC_COMPLETE_READ		0x80
/* Force UMP back into BOOT Mode */
#define	UMPC_HARDWARE_RESET		0x81
/*
 * Copy current download image to type 0xf2 record in 16k I2C
 * firmware will change 0xff record to type 2 record when complete
 */
#define	UMPC_COPY_DNLD_TO_I2C		0x82

/*
 * Special function register commands
 * wIndex is register address
 * wValue is MSB/LSB mask/data
 */
#define	UMPC_WRITE_SFR			0x83	/* Write SFR Register */

/* wIndex is register address */
#define	UMPC_READ_SFR			0x84	/* Read SRF Register */

/* Set or Clear DTR (wValue bit 0 Set/Clear)	wIndex ModuleID (port) */
#define	UMPC_SET_CLR_DTR		0x85

/* Set or Clear RTS (wValue bit 0 Set/Clear)	wIndex ModuleID (port) */
#define	UMPC_SET_CLR_RTS		0x86

/* Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
#define	UMPC_SET_CLR_LOOPBACK		0x87

/* Set or Clear BREAK (wValue bit 0 Set/Clear)	wIndex ModuleID (port) */
#define	UMPC_SET_CLR_BREAK		0x88

/* Read MSR wIndex ModuleID (port) */
#define	UMPC_READ_MSR			0x89

/* Toolkit commands */
/* Read-write group */
#define	UMPC_MEMORY_READ		0x92
#define	UMPC_MEMORY_WRITE		0x93

/*
 *	UMP DMA Definitions
 */
#define UMPD_OEDB1_ADDRESS		0xFF08
#define UMPD_OEDB2_ADDRESS		0xFF10

struct out_endpoint_desc_block {
	__u8 Configuration;
	__u8 XBufAddr;
	__u8 XByteCount;
	__u8 Unused1;
	__u8 Unused2;
	__u8 YBufAddr;
	__u8 YByteCount;
	__u8 BufferSize;
} __attribute__((packed));


/*
 * TYPE DEFINITIONS
 * Structures for Firmware commands
 */
/* UART settings */
struct ump_uart_config {
	__u16 wBaudRate;	/* Baud rate                        */
	__u16 wFlags;		/* Bitmap mask of flags             */
	__u8 bDataBits;		/* 5..8 - data bits per character   */
	__u8 bParity;		/* Parity settings                  */
	__u8 bStopBits;		/* Stop bits settings               */
	char cXon;		/* XON character                    */
	char cXoff;		/* XOFF character                   */
	__u8 bUartMode;		/* Will be updated when a user      */
				/* interface is defined             */
} __attribute__((packed));


/*
 * TYPE DEFINITIONS
 * Structures for USB interrupts
 */
/* Interrupt packet structure */
struct ump_interrupt {
	__u8 bICode;			/* Interrupt code (interrupt num)   */
	__u8 bIInfo;			/* Interrupt information            */
}  __attribute__((packed));


#define TIUMP_GET_PORT_FROM_CODE(c)	(((c) >> 4) - 3)
#define TIUMP_GET_FUNC_FROM_CODE(c)	((c) & 0x0f)
#define TIUMP_INTERRUPT_CODE_LSR	0x03
#define TIUMP_INTERRUPT_CODE_MSR	0x04

#endif
Commit	Line	Data
a3204711	1	/*****************************************************************************
1da177e4 LT	2	*
	3	* Copyright (C) 1997-2002 Inside Out Networks, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	*
	11	* Feb-16-2001 DMI Added I2C structure definitions
	12	* May-29-2002 gkh Ported to Linux
	13	*
	14	*
	15	******************************************************************************/
	16
	17	#ifndef _IO_TI_H_
	18	#define _IO_TI_H_
	19
	20	/* Address Space */
	21	#define DTK_ADDR_SPACE_XDATA 0x03 /* Addr is placed in XDATA space */
	22	#define DTK_ADDR_SPACE_I2C_TYPE_II 0x82 /* Addr is placed in I2C area */
	23	#define DTK_ADDR_SPACE_I2C_TYPE_III 0x83 /* Addr is placed in I2C area */
	24
a3204711 GKH	25	/* UART Defines */
	26	#define UMPMEM_BASE_UART1 0xFFA0 /* UMP UART1 base address */
	27	#define UMPMEM_BASE_UART2 0xFFB0 /* UMP UART2 base address */
	28	#define UMPMEM_OFFS_UART_LSR 0x05 /* UMP UART LSR register offset */
1da177e4 LT	29
	30	/* Bits per character */
	31	#define UMP_UART_CHAR5BITS 0x00
	32	#define UMP_UART_CHAR6BITS 0x01
	33	#define UMP_UART_CHAR7BITS 0x02
	34	#define UMP_UART_CHAR8BITS 0x03
	35
	36	/* Parity */
	37	#define UMP_UART_NOPARITY 0x00
	38	#define UMP_UART_ODDPARITY 0x01
	39	#define UMP_UART_EVENPARITY 0x02
	40	#define UMP_UART_MARKPARITY 0x03
	41	#define UMP_UART_SPACEPARITY 0x04
	42
	43	/* Stop bits */
	44	#define UMP_UART_STOPBIT1 0x00
	45	#define UMP_UART_STOPBIT15 0x01
	46	#define UMP_UART_STOPBIT2 0x02
	47
	48	/* Line status register masks */
	49	#define UMP_UART_LSR_OV_MASK 0x01
	50	#define UMP_UART_LSR_PE_MASK 0x02
	51	#define UMP_UART_LSR_FE_MASK 0x04
	52	#define UMP_UART_LSR_BR_MASK 0x08
	53	#define UMP_UART_LSR_ER_MASK 0x0F
	54	#define UMP_UART_LSR_RX_MASK 0x10
	55	#define UMP_UART_LSR_TX_MASK 0x20
	56
a3204711	57	#define UMP_UART_LSR_DATA_MASK (LSR_PAR_ERR \| LSR_FRM_ERR \| LSR_BREAK)
1da177e4 LT	58
	59	/* Port Settings Constants) */
	60	#define UMP_MASK_UART_FLAGS_RTS_FLOW 0x0001
	61	#define UMP_MASK_UART_FLAGS_RTS_DISABLE 0x0002
	62	#define UMP_MASK_UART_FLAGS_PARITY 0x0008
	63	#define UMP_MASK_UART_FLAGS_OUT_X_DSR_FLOW 0x0010
	64	#define UMP_MASK_UART_FLAGS_OUT_X_CTS_FLOW 0x0020
	65	#define UMP_MASK_UART_FLAGS_OUT_X 0x0040
	66	#define UMP_MASK_UART_FLAGS_OUT_XA 0x0080
	67	#define UMP_MASK_UART_FLAGS_IN_X 0x0100
	68	#define UMP_MASK_UART_FLAGS_DTR_FLOW 0x0800
	69	#define UMP_MASK_UART_FLAGS_DTR_DISABLE 0x1000
	70	#define UMP_MASK_UART_FLAGS_RECEIVE_MS_INT 0x2000
	71	#define UMP_MASK_UART_FLAGS_AUTO_START_ON_ERR 0x4000
	72
	73	#define UMP_DMA_MODE_CONTINOUS 0x01
	74	#define UMP_PIPE_TRANS_TIMEOUT_ENA 0x80
	75	#define UMP_PIPE_TRANSFER_MODE_MASK 0x03
	76	#define UMP_PIPE_TRANS_TIMEOUT_MASK 0x7C
	77
	78	/* Purge port Direction Mask Bits */
	79	#define UMP_PORT_DIR_OUT 0x01
	80	#define UMP_PORT_DIR_IN 0x02
	81
a3204711 GKH	82	/* Address of Port 0 */
	83	#define UMPM_UART1_PORT 0x03
	84
	85	/* Commands */
	86	#define UMPC_SET_CONFIG 0x05
	87	#define UMPC_OPEN_PORT 0x06
	88	#define UMPC_CLOSE_PORT 0x07
	89	#define UMPC_START_PORT 0x08
	90	#define UMPC_STOP_PORT 0x09
	91	#define UMPC_TEST_PORT 0x0A
	92	#define UMPC_PURGE_PORT 0x0B
	93
	94	/* Force the Firmware to complete the current Read */
	95	#define UMPC_COMPLETE_READ 0x80
	96	/* Force UMP back into BOOT Mode */
	97	#define UMPC_HARDWARE_RESET 0x81
	98	/*
	99	* Copy current download image to type 0xf2 record in 16k I2C
	100	* firmware will change 0xff record to type 2 record when complete
	101	*/
	102	#define UMPC_COPY_DNLD_TO_I2C 0x82
1da177e4	103
a3204711 GKH	104	/*
	105	* Special function register commands
	106	* wIndex is register address
	107	* wValue is MSB/LSB mask/data
	108	*/
	109	#define UMPC_WRITE_SFR 0x83 /* Write SFR Register */
1da177e4	110
a3204711 GKH	111	/* wIndex is register address */
a3204711 GKH	112	#define UMPC_READ_SFR 0x84 /* Read SRF Register */
1da177e4	113
a3204711	114	/* Set or Clear DTR (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
1da177e4 LT	115	#define UMPC_SET_CLR_DTR 0x85
1da177e4 LT	116
a3204711	117	/* Set or Clear RTS (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
1da177e4 LT	118	#define UMPC_SET_CLR_RTS 0x86
1da177e4 LT	119
a3204711	120	/* Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
1da177e4 LT	121	#define UMPC_SET_CLR_LOOPBACK 0x87
1da177e4 LT	122
a3204711	123	/* Set or Clear BREAK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
1da177e4 LT	124	#define UMPC_SET_CLR_BREAK 0x88
1da177e4 LT	125
a3204711	126	/* Read MSR wIndex ModuleID (port) */
1da177e4 LT	127	#define UMPC_READ_MSR 0x89
1da177e4 LT	128
a3204711 GKH	129	/* Toolkit commands */
	130	/* Read-write group */
	131	#define UMPC_MEMORY_READ 0x92
	132	#define UMPC_MEMORY_WRITE 0x93
1da177e4 LT	133
	134	/*
	135	* UMP DMA Definitions
	136	*/
	137	#define UMPD_OEDB1_ADDRESS 0xFF08
	138	#define UMPD_OEDB2_ADDRESS 0xFF10
	139
a3204711	140	struct out_endpoint_desc_block {
1da177e4 LT	141	__u8 Configuration;
	142	__u8 XBufAddr;
	143	__u8 XByteCount;
	144	__u8 Unused1;
	145	__u8 Unused2;
	146	__u8 YBufAddr;
	147	__u8 YByteCount;
	148	__u8 BufferSize;
	149	} __attribute__((packed));
	150
	151
	152	/*
	153	* TYPE DEFINITIONS
	154	* Structures for Firmware commands
	155	*/
a3204711 GKH	156	/* UART settings */
a3204711 GKH	157	struct ump_uart_config {
1da177e4 LT	158	__u16 wBaudRate; /* Baud rate */
	159	__u16 wFlags; /* Bitmap mask of flags */
	160	__u8 bDataBits; /* 5..8 - data bits per character */
	161	__u8 bParity; /* Parity settings */
	162	__u8 bStopBits; /* Stop bits settings */
	163	char cXon; /* XON character */
	164	char cXoff; /* XOFF character */
	165	__u8 bUartMode; /* Will be updated when a user */
	166	/* interface is defined */
	167	} __attribute__((packed));
	168
	169
	170	/*
	171	* TYPE DEFINITIONS
	172	* Structures for USB interrupts
	173	*/
a3204711 GKH	174	/* Interrupt packet structure */
a3204711 GKH	175	struct ump_interrupt {
1da177e4 LT	176	__u8 bICode; /* Interrupt code (interrupt num) */
	177	__u8 bIInfo; /* Interrupt information */
	178	} __attribute__((packed));
	179
	180
	181	#define TIUMP_GET_PORT_FROM_CODE(c) (((c) >> 4) - 3)
	182	#define TIUMP_GET_FUNC_FROM_CODE(c) ((c) & 0x0f)
	183	#define TIUMP_INTERRUPT_CODE_LSR 0x03
	184	#define TIUMP_INTERRUPT_CODE_MSR 0x04
	185
	186	#endif