[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / renesas_usbhs / common.h

/*
 * Renesas USB driver
 *
 * Copyright (C) 2011 Renesas Solutions Corp.
 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 *
 */
#ifndef RENESAS_USB_DRIVER_H
#define RENESAS_USB_DRIVER_H

#include <linux/platform_device.h>
#include <linux/usb/renesas_usbhs.h>

struct usbhs_priv;

#include "mod.h"
#include "pipe.h"

/*
 *
 *		register define
 *
 */
#define SYSCFG		0x0000
#define BUSWAIT		0x0002
#define DVSTCTR		0x0008
#define TESTMODE	0x000C
#define CFIFO		0x0014
#define CFIFOSEL	0x0020
#define CFIFOCTR	0x0022
#define D0FIFO		0x0100
#define D0FIFOSEL	0x0028
#define D0FIFOCTR	0x002A
#define D1FIFO		0x0120
#define D1FIFOSEL	0x002C
#define D1FIFOCTR	0x002E
#define INTENB0		0x0030
#define INTENB1		0x0032
#define BRDYENB		0x0036
#define NRDYENB		0x0038
#define BEMPENB		0x003A
#define INTSTS0		0x0040
#define INTSTS1		0x0042
#define BRDYSTS		0x0046
#define NRDYSTS		0x0048
#define BEMPSTS		0x004A
#define FRMNUM		0x004C
#define USBREQ		0x0054	/* USB request type register */
#define USBVAL		0x0056	/* USB request value register */
#define USBINDX		0x0058	/* USB request index register */
#define USBLENG		0x005A	/* USB request length register */
#define DCPCFG		0x005C
#define DCPMAXP		0x005E
#define DCPCTR		0x0060
#define PIPESEL		0x0064
#define PIPECFG		0x0068
#define PIPEBUF		0x006A
#define PIPEMAXP	0x006C
#define PIPEPERI	0x006E
#define PIPEnCTR	0x0070
#define PIPE1TRE	0x0090
#define PIPE1TRN	0x0092
#define PIPE2TRE	0x0094
#define PIPE2TRN	0x0096
#define PIPE3TRE	0x0098
#define PIPE3TRN	0x009A
#define PIPE4TRE	0x009C
#define PIPE4TRN	0x009E
#define PIPE5TRE	0x00A0
#define PIPE5TRN	0x00A2
#define PIPEBTRE	0x00A4
#define PIPEBTRN	0x00A6
#define PIPECTRE	0x00A8
#define PIPECTRN	0x00AA
#define PIPEDTRE	0x00AC
#define PIPEDTRN	0x00AE
#define PIPEETRE	0x00B0
#define PIPEETRN	0x00B2
#define PIPEFTRE	0x00B4
#define PIPEFTRN	0x00B6
#define PIPE9TRE	0x00B8
#define PIPE9TRN	0x00BA
#define PIPEATRE	0x00BC
#define PIPEATRN	0x00BE
#define DEVADD0		0x00D0 /* Device address n configuration */
#define DEVADD1		0x00D2
#define DEVADD2		0x00D4
#define DEVADD3		0x00D6
#define DEVADD4		0x00D8
#define DEVADD5		0x00DA
#define DEVADD6		0x00DC
#define DEVADD7		0x00DE
#define DEVADD8		0x00E0
#define DEVADD9		0x00E2
#define DEVADDA		0x00E4

/* SYSCFG */
#define SCKE	(1 << 10)	/* USB Module Clock Enable */
#define HSE	(1 << 7)	/* High-Speed Operation Enable */
#define DCFM	(1 << 6)	/* Controller Function Select */
#define DRPD	(1 << 5)	/* D+ Line/D- Line Resistance Control */
#define DPRPU	(1 << 4)	/* D+ Line Resistance Control */
#define USBE	(1 << 0)	/* USB Module Operation Enable */

/* DVSTCTR */
#define EXTLP	(1 << 10)	/* Controls the EXTLP pin output state */
#define PWEN	(1 << 9)	/* Controls the PWEN pin output state */
#define USBRST	(1 << 6)	/* Bus Reset Output */
#define UACT	(1 << 4)	/* USB Bus Enable */
#define RHST	(0x7)		/* Reset Handshake */
#define  RHST_LOW_SPEED  1	/* Low-speed connection */
#define  RHST_FULL_SPEED 2	/* Full-speed connection */
#define  RHST_HIGH_SPEED 3	/* High-speed connection */

/* CFIFOSEL */
#define DREQE	(1 << 12)	/* DMA Transfer Request Enable */
#define MBW_32	(0x2 << 10)	/* CFIFO Port Access Bit Width */

/* CFIFOCTR */
#define BVAL	(1 << 15)	/* Buffer Memory Enable Flag */
#define BCLR	(1 << 14)	/* CPU buffer clear */
#define FRDY	(1 << 13)	/* FIFO Port Ready */
#define DTLN_MASK (0x0FFF)	/* Receive Data Length */

/* INTENB0 */
#define VBSE	(1 << 15)	/* Enable IRQ VBUS_0 and VBUSIN_0 */
#define RSME	(1 << 14)	/* Enable IRQ Resume */
#define SOFE	(1 << 13)	/* Enable IRQ Frame Number Update */
#define DVSE	(1 << 12)	/* Enable IRQ Device State Transition */
#define CTRE	(1 << 11)	/* Enable IRQ Control Stage Transition */
#define BEMPE	(1 << 10)	/* Enable IRQ Buffer Empty */
#define NRDYE	(1 << 9)	/* Enable IRQ Buffer Not Ready Response */
#define BRDYE	(1 << 8)	/* Enable IRQ Buffer Ready */

/* INTENB1 */
#define BCHGE	(1 << 14)	/* USB Bus Change Interrupt Enable */
#define DTCHE	(1 << 12)	/* Disconnection Detect Interrupt Enable */
#define ATTCHE	(1 << 11)	/* Connection Detect Interrupt Enable */
#define EOFERRE	(1 << 6)	/* EOF Error Detect Interrupt Enable */
#define SIGNE	(1 << 5)	/* Setup Transaction Error Interrupt Enable */
#define SACKE	(1 << 4)	/* Setup Transaction ACK Interrupt Enable */

/* INTSTS0 */
#define VBINT	(1 << 15)	/* VBUS0_0 and VBUS1_0 Interrupt Status */
#define DVST	(1 << 12)	/* Device State Transition Interrupt Status */
#define CTRT	(1 << 11)	/* Control Stage Interrupt Status */
#define BEMP	(1 << 10)	/* Buffer Empty Interrupt Status */
#define BRDY	(1 << 8)	/* Buffer Ready Interrupt Status */
#define VBSTS	(1 << 7)	/* VBUS_0 and VBUSIN_0 Input Status */
#define VALID	(1 << 3)	/* USB Request Receive */

#define DVSQ_MASK		(0x3 << 4)	/* Device State */
#define  POWER_STATE		(0 << 4)
#define  DEFAULT_STATE		(1 << 4)
#define  ADDRESS_STATE		(2 << 4)
#define  CONFIGURATION_STATE	(3 << 4)

#define CTSQ_MASK		(0x7)	/* Control Transfer Stage */
#define  IDLE_SETUP_STAGE	0	/* Idle stage or setup stage */
#define  READ_DATA_STAGE	1	/* Control read data stage */
#define  READ_STATUS_STAGE	2	/* Control read status stage */
#define  WRITE_DATA_STAGE	3	/* Control write data stage */
#define  WRITE_STATUS_STAGE	4	/* Control write status stage */
#define  NODATA_STATUS_STAGE	5	/* Control write NoData status stage */
#define  SEQUENCE_ERROR		6	/* Control transfer sequence error */

/* INTSTS1 */
#define OVRCR	(1 << 15) /* OVRCR Interrupt Status */
#define BCHG	(1 << 14) /* USB Bus Change Interrupt Status */
#define DTCH	(1 << 12) /* USB Disconnection Detect Interrupt Status */
#define ATTCH	(1 << 11) /* ATTCH Interrupt Status */
#define EOFERR	(1 << 6)  /* EOF Error Detect Interrupt Status */
#define SIGN	(1 << 5)  /* Setup Transaction Error Interrupt Status */
#define SACK	(1 << 4)  /* Setup Transaction ACK Response Interrupt Status */

/* PIPECFG */
/* DCPCFG */
#define TYPE_NONE	(0 << 14)	/* Transfer Type */
#define TYPE_BULK	(1 << 14)
#define TYPE_INT	(2 << 14)
#define TYPE_ISO	(3 << 14)
#define DBLB		(1 << 9)	/* Double Buffer Mode */
#define SHTNAK		(1 << 7)	/* Pipe Disable in Transfer End */
#define DIR_OUT		(1 << 4)	/* Transfer Direction */

/* PIPEMAXP */
/* DCPMAXP */
#define DEVSEL_MASK	(0xF << 12)	/* Device Select */
#define DCP_MAXP_MASK	(0x7F)
#define PIPE_MAXP_MASK	(0x7FF)

/* PIPEBUF */
#define BUFSIZE_SHIFT	10
#define BUFSIZE_MASK	(0x1F << BUFSIZE_SHIFT)
#define BUFNMB_MASK	(0xFF)

/* PIPEnCTR */
/* DCPCTR */
#define BSTS		(1 << 15)	/* Buffer Status */
#define SUREQ		(1 << 14)	/* Sending SETUP Token */
#define CSSTS		(1 << 12)	/* CSSTS Status */
#define	ACLRM		(1 << 9)	/* Buffer Auto-Clear Mode */
#define SQCLR		(1 << 8)	/* Toggle Bit Clear */
#define SQSET		(1 << 7)	/* Toggle Bit Set */
#define PBUSY		(1 << 5)	/* Pipe Busy */
#define PID_MASK	(0x3)		/* Response PID */
#define  PID_NAK	0
#define  PID_BUF	1
#define  PID_STALL10	2
#define  PID_STALL11	3

#define CCPL		(1 << 2)	/* Control Transfer End Enable */

/* PIPEnTRE */
#define TRENB		(1 << 9)	/* Transaction Counter Enable */
#define TRCLR		(1 << 8)	/* Transaction Counter Clear */

/* FRMNUM */
#define FRNM_MASK	(0x7FF)

/* DEVADDn */
#define UPPHUB(x)	(((x) & 0xF) << 11)	/* HUB Register */
#define HUBPORT(x)	(((x) & 0x7) << 8)	/* HUB Port for Target Device */
#define USBSPD(x)	(((x) & 0x3) << 6)	/* Device Transfer Rate */
#define USBSPD_SPEED_LOW	0x1
#define USBSPD_SPEED_FULL	0x2
#define USBSPD_SPEED_HIGH	0x3

/*
 *		struct
 */
struct usbhs_priv {

	void __iomem *base;
	unsigned int irq;
	unsigned long irqflags;

	struct renesas_usbhs_platform_callback	pfunc;
	struct renesas_usbhs_driver_param	dparam;

	struct delayed_work notify_hotplug_work;
	struct platform_device *pdev;

	spinlock_t		lock;

	u32 flags;

	/*
	 * module control
	 */
	struct usbhs_mod_info mod_info;

	/*
	 * pipe control
	 */
	struct usbhs_pipe_info pipe_info;

	/*
	 * fifo control
	 */
	struct usbhs_fifo_info fifo_info;
};

/*
 * common
 */
u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);

#define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f)
#define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f)

/*
 * sysconfig
 */
void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable);
void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode);

/*
 * usb request
 */
void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);

/*
 * bus
 */
void usbhs_bus_send_sof_enable(struct usbhs_priv *priv);
void usbhs_bus_send_reset(struct usbhs_priv *priv);
int usbhs_bus_get_speed(struct usbhs_priv *priv);
int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);

/*
 * frame
 */
int usbhs_frame_get_num(struct usbhs_priv *priv);

/*
 * device config
 */
int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub,
			   u16 hubport, u16 speed);

/*
 * data
 */
struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
#define usbhs_get_dparam(priv, param)	(priv->dparam.param)
#define usbhs_priv_to_pdev(priv)	(priv->pdev)
#define usbhs_priv_to_dev(priv)		(&priv->pdev->dev)
#define usbhs_priv_to_lock(priv)	(&priv->lock)

#endif /* RENESAS_USB_DRIVER_H */
Commit	Line	Data
f1407d5c KM	1	/*
	2	* Renesas USB driver
	3	*
	4	* Copyright (C) 2011 Renesas Solutions Corp.
	5	* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program; if not, write to the Free Software
	14	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	15	*
	16	*/
	17	#ifndef RENESAS_USB_DRIVER_H
	18	#define RENESAS_USB_DRIVER_H
	19
	20	#include <linux/platform_device.h>
	21	#include <linux/usb/renesas_usbhs.h>
	22
	23	struct usbhs_priv;
	24
cc502bb7 PB	25	#include "mod.h"
cc502bb7 PB	26	#include "pipe.h"
f1407d5c KM	27
	28	/*
	29	*
	30	* register define
	31	*
	32	*/
	33	#define SYSCFG 0x0000
	34	#define BUSWAIT 0x0002
	35	#define DVSTCTR 0x0008
dfbb7f4f	36	#define TESTMODE 0x000C
f1407d5c KM	37	#define CFIFO 0x0014
	38	#define CFIFOSEL 0x0020
	39	#define CFIFOCTR 0x0022
e73a9891 KM	40	#define D0FIFO 0x0100
	41	#define D0FIFOSEL 0x0028
	42	#define D0FIFOCTR 0x002A
	43	#define D1FIFO 0x0120
	44	#define D1FIFOSEL 0x002C
	45	#define D1FIFOCTR 0x002E
f1407d5c KM	46	#define INTENB0 0x0030
	47	#define INTENB1 0x0032
	48	#define BRDYENB 0x0036
	49	#define NRDYENB 0x0038
	50	#define BEMPENB 0x003A
	51	#define INTSTS0 0x0040
	52	#define INTSTS1 0x0042
	53	#define BRDYSTS 0x0046
	54	#define NRDYSTS 0x0048
	55	#define BEMPSTS 0x004A
	56	#define FRMNUM 0x004C
	57	#define USBREQ 0x0054 /* USB request type register */
	58	#define USBVAL 0x0056 /* USB request value register */
	59	#define USBINDX 0x0058 /* USB request index register */
	60	#define USBLENG 0x005A /* USB request length register */
	61	#define DCPCFG 0x005C
	62	#define DCPMAXP 0x005E
	63	#define DCPCTR 0x0060
	64	#define PIPESEL 0x0064
	65	#define PIPECFG 0x0068
	66	#define PIPEBUF 0x006A
	67	#define PIPEMAXP 0x006C
	68	#define PIPEPERI 0x006E
	69	#define PIPEnCTR 0x0070
e73a9891 KM	70	#define PIPE1TRE 0x0090
	71	#define PIPE1TRN 0x0092
	72	#define PIPE2TRE 0x0094
	73	#define PIPE2TRN 0x0096
	74	#define PIPE3TRE 0x0098
	75	#define PIPE3TRN 0x009A
	76	#define PIPE4TRE 0x009C
	77	#define PIPE4TRN 0x009E
	78	#define PIPE5TRE 0x00A0
	79	#define PIPE5TRN 0x00A2
	80	#define PIPEBTRE 0x00A4
	81	#define PIPEBTRN 0x00A6
	82	#define PIPECTRE 0x00A8
	83	#define PIPECTRN 0x00AA
	84	#define PIPEDTRE 0x00AC
	85	#define PIPEDTRN 0x00AE
	86	#define PIPEETRE 0x00B0
	87	#define PIPEETRN 0x00B2
	88	#define PIPEFTRE 0x00B4
	89	#define PIPEFTRN 0x00B6
	90	#define PIPE9TRE 0x00B8
	91	#define PIPE9TRN 0x00BA
	92	#define PIPEATRE 0x00BC
	93	#define PIPEATRN 0x00BE
eb05191f KM	94	#define DEVADD0 0x00D0 /* Device address n configuration */
	95	#define DEVADD1 0x00D2
	96	#define DEVADD2 0x00D4
	97	#define DEVADD3 0x00D6
	98	#define DEVADD4 0x00D8
	99	#define DEVADD5 0x00DA
	100	#define DEVADD6 0x00DC
	101	#define DEVADD7 0x00DE
	102	#define DEVADD8 0x00E0
	103	#define DEVADD9 0x00E2
	104	#define DEVADDA 0x00E4
f1407d5c KM	105
	106	/* SYSCFG */
	107	#define SCKE (1 << 10) /* USB Module Clock Enable */
	108	#define HSE (1 << 7) /* High-Speed Operation Enable */
	109	#define DCFM (1 << 6) /* Controller Function Select */
	110	#define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
	111	#define DPRPU (1 << 4) /* D+ Line Resistance Control */
	112	#define USBE (1 << 0) /* USB Module Operation Enable */
	113
	114	/* DVSTCTR */
	115	#define EXTLP (1 << 10) /* Controls the EXTLP pin output state */
	116	#define PWEN (1 << 9) /* Controls the PWEN pin output state */
258485d9 KM	117	#define USBRST (1 << 6) /* Bus Reset Output */
258485d9 KM	118	#define UACT (1 << 4) /* USB Bus Enable */
f1407d5c KM	119	#define RHST (0x7) /* Reset Handshake */
	120	#define RHST_LOW_SPEED 1 /* Low-speed connection */
	121	#define RHST_FULL_SPEED 2 /* Full-speed connection */
	122	#define RHST_HIGH_SPEED 3 /* High-speed connection */
	123
	124	/* CFIFOSEL */
e73a9891	125	#define DREQE (1 << 12) /* DMA Transfer Request Enable */
f1407d5c KM	126	#define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */
	127
	128	/* CFIFOCTR */
	129	#define BVAL (1 << 15) /* Buffer Memory Enable Flag */
	130	#define BCLR (1 << 14) /* CPU buffer clear */
	131	#define FRDY (1 << 13) /* FIFO Port Ready */
	132	#define DTLN_MASK (0x0FFF) /* Receive Data Length */
	133
	134	/* INTENB0 */
	135	#define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */
	136	#define RSME (1 << 14) /* Enable IRQ Resume */
	137	#define SOFE (1 << 13) /* Enable IRQ Frame Number Update */
	138	#define DVSE (1 << 12) /* Enable IRQ Device State Transition */
	139	#define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */
	140	#define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */
	141	#define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */
	142	#define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */
	143
	144	/* INTENB1 */
	145	#define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */
	146	#define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */
	147	#define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */
	148	#define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */
	149	#define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */
	150	#define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */
	151
	152	/* INTSTS0 */
b002ff6e	153	#define VBINT (1 << 15) /* VBUS0_0 and VBUS1_0 Interrupt Status */
f1407d5c KM	154	#define DVST (1 << 12) /* Device State Transition Interrupt Status */
	155	#define CTRT (1 << 11) /* Control Stage Interrupt Status */
	156	#define BEMP (1 << 10) /* Buffer Empty Interrupt Status */
	157	#define BRDY (1 << 8) /* Buffer Ready Interrupt Status */
	158	#define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */
	159	#define VALID (1 << 3) /* USB Request Receive */
	160
	161	#define DVSQ_MASK (0x3 << 4) /* Device State */
	162	#define POWER_STATE (0 << 4)
	163	#define DEFAULT_STATE (1 << 4)
	164	#define ADDRESS_STATE (2 << 4)
	165	#define CONFIGURATION_STATE (3 << 4)
	166
	167	#define CTSQ_MASK (0x7) /* Control Transfer Stage */
	168	#define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */
	169	#define READ_DATA_STAGE 1 /* Control read data stage */
	170	#define READ_STATUS_STAGE 2 /* Control read status stage */
	171	#define WRITE_DATA_STAGE 3 /* Control write data stage */
	172	#define WRITE_STATUS_STAGE 4 /* Control write status stage */
	173	#define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */
	174	#define SEQUENCE_ERROR 6 /* Control transfer sequence error */
	175
89c1d2e7 KM	176	/* INTSTS1 */
	177	#define OVRCR (1 << 15) /* OVRCR Interrupt Status */
	178	#define BCHG (1 << 14) /* USB Bus Change Interrupt Status */
	179	#define DTCH (1 << 12) /* USB Disconnection Detect Interrupt Status */
	180	#define ATTCH (1 << 11) /* ATTCH Interrupt Status */
	181	#define EOFERR (1 << 6) /* EOF Error Detect Interrupt Status */
	182	#define SIGN (1 << 5) /* Setup Transaction Error Interrupt Status */
	183	#define SACK (1 << 4) /* Setup Transaction ACK Response Interrupt Status */
	184
f1407d5c KM	185	/* PIPECFG */
	186	/* DCPCFG */
	187	#define TYPE_NONE (0 << 14) /* Transfer Type */
	188	#define TYPE_BULK (1 << 14)
	189	#define TYPE_INT (2 << 14)
	190	#define TYPE_ISO (3 << 14)
	191	#define DBLB (1 << 9) /* Double Buffer Mode */
	192	#define SHTNAK (1 << 7) /* Pipe Disable in Transfer End */
	193	#define DIR_OUT (1 << 4) /* Transfer Direction */
	194
	195	/* PIPEMAXP */
	196	/* DCPMAXP */
	197	#define DEVSEL_MASK (0xF << 12) /* Device Select */
	198	#define DCP_MAXP_MASK (0x7F)
	199	#define PIPE_MAXP_MASK (0x7FF)
	200
	201	/* PIPEBUF */
	202	#define BUFSIZE_SHIFT 10
	203	#define BUFSIZE_MASK (0x1F << BUFSIZE_SHIFT)
	204	#define BUFNMB_MASK (0xFF)
	205
	206	/* PIPEnCTR */
	207	/* DCPCTR */
	208	#define BSTS (1 << 15) /* Buffer Status */
ef8bedb9	209	#define SUREQ (1 << 14) /* Sending SETUP Token */
f1407d5c	210	#define CSSTS (1 << 12) /* CSSTS Status */
f1407d5c	211	#define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */
6e6db82b KM	212	#define SQCLR (1 << 8) /* Toggle Bit Clear */
6e6db82b KM	213	#define SQSET (1 << 7) /* Toggle Bit Set */
f1407d5c KM	214	#define PBUSY (1 << 5) /* Pipe Busy */
	215	#define PID_MASK (0x3) /* Response PID */
	216	#define PID_NAK 0
	217	#define PID_BUF 1
	218	#define PID_STALL10 2
	219	#define PID_STALL11 3
	220
	221	#define CCPL (1 << 2) /* Control Transfer End Enable */
	222
e73a9891 KM	223	/* PIPEnTRE */
	224	#define TRENB (1 << 9) /* Transaction Counter Enable */
	225	#define TRCLR (1 << 8) /* Transaction Counter Clear */
	226
f1407d5c KM	227	/* FRMNUM */
	228	#define FRNM_MASK (0x7FF)
	229
eb05191f KM	230	/* DEVADDn */
	231	#define UPPHUB(x) (((x) & 0xF) << 11) /* HUB Register */
	232	#define HUBPORT(x) (((x) & 0x7) << 8) /* HUB Port for Target Device */
	233	#define USBSPD(x) (((x) & 0x3) << 6) /* Device Transfer Rate */
	234	#define USBSPD_SPEED_LOW 0x1
	235	#define USBSPD_SPEED_FULL 0x2
	236	#define USBSPD_SPEED_HIGH 0x3
	237
f1407d5c KM	238	/*
	239	* struct
	240	*/
	241	struct usbhs_priv {
	242
	243	void __iomem *base;
	244	unsigned int irq;
53069af3	245	unsigned long irqflags;
f1407d5c	246
48298206 KM	247	struct renesas_usbhs_platform_callback pfunc;
48298206 KM	248	struct renesas_usbhs_driver_param dparam;
f1407d5c	249
bc57381e	250	struct delayed_work notify_hotplug_work;
f1407d5c KM	251	struct platform_device *pdev;
	252
	253	spinlock_t lock;
	254
b002ff6e KM	255	u32 flags;
b002ff6e KM	256
f1407d5c KM	257	/*
	258	* module control
	259	*/
	260	struct usbhs_mod_info mod_info;
	261
	262	/*
	263	* pipe control
	264	*/
	265	struct usbhs_pipe_info pipe_info;
d3af90a5 KM	266
	267	/*
	268	* fifo control
	269	*/
	270	struct usbhs_fifo_info fifo_info;
f1407d5c KM	271	};
	272
	273	/*
	274	* common
	275	*/
	276	u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
	277	void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
	278	void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
	279
97664a20 KM	280	#define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f)
	281	#define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f)
	282
f1407d5c KM	283	/*
	284	* sysconfig
	285	*/
f1407d5c KM	286	void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
f1407d5c KM	287	void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
4cd2f599	288	void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable);
dfbb7f4f	289	void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode);
f1407d5c	290
ef8bedb9 KM	291	/*
	292	* usb request
	293	*/
	294	void usbhs_usbreq_get_val(struct usbhs_priv priv, struct usb_ctrlrequest req);
	295	void usbhs_usbreq_set_val(struct usbhs_priv priv, struct usb_ctrlrequest req);
	296
258485d9 KM	297	/*
	298	* bus
	299	*/
	300	void usbhs_bus_send_sof_enable(struct usbhs_priv *priv);
	301	void usbhs_bus_send_reset(struct usbhs_priv *priv);
75587f52	302	int usbhs_bus_get_speed(struct usbhs_priv *priv);
258485d9 KM	303	int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);
258485d9 KM	304
f1407d5c KM	305	/*
	306	* frame
	307	*/
	308	int usbhs_frame_get_num(struct usbhs_priv *priv);
	309
eb05191f KM	310	/*
	311	* device config
	312	*/
3dd49268	313	int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub,
eb05191f KM	314	u16 hubport, u16 speed);
eb05191f KM	315
f1407d5c KM	316	/*
	317	* data
	318	*/
206dcc2c	319	struct usbhs_priv usbhs_pdev_to_priv(struct platform_device pdev);
48298206	320	#define usbhs_get_dparam(priv, param) (priv->dparam.param)
f1407d5c KM	321	#define usbhs_priv_to_pdev(priv) (priv->pdev)
	322	#define usbhs_priv_to_dev(priv) (&priv->pdev->dev)
	323	#define usbhs_priv_to_lock(priv) (&priv->lock)
	324
	325	#endif /* RENESAS_USB_DRIVER_H */