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Merge tag 'v3.10.97' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / musb / tusb6010_omap.c
CommitLineData
550a7375
FB		 1/*
2 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/init.h>
15#include <linux/usb.h>
16#include <linux/platform_device.h>
17#include <linux/dma-mapping.h>
5a0e3ad6 18#include <linux/slab.h>
45c3eb7d 19#include <linux/omap-dma.h>
550a7375
FB		 20
21#include "musb_core.h"
240a16e2 22#include "tusb6010.h"
550a7375
FB		 23
24#define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data)
25
26#define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
27
d5e7c864
LV		 28#define OMAP24XX_DMA_EXT_DMAREQ0 2
29#define OMAP24XX_DMA_EXT_DMAREQ1 3
30#define OMAP242X_DMA_EXT_DMAREQ2 14
31#define OMAP242X_DMA_EXT_DMAREQ3 15
32#define OMAP242X_DMA_EXT_DMAREQ4 16
33#define OMAP242X_DMA_EXT_DMAREQ5 64
34
550a7375
FB		 35struct tusb_omap_dma_ch {
36 struct musb *musb;
37 void __iomem *tbase;
38 unsigned long phys_offset;
39 int epnum;
40 u8 tx;
41 struct musb_hw_ep *hw_ep;
42
43 int ch;
44 s8 dmareq;
45 s8 sync_dev;
46
47 struct tusb_omap_dma *tusb_dma;
48
1d0f11b3 49 dma_addr_t dma_addr;
550a7375
FB		 50
51 u32 len;
52 u16 packet_sz;
53 u16 transfer_packet_sz;
54 u32 transfer_len;
55 u32 completed_len;
56};
57
58struct tusb_omap_dma {
59 struct dma_controller controller;
60 struct musb *musb;
61 void __iomem *tbase;
62
63 int ch;
64 s8 dmareq;
65 s8 sync_dev;
66 unsigned multichannel:1;
67};
68
69static int tusb_omap_dma_start(struct dma_controller *c)
70{
71 struct tusb_omap_dma *tusb_dma;
72
73 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
74
5c8a86e1 75 /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
550a7375
FB		 76
77 return 0;
78}
79
80static int tusb_omap_dma_stop(struct dma_controller *c)
81{
82 struct tusb_omap_dma *tusb_dma;
83
84 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
85
5c8a86e1 86 /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
550a7375
FB		 87
88 return 0;
89}
90
91/*
92 * Allocate dmareq0 to the current channel unless it's already taken
93 */
94static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
95{
96 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
97
98 if (reg != 0) {
74c6f3a4 99 dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n",
550a7375
FB		 100 chdat->epnum, reg & 0xf);
101 return -EAGAIN;
102 }
103
104 if (chdat->tx)
105 reg = (1 << 4) | chdat->epnum;
106 else
107 reg = chdat->epnum;
108
109 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
110
111 return 0;
112}
113
114static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
115{
116 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
117
118 if ((reg & 0xf) != chdat->epnum) {
119 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
120 chdat->epnum, reg & 0xf);
121 return;
122 }
123 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0);
124}
125
126/*
127 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
128 * musb_gadget.c.
129 */
130static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
131{
132 struct dma_channel *channel = (struct dma_channel *)data;
133 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
134 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
135 struct musb *musb = chdat->musb;
1d0f11b3 136 struct device *dev = musb->controller;
550a7375
FB		 137 struct musb_hw_ep *hw_ep = chdat->hw_ep;
138 void __iomem *ep_conf = hw_ep->conf;
139 void __iomem *mbase = musb->mregs;
140 unsigned long remaining, flags, pio;
141 int ch;
142
143 spin_lock_irqsave(&musb->lock, flags);
144
145 if (tusb_dma->multichannel)
146 ch = chdat->ch;
147 else
148 ch = tusb_dma->ch;
149
150 if (ch_status != OMAP_DMA_BLOCK_IRQ)
151 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
152
5c8a86e1 153 dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n",
550a7375
FB		 154 chdat->epnum, chdat->tx ? "tx" : "rx",
155 ch, ch_status);
156
157 if (chdat->tx)
158 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
159 else
160 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
161
162 remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);
163
164 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
165 if (unlikely(remaining > chdat->transfer_len)) {
5c8a86e1 166 dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
550a7375
FB		 167 chdat->tx ? "tx" : "rx", chdat->ch,
168 remaining);
169 remaining = 0;
170 }
171
172 channel->actual_len = chdat->transfer_len - remaining;
173 pio = chdat->len - channel->actual_len;
174
5c8a86e1 175 dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
550a7375
FB		 176
177 /* Transfer remaining 1 - 31 bytes */
178 if (pio > 0 && pio < 32) {
179 u8 *buf;
180
5c8a86e1 181 dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
550a7375
FB		 182 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
183 if (chdat->tx) {
1d0f11b3
TL		 184 dma_unmap_single(dev, chdat->dma_addr,
185 chdat->transfer_len,
186 DMA_TO_DEVICE);
550a7375
FB		 187 musb_write_fifo(hw_ep, pio, buf);
188 } else {
1d0f11b3
TL		 189 dma_unmap_single(dev, chdat->dma_addr,
190 chdat->transfer_len,
191 DMA_FROM_DEVICE);
550a7375 192 musb_read_fifo(hw_ep, pio, buf);
550a7375
FB		 193 }
194 channel->actual_len += pio;
195 }
196
197 if (!tusb_dma->multichannel)
198 tusb_omap_free_shared_dmareq(chdat);
199
200 channel->status = MUSB_DMA_STATUS_FREE;
201
202 /* Handle only RX callbacks here. TX callbacks must be handled based
203 * on the TUSB DMA status interrupt.
204 * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback
205 * interrupt for RX and TX.
206 */
207 if (!chdat->tx)
208 musb_dma_completion(musb, chdat->epnum, chdat->tx);
209
210 /* We must terminate short tx transfers manually by setting TXPKTRDY.
211 * REVISIT: This same problem may occur with other MUSB dma as well.
212 * Easy to test with g_ether by pinging the MUSB board with ping -s54.
213 */
214 if ((chdat->transfer_len < chdat->packet_sz)
215 || (chdat->transfer_len % chdat->packet_sz != 0)) {
216 u16 csr;
217
218 if (chdat->tx) {
5c8a86e1 219 dev_dbg(musb->controller, "terminating short tx packet\n");
550a7375
FB		 220 musb_ep_select(mbase, chdat->epnum);
221 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
222 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
223 | MUSB_TXCSR_P_WZC_BITS;
224 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
225 }
226 }
227
228 spin_unlock_irqrestore(&musb->lock, flags);
229}
230
231static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
232 u8 rndis_mode, dma_addr_t dma_addr, u32 len)
233{
234 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
235 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
236 struct musb *musb = chdat->musb;
1d0f11b3 237 struct device *dev = musb->controller;
550a7375
FB		 238 struct musb_hw_ep *hw_ep = chdat->hw_ep;
239 void __iomem *mbase = musb->mregs;
240 void __iomem *ep_conf = hw_ep->conf;
241 dma_addr_t fifo = hw_ep->fifo_sync;
242 struct omap_dma_channel_params dma_params;
243 u32 dma_remaining;
244 int src_burst, dst_burst;
245 u16 csr;
246 int ch;
247 s8 dmareq;
248 s8 sync_dev;
249
250 if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
251 return false;
252
253 /*
254 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE
255 * register which will cause missed DMA interrupt. We could try to
256 * use a timer for the callback, but it is unsafe as the XFR_SIZE
257 * register is corrupt, and we won't know if the DMA worked.
258 */
259 if (dma_addr & 0x2)
260 return false;
261
262 /*
263 * Because of HW issue #10, it seems like mixing sync DMA and async
264 * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
265 * using the channel for DMA.
266 */
267 if (chdat->tx)
268 dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
269 else
270 dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
271
272 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
273 if (dma_remaining) {
5c8a86e1 274 dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n",
550a7375
FB		 275 chdat->tx ? "tx" : "rx", chdat->ch,
276 dma_remaining);
277 return false;
278 }
279
280 chdat->transfer_len = len & ~0x1f;
281
282 if (len < packet_sz)
283 chdat->transfer_packet_sz = chdat->transfer_len;
284 else
285 chdat->transfer_packet_sz = packet_sz;
286
287 if (tusb_dma->multichannel) {
288 ch = chdat->ch;
289 dmareq = chdat->dmareq;
290 sync_dev = chdat->sync_dev;
291 } else {
292 if (tusb_omap_use_shared_dmareq(chdat) != 0) {
5c8a86e1 293 dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
550a7375
FB		 294 return false;
295 }
296 if (tusb_dma->ch < 0) {
297 /* REVISIT: This should get blocked earlier, happens
298 * with MSC ErrorRecoveryTest
299 */
300 WARN_ON(1);
301 return false;
302 }
303
304 ch = tusb_dma->ch;
305 dmareq = tusb_dma->dmareq;
306 sync_dev = tusb_dma->sync_dev;
307 omap_set_dma_callback(ch, tusb_omap_dma_cb, channel);
308 }
309
310 chdat->packet_sz = packet_sz;
311 chdat->len = len;
312 channel->actual_len = 0;
1d0f11b3 313 chdat->dma_addr = dma_addr;
550a7375
FB		 314 channel->status = MUSB_DMA_STATUS_BUSY;
315
316 /* Since we're recycling dma areas, we need to clean or invalidate */
317 if (chdat->tx)
1d0f11b3
TL		 318 dma_map_single(dev, phys_to_virt(dma_addr), len,
319 DMA_TO_DEVICE);
550a7375 320 else
1d0f11b3
TL		 321 dma_map_single(dev, phys_to_virt(dma_addr), len,
322 DMA_FROM_DEVICE);
550a7375
FB		 323
324 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */
325 if ((dma_addr & 0x3) == 0) {
326 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32;
327 dma_params.elem_count = 8; /* Elements in frame */
328 } else {
329 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16;
330 dma_params.elem_count = 16; /* Elements in frame */
331 fifo = hw_ep->fifo_async;
332 }
333
334 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
335
5c8a86e1 336 dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
550a7375
FB		 337 chdat->epnum, chdat->tx ? "tx" : "rx",
338 ch, dma_addr, chdat->transfer_len, len,
339 chdat->transfer_packet_sz, packet_sz);
340
341 /*
342 * Prepare omap DMA for transfer
343 */
344 if (chdat->tx) {
345 dma_params.src_amode = OMAP_DMA_AMODE_POST_INC;
346 dma_params.src_start = (unsigned long)dma_addr;
347 dma_params.src_ei = 0;
348 dma_params.src_fi = 0;
349
350 dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
351 dma_params.dst_start = (unsigned long)fifo;
352 dma_params.dst_ei = 1;
353 dma_params.dst_fi = -31; /* Loop 32 byte window */
354
355 dma_params.trigger = sync_dev;
356 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
357 dma_params.src_or_dst_synch = 0; /* Dest sync */
358
359 src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */
360 dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */
361 } else {
362 dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
363 dma_params.src_start = (unsigned long)fifo;
364 dma_params.src_ei = 1;
365 dma_params.src_fi = -31; /* Loop 32 byte window */
366
367 dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC;
368 dma_params.dst_start = (unsigned long)dma_addr;
369 dma_params.dst_ei = 0;
370 dma_params.dst_fi = 0;
371
372 dma_params.trigger = sync_dev;
373 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
374 dma_params.src_or_dst_synch = 1; /* Source sync */
375
376 src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */
377 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
378 }
379
5c8a86e1 380 dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
550a7375
FB		 381 chdat->epnum, chdat->tx ? "tx" : "rx",
382 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
383 ((dma_addr & 0x3) == 0) ? "sync" : "async",
384 dma_params.src_start, dma_params.dst_start);
385
386 omap_set_dma_params(ch, &dma_params);
387 omap_set_dma_src_burst_mode(ch, src_burst);
388 omap_set_dma_dest_burst_mode(ch, dst_burst);
389 omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
390
391 /*
392 * Prepare MUSB for DMA transfer
393 */
394 if (chdat->tx) {
395 musb_ep_select(mbase, chdat->epnum);
396 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
397 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
398 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
399 csr &= ~MUSB_TXCSR_P_UNDERRUN;
400 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
401 } else {
402 musb_ep_select(mbase, chdat->epnum);
403 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
404 csr |= MUSB_RXCSR_DMAENAB;
405 csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
406 musb_writew(hw_ep->regs, MUSB_RXCSR,
407 csr | MUSB_RXCSR_P_WZC_BITS);
408 }
409
410 /*
411 * Start DMA transfer
412 */
413 omap_start_dma(ch);
414
415 if (chdat->tx) {
416 /* Send transfer_packet_sz packets at a time */
417 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
418 chdat->transfer_packet_sz);
419
420 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
421 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
422 } else {
423 /* Receive transfer_packet_sz packets at a time */
424 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
425 chdat->transfer_packet_sz << 16);
426
427 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
428 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
429 }
430
431 return true;
432}
433
434static int tusb_omap_dma_abort(struct dma_channel *channel)
435{
436 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
437 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
438
439 if (!tusb_dma->multichannel) {
440 if (tusb_dma->ch >= 0) {
441 omap_stop_dma(tusb_dma->ch);
442 omap_free_dma(tusb_dma->ch);
443 tusb_dma->ch = -1;
444 }
445
446 tusb_dma->dmareq = -1;
447 tusb_dma->sync_dev = -1;
448 }
449
450 channel->status = MUSB_DMA_STATUS_FREE;
451
452 return 0;
453}
454
455static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
456{
457 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
458 int i, dmareq_nr = -1;
459
460 const int sync_dev[6] = {
461 OMAP24XX_DMA_EXT_DMAREQ0,
462 OMAP24XX_DMA_EXT_DMAREQ1,
463 OMAP242X_DMA_EXT_DMAREQ2,
464 OMAP242X_DMA_EXT_DMAREQ3,
465 OMAP242X_DMA_EXT_DMAREQ4,
466 OMAP242X_DMA_EXT_DMAREQ5,
467 };
468
469 for (i = 0; i < MAX_DMAREQ; i++) {
470 int cur = (reg & (0xf << (i * 5))) >> (i * 5);
471 if (cur == 0) {
472 dmareq_nr = i;
473 break;
474 }
475 }
476
477 if (dmareq_nr == -1)
478 return -EAGAIN;
479
480 reg |= (chdat->epnum << (dmareq_nr * 5));
481 if (chdat->tx)
482 reg |= ((1 << 4) << (dmareq_nr * 5));
483 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
484
485 chdat->dmareq = dmareq_nr;
486 chdat->sync_dev = sync_dev[chdat->dmareq];
487
488 return 0;
489}
490
491static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
492{
493 u32 reg;
494
495 if (!chdat || chdat->dmareq < 0)
496 return;
497
498 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
499 reg &= ~(0x1f << (chdat->dmareq * 5));
500 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
501
502 chdat->dmareq = -1;
503 chdat->sync_dev = -1;
504}
505
506static struct dma_channel *dma_channel_pool[MAX_DMAREQ];
507
508static struct dma_channel *
509tusb_omap_dma_allocate(struct dma_controller *c,
510 struct musb_hw_ep *hw_ep,
511 u8 tx)
512{
513 int ret, i;
514 const char *dev_name;
515 struct tusb_omap_dma *tusb_dma;
516 struct musb *musb;
517 void __iomem *tbase;
518 struct dma_channel *channel = NULL;
519 struct tusb_omap_dma_ch *chdat = NULL;
520 u32 reg;
521
522 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
523 musb = tusb_dma->musb;
524 tbase = musb->ctrl_base;
525
526 reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
527 if (tx)
528 reg &= ~(1 << hw_ep->epnum);
529 else
530 reg &= ~(1 << (hw_ep->epnum + 15));
531 musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
532
533 /* REVISIT: Why does dmareq5 not work? */
534 if (hw_ep->epnum == 0) {
5c8a86e1 535 dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
550a7375
FB		 536 return NULL;
537 }
538
539 for (i = 0; i < MAX_DMAREQ; i++) {
540 struct dma_channel *ch = dma_channel_pool[i];
541 if (ch->status == MUSB_DMA_STATUS_UNKNOWN) {
542 ch->status = MUSB_DMA_STATUS_FREE;
543 channel = ch;
544 chdat = ch->private_data;
545 break;
546 }
547 }
548
549 if (!channel)
550 return NULL;
551
552 if (tx) {
553 chdat->tx = 1;
554 dev_name = "TUSB transmit";
555 } else {
556 chdat->tx = 0;
557 dev_name = "TUSB receive";
558 }
559
560 chdat->musb = tusb_dma->musb;
561 chdat->tbase = tusb_dma->tbase;
562 chdat->hw_ep = hw_ep;
563 chdat->epnum = hw_ep->epnum;
564 chdat->dmareq = -1;
565 chdat->completed_len = 0;
566 chdat->tusb_dma = tusb_dma;
567
568 channel->max_len = 0x7fffffff;
569 channel->desired_mode = 0;
570 channel->actual_len = 0;
571
572 if (tusb_dma->multichannel) {
573 ret = tusb_omap_dma_allocate_dmareq(chdat);
574 if (ret != 0)
575 goto free_dmareq;
576
577 ret = omap_request_dma(chdat->sync_dev, dev_name,
578 tusb_omap_dma_cb, channel, &chdat->ch);
579 if (ret != 0)
580 goto free_dmareq;
581 } else if (tusb_dma->ch == -1) {
582 tusb_dma->dmareq = 0;
583 tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0;
584
585 /* Callback data gets set later in the shared dmareq case */
586 ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared",
587 tusb_omap_dma_cb, NULL, &tusb_dma->ch);
588 if (ret != 0)
589 goto free_dmareq;
590
591 chdat->dmareq = -1;
592 chdat->ch = -1;
593 }
594
5c8a86e1 595 dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
550a7375
FB		 596 chdat->epnum,
597 chdat->tx ? "tx" : "rx",
598 chdat->ch >= 0 ? "dedicated" : "shared",
599 chdat->ch >= 0 ? chdat->ch : tusb_dma->ch,
600 chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq,
601 chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev);
602
603 return channel;
604
605free_dmareq:
606 tusb_omap_dma_free_dmareq(chdat);
607
5c8a86e1 608 dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
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FB		 609 channel->status = MUSB_DMA_STATUS_UNKNOWN;
610
611 return NULL;
612}
613
614static void tusb_omap_dma_release(struct dma_channel *channel)
615{
616 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
617 struct musb *musb = chdat->musb;
618 void __iomem *tbase = musb->ctrl_base;
619 u32 reg;
620
5c8a86e1 621 dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch);
550a7375
FB		 622
623 reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
624 if (chdat->tx)
625 reg |= (1 << chdat->epnum);
626 else
627 reg |= (1 << (chdat->epnum + 15));
628 musb_writel(tbase, TUSB_DMA_INT_MASK, reg);
629
630 reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR);
631 if (chdat->tx)
632 reg |= (1 << chdat->epnum);
633 else
634 reg |= (1 << (chdat->epnum + 15));
635 musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg);
636
637 channel->status = MUSB_DMA_STATUS_UNKNOWN;
638
639 if (chdat->ch >= 0) {
640 omap_stop_dma(chdat->ch);
641 omap_free_dma(chdat->ch);
642 chdat->ch = -1;
643 }
644
645 if (chdat->dmareq >= 0)
646 tusb_omap_dma_free_dmareq(chdat);
647
648 channel = NULL;
649}
650
651void dma_controller_destroy(struct dma_controller *c)
652{
653 struct tusb_omap_dma *tusb_dma;
654 int i;
655
656 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
657 for (i = 0; i < MAX_DMAREQ; i++) {
658 struct dma_channel *ch = dma_channel_pool[i];
659 if (ch) {
660 kfree(ch->private_data);
661 kfree(ch);
662 }
663 }
664
94089d56 665 if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0)
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FB		 666 omap_free_dma(tusb_dma->ch);
667
668 kfree(tusb_dma);
669}
670
41ac7b3a 671struct dma_controller *dma_controller_create(struct musb *musb, void __iomem *base)
550a7375
FB		 672{
673 void __iomem *tbase = musb->ctrl_base;
674 struct tusb_omap_dma *tusb_dma;
675 int i;
676
677 /* REVISIT: Get dmareq lines used from board-*.c */
678
679 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
680 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);
681
682 musb_writel(tbase, TUSB_DMA_REQ_CONF,
683 TUSB_DMA_REQ_CONF_BURST_SIZE(2)
684 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
685 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
686
687 tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
688 if (!tusb_dma)
c88ba39c 689 goto out;
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FB		 690
691 tusb_dma->musb = musb;
692 tusb_dma->tbase = musb->ctrl_base;
693
694 tusb_dma->ch = -1;
695 tusb_dma->dmareq = -1;
696 tusb_dma->sync_dev = -1;
697
698 tusb_dma->controller.start = tusb_omap_dma_start;
699 tusb_dma->controller.stop = tusb_omap_dma_stop;
700 tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
701 tusb_dma->controller.channel_release = tusb_omap_dma_release;
702 tusb_dma->controller.channel_program = tusb_omap_dma_program;
703 tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
704
705 if (tusb_get_revision(musb) >= TUSB_REV_30)
706 tusb_dma->multichannel = 1;
707
708 for (i = 0; i < MAX_DMAREQ; i++) {
709 struct dma_channel *ch;
710 struct tusb_omap_dma_ch *chdat;
711
712 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
713 if (!ch)
714 goto cleanup;
715
716 dma_channel_pool[i] = ch;
717
718 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
719 if (!chdat)
720 goto cleanup;
721
722 ch->status = MUSB_DMA_STATUS_UNKNOWN;
723 ch->private_data = chdat;
724 }
725
726 return &tusb_dma->controller;
727
728cleanup:
729 dma_controller_destroy(&tusb_dma->controller);
c88ba39c 730out:
550a7375
FB		 731 return NULL;
732}
kernel source for telekom puls (alcatel/mediatek)