[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / musb / davinci.c

/*
 * Copyright (C) 2005-2006 by Texas Instruments
 *
 * This file is part of the Inventra Controller Driver for Linux.
 *
 * The Inventra Controller Driver for Linux is free software; you
 * can redistribute it and/or modify it under the terms of the GNU
 * General Public License version 2 as published by the Free Software
 * Foundation.
 *
 * The Inventra Controller Driver for Linux is distributed in
 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
 * without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 * License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with The Inventra Controller Driver for Linux ; if not,
 * write to the Free Software Foundation, Inc., 59 Temple Place,
 * Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>

#include <mach/hardware.h>
#include <mach/memory.h>
#include <mach/gpio.h>
#include <mach/cputype.h>

#include <asm/mach-types.h>

#include "musb_core.h"

#ifdef CONFIG_MACH_DAVINCI_EVM
#define GPIO_nVBUS_DRV		160
#endif

#include "davinci.h"
#include "cppi_dma.h"


#define USB_PHY_CTRL	IO_ADDRESS(USBPHY_CTL_PADDR)
#define DM355_DEEPSLEEP	IO_ADDRESS(DM355_DEEPSLEEP_PADDR)

/* REVISIT (PM) we should be able to keep the PHY in low power mode most
 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
 * and, when in host mode, autosuspending idle root ports... PHYPLLON
 * (overriding SUSPENDM?) then likely needs to stay off.
 */

static inline void phy_on(void)
{
	u32	phy_ctrl = __raw_readl(USB_PHY_CTRL);

	/* power everything up; start the on-chip PHY and its PLL */
	phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
	phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
	__raw_writel(phy_ctrl, USB_PHY_CTRL);

	/* wait for PLL to lock before proceeding */
	while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
		cpu_relax();
}

static inline void phy_off(void)
{
	u32	phy_ctrl = __raw_readl(USB_PHY_CTRL);

	/* powerdown the on-chip PHY, its PLL, and the OTG block */
	phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON);
	phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN;
	__raw_writel(phy_ctrl, USB_PHY_CTRL);
}

static int dma_off = 1;

void musb_platform_enable(struct musb *musb)
{
	u32	tmp, old, val;

	/* workaround:  setup irqs through both register sets */
	tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
			<< DAVINCI_USB_TXINT_SHIFT;
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	old = tmp;
	tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
			<< DAVINCI_USB_RXINT_SHIFT;
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	tmp |= old;

	val = ~MUSB_INTR_SOF;
	tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);

	if (is_dma_capable() && !dma_off)
		printk(KERN_WARNING "%s %s: dma not reactivated\n",
				__FILE__, __func__);
	else
		dma_off = 0;

	/* force a DRVVBUS irq so we can start polling for ID change */
	if (is_otg_enabled(musb))
		musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
			DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
}

/*
 * Disable the HDRC and flush interrupts
 */
void musb_platform_disable(struct musb *musb)
{
	/* because we don't set CTRLR.UINT, "important" to:
	 *  - not read/write INTRUSB/INTRUSBE
	 *  - (except during initial setup, as workaround)
	 *  - use INTSETR/INTCLRR instead
	 */
	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
			  DAVINCI_USB_USBINT_MASK
			| DAVINCI_USB_TXINT_MASK
			| DAVINCI_USB_RXINT_MASK);
	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);

	if (is_dma_capable() && !dma_off)
		WARNING("dma still active\n");
}


#ifdef CONFIG_USB_MUSB_HDRC_HCD
#define	portstate(stmt)		stmt
#else
#define	portstate(stmt)
#endif


/*
 * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
 * which doesn't wire DRVVBUS to the FET that switches it.  Unclear
 * if that's a problem with the DM6446 chip or just with that board.
 *
 * In either case, the DM355 EVM automates DRVVBUS the normal way,
 * when J10 is out, and TI documents it as handling OTG.
 */

#ifdef CONFIG_MACH_DAVINCI_EVM

static int vbus_state = -1;

/* I2C operations are always synchronous, and require a task context.
 * With unloaded systems, using the shared workqueue seems to suffice
 * to satisfy the 100msec A_WAIT_VRISE timeout...
 */
static void evm_deferred_drvvbus(struct work_struct *ignored)
{
	gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
	vbus_state = !vbus_state;
}

#endif	/* EVM */

static void davinci_source_power(struct musb *musb, int is_on, int immediate)
{
#ifdef CONFIG_MACH_DAVINCI_EVM
	if (is_on)
		is_on = 1;

	if (vbus_state == is_on)
		return;
	vbus_state = !is_on;		/* 0/1 vs "-1 == unknown/init" */

	if (machine_is_davinci_evm()) {
		static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);

		if (immediate)
			gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
		else
			schedule_work(&evm_vbus_work);
	}
	if (immediate)
		vbus_state = is_on;
#endif
}

static void davinci_set_vbus(struct musb *musb, int is_on)
{
	WARN_ON(is_on && is_peripheral_active(musb));
	davinci_source_power(musb, is_on, 0);
}


#define	POLL_SECONDS	2

static struct timer_list otg_workaround;

static void otg_timer(unsigned long _musb)
{
	struct musb		*musb = (void *)_musb;
	void __iomem		*mregs = musb->mregs;
	u8			devctl;
	unsigned long		flags;

	/* We poll because DaVinci's won't expose several OTG-critical
	* status change events (from the transceiver) otherwise.
	 */
	devctl = musb_readb(mregs, MUSB_DEVCTL);
	DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_WAIT_VFALL:
		/* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
		 * seems to mis-handle session "start" otherwise (or in our
		 * case "recover"), in routine "VBUS was valid by the time
		 * VBUSERR got reported during enumeration" cases.
		 */
		if (devctl & MUSB_DEVCTL_VBUS) {
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
			break;
		}
		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
		musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
			MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
		break;
	case OTG_STATE_B_IDLE:
		if (!is_peripheral_enabled(musb))
			break;

		/* There's no ID-changed IRQ, so we have no good way to tell
		 * when to switch to the A-Default state machine (by setting
		 * the DEVCTL.SESSION flag).
		 *
		 * Workaround:  whenever we're in B_IDLE, try setting the
		 * session flag every few seconds.  If it works, ID was
		 * grounded and we're now in the A-Default state machine.
		 *
		 * NOTE setting the session flag is _supposed_ to trigger
		 * SRP, but clearly it doesn't.
		 */
		musb_writeb(mregs, MUSB_DEVCTL,
				devctl | MUSB_DEVCTL_SESSION);
		devctl = musb_readb(mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE)
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
		else
			musb->xceiv->state = OTG_STATE_A_IDLE;
		break;
	default:
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);
}

static irqreturn_t davinci_interrupt(int irq, void *__hci)
{
	unsigned long	flags;
	irqreturn_t	retval = IRQ_NONE;
	struct musb	*musb = __hci;
	void __iomem	*tibase = musb->ctrl_base;
	struct cppi	*cppi;
	u32		tmp;

	spin_lock_irqsave(&musb->lock, flags);

	/* NOTE: DaVinci shadows the Mentor IRQs.  Don't manage them through
	 * the Mentor registers (except for setup), use the TI ones and EOI.
	 *
	 * Docs describe irq "vector" registers associated with the CPPI and
	 * USB EOI registers.  These hold a bitmask corresponding to the
	 * current IRQ, not an irq handler address.  Would using those bits
	 * resolve some of the races observed in this dispatch code??
	 */

	/* CPPI interrupts share the same IRQ line, but have their own
	 * mask, state, "vector", and EOI registers.
	 */
	cppi = container_of(musb->dma_controller, struct cppi, controller);
	if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
		retval = cppi_interrupt(irq, __hci);

	/* ack and handle non-CPPI interrupts */
	tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
	musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
	DBG(4, "IRQ %08x\n", tmp);

	musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
			>> DAVINCI_USB_RXINT_SHIFT;
	musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
			>> DAVINCI_USB_TXINT_SHIFT;
	musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
			>> DAVINCI_USB_USBINT_SHIFT;

	/* DRVVBUS irqs are the only proxy we have (a very poor one!) for
	 * DaVinci's missing ID change IRQ.  We need an ID change IRQ to
	 * switch appropriately between halves of the OTG state machine.
	 * Managing DEVCTL.SESSION per Mentor docs requires we know its
	 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
	 */
	if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
		int	drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
		void __iomem *mregs = musb->mregs;
		u8	devctl = musb_readb(mregs, MUSB_DEVCTL);
		int	err = musb->int_usb & MUSB_INTR_VBUSERROR;

		err = is_host_enabled(musb)
				&& (musb->int_usb & MUSB_INTR_VBUSERROR);
		if (err) {
			/* The Mentor core doesn't debounce VBUS as needed
			 * to cope with device connect current spikes. This
			 * means it's not uncommon for bus-powered devices
			 * to get VBUS errors during enumeration.
			 *
			 * This is a workaround, but newer RTL from Mentor
			 * seems to allow a better one: "re"starting sessions
			 * without waiting (on EVM, a **long** time) for VBUS
			 * to stop registering in devctl.
			 */
			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
			WARNING("VBUS error workaround (delay coming)\n");
		} else if (is_host_enabled(musb) && drvvbus) {
			MUSB_HST_MODE(musb);
			musb->xceiv->default_a = 1;
			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
			del_timer(&otg_workaround);
		} else {
			musb->is_active = 0;
			MUSB_DEV_MODE(musb);
			musb->xceiv->default_a = 0;
			musb->xceiv->state = OTG_STATE_B_IDLE;
			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
		}

		/* NOTE:  this must complete poweron within 100 msec
		 * (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
		 */
		davinci_source_power(musb, drvvbus, 0);
		DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
				drvvbus ? "on" : "off",
				otg_state_string(musb),
				err ? " ERROR" : "",
				devctl);
		retval = IRQ_HANDLED;
	}

	if (musb->int_tx || musb->int_rx || musb->int_usb)
		retval |= musb_interrupt(musb);

	/* irq stays asserted until EOI is written */
	musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);

	/* poll for ID change */
	if (is_otg_enabled(musb)
			&& musb->xceiv->state == OTG_STATE_B_IDLE)
		mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);

	spin_unlock_irqrestore(&musb->lock, flags);

	return retval;
}

int musb_platform_set_mode(struct musb *musb, u8 mode)
{
	/* EVM can't do this (right?) */
	return -EIO;
}

int __init musb_platform_init(struct musb *musb)
{
	void __iomem	*tibase = musb->ctrl_base;
	u32		revision;

	usb_nop_xceiv_register();
	musb->xceiv = otg_get_transceiver();
	if (!musb->xceiv)
		return -ENODEV;

	musb->mregs += DAVINCI_BASE_OFFSET;

	clk_enable(musb->clock);

	/* returns zero if e.g. not clocked */
	revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
	if (revision == 0)
		goto fail;

	if (is_host_enabled(musb))
		setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);

	musb->board_set_vbus = davinci_set_vbus;
	davinci_source_power(musb, 0, 1);

	/* dm355 EVM swaps D+/D- for signal integrity, and
	 * is clocked from the main 24 MHz crystal.
	 */
	if (machine_is_davinci_dm355_evm()) {
		u32	phy_ctrl = __raw_readl(USB_PHY_CTRL);

		phy_ctrl &= ~(3 << 9);
		phy_ctrl |= USBPHY_DATAPOL;
		__raw_writel(phy_ctrl, USB_PHY_CTRL);
	}

	/* On dm355, the default-A state machine needs DRVVBUS control.
	 * If we won't be a host, there's no need to turn it on.
	 */
	if (cpu_is_davinci_dm355()) {
		u32	deepsleep = __raw_readl(DM355_DEEPSLEEP);

		if (is_host_enabled(musb)) {
			deepsleep &= ~DRVVBUS_OVERRIDE;
		} else {
			deepsleep &= ~DRVVBUS_FORCE;
			deepsleep |= DRVVBUS_OVERRIDE;
		}
		__raw_writel(deepsleep, DM355_DEEPSLEEP);
	}

	/* reset the controller */
	musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);

	/* start the on-chip PHY and its PLL */
	phy_on();

	msleep(5);

	/* NOTE:  irqs are in mixed mode, not bypass to pure-musb */
	pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
		revision, __raw_readl(USB_PHY_CTRL),
		musb_readb(tibase, DAVINCI_USB_CTRL_REG));

	musb->isr = davinci_interrupt;
	return 0;

fail:
	usb_nop_xceiv_unregister();
	return -ENODEV;
}

int musb_platform_exit(struct musb *musb)
{
	if (is_host_enabled(musb))
		del_timer_sync(&otg_workaround);

	/* force VBUS off */
	if (cpu_is_davinci_dm355()) {
		u32	deepsleep = __raw_readl(DM355_DEEPSLEEP);

		deepsleep &= ~DRVVBUS_FORCE;
		deepsleep |= DRVVBUS_OVERRIDE;
		__raw_writel(deepsleep, DM355_DEEPSLEEP);
	}

	davinci_source_power(musb, 0 /*off*/, 1);

	/* delay, to avoid problems with module reload */
	if (is_host_enabled(musb) && musb->xceiv->default_a) {
		int	maxdelay = 30;
		u8	devctl, warn = 0;

		/* if there's no peripheral connected, this can take a
		 * long time to fall, especially on EVM with huge C133.
		 */
		do {
			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
			if (!(devctl & MUSB_DEVCTL_VBUS))
				break;
			if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
				warn = devctl & MUSB_DEVCTL_VBUS;
				DBG(1, "VBUS %d\n",
					warn >> MUSB_DEVCTL_VBUS_SHIFT);
			}
			msleep(1000);
			maxdelay--;
		} while (maxdelay > 0);

		/* in OTG mode, another host might be connected */
		if (devctl & MUSB_DEVCTL_VBUS)
			DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
	}

	phy_off();

	clk_disable(musb->clock);

	usb_nop_xceiv_unregister();

	return 0;
}
Commit	Line	Data
550a7375 FB	1	/*
	2	* Copyright (C) 2005-2006 by Texas Instruments
	3	*
	4	* This file is part of the Inventra Controller Driver for Linux.
	5	*
	6	* The Inventra Controller Driver for Linux is free software; you
	7	* can redistribute it and/or modify it under the terms of the GNU
	8	* General Public License version 2 as published by the Free Software
	9	* Foundation.
	10	*
	11	* The Inventra Controller Driver for Linux is distributed in
	12	* the hope that it will be useful, but WITHOUT ANY WARRANTY;
	13	* without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	* License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with The Inventra Controller Driver for Linux ; if not,
	19	* write to the Free Software Foundation, Inc., 59 Temple Place,
	20	* Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*/
	23
	24	#include <linux/module.h>
	25	#include <linux/kernel.h>
	26	#include <linux/sched.h>
550a7375 FB	27	#include <linux/init.h>
	28	#include <linux/list.h>
	29	#include <linux/delay.h>
	30	#include <linux/clk.h>
	31	#include <linux/io.h>
c767c1c6	32	#include <linux/gpio.h>
550a7375	33
10b4eade DB	34	#include <mach/hardware.h>
	35	#include <mach/memory.h>
	36	#include <mach/gpio.h>
d163ef24	37	#include <mach/cputype.h>
10b4eade	38
550a7375 FB	39	#include <asm/mach-types.h>
	40
	41	#include "musb_core.h"
	42
	43	#ifdef CONFIG_MACH_DAVINCI_EVM
a2396a32	44	#define GPIO_nVBUS_DRV 160
550a7375 FB	45	#endif
	46
	47	#include "davinci.h"
	48	#include "cppi_dma.h"
	49
	50
a227fd7d DB	51	#define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR)
	52	#define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR)
	53
550a7375 FB	54	/* REVISIT (PM) we should be able to keep the PHY in low power mode most
	55	* of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
	56	* and, when in host mode, autosuspending idle root ports... PHYPLLON
	57	* (overriding SUSPENDM?) then likely needs to stay off.
	58	*/
	59
	60	static inline void phy_on(void)
	61	{
a227fd7d DB	62	u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
	63
	64	/* power everything up; start the on-chip PHY and its PLL */
	65	phy_ctrl &= ~(USBPHY_OSCPDWN \| USBPHY_OTGPDWN \| USBPHY_PHYPDWN);
	66	phy_ctrl \|= USBPHY_SESNDEN \| USBPHY_VBDTCTEN \| USBPHY_PHYPLLON;
	67	__raw_writel(phy_ctrl, USB_PHY_CTRL);
	68
	69	/* wait for PLL to lock before proceeding */
	70	while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
550a7375 FB	71	cpu_relax();
	72	}
	73
	74	static inline void phy_off(void)
	75	{
a227fd7d DB	76	u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
	77
	78	/* powerdown the on-chip PHY, its PLL, and the OTG block */
	79	phy_ctrl &= ~(USBPHY_SESNDEN \| USBPHY_VBDTCTEN \| USBPHY_PHYPLLON);
	80	phy_ctrl \|= USBPHY_OSCPDWN \| USBPHY_OTGPDWN \| USBPHY_PHYPDWN;
	81	__raw_writel(phy_ctrl, USB_PHY_CTRL);
550a7375 FB	82	}
	83
	84	static int dma_off = 1;
	85
	86	void musb_platform_enable(struct musb *musb)
	87	{
	88	u32 tmp, old, val;
	89
	90	/* workaround: setup irqs through both register sets */
	91	tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
	92	<< DAVINCI_USB_TXINT_SHIFT;
	93	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	94	old = tmp;
	95	tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
	96	<< DAVINCI_USB_RXINT_SHIFT;
	97	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	98	tmp \|= old;
	99
	100	val = ~MUSB_INTR_SOF;
	101	tmp \|= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
	102	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
	103
	104	if (is_dma_capable() && !dma_off)
	105	printk(KERN_WARNING "%s %s: dma not reactivated\n",
	106	__FILE__, __func__);
	107	else
	108	dma_off = 0;
	109
	110	/* force a DRVVBUS irq so we can start polling for ID change */
	111	if (is_otg_enabled(musb))
	112	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
	113	DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
	114	}
	115
	116	/*
	117	* Disable the HDRC and flush interrupts
	118	*/
	119	void musb_platform_disable(struct musb *musb)
	120	{
	121	/* because we don't set CTRLR.UINT, "important" to:
	122	* - not read/write INTRUSB/INTRUSBE
	123	* - (except during initial setup, as workaround)
	124	* - use INTSETR/INTCLRR instead
	125	*/
	126	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
	127	DAVINCI_USB_USBINT_MASK
	128	\| DAVINCI_USB_TXINT_MASK
	129	\| DAVINCI_USB_RXINT_MASK);
	130	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	131	musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
	132
	133	if (is_dma_capable() && !dma_off)
	134	WARNING("dma still active\n");
	135	}
	136
	137
550a7375 FB	138	#ifdef CONFIG_USB_MUSB_HDRC_HCD
	139	#define portstate(stmt) stmt
	140	#else
	141	#define portstate(stmt)
	142	#endif
	143
	144
a227fd7d DB	145	/*
	146	* VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
	147	* which doesn't wire DRVVBUS to the FET that switches it. Unclear
	148	* if that's a problem with the DM6446 chip or just with that board.
	149	*
	150	* In either case, the DM355 EVM automates DRVVBUS the normal way,
	151	* when J10 is out, and TI documents it as handling OTG.
	152	*/
550a7375 FB	153
550a7375 FB	154	#ifdef CONFIG_MACH_DAVINCI_EVM
550a7375	155
a227fd7d DB	156	static int vbus_state = -1;
a227fd7d DB	157
550a7375 FB	158	/* I2C operations are always synchronous, and require a task context.
	159	* With unloaded systems, using the shared workqueue seems to suffice
	160	* to satisfy the 100msec A_WAIT_VRISE timeout...
	161	*/
	162	static void evm_deferred_drvvbus(struct work_struct *ignored)
	163	{
c767c1c6	164	gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
550a7375 FB	165	vbus_state = !vbus_state;
550a7375 FB	166	}
550a7375	167
550a7375 FB	168	#endif /* EVM */
	169
	170	static void davinci_source_power(struct musb *musb, int is_on, int immediate)
	171	{
a227fd7d	172	#ifdef CONFIG_MACH_DAVINCI_EVM
550a7375 FB	173	if (is_on)
	174	is_on = 1;
	175
	176	if (vbus_state == is_on)
	177	return;
	178	vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
	179
550a7375	180	if (machine_is_davinci_evm()) {
a227fd7d DB	181	static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
a227fd7d DB	182
550a7375	183	if (immediate)
c767c1c6	184	gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
550a7375 FB	185	else
550a7375 FB	186	schedule_work(&evm_vbus_work);
550a7375	187	}
550a7375 FB	188	if (immediate)
550a7375 FB	189	vbus_state = is_on;
a227fd7d	190	#endif
550a7375 FB	191	}
	192
	193	static void davinci_set_vbus(struct musb *musb, int is_on)
	194	{
	195	WARN_ON(is_on && is_peripheral_active(musb));
	196	davinci_source_power(musb, is_on, 0);
	197	}
	198
	199
	200	#define POLL_SECONDS 2
	201
	202	static struct timer_list otg_workaround;
	203
	204	static void otg_timer(unsigned long _musb)
	205	{
	206	struct musb musb = (void )_musb;
	207	void __iomem *mregs = musb->mregs;
	208	u8 devctl;
	209	unsigned long flags;
	210
	211	/* We poll because DaVinci's won't expose several OTG-critical
	212	* status change events (from the transceiver) otherwise.
	213	*/
	214	devctl = musb_readb(mregs, MUSB_DEVCTL);
	215	DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
	216
	217	spin_lock_irqsave(&musb->lock, flags);
84e250ff	218	switch (musb->xceiv->state) {
550a7375 FB	219	case OTG_STATE_A_WAIT_VFALL:
	220	/* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
	221	* seems to mis-handle session "start" otherwise (or in our
	222	* case "recover"), in routine "VBUS was valid by the time
	223	* VBUSERR got reported during enumeration" cases.
	224	*/
	225	if (devctl & MUSB_DEVCTL_VBUS) {
	226	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	227	break;
	228	}
84e250ff	229	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
550a7375 FB	230	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
	231	MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
	232	break;
	233	case OTG_STATE_B_IDLE:
	234	if (!is_peripheral_enabled(musb))
	235	break;
	236
	237	/* There's no ID-changed IRQ, so we have no good way to tell
	238	* when to switch to the A-Default state machine (by setting
	239	* the DEVCTL.SESSION flag).
	240	*
	241	* Workaround: whenever we're in B_IDLE, try setting the
	242	* session flag every few seconds. If it works, ID was
	243	* grounded and we're now in the A-Default state machine.
	244	*
	245	* NOTE setting the session flag is _supposed_ to trigger
	246	* SRP, but clearly it doesn't.
	247	*/
	248	musb_writeb(mregs, MUSB_DEVCTL,
	249	devctl \| MUSB_DEVCTL_SESSION);
	250	devctl = musb_readb(mregs, MUSB_DEVCTL);
	251	if (devctl & MUSB_DEVCTL_BDEVICE)
	252	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	253	else
84e250ff	254	musb->xceiv->state = OTG_STATE_A_IDLE;
550a7375 FB	255	break;
	256	default:
	257	break;
	258	}
	259	spin_unlock_irqrestore(&musb->lock, flags);
	260	}
	261
	262	static irqreturn_t davinci_interrupt(int irq, void *__hci)
	263	{
	264	unsigned long flags;
	265	irqreturn_t retval = IRQ_NONE;
	266	struct musb *musb = __hci;
	267	void __iomem *tibase = musb->ctrl_base;
91e9c4fe	268	struct cppi *cppi;
550a7375 FB	269	u32 tmp;
	270
	271	spin_lock_irqsave(&musb->lock, flags);
	272
	273	/* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
	274	* the Mentor registers (except for setup), use the TI ones and EOI.
	275	*
dfff0615	276	* Docs describe irq "vector" registers associated with the CPPI and
550a7375 FB	277	* USB EOI registers. These hold a bitmask corresponding to the
	278	* current IRQ, not an irq handler address. Would using those bits
	279	* resolve some of the races observed in this dispatch code??
	280	*/
	281
	282	/* CPPI interrupts share the same IRQ line, but have their own
	283	* mask, state, "vector", and EOI registers.
	284	*/
91e9c4fe SS	285	cppi = container_of(musb->dma_controller, struct cppi, controller);
	286	if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
	287	retval = cppi_interrupt(irq, __hci);
550a7375 FB	288
	289	/* ack and handle non-CPPI interrupts */
	290	tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
	291	musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
	292	DBG(4, "IRQ %08x\n", tmp);
	293
	294	musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
	295	>> DAVINCI_USB_RXINT_SHIFT;
	296	musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
	297	>> DAVINCI_USB_TXINT_SHIFT;
	298	musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
	299	>> DAVINCI_USB_USBINT_SHIFT;
	300
	301	/* DRVVBUS irqs are the only proxy we have (a very poor one!) for
	302	* DaVinci's missing ID change IRQ. We need an ID change IRQ to
	303	* switch appropriately between halves of the OTG state machine.
	304	* Managing DEVCTL.SESSION per Mentor docs requires we know its
	305	* value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
	306	* Also, DRVVBUS pulses for SRP (but not at 5V) ...
	307	*/
	308	if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
	309	int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
	310	void __iomem *mregs = musb->mregs;
	311	u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
	312	int err = musb->int_usb & MUSB_INTR_VBUSERROR;
	313
	314	err = is_host_enabled(musb)
	315	&& (musb->int_usb & MUSB_INTR_VBUSERROR);
	316	if (err) {
	317	/* The Mentor core doesn't debounce VBUS as needed
	318	* to cope with device connect current spikes. This
	319	* means it's not uncommon for bus-powered devices
	320	* to get VBUS errors during enumeration.
	321	*
	322	* This is a workaround, but newer RTL from Mentor
	323	* seems to allow a better one: "re"starting sessions
	324	* without waiting (on EVM, a long time) for VBUS
	325	* to stop registering in devctl.
	326	*/
	327	musb->int_usb &= ~MUSB_INTR_VBUSERROR;
84e250ff	328	musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
550a7375 FB	329	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	330	WARNING("VBUS error workaround (delay coming)\n");
	331	} else if (is_host_enabled(musb) && drvvbus) {
550a7375	332	MUSB_HST_MODE(musb);
84e250ff DB	333	musb->xceiv->default_a = 1;
84e250ff DB	334	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
550a7375 FB	335	portstate(musb->port1_status \|= USB_PORT_STAT_POWER);
	336	del_timer(&otg_workaround);
	337	} else {
	338	musb->is_active = 0;
	339	MUSB_DEV_MODE(musb);
84e250ff DB	340	musb->xceiv->default_a = 0;
84e250ff DB	341	musb->xceiv->state = OTG_STATE_B_IDLE;
550a7375 FB	342	portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
	343	}
	344
89368d3d DB	345	/* NOTE: this must complete poweron within 100 msec
	346	* (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
	347	*/
550a7375 FB	348	davinci_source_power(musb, drvvbus, 0);
	349	DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
	350	drvvbus ? "on" : "off",
	351	otg_state_string(musb),
	352	err ? " ERROR" : "",
	353	devctl);
	354	retval = IRQ_HANDLED;
	355	}
	356
	357	if (musb->int_tx \|\| musb->int_rx \|\| musb->int_usb)
	358	retval \|= musb_interrupt(musb);
	359
	360	/* irq stays asserted until EOI is written */
	361	musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
	362
	363	/* poll for ID change */
	364	if (is_otg_enabled(musb)
84e250ff	365	&& musb->xceiv->state == OTG_STATE_B_IDLE)
550a7375 FB	366	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	367
	368	spin_unlock_irqrestore(&musb->lock, flags);
	369
a5073b52	370	return retval;
550a7375 FB	371	}
550a7375 FB	372
96a274d1 DB	373	int musb_platform_set_mode(struct musb *musb, u8 mode)
	374	{
	375	/* EVM can't do this (right?) */
	376	return -EIO;
	377	}
	378
550a7375 FB	379	int __init musb_platform_init(struct musb *musb)
	380	{
	381	void __iomem *tibase = musb->ctrl_base;
	382	u32 revision;
	383
84e250ff DB	384	usb_nop_xceiv_register();
	385	musb->xceiv = otg_get_transceiver();
	386	if (!musb->xceiv)
	387	return -ENODEV;
	388
550a7375	389	musb->mregs += DAVINCI_BASE_OFFSET;
550a7375	390
34f32c97	391	clk_enable(musb->clock);
550a7375 FB	392
	393	/* returns zero if e.g. not clocked */
	394	revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
	395	if (revision == 0)
84e250ff	396	goto fail;
550a7375 FB	397
	398	if (is_host_enabled(musb))
	399	setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
	400
	401	musb->board_set_vbus = davinci_set_vbus;
	402	davinci_source_power(musb, 0, 1);
	403
a227fd7d DB	404	/* dm355 EVM swaps D+/D- for signal integrity, and
	405	* is clocked from the main 24 MHz crystal.
	406	*/
	407	if (machine_is_davinci_dm355_evm()) {
	408	u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
	409
	410	phy_ctrl &= ~(3 << 9);
	411	phy_ctrl \|= USBPHY_DATAPOL;
	412	__raw_writel(phy_ctrl, USB_PHY_CTRL);
	413	}
	414
d163ef24 DB	415	/* On dm355, the default-A state machine needs DRVVBUS control.
	416	* If we won't be a host, there's no need to turn it on.
	417	*/
	418	if (cpu_is_davinci_dm355()) {
	419	u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
	420
	421	if (is_host_enabled(musb)) {
	422	deepsleep &= ~DRVVBUS_OVERRIDE;
	423	} else {
	424	deepsleep &= ~DRVVBUS_FORCE;
	425	deepsleep \|= DRVVBUS_OVERRIDE;
	426	}
	427	__raw_writel(deepsleep, DM355_DEEPSLEEP);
	428	}
	429
550a7375 FB	430	/* reset the controller */
	431	musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
	432
	433	/* start the on-chip PHY and its PLL */
	434	phy_on();
	435
	436	msleep(5);
	437
	438	/* NOTE: irqs are in mixed mode, not bypass to pure-musb */
	439	pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
a227fd7d	440	revision, __raw_readl(USB_PHY_CTRL),
550a7375 FB	441	musb_readb(tibase, DAVINCI_USB_CTRL_REG));
	442
	443	musb->isr = davinci_interrupt;
	444	return 0;
84e250ff DB	445
	446	fail:
	447	usb_nop_xceiv_unregister();
	448	return -ENODEV;
550a7375 FB	449	}
	450
	451	int musb_platform_exit(struct musb *musb)
	452	{
	453	if (is_host_enabled(musb))
	454	del_timer_sync(&otg_workaround);
	455
d163ef24 DB	456	/* force VBUS off */
	457	if (cpu_is_davinci_dm355()) {
	458	u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
	459
	460	deepsleep &= ~DRVVBUS_FORCE;
	461	deepsleep \|= DRVVBUS_OVERRIDE;
	462	__raw_writel(deepsleep, DM355_DEEPSLEEP);
	463	}
	464
550a7375 FB	465	davinci_source_power(musb, 0 /off/, 1);
	466
	467	/* delay, to avoid problems with module reload */
84e250ff	468	if (is_host_enabled(musb) && musb->xceiv->default_a) {
550a7375 FB	469	int maxdelay = 30;
	470	u8 devctl, warn = 0;
	471
	472	/* if there's no peripheral connected, this can take a
	473	* long time to fall, especially on EVM with huge C133.
	474	*/
	475	do {
	476	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	477	if (!(devctl & MUSB_DEVCTL_VBUS))
	478	break;
	479	if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
	480	warn = devctl & MUSB_DEVCTL_VBUS;
	481	DBG(1, "VBUS %d\n",
	482	warn >> MUSB_DEVCTL_VBUS_SHIFT);
	483	}
	484	msleep(1000);
	485	maxdelay--;
	486	} while (maxdelay > 0);
	487
	488	/* in OTG mode, another host might be connected */
	489	if (devctl & MUSB_DEVCTL_VBUS)
	490	DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
	491	}
	492
	493	phy_off();
34f32c97 DB	494
	495	clk_disable(musb->clock);
	496
84e250ff DB	497	usb_nop_xceiv_unregister();
84e250ff DB	498
550a7375 FB	499	return 0;
550a7375 FB	500	}