Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * Copyright (C) 2005-2006 by Texas Instruments | |
3 | * | |
4 | * This file is part of the Inventra Controller Driver for Linux. | |
5 | * | |
6 | * The Inventra Controller Driver for Linux is free software; you | |
7 | * can redistribute it and/or modify it under the terms of the GNU | |
8 | * General Public License version 2 as published by the Free Software | |
9 | * Foundation. | |
10 | * | |
11 | * The Inventra Controller Driver for Linux is distributed in | |
12 | * the hope that it will be useful, but WITHOUT ANY WARRANTY; | |
13 | * without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | * License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with The Inventra Controller Driver for Linux ; if not, | |
19 | * write to the Free Software Foundation, Inc., 59 Temple Place, | |
20 | * Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
550a7375 FB |
27 | #include <linux/init.h> |
28 | #include <linux/list.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/io.h> | |
c767c1c6 | 32 | #include <linux/gpio.h> |
73b089b0 FB |
33 | #include <linux/platform_device.h> |
34 | #include <linux/dma-mapping.h> | |
550a7375 | 35 | |
d163ef24 | 36 | #include <mach/cputype.h> |
10b4eade | 37 | |
550a7375 FB |
38 | #include <asm/mach-types.h> |
39 | ||
40 | #include "musb_core.h" | |
41 | ||
42 | #ifdef CONFIG_MACH_DAVINCI_EVM | |
a2396a32 | 43 | #define GPIO_nVBUS_DRV 160 |
550a7375 FB |
44 | #endif |
45 | ||
46 | #include "davinci.h" | |
47 | #include "cppi_dma.h" | |
48 | ||
49 | ||
a227fd7d DB |
50 | #define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR) |
51 | #define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR) | |
52 | ||
e110de4d FB |
53 | struct davinci_glue { |
54 | struct device *dev; | |
55 | struct platform_device *musb; | |
03491761 | 56 | struct clk *clk; |
e110de4d FB |
57 | }; |
58 | ||
550a7375 FB |
59 | /* REVISIT (PM) we should be able to keep the PHY in low power mode most |
60 | * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0 | |
61 | * and, when in host mode, autosuspending idle root ports... PHYPLLON | |
62 | * (overriding SUSPENDM?) then likely needs to stay off. | |
63 | */ | |
64 | ||
65 | static inline void phy_on(void) | |
66 | { | |
a227fd7d DB |
67 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); |
68 | ||
69 | /* power everything up; start the on-chip PHY and its PLL */ | |
70 | phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN); | |
71 | phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON; | |
72 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
73 | ||
74 | /* wait for PLL to lock before proceeding */ | |
75 | while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0) | |
550a7375 FB |
76 | cpu_relax(); |
77 | } | |
78 | ||
79 | static inline void phy_off(void) | |
80 | { | |
a227fd7d DB |
81 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); |
82 | ||
83 | /* powerdown the on-chip PHY, its PLL, and the OTG block */ | |
84 | phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON); | |
85 | phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN; | |
86 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
550a7375 FB |
87 | } |
88 | ||
89 | static int dma_off = 1; | |
90 | ||
743411b3 | 91 | static void davinci_musb_enable(struct musb *musb) |
550a7375 FB |
92 | { |
93 | u32 tmp, old, val; | |
94 | ||
95 | /* workaround: setup irqs through both register sets */ | |
96 | tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK) | |
97 | << DAVINCI_USB_TXINT_SHIFT; | |
98 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
99 | old = tmp; | |
100 | tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK)) | |
101 | << DAVINCI_USB_RXINT_SHIFT; | |
102 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
103 | tmp |= old; | |
104 | ||
105 | val = ~MUSB_INTR_SOF; | |
106 | tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT); | |
107 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
108 | ||
109 | if (is_dma_capable() && !dma_off) | |
110 | printk(KERN_WARNING "%s %s: dma not reactivated\n", | |
111 | __FILE__, __func__); | |
112 | else | |
113 | dma_off = 0; | |
114 | ||
115 | /* force a DRVVBUS irq so we can start polling for ID change */ | |
116 | if (is_otg_enabled(musb)) | |
117 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, | |
118 | DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT); | |
119 | } | |
120 | ||
121 | /* | |
122 | * Disable the HDRC and flush interrupts | |
123 | */ | |
743411b3 | 124 | static void davinci_musb_disable(struct musb *musb) |
550a7375 FB |
125 | { |
126 | /* because we don't set CTRLR.UINT, "important" to: | |
127 | * - not read/write INTRUSB/INTRUSBE | |
128 | * - (except during initial setup, as workaround) | |
129 | * - use INTSETR/INTCLRR instead | |
130 | */ | |
131 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG, | |
132 | DAVINCI_USB_USBINT_MASK | |
133 | | DAVINCI_USB_TXINT_MASK | |
134 | | DAVINCI_USB_RXINT_MASK); | |
135 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
136 | musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0); | |
137 | ||
138 | if (is_dma_capable() && !dma_off) | |
139 | WARNING("dma still active\n"); | |
140 | } | |
141 | ||
142 | ||
550a7375 | 143 | #define portstate(stmt) stmt |
550a7375 | 144 | |
a227fd7d DB |
145 | /* |
146 | * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM, | |
147 | * which doesn't wire DRVVBUS to the FET that switches it. Unclear | |
148 | * if that's a problem with the DM6446 chip or just with that board. | |
149 | * | |
150 | * In either case, the DM355 EVM automates DRVVBUS the normal way, | |
151 | * when J10 is out, and TI documents it as handling OTG. | |
152 | */ | |
550a7375 FB |
153 | |
154 | #ifdef CONFIG_MACH_DAVINCI_EVM | |
550a7375 | 155 | |
a227fd7d DB |
156 | static int vbus_state = -1; |
157 | ||
550a7375 FB |
158 | /* I2C operations are always synchronous, and require a task context. |
159 | * With unloaded systems, using the shared workqueue seems to suffice | |
160 | * to satisfy the 100msec A_WAIT_VRISE timeout... | |
161 | */ | |
162 | static void evm_deferred_drvvbus(struct work_struct *ignored) | |
163 | { | |
c767c1c6 | 164 | gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state); |
550a7375 FB |
165 | vbus_state = !vbus_state; |
166 | } | |
550a7375 | 167 | |
550a7375 FB |
168 | #endif /* EVM */ |
169 | ||
743411b3 | 170 | static void davinci_musb_source_power(struct musb *musb, int is_on, int immediate) |
550a7375 | 171 | { |
a227fd7d | 172 | #ifdef CONFIG_MACH_DAVINCI_EVM |
550a7375 FB |
173 | if (is_on) |
174 | is_on = 1; | |
175 | ||
176 | if (vbus_state == is_on) | |
177 | return; | |
178 | vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */ | |
179 | ||
550a7375 | 180 | if (machine_is_davinci_evm()) { |
a227fd7d DB |
181 | static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus); |
182 | ||
550a7375 | 183 | if (immediate) |
c767c1c6 | 184 | gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state); |
550a7375 FB |
185 | else |
186 | schedule_work(&evm_vbus_work); | |
550a7375 | 187 | } |
550a7375 FB |
188 | if (immediate) |
189 | vbus_state = is_on; | |
a227fd7d | 190 | #endif |
550a7375 FB |
191 | } |
192 | ||
743411b3 | 193 | static void davinci_musb_set_vbus(struct musb *musb, int is_on) |
550a7375 FB |
194 | { |
195 | WARN_ON(is_on && is_peripheral_active(musb)); | |
743411b3 | 196 | davinci_musb_source_power(musb, is_on, 0); |
550a7375 FB |
197 | } |
198 | ||
199 | ||
200 | #define POLL_SECONDS 2 | |
201 | ||
202 | static struct timer_list otg_workaround; | |
203 | ||
204 | static void otg_timer(unsigned long _musb) | |
205 | { | |
206 | struct musb *musb = (void *)_musb; | |
207 | void __iomem *mregs = musb->mregs; | |
208 | u8 devctl; | |
209 | unsigned long flags; | |
210 | ||
211 | /* We poll because DaVinci's won't expose several OTG-critical | |
212 | * status change events (from the transceiver) otherwise. | |
213 | */ | |
214 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
5c8a86e1 | 215 | dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl, |
3df00453 | 216 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
217 | |
218 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 219 | switch (musb->xceiv->state) { |
550a7375 FB |
220 | case OTG_STATE_A_WAIT_VFALL: |
221 | /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL | |
222 | * seems to mis-handle session "start" otherwise (or in our | |
223 | * case "recover"), in routine "VBUS was valid by the time | |
224 | * VBUSERR got reported during enumeration" cases. | |
225 | */ | |
226 | if (devctl & MUSB_DEVCTL_VBUS) { | |
227 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
228 | break; | |
229 | } | |
84e250ff | 230 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; |
550a7375 FB |
231 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, |
232 | MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT); | |
233 | break; | |
234 | case OTG_STATE_B_IDLE: | |
235 | if (!is_peripheral_enabled(musb)) | |
236 | break; | |
237 | ||
238 | /* There's no ID-changed IRQ, so we have no good way to tell | |
239 | * when to switch to the A-Default state machine (by setting | |
240 | * the DEVCTL.SESSION flag). | |
241 | * | |
242 | * Workaround: whenever we're in B_IDLE, try setting the | |
243 | * session flag every few seconds. If it works, ID was | |
244 | * grounded and we're now in the A-Default state machine. | |
245 | * | |
246 | * NOTE setting the session flag is _supposed_ to trigger | |
247 | * SRP, but clearly it doesn't. | |
248 | */ | |
249 | musb_writeb(mregs, MUSB_DEVCTL, | |
250 | devctl | MUSB_DEVCTL_SESSION); | |
251 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
252 | if (devctl & MUSB_DEVCTL_BDEVICE) | |
253 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
254 | else | |
84e250ff | 255 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 FB |
256 | break; |
257 | default: | |
258 | break; | |
259 | } | |
260 | spin_unlock_irqrestore(&musb->lock, flags); | |
261 | } | |
262 | ||
743411b3 | 263 | static irqreturn_t davinci_musb_interrupt(int irq, void *__hci) |
550a7375 FB |
264 | { |
265 | unsigned long flags; | |
266 | irqreturn_t retval = IRQ_NONE; | |
267 | struct musb *musb = __hci; | |
d445b6da | 268 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 | 269 | void __iomem *tibase = musb->ctrl_base; |
91e9c4fe | 270 | struct cppi *cppi; |
550a7375 FB |
271 | u32 tmp; |
272 | ||
273 | spin_lock_irqsave(&musb->lock, flags); | |
274 | ||
275 | /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through | |
276 | * the Mentor registers (except for setup), use the TI ones and EOI. | |
277 | * | |
dfff0615 | 278 | * Docs describe irq "vector" registers associated with the CPPI and |
550a7375 FB |
279 | * USB EOI registers. These hold a bitmask corresponding to the |
280 | * current IRQ, not an irq handler address. Would using those bits | |
281 | * resolve some of the races observed in this dispatch code?? | |
282 | */ | |
283 | ||
284 | /* CPPI interrupts share the same IRQ line, but have their own | |
285 | * mask, state, "vector", and EOI registers. | |
286 | */ | |
91e9c4fe SS |
287 | cppi = container_of(musb->dma_controller, struct cppi, controller); |
288 | if (is_cppi_enabled() && musb->dma_controller && !cppi->irq) | |
289 | retval = cppi_interrupt(irq, __hci); | |
550a7375 FB |
290 | |
291 | /* ack and handle non-CPPI interrupts */ | |
292 | tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG); | |
293 | musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp); | |
5c8a86e1 | 294 | dev_dbg(musb->controller, "IRQ %08x\n", tmp); |
550a7375 FB |
295 | |
296 | musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK) | |
297 | >> DAVINCI_USB_RXINT_SHIFT; | |
298 | musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK) | |
299 | >> DAVINCI_USB_TXINT_SHIFT; | |
300 | musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK) | |
301 | >> DAVINCI_USB_USBINT_SHIFT; | |
302 | ||
303 | /* DRVVBUS irqs are the only proxy we have (a very poor one!) for | |
304 | * DaVinci's missing ID change IRQ. We need an ID change IRQ to | |
305 | * switch appropriately between halves of the OTG state machine. | |
306 | * Managing DEVCTL.SESSION per Mentor docs requires we know its | |
307 | * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. | |
308 | * Also, DRVVBUS pulses for SRP (but not at 5V) ... | |
309 | */ | |
310 | if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) { | |
311 | int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG); | |
312 | void __iomem *mregs = musb->mregs; | |
313 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
314 | int err = musb->int_usb & MUSB_INTR_VBUSERROR; | |
315 | ||
316 | err = is_host_enabled(musb) | |
317 | && (musb->int_usb & MUSB_INTR_VBUSERROR); | |
318 | if (err) { | |
319 | /* The Mentor core doesn't debounce VBUS as needed | |
320 | * to cope with device connect current spikes. This | |
321 | * means it's not uncommon for bus-powered devices | |
322 | * to get VBUS errors during enumeration. | |
323 | * | |
324 | * This is a workaround, but newer RTL from Mentor | |
325 | * seems to allow a better one: "re"starting sessions | |
326 | * without waiting (on EVM, a **long** time) for VBUS | |
327 | * to stop registering in devctl. | |
328 | */ | |
329 | musb->int_usb &= ~MUSB_INTR_VBUSERROR; | |
84e250ff | 330 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
331 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
332 | WARNING("VBUS error workaround (delay coming)\n"); | |
333 | } else if (is_host_enabled(musb) && drvvbus) { | |
550a7375 | 334 | MUSB_HST_MODE(musb); |
d445b6da | 335 | otg->default_a = 1; |
84e250ff | 336 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; |
550a7375 FB |
337 | portstate(musb->port1_status |= USB_PORT_STAT_POWER); |
338 | del_timer(&otg_workaround); | |
339 | } else { | |
340 | musb->is_active = 0; | |
341 | MUSB_DEV_MODE(musb); | |
d445b6da | 342 | otg->default_a = 0; |
84e250ff | 343 | musb->xceiv->state = OTG_STATE_B_IDLE; |
550a7375 FB |
344 | portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); |
345 | } | |
346 | ||
89368d3d DB |
347 | /* NOTE: this must complete poweron within 100 msec |
348 | * (OTG_TIME_A_WAIT_VRISE) but we don't check for that. | |
349 | */ | |
743411b3 | 350 | davinci_musb_source_power(musb, drvvbus, 0); |
5c8a86e1 | 351 | dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", |
550a7375 | 352 | drvvbus ? "on" : "off", |
3df00453 | 353 | otg_state_string(musb->xceiv->state), |
550a7375 FB |
354 | err ? " ERROR" : "", |
355 | devctl); | |
356 | retval = IRQ_HANDLED; | |
357 | } | |
358 | ||
359 | if (musb->int_tx || musb->int_rx || musb->int_usb) | |
360 | retval |= musb_interrupt(musb); | |
361 | ||
362 | /* irq stays asserted until EOI is written */ | |
363 | musb_writel(tibase, DAVINCI_USB_EOI_REG, 0); | |
364 | ||
365 | /* poll for ID change */ | |
366 | if (is_otg_enabled(musb) | |
84e250ff | 367 | && musb->xceiv->state == OTG_STATE_B_IDLE) |
550a7375 FB |
368 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
369 | ||
370 | spin_unlock_irqrestore(&musb->lock, flags); | |
371 | ||
a5073b52 | 372 | return retval; |
550a7375 FB |
373 | } |
374 | ||
743411b3 | 375 | static int davinci_musb_set_mode(struct musb *musb, u8 mode) |
96a274d1 DB |
376 | { |
377 | /* EVM can't do this (right?) */ | |
378 | return -EIO; | |
379 | } | |
380 | ||
743411b3 | 381 | static int davinci_musb_init(struct musb *musb) |
550a7375 FB |
382 | { |
383 | void __iomem *tibase = musb->ctrl_base; | |
384 | u32 revision; | |
385 | ||
84e250ff | 386 | usb_nop_xceiv_register(); |
b96d3b08 | 387 | musb->xceiv = usb_get_transceiver(); |
84e250ff DB |
388 | if (!musb->xceiv) |
389 | return -ENODEV; | |
390 | ||
550a7375 | 391 | musb->mregs += DAVINCI_BASE_OFFSET; |
550a7375 | 392 | |
550a7375 FB |
393 | /* returns zero if e.g. not clocked */ |
394 | revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG); | |
395 | if (revision == 0) | |
84e250ff | 396 | goto fail; |
550a7375 FB |
397 | |
398 | if (is_host_enabled(musb)) | |
399 | setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); | |
400 | ||
743411b3 | 401 | davinci_musb_source_power(musb, 0, 1); |
550a7375 | 402 | |
a227fd7d DB |
403 | /* dm355 EVM swaps D+/D- for signal integrity, and |
404 | * is clocked from the main 24 MHz crystal. | |
405 | */ | |
406 | if (machine_is_davinci_dm355_evm()) { | |
407 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); | |
408 | ||
409 | phy_ctrl &= ~(3 << 9); | |
410 | phy_ctrl |= USBPHY_DATAPOL; | |
411 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
412 | } | |
413 | ||
d163ef24 DB |
414 | /* On dm355, the default-A state machine needs DRVVBUS control. |
415 | * If we won't be a host, there's no need to turn it on. | |
416 | */ | |
417 | if (cpu_is_davinci_dm355()) { | |
418 | u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); | |
419 | ||
420 | if (is_host_enabled(musb)) { | |
421 | deepsleep &= ~DRVVBUS_OVERRIDE; | |
422 | } else { | |
423 | deepsleep &= ~DRVVBUS_FORCE; | |
424 | deepsleep |= DRVVBUS_OVERRIDE; | |
425 | } | |
426 | __raw_writel(deepsleep, DM355_DEEPSLEEP); | |
427 | } | |
428 | ||
550a7375 FB |
429 | /* reset the controller */ |
430 | musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1); | |
431 | ||
432 | /* start the on-chip PHY and its PLL */ | |
433 | phy_on(); | |
434 | ||
435 | msleep(5); | |
436 | ||
437 | /* NOTE: irqs are in mixed mode, not bypass to pure-musb */ | |
438 | pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n", | |
a227fd7d | 439 | revision, __raw_readl(USB_PHY_CTRL), |
550a7375 FB |
440 | musb_readb(tibase, DAVINCI_USB_CTRL_REG)); |
441 | ||
743411b3 | 442 | musb->isr = davinci_musb_interrupt; |
550a7375 | 443 | return 0; |
84e250ff DB |
444 | |
445 | fail: | |
b96d3b08 | 446 | usb_put_transceiver(musb->xceiv); |
84e250ff DB |
447 | usb_nop_xceiv_unregister(); |
448 | return -ENODEV; | |
550a7375 FB |
449 | } |
450 | ||
743411b3 | 451 | static int davinci_musb_exit(struct musb *musb) |
550a7375 FB |
452 | { |
453 | if (is_host_enabled(musb)) | |
454 | del_timer_sync(&otg_workaround); | |
455 | ||
d163ef24 DB |
456 | /* force VBUS off */ |
457 | if (cpu_is_davinci_dm355()) { | |
458 | u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); | |
459 | ||
460 | deepsleep &= ~DRVVBUS_FORCE; | |
461 | deepsleep |= DRVVBUS_OVERRIDE; | |
462 | __raw_writel(deepsleep, DM355_DEEPSLEEP); | |
463 | } | |
464 | ||
743411b3 | 465 | davinci_musb_source_power(musb, 0 /*off*/, 1); |
550a7375 FB |
466 | |
467 | /* delay, to avoid problems with module reload */ | |
d445b6da | 468 | if (is_host_enabled(musb) && musb->xceiv->otg->default_a) { |
550a7375 FB |
469 | int maxdelay = 30; |
470 | u8 devctl, warn = 0; | |
471 | ||
472 | /* if there's no peripheral connected, this can take a | |
473 | * long time to fall, especially on EVM with huge C133. | |
474 | */ | |
475 | do { | |
476 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
477 | if (!(devctl & MUSB_DEVCTL_VBUS)) | |
478 | break; | |
479 | if ((devctl & MUSB_DEVCTL_VBUS) != warn) { | |
480 | warn = devctl & MUSB_DEVCTL_VBUS; | |
5c8a86e1 | 481 | dev_dbg(musb->controller, "VBUS %d\n", |
550a7375 FB |
482 | warn >> MUSB_DEVCTL_VBUS_SHIFT); |
483 | } | |
484 | msleep(1000); | |
485 | maxdelay--; | |
486 | } while (maxdelay > 0); | |
487 | ||
488 | /* in OTG mode, another host might be connected */ | |
489 | if (devctl & MUSB_DEVCTL_VBUS) | |
5c8a86e1 | 490 | dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl); |
550a7375 FB |
491 | } |
492 | ||
493 | phy_off(); | |
34f32c97 | 494 | |
b96d3b08 | 495 | usb_put_transceiver(musb->xceiv); |
84e250ff DB |
496 | usb_nop_xceiv_unregister(); |
497 | ||
550a7375 FB |
498 | return 0; |
499 | } | |
743411b3 | 500 | |
f7ec9437 | 501 | static const struct musb_platform_ops davinci_ops = { |
743411b3 FB |
502 | .init = davinci_musb_init, |
503 | .exit = davinci_musb_exit, | |
504 | ||
505 | .enable = davinci_musb_enable, | |
506 | .disable = davinci_musb_disable, | |
507 | ||
508 | .set_mode = davinci_musb_set_mode, | |
509 | ||
510 | .set_vbus = davinci_musb_set_vbus, | |
511 | }; | |
73b089b0 FB |
512 | |
513 | static u64 davinci_dmamask = DMA_BIT_MASK(32); | |
514 | ||
e9e8c85e | 515 | static int __devinit davinci_probe(struct platform_device *pdev) |
73b089b0 FB |
516 | { |
517 | struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; | |
518 | struct platform_device *musb; | |
e110de4d | 519 | struct davinci_glue *glue; |
03491761 | 520 | struct clk *clk; |
73b089b0 FB |
521 | |
522 | int ret = -ENOMEM; | |
523 | ||
e110de4d FB |
524 | glue = kzalloc(sizeof(*glue), GFP_KERNEL); |
525 | if (!glue) { | |
526 | dev_err(&pdev->dev, "failed to allocate glue context\n"); | |
527 | goto err0; | |
528 | } | |
529 | ||
73b089b0 FB |
530 | musb = platform_device_alloc("musb-hdrc", -1); |
531 | if (!musb) { | |
532 | dev_err(&pdev->dev, "failed to allocate musb device\n"); | |
e110de4d | 533 | goto err1; |
73b089b0 FB |
534 | } |
535 | ||
03491761 FB |
536 | clk = clk_get(&pdev->dev, "usb"); |
537 | if (IS_ERR(clk)) { | |
538 | dev_err(&pdev->dev, "failed to get clock\n"); | |
539 | ret = PTR_ERR(clk); | |
540 | goto err2; | |
541 | } | |
542 | ||
543 | ret = clk_enable(clk); | |
544 | if (ret) { | |
545 | dev_err(&pdev->dev, "failed to enable clock\n"); | |
546 | goto err3; | |
547 | } | |
548 | ||
73b089b0 FB |
549 | musb->dev.parent = &pdev->dev; |
550 | musb->dev.dma_mask = &davinci_dmamask; | |
551 | musb->dev.coherent_dma_mask = davinci_dmamask; | |
552 | ||
e110de4d FB |
553 | glue->dev = &pdev->dev; |
554 | glue->musb = musb; | |
03491761 | 555 | glue->clk = clk; |
e110de4d | 556 | |
f7ec9437 FB |
557 | pdata->platform_ops = &davinci_ops; |
558 | ||
e110de4d | 559 | platform_set_drvdata(pdev, glue); |
73b089b0 FB |
560 | |
561 | ret = platform_device_add_resources(musb, pdev->resource, | |
562 | pdev->num_resources); | |
563 | if (ret) { | |
564 | dev_err(&pdev->dev, "failed to add resources\n"); | |
03491761 | 565 | goto err4; |
73b089b0 FB |
566 | } |
567 | ||
568 | ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); | |
569 | if (ret) { | |
570 | dev_err(&pdev->dev, "failed to add platform_data\n"); | |
03491761 | 571 | goto err4; |
73b089b0 FB |
572 | } |
573 | ||
574 | ret = platform_device_add(musb); | |
575 | if (ret) { | |
576 | dev_err(&pdev->dev, "failed to register musb device\n"); | |
03491761 | 577 | goto err4; |
73b089b0 FB |
578 | } |
579 | ||
580 | return 0; | |
581 | ||
03491761 FB |
582 | err4: |
583 | clk_disable(clk); | |
584 | ||
585 | err3: | |
586 | clk_put(clk); | |
587 | ||
e110de4d | 588 | err2: |
73b089b0 FB |
589 | platform_device_put(musb); |
590 | ||
e110de4d FB |
591 | err1: |
592 | kfree(glue); | |
593 | ||
73b089b0 FB |
594 | err0: |
595 | return ret; | |
596 | } | |
597 | ||
e9e8c85e | 598 | static int __devexit davinci_remove(struct platform_device *pdev) |
73b089b0 | 599 | { |
e110de4d | 600 | struct davinci_glue *glue = platform_get_drvdata(pdev); |
73b089b0 | 601 | |
e110de4d FB |
602 | platform_device_del(glue->musb); |
603 | platform_device_put(glue->musb); | |
03491761 FB |
604 | clk_disable(glue->clk); |
605 | clk_put(glue->clk); | |
e110de4d | 606 | kfree(glue); |
73b089b0 FB |
607 | |
608 | return 0; | |
609 | } | |
610 | ||
611 | static struct platform_driver davinci_driver = { | |
e9e8c85e FB |
612 | .probe = davinci_probe, |
613 | .remove = __devexit_p(davinci_remove), | |
73b089b0 FB |
614 | .driver = { |
615 | .name = "musb-davinci", | |
616 | }, | |
617 | }; | |
618 | ||
619 | MODULE_DESCRIPTION("DaVinci MUSB Glue Layer"); | |
620 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); | |
621 | MODULE_LICENSE("GPL v2"); | |
622 | ||
623 | static int __init davinci_init(void) | |
624 | { | |
e9e8c85e | 625 | return platform_driver_register(&davinci_driver); |
73b089b0 | 626 | } |
e9e8c85e | 627 | module_init(davinci_init); |
73b089b0 FB |
628 | |
629 | static void __exit davinci_exit(void) | |
630 | { | |
631 | platform_driver_unregister(&davinci_driver); | |
632 | } | |
633 | module_exit(davinci_exit); |