[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / musb / cppi_dma.h

/* Copyright (C) 2005-2006 by Texas Instruments */

#ifndef _CPPI_DMA_H_
#define _CPPI_DMA_H_

#include <linux/slab.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/dmapool.h>

#include "musb_dma.h"
#include "musb_core.h"


/* FIXME fully isolate CPPI from DaVinci ... the "CPPI generic" registers
 * would seem to be shared with the TUSB6020 (over VLYNQ).
 */

#include "davinci.h"


/* CPPI RX/TX state RAM */

struct cppi_tx_stateram {
	u32 tx_head;			/* "DMA packet" head descriptor */
	u32 tx_buf;
	u32 tx_current;			/* current descriptor */
	u32 tx_buf_current;
	u32 tx_info;			/* flags, remaining buflen */
	u32 tx_rem_len;
	u32 tx_dummy;			/* unused */
	u32 tx_complete;
};

struct cppi_rx_stateram {
	u32 rx_skipbytes;
	u32 rx_head;
	u32 rx_sop;			/* "DMA packet" head descriptor */
	u32 rx_current;			/* current descriptor */
	u32 rx_buf_current;
	u32 rx_len_len;
	u32 rx_cnt_cnt;
	u32 rx_complete;
};

/* hw_options bits in CPPI buffer descriptors */
#define CPPI_SOP_SET	((u32)(1 << 31))
#define CPPI_EOP_SET	((u32)(1 << 30))
#define CPPI_OWN_SET	((u32)(1 << 29))	/* owned by cppi */
#define CPPI_EOQ_MASK	((u32)(1 << 28))
#define CPPI_ZERO_SET	((u32)(1 << 23))	/* rx saw zlp; tx issues one */
#define CPPI_RXABT_MASK	((u32)(1 << 19))	/* need more rx buffers */

#define CPPI_RECV_PKTLEN_MASK 0xFFFF
#define CPPI_BUFFER_LEN_MASK 0xFFFF

#define CPPI_TEAR_READY ((u32)(1 << 31))

/* CPPI data structure definitions */

#define	CPPI_DESCRIPTOR_ALIGN	16	/* bytes; 5-dec docs say 4-byte align */

struct cppi_descriptor {
	/* hardware overlay */
	u32		hw_next;	/* next buffer descriptor Pointer */
	u32		hw_bufp;	/* i/o buffer pointer */
	u32		hw_off_len;	/* buffer_offset16, buffer_length16 */
	u32		hw_options;	/* flags:  SOP, EOP etc*/

	struct cppi_descriptor *next;
	dma_addr_t	dma;		/* address of this descriptor */
	u32		buflen;		/* for RX: original buffer length */
} __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN)));


struct cppi;

/* CPPI  Channel Control structure */
struct cppi_channel {
	struct dma_channel	channel;

	/* back pointer to the DMA controller structure */
	struct cppi		*controller;

	/* which direction of which endpoint? */
	struct musb_hw_ep	*hw_ep;
	bool			transmit;
	u8			index;

	/* DMA modes:  RNDIS or "transparent" */
	u8			is_rndis;

	/* book keeping for current transfer request */
	dma_addr_t		buf_dma;
	u32			buf_len;
	u32			maxpacket;
	u32			offset;		/* dma requested */

	void __iomem		*state_ram;	/* CPPI state */

	struct cppi_descriptor	*freelist;

	/* BD management fields */
	struct cppi_descriptor	*head;
	struct cppi_descriptor	*tail;
	struct cppi_descriptor	*last_processed;

	/* use tx_complete in host role to track endpoints waiting for
	 * FIFONOTEMPTY to clear.
	 */
	struct list_head	tx_complete;
};

/* CPPI DMA controller object */
struct cppi {
	struct dma_controller		controller;
	struct musb			*musb;
	void __iomem			*mregs;		/* Mentor regs */
	void __iomem			*tibase;	/* TI/CPPI regs */

	int				irq;

	struct cppi_channel		tx[4];
	struct cppi_channel		rx[4];

	struct dma_pool			*pool;

	struct list_head		tx_complete;
};

/* CPPI IRQ handler */
extern irqreturn_t cppi_interrupt(int, void *);

#endif				/* end of ifndef _CPPI_DMA_H_ */
Commit	Line	Data
550a7375 FB	1	/* Copyright (C) 2005-2006 by Texas Instruments */
	2
	3	#ifndef _CPPI_DMA_H_
	4	#define _CPPI_DMA_H_
	5
	6	#include <linux/slab.h>
	7	#include <linux/list.h>
550a7375 FB	8	#include <linux/errno.h>
	9	#include <linux/dmapool.h>
	10
	11	#include "musb_dma.h"
	12	#include "musb_core.h"
	13
	14
	15	/* FIXME fully isolate CPPI from DaVinci ... the "CPPI generic" registers
	16	* would seem to be shared with the TUSB6020 (over VLYNQ).
	17	*/
	18
	19	#include "davinci.h"
	20
	21
	22	/* CPPI RX/TX state RAM */
	23
	24	struct cppi_tx_stateram {
	25	u32 tx_head; /* "DMA packet" head descriptor */
	26	u32 tx_buf;
	27	u32 tx_current; /* current descriptor */
	28	u32 tx_buf_current;
	29	u32 tx_info; /* flags, remaining buflen */
	30	u32 tx_rem_len;
	31	u32 tx_dummy; /* unused */
	32	u32 tx_complete;
	33	};
	34
	35	struct cppi_rx_stateram {
	36	u32 rx_skipbytes;
	37	u32 rx_head;
	38	u32 rx_sop; /* "DMA packet" head descriptor */
	39	u32 rx_current; /* current descriptor */
	40	u32 rx_buf_current;
	41	u32 rx_len_len;
	42	u32 rx_cnt_cnt;
	43	u32 rx_complete;
	44	};
	45
	46	/* hw_options bits in CPPI buffer descriptors */
	47	#define CPPI_SOP_SET ((u32)(1 << 31))
	48	#define CPPI_EOP_SET ((u32)(1 << 30))
	49	#define CPPI_OWN_SET ((u32)(1 << 29)) /* owned by cppi */
	50	#define CPPI_EOQ_MASK ((u32)(1 << 28))
	51	#define CPPI_ZERO_SET ((u32)(1 << 23)) /* rx saw zlp; tx issues one */
	52	#define CPPI_RXABT_MASK ((u32)(1 << 19)) /* need more rx buffers */
	53
	54	#define CPPI_RECV_PKTLEN_MASK 0xFFFF
	55	#define CPPI_BUFFER_LEN_MASK 0xFFFF
	56
	57	#define CPPI_TEAR_READY ((u32)(1 << 31))
	58
	59	/* CPPI data structure definitions */
	60
	61	#define CPPI_DESCRIPTOR_ALIGN 16 /* bytes; 5-dec docs say 4-byte align */
	62
	63	struct cppi_descriptor {
	64	/* hardware overlay */
	65	u32 hw_next; /* next buffer descriptor Pointer */
	66	u32 hw_bufp; /* i/o buffer pointer */
	67	u32 hw_off_len; /* buffer_offset16, buffer_length16 */
	68	u32 hw_options; /* flags: SOP, EOP etc*/
	69
	70	struct cppi_descriptor *next;
	71	dma_addr_t dma; /* address of this descriptor */
72	u32 buflen; /* for RX: original buffer length */
73	} __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN)));
74
75
76	struct cppi;
77
78	/* CPPI Channel Control structure */
79	struct cppi_channel {
80	struct dma_channel channel;
81
82	/* back pointer to the DMA controller structure */
83	struct cppi *controller;
84
85	/* which direction of which endpoint? */
86	struct musb_hw_ep *hw_ep;
87	bool transmit;
88	u8 index;
89
90	/* DMA modes: RNDIS or "transparent" */
91	u8 is_rndis;
92
93	/* book keeping for current transfer request */
94	dma_addr_t buf_dma;
95	u32 buf_len;
96	u32 maxpacket;
97	u32 offset; /* dma requested */
98
99	void __iomem state_ram; / CPPI state */
100
101	struct cppi_descriptor *freelist;
102
103	/* BD management fields */
104	struct cppi_descriptor *head;
105	struct cppi_descriptor *tail;
106	struct cppi_descriptor *last_processed;
107
108	/* use tx_complete in host role to track endpoints waiting for
109	* FIFONOTEMPTY to clear.
110	*/
111	struct list_head tx_complete;
112	};
113
114	/* CPPI DMA controller object */
115	struct cppi {
116	struct dma_controller controller;
117	struct musb *musb;
118	void __iomem mregs; / Mentor regs */
119	void __iomem tibase; / TI/CPPI regs */
120
91e9c4fe SS	121	int irq;
91e9c4fe SS	122
c767c1c6 DB	123	struct cppi_channel tx[4];
c767c1c6 DB	124	struct cppi_channel rx[4];
550a7375 FB	125
	126	struct dma_pool *pool;
	127
	128	struct list_head tx_complete;
	129	};
	130
91e9c4fe SS	131	/* CPPI IRQ handler */
91e9c4fe SS	132	extern irqreturn_t cppi_interrupt(int, void *);
550a7375 FB	133
550a7375 FB	134	#endif /* end of ifndef _CPPI_DMA_H_ */