[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / musb / am35x.c

/*
 * Texas Instruments AM35x "glue layer"
 *
 * Copyright (c) 2010, by Texas Instruments
 *
 * Based on the DA8xx "glue layer" code.
 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
 *
 * This file is part of the Inventra Controller Driver for Linux.
 *
 * The Inventra Controller Driver for Linux is free software; you
 * can redistribute it and/or modify it under the terms of the GNU
 * General Public License version 2 as published by the Free Software
 * Foundation.
 *
 * The Inventra Controller Driver for Linux is distributed in
 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
 * without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 * License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with The Inventra Controller Driver for Linux ; if not,
 * write to the Free Software Foundation, Inc., 59 Temple Place,
 * Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>

#include <plat/usb.h>

#include "musb_core.h"

/*
 * AM35x specific definitions
 */
/* USB 2.0 OTG module registers */
#define USB_REVISION_REG	0x00
#define USB_CTRL_REG		0x04
#define USB_STAT_REG		0x08
#define USB_EMULATION_REG	0x0c
/* 0x10 Reserved */
#define USB_AUTOREQ_REG		0x14
#define USB_SRP_FIX_TIME_REG	0x18
#define USB_TEARDOWN_REG	0x1c
#define EP_INTR_SRC_REG		0x20
#define EP_INTR_SRC_SET_REG	0x24
#define EP_INTR_SRC_CLEAR_REG	0x28
#define EP_INTR_MASK_REG	0x2c
#define EP_INTR_MASK_SET_REG	0x30
#define EP_INTR_MASK_CLEAR_REG	0x34
#define EP_INTR_SRC_MASKED_REG	0x38
#define CORE_INTR_SRC_REG	0x40
#define CORE_INTR_SRC_SET_REG	0x44
#define CORE_INTR_SRC_CLEAR_REG	0x48
#define CORE_INTR_MASK_REG	0x4c
#define CORE_INTR_MASK_SET_REG	0x50
#define CORE_INTR_MASK_CLEAR_REG 0x54
#define CORE_INTR_SRC_MASKED_REG 0x58
/* 0x5c Reserved */
#define USB_END_OF_INTR_REG	0x60

/* Control register bits */
#define AM35X_SOFT_RESET_MASK	1

/* USB interrupt register bits */
#define AM35X_INTR_USB_SHIFT	16
#define AM35X_INTR_USB_MASK	(0x1ff << AM35X_INTR_USB_SHIFT)
#define AM35X_INTR_DRVVBUS	0x100
#define AM35X_INTR_RX_SHIFT	16
#define AM35X_INTR_TX_SHIFT	0
#define AM35X_TX_EP_MASK	0xffff		/* EP0 + 15 Tx EPs */
#define AM35X_RX_EP_MASK	0xfffe		/* 15 Rx EPs */
#define AM35X_TX_INTR_MASK	(AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
#define AM35X_RX_INTR_MASK	(AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)

#define USB_MENTOR_CORE_OFFSET	0x400

struct am35x_glue {
	struct device		*dev;
	struct platform_device	*musb;
	struct clk		*phy_clk;
	struct clk		*clk;
};
#define glue_to_musb(g)		platform_get_drvdata(g->musb)

/*
 * am35x_musb_enable - enable interrupts
 */
static void am35x_musb_enable(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;
	u32 epmask;

	/* Workaround: setup IRQs through both register sets. */
	epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
	       ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);

	musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
	musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);

	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
	if (is_otg_enabled(musb))
		musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
			    AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
}

/*
 * am35x_musb_disable - disable HDRC and flush interrupts
 */
static void am35x_musb_disable(struct musb *musb)
{
	void __iomem *reg_base = musb->ctrl_base;

	musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
	musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
			 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
}

#define portstate(stmt)		stmt

static void am35x_musb_set_vbus(struct musb *musb, int is_on)
{
	WARN_ON(is_on && is_peripheral_active(musb));
}

#define	POLL_SECONDS	2

static struct timer_list otg_workaround;

static void otg_timer(unsigned long _musb)
{
	struct musb		*musb = (void *)_musb;
	void __iomem		*mregs = musb->mregs;
	u8			devctl;
	unsigned long		flags;

	/*
	 * We poll because AM35x's won't expose several OTG-critical
	 * status change events (from the transceiver) otherwise.
	 */
	devctl = musb_readb(mregs, MUSB_DEVCTL);
	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
		otg_state_string(musb->xceiv->state));

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->state) {
	case OTG_STATE_A_WAIT_BCON:
		devctl &= ~MUSB_DEVCTL_SESSION;
		musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);

		devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE) {
			musb->xceiv->state = OTG_STATE_B_IDLE;
			MUSB_DEV_MODE(musb);
		} else {
			musb->xceiv->state = OTG_STATE_A_IDLE;
			MUSB_HST_MODE(musb);
		}
		break;
	case OTG_STATE_A_WAIT_VFALL:
		musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
		musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
			    MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
		break;
	case OTG_STATE_B_IDLE:
		if (!is_peripheral_enabled(musb))
			break;

		devctl = musb_readb(mregs, MUSB_DEVCTL);
		if (devctl & MUSB_DEVCTL_BDEVICE)
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
		else
			musb->xceiv->state = OTG_STATE_A_IDLE;
		break;
	default:
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);
}

static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
{
	static unsigned long last_timer;

	if (!is_otg_enabled(musb))
		return;

	if (timeout == 0)
		timeout = jiffies + msecs_to_jiffies(3);

	/* Never idle if active, or when VBUS timeout is not set as host */
	if (musb->is_active || (musb->a_wait_bcon == 0 &&
				musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
		dev_dbg(musb->controller, "%s active, deleting timer\n",
			otg_state_string(musb->xceiv->state));
		del_timer(&otg_workaround);
		last_timer = jiffies;
		return;
	}

	if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
		dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
		return;
	}
	last_timer = timeout;

	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
		otg_state_string(musb->xceiv->state),
		jiffies_to_msecs(timeout - jiffies));
	mod_timer(&otg_workaround, timeout);
}

static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
{
	struct musb  *musb = hci;
	void __iomem *reg_base = musb->ctrl_base;
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	unsigned long flags;
	irqreturn_t ret = IRQ_NONE;
	u32 epintr, usbintr;

	spin_lock_irqsave(&musb->lock, flags);

	/* Get endpoint interrupts */
	epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);

	if (epintr) {
		musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);

		musb->int_rx =
			(epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
		musb->int_tx =
			(epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
	}

	/* Get usb core interrupts */
	usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
	if (!usbintr && !epintr)
		goto eoi;

	if (usbintr) {
		musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);

		musb->int_usb =
			(usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
	}
	/*
	 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
	 * AM35x's missing ID change IRQ.  We need an ID change IRQ to
	 * switch appropriately between halves of the OTG state machine.
	 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
	 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
	 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
	 */
	if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
		int drvvbus = musb_readl(reg_base, USB_STAT_REG);
		void __iomem *mregs = musb->mregs;
		u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
		int err;

		err = is_host_enabled(musb) && (musb->int_usb &
						MUSB_INTR_VBUSERROR);
		if (err) {
			/*
			 * The Mentor core doesn't debounce VBUS as needed
			 * to cope with device connect current spikes. This
			 * means it's not uncommon for bus-powered devices
			 * to get VBUS errors during enumeration.
			 *
			 * This is a workaround, but newer RTL from Mentor
			 * seems to allow a better one: "re"-starting sessions
			 * without waiting for VBUS to stop registering in
			 * devctl.
			 */
			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
			musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
			WARNING("VBUS error workaround (delay coming)\n");
		} else if (is_host_enabled(musb) && drvvbus) {
			MUSB_HST_MODE(musb);
			musb->xceiv->default_a = 1;
			musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
			portstate(musb->port1_status |= USB_PORT_STAT_POWER);
			del_timer(&otg_workaround);
		} else {
			musb->is_active = 0;
			MUSB_DEV_MODE(musb);
			musb->xceiv->default_a = 0;
			musb->xceiv->state = OTG_STATE_B_IDLE;
			portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
		}

		/* NOTE: this must complete power-on within 100 ms. */
		dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
				drvvbus ? "on" : "off",
				otg_state_string(musb->xceiv->state),
				err ? " ERROR" : "",
				devctl);
		ret = IRQ_HANDLED;
	}

	if (musb->int_tx || musb->int_rx || musb->int_usb)
		ret |= musb_interrupt(musb);

eoi:
	/* EOI needs to be written for the IRQ to be re-asserted. */
	if (ret == IRQ_HANDLED || epintr || usbintr) {
		/* clear level interrupt */
		if (data->clear_irq)
			data->clear_irq();
		/* write EOI */
		musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
	}

	/* Poll for ID change */
	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
		mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);

	spin_unlock_irqrestore(&musb->lock, flags);

	return ret;
}

static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
{
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	int     retval = 0;

	if (data->set_mode)
		data->set_mode(musb_mode);
	else
		retval = -EIO;

	return retval;
}

static int am35x_musb_init(struct musb *musb)
{
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	void __iomem *reg_base = musb->ctrl_base;
	u32 rev;

	musb->mregs += USB_MENTOR_CORE_OFFSET;

	/* Returns zero if e.g. not clocked */
	rev = musb_readl(reg_base, USB_REVISION_REG);
	if (!rev)
		return -ENODEV;

	usb_nop_xceiv_register();
	musb->xceiv = otg_get_transceiver();
	if (!musb->xceiv)
		return -ENODEV;

	if (is_host_enabled(musb))
		setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);

	/* Reset the musb */
	if (data->reset)
		data->reset();

	/* Reset the controller */
	musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);

	/* Start the on-chip PHY and its PLL. */
	if (data->set_phy_power)
		data->set_phy_power(1);

	msleep(5);

	musb->isr = am35x_musb_interrupt;

	/* clear level interrupt */
	if (data->clear_irq)
		data->clear_irq();

	return 0;
}

static int am35x_musb_exit(struct musb *musb)
{
	struct device *dev = musb->controller;
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;

	if (is_host_enabled(musb))
		del_timer_sync(&otg_workaround);

	/* Shutdown the on-chip PHY and its PLL. */
	if (data->set_phy_power)
		data->set_phy_power(0);

	otg_put_transceiver(musb->xceiv);
	usb_nop_xceiv_unregister();

	return 0;
}

/* AM35x supports only 32bit read operation */
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
	void __iomem *fifo = hw_ep->fifo;
	u32		val;
	int		i;

	/* Read for 32bit-aligned destination address */
	if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
		readsl(fifo, dst, len >> 2);
		dst += len & ~0x03;
		len &= 0x03;
	}
	/*
	 * Now read the remaining 1 to 3 byte or complete length if
	 * unaligned address.
	 */
	if (len > 4) {
		for (i = 0; i < (len >> 2); i++) {
			*(u32 *) dst = musb_readl(fifo, 0);
			dst += 4;
		}
		len &= 0x03;
	}
	if (len > 0) {
		val = musb_readl(fifo, 0);
		memcpy(dst, &val, len);
	}
}

static const struct musb_platform_ops am35x_ops = {
	.init		= am35x_musb_init,
	.exit		= am35x_musb_exit,

	.enable		= am35x_musb_enable,
	.disable	= am35x_musb_disable,

	.set_mode	= am35x_musb_set_mode,
	.try_idle	= am35x_musb_try_idle,

	.set_vbus	= am35x_musb_set_vbus,
};

static u64 am35x_dmamask = DMA_BIT_MASK(32);

static int __init am35x_probe(struct platform_device *pdev)
{
	struct musb_hdrc_platform_data	*pdata = pdev->dev.platform_data;
	struct platform_device		*musb;
	struct am35x_glue		*glue;

	struct clk			*phy_clk;
	struct clk			*clk;

	int				ret = -ENOMEM;

	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	if (!glue) {
		dev_err(&pdev->dev, "failed to allocate glue context\n");
		goto err0;
	}

	musb = platform_device_alloc("musb-hdrc", -1);
	if (!musb) {
		dev_err(&pdev->dev, "failed to allocate musb device\n");
		goto err1;
	}

	phy_clk = clk_get(&pdev->dev, "fck");
	if (IS_ERR(phy_clk)) {
		dev_err(&pdev->dev, "failed to get PHY clock\n");
		ret = PTR_ERR(phy_clk);
		goto err2;
	}

	clk = clk_get(&pdev->dev, "ick");
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		ret = PTR_ERR(clk);
		goto err3;
	}

	ret = clk_enable(phy_clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable PHY clock\n");
		goto err4;
	}

	ret = clk_enable(clk);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable clock\n");
		goto err5;
	}

	musb->dev.parent		= &pdev->dev;
	musb->dev.dma_mask		= &am35x_dmamask;
	musb->dev.coherent_dma_mask	= am35x_dmamask;

	glue->dev			= &pdev->dev;
	glue->musb			= musb;
	glue->phy_clk			= phy_clk;
	glue->clk			= clk;

	pdata->platform_ops		= &am35x_ops;

	platform_set_drvdata(pdev, glue);

	ret = platform_device_add_resources(musb, pdev->resource,
			pdev->num_resources);
	if (ret) {
		dev_err(&pdev->dev, "failed to add resources\n");
		goto err6;
	}

	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	if (ret) {
		dev_err(&pdev->dev, "failed to add platform_data\n");
		goto err6;
	}

	ret = platform_device_add(musb);
	if (ret) {
		dev_err(&pdev->dev, "failed to register musb device\n");
		goto err6;
	}

	return 0;

err6:
	clk_disable(clk);

err5:
	clk_disable(phy_clk);

err4:
	clk_put(clk);

err3:
	clk_put(phy_clk);

err2:
	platform_device_put(musb);

err1:
	kfree(glue);

err0:
	return ret;
}

static int __exit am35x_remove(struct platform_device *pdev)
{
	struct am35x_glue	*glue = platform_get_drvdata(pdev);

	platform_device_del(glue->musb);
	platform_device_put(glue->musb);
	clk_disable(glue->clk);
	clk_disable(glue->phy_clk);
	clk_put(glue->clk);
	clk_put(glue->phy_clk);
	kfree(glue);

	return 0;
}

#ifdef CONFIG_PM
static int am35x_suspend(struct device *dev)
{
	struct am35x_glue	*glue = dev_get_drvdata(dev);
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;

	/* Shutdown the on-chip PHY and its PLL. */
	if (data->set_phy_power)
		data->set_phy_power(0);

	clk_disable(glue->phy_clk);
	clk_disable(glue->clk);

	return 0;
}

static int am35x_resume(struct device *dev)
{
	struct am35x_glue	*glue = dev_get_drvdata(dev);
	struct musb_hdrc_platform_data *plat = dev->platform_data;
	struct omap_musb_board_data *data = plat->board_data;
	int			ret;

	/* Start the on-chip PHY and its PLL. */
	if (data->set_phy_power)
		data->set_phy_power(1);

	ret = clk_enable(glue->phy_clk);
	if (ret) {
		dev_err(dev, "failed to enable PHY clock\n");
		return ret;
	}

	ret = clk_enable(glue->clk);
	if (ret) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}

	return 0;
}

static struct dev_pm_ops am35x_pm_ops = {
	.suspend	= am35x_suspend,
	.resume		= am35x_resume,
};

#define DEV_PM_OPS	&am35x_pm_ops
#else
#define DEV_PM_OPS	NULL
#endif

static struct platform_driver am35x_driver = {
	.remove		= __exit_p(am35x_remove),
	.driver		= {
		.name	= "musb-am35x",
		.pm	= DEV_PM_OPS,
	},
};

MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
MODULE_LICENSE("GPL v2");

static int __init am35x_init(void)
{
	return platform_driver_probe(&am35x_driver, am35x_probe);
}
subsys_initcall(am35x_init);

static void __exit am35x_exit(void)
{
	platform_driver_unregister(&am35x_driver);
}
module_exit(am35x_exit);
Commit	Line	Data
eb83092c AKG	1	/*
	2	* Texas Instruments AM35x "glue layer"
	3	*
	4	* Copyright (c) 2010, by Texas Instruments
	5	*
	6	* Based on the DA8xx "glue layer" code.
	7	* Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
	8	*
	9	* This file is part of the Inventra Controller Driver for Linux.
	10	*
	11	* The Inventra Controller Driver for Linux is free software; you
	12	* can redistribute it and/or modify it under the terms of the GNU
	13	* General Public License version 2 as published by the Free Software
	14	* Foundation.
	15	*
	16	* The Inventra Controller Driver for Linux is distributed in
	17	* the hope that it will be useful, but WITHOUT ANY WARRANTY;
	18	* without even the implied warranty of MERCHANTABILITY or
	19	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	20	* License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with The Inventra Controller Driver for Linux ; if not,
	24	* write to the Free Software Foundation, Inc., 59 Temple Place,
	25	* Suite 330, Boston, MA 02111-1307 USA
	26	*
	27	*/
	28
	29	#include <linux/init.h>
ab570da2	30	#include <linux/module.h>
eb83092c AKG	31	#include <linux/clk.h>
eb83092c AKG	32	#include <linux/io.h>
ce40c576 FB	33	#include <linux/platform_device.h>
ce40c576 FB	34	#include <linux/dma-mapping.h>
eb83092c	35
eb83092c AKG	36	#include <plat/usb.h>
	37
	38	#include "musb_core.h"
	39
	40	/*
	41	* AM35x specific definitions
	42	*/
	43	/* USB 2.0 OTG module registers */
	44	#define USB_REVISION_REG 0x00
	45	#define USB_CTRL_REG 0x04
	46	#define USB_STAT_REG 0x08
	47	#define USB_EMULATION_REG 0x0c
	48	/* 0x10 Reserved */
	49	#define USB_AUTOREQ_REG 0x14
	50	#define USB_SRP_FIX_TIME_REG 0x18
	51	#define USB_TEARDOWN_REG 0x1c
	52	#define EP_INTR_SRC_REG 0x20
	53	#define EP_INTR_SRC_SET_REG 0x24
	54	#define EP_INTR_SRC_CLEAR_REG 0x28
	55	#define EP_INTR_MASK_REG 0x2c
	56	#define EP_INTR_MASK_SET_REG 0x30
	57	#define EP_INTR_MASK_CLEAR_REG 0x34
	58	#define EP_INTR_SRC_MASKED_REG 0x38
	59	#define CORE_INTR_SRC_REG 0x40
	60	#define CORE_INTR_SRC_SET_REG 0x44
	61	#define CORE_INTR_SRC_CLEAR_REG 0x48
	62	#define CORE_INTR_MASK_REG 0x4c
	63	#define CORE_INTR_MASK_SET_REG 0x50
	64	#define CORE_INTR_MASK_CLEAR_REG 0x54
	65	#define CORE_INTR_SRC_MASKED_REG 0x58
	66	/* 0x5c Reserved */
	67	#define USB_END_OF_INTR_REG 0x60
	68
	69	/* Control register bits */
	70	#define AM35X_SOFT_RESET_MASK 1
	71
	72	/* USB interrupt register bits */
	73	#define AM35X_INTR_USB_SHIFT 16
	74	#define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
	75	#define AM35X_INTR_DRVVBUS 0x100
	76	#define AM35X_INTR_RX_SHIFT 16
	77	#define AM35X_INTR_TX_SHIFT 0
	78	#define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
	79	#define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
	80	#define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
	81	#define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
	82
	83	#define USB_MENTOR_CORE_OFFSET 0x400
	84
0919dfc1 FB	85	struct am35x_glue {
	86	struct device *dev;
	87	struct platform_device *musb;
03491761 FB	88	struct clk *phy_clk;
03491761 FB	89	struct clk *clk;
0919dfc1	90	};
6f783e28	91	#define glue_to_musb(g) platform_get_drvdata(g->musb)
0919dfc1	92
eb83092c	93	/*
743411b3	94	* am35x_musb_enable - enable interrupts
eb83092c	95	*/
743411b3	96	static void am35x_musb_enable(struct musb *musb)
eb83092c AKG	97	{
	98	void __iomem *reg_base = musb->ctrl_base;
	99	u32 epmask;
	100
	101	/* Workaround: setup IRQs through both register sets. */
	102	epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) \|
	103	((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
	104
	105	musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
	106	musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
	107
	108	/* Force the DRVVBUS IRQ so we can start polling for ID change. */
	109	if (is_otg_enabled(musb))
	110	musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
	111	AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
	112	}
	113
	114	/*
743411b3	115	* am35x_musb_disable - disable HDRC and flush interrupts
eb83092c	116	*/
743411b3	117	static void am35x_musb_disable(struct musb *musb)
eb83092c AKG	118	{
	119	void __iomem *reg_base = musb->ctrl_base;
	120
	121	musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
	122	musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
	123	AM35X_TX_INTR_MASK \| AM35X_RX_INTR_MASK);
	124	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
	125	musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
	126	}
	127
eb83092c	128	#define portstate(stmt) stmt
eb83092c	129
743411b3	130	static void am35x_musb_set_vbus(struct musb *musb, int is_on)
eb83092c AKG	131	{
	132	WARN_ON(is_on && is_peripheral_active(musb));
	133	}
	134
	135	#define POLL_SECONDS 2
	136
	137	static struct timer_list otg_workaround;
	138
	139	static void otg_timer(unsigned long _musb)
	140	{
	141	struct musb musb = (void )_musb;
	142	void __iomem *mregs = musb->mregs;
	143	u8 devctl;
	144	unsigned long flags;
	145
	146	/*
	147	* We poll because AM35x's won't expose several OTG-critical
	148	* status change events (from the transceiver) otherwise.
	149	*/
	150	devctl = musb_readb(mregs, MUSB_DEVCTL);
5c8a86e1	151	dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
3df00453	152	otg_state_string(musb->xceiv->state));
eb83092c AKG	153
	154	spin_lock_irqsave(&musb->lock, flags);
	155	switch (musb->xceiv->state) {
	156	case OTG_STATE_A_WAIT_BCON:
	157	devctl &= ~MUSB_DEVCTL_SESSION;
	158	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
	159
	160	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
	161	if (devctl & MUSB_DEVCTL_BDEVICE) {
	162	musb->xceiv->state = OTG_STATE_B_IDLE;
	163	MUSB_DEV_MODE(musb);
	164	} else {
	165	musb->xceiv->state = OTG_STATE_A_IDLE;
	166	MUSB_HST_MODE(musb);
	167	}
	168	break;
	169	case OTG_STATE_A_WAIT_VFALL:
	170	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
	171	musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
	172	MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
	173	break;
	174	case OTG_STATE_B_IDLE:
	175	if (!is_peripheral_enabled(musb))
	176	break;
	177
	178	devctl = musb_readb(mregs, MUSB_DEVCTL);
	179	if (devctl & MUSB_DEVCTL_BDEVICE)
	180	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	181	else
	182	musb->xceiv->state = OTG_STATE_A_IDLE;
	183	break;
	184	default:
	185	break;
	186	}
	187	spin_unlock_irqrestore(&musb->lock, flags);
	188	}
	189
743411b3	190	static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
eb83092c AKG	191	{
	192	static unsigned long last_timer;
	193
	194	if (!is_otg_enabled(musb))
	195	return;
	196
	197	if (timeout == 0)
	198	timeout = jiffies + msecs_to_jiffies(3);
	199
	200	/* Never idle if active, or when VBUS timeout is not set as host */
	201	if (musb->is_active \|\| (musb->a_wait_bcon == 0 &&
	202	musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
5c8a86e1	203	dev_dbg(musb->controller, "%s active, deleting timer\n",
3df00453	204	otg_state_string(musb->xceiv->state));
eb83092c AKG	205	del_timer(&otg_workaround);
	206	last_timer = jiffies;
	207	return;
	208	}
	209
	210	if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
5c8a86e1	211	dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
eb83092c AKG	212	return;
	213	}
	214	last_timer = timeout;
	215
5c8a86e1	216	dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
3df00453 AG	217	otg_state_string(musb->xceiv->state),
3df00453 AG	218	jiffies_to_msecs(timeout - jiffies));
eb83092c AKG	219	mod_timer(&otg_workaround, timeout);
	220	}
	221
743411b3	222	static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
eb83092c AKG	223	{
	224	struct musb *musb = hci;
	225	void __iomem *reg_base = musb->ctrl_base;
a9c03783 AKG	226	struct device *dev = musb->controller;
	227	struct musb_hdrc_platform_data *plat = dev->platform_data;
	228	struct omap_musb_board_data *data = plat->board_data;
eb83092c AKG	229	unsigned long flags;
eb83092c AKG	230	irqreturn_t ret = IRQ_NONE;
a9c03783	231	u32 epintr, usbintr;
eb83092c AKG	232
	233	spin_lock_irqsave(&musb->lock, flags);
	234
	235	/* Get endpoint interrupts */
	236	epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
	237
	238	if (epintr) {
	239	musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
	240
	241	musb->int_rx =
	242	(epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
	243	musb->int_tx =
	244	(epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
	245	}
	246
	247	/* Get usb core interrupts */
	248	usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
	249	if (!usbintr && !epintr)
	250	goto eoi;
	251
	252	if (usbintr) {
	253	musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
	254
	255	musb->int_usb =
	256	(usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
	257	}
	258	/*
	259	* DRVVBUS IRQs are the only proxy we have (a very poor one!) for
	260	* AM35x's missing ID change IRQ. We need an ID change IRQ to
	261	* switch appropriately between halves of the OTG state machine.
	262	* Managing DEVCTL.SESSION per Mentor docs requires that we know its
	263	* value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
	264	* Also, DRVVBUS pulses for SRP (but not at 5V) ...
	265	*/
	266	if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
	267	int drvvbus = musb_readl(reg_base, USB_STAT_REG);
	268	void __iomem *mregs = musb->mregs;
	269	u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
	270	int err;
	271
	272	err = is_host_enabled(musb) && (musb->int_usb &
	273	MUSB_INTR_VBUSERROR);
	274	if (err) {
	275	/*
	276	* The Mentor core doesn't debounce VBUS as needed
	277	* to cope with device connect current spikes. This
	278	* means it's not uncommon for bus-powered devices
	279	* to get VBUS errors during enumeration.
	280	*
	281	* This is a workaround, but newer RTL from Mentor
	282	* seems to allow a better one: "re"-starting sessions
	283	* without waiting for VBUS to stop registering in
	284	* devctl.
	285	*/
	286	musb->int_usb &= ~MUSB_INTR_VBUSERROR;
	287	musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
	288	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	289	WARNING("VBUS error workaround (delay coming)\n");
	290	} else if (is_host_enabled(musb) && drvvbus) {
	291	MUSB_HST_MODE(musb);
	292	musb->xceiv->default_a = 1;
	293	musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
	294	portstate(musb->port1_status \|= USB_PORT_STAT_POWER);
	295	del_timer(&otg_workaround);
296	} else {
297	musb->is_active = 0;
298	MUSB_DEV_MODE(musb);
299	musb->xceiv->default_a = 0;
300	musb->xceiv->state = OTG_STATE_B_IDLE;
301	portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
302	}
303
304	/* NOTE: this must complete power-on within 100 ms. */
5c8a86e1	305	dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
eb83092c	306	drvvbus ? "on" : "off",
3df00453	307	otg_state_string(musb->xceiv->state),
eb83092c AKG	308	err ? " ERROR" : "",
	309	devctl);
	310	ret = IRQ_HANDLED;
	311	}
	312
	313	if (musb->int_tx \|\| musb->int_rx \|\| musb->int_usb)
	314	ret \|= musb_interrupt(musb);
	315
	316	eoi:
	317	/* EOI needs to be written for the IRQ to be re-asserted. */
	318	if (ret == IRQ_HANDLED \|\| epintr \|\| usbintr) {
	319	/* clear level interrupt */
a9c03783 AKG	320	if (data->clear_irq)
a9c03783 AKG	321	data->clear_irq();
eb83092c AKG	322	/* write EOI */
	323	musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
	324	}
	325
	326	/* Poll for ID change */
	327	if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
	328	mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
	329
	330	spin_unlock_irqrestore(&musb->lock, flags);
	331
	332	return ret;
	333	}
	334
743411b3	335	static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
eb83092c	336	{
a9c03783 AKG	337	struct device *dev = musb->controller;
	338	struct musb_hdrc_platform_data *plat = dev->platform_data;
	339	struct omap_musb_board_data *data = plat->board_data;
	340	int retval = 0;
eb83092c	341
a9c03783 AKG	342	if (data->set_mode)
	343	data->set_mode(musb_mode);
	344	else
	345	retval = -EIO;
eb83092c	346
a9c03783	347	return retval;
eb83092c AKG	348	}
eb83092c AKG	349
743411b3	350	static int am35x_musb_init(struct musb *musb)
eb83092c	351	{
a9c03783 AKG	352	struct device *dev = musb->controller;
	353	struct musb_hdrc_platform_data *plat = dev->platform_data;
	354	struct omap_musb_board_data *data = plat->board_data;
eb83092c	355	void __iomem *reg_base = musb->ctrl_base;
a9c03783	356	u32 rev;
eb83092c AKG	357
	358	musb->mregs += USB_MENTOR_CORE_OFFSET;
	359
eb83092c AKG	360	/* Returns zero if e.g. not clocked */
eb83092c AKG	361	rev = musb_readl(reg_base, USB_REVISION_REG);
03491761 FB	362	if (!rev)
03491761 FB	363	return -ENODEV;
eb83092c AKG	364
	365	usb_nop_xceiv_register();
	366	musb->xceiv = otg_get_transceiver();
03491761 FB	367	if (!musb->xceiv)
03491761 FB	368	return -ENODEV;
eb83092c AKG	369
	370	if (is_host_enabled(musb))
	371	setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
	372
a9c03783 AKG	373	/* Reset the musb */
	374	if (data->reset)
	375	data->reset();
eb83092c AKG	376
	377	/* Reset the controller */
	378	musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
	379
	380	/* Start the on-chip PHY and its PLL. */
a9c03783 AKG	381	if (data->set_phy_power)
a9c03783 AKG	382	data->set_phy_power(1);
eb83092c AKG	383
	384	msleep(5);
	385
743411b3	386	musb->isr = am35x_musb_interrupt;
eb83092c AKG	387
eb83092c AKG	388	/* clear level interrupt */
a9c03783 AKG	389	if (data->clear_irq)
a9c03783 AKG	390	data->clear_irq();
03491761	391
eb83092c	392	return 0;
eb83092c AKG	393	}
eb83092c AKG	394
743411b3	395	static int am35x_musb_exit(struct musb *musb)
eb83092c	396	{
a9c03783 AKG	397	struct device *dev = musb->controller;
	398	struct musb_hdrc_platform_data *plat = dev->platform_data;
	399	struct omap_musb_board_data *data = plat->board_data;
	400
eb83092c AKG	401	if (is_host_enabled(musb))
	402	del_timer_sync(&otg_workaround);
	403
a9c03783 AKG	404	/* Shutdown the on-chip PHY and its PLL. */
	405	if (data->set_phy_power)
	406	data->set_phy_power(0);
eb83092c AKG	407
	408	otg_put_transceiver(musb->xceiv);
	409	usb_nop_xceiv_unregister();
	410
eb83092c AKG	411	return 0;
	412	}
	413
843bb1d0 AKG	414	/* AM35x supports only 32bit read operation */
	415	void musb_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
	416	{
	417	void __iomem *fifo = hw_ep->fifo;
	418	u32 val;
	419	int i;
	420
	421	/* Read for 32bit-aligned destination address */
	422	if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
	423	readsl(fifo, dst, len >> 2);
	424	dst += len & ~0x03;
	425	len &= 0x03;
	426	}
	427	/*
	428	* Now read the remaining 1 to 3 byte or complete length if
	429	* unaligned address.
	430	*/
	431	if (len > 4) {
	432	for (i = 0; i < (len >> 2); i++) {
	433	(u32 ) dst = musb_readl(fifo, 0);
	434	dst += 4;
	435	}
	436	len &= 0x03;
	437	}
	438	if (len > 0) {
	439	val = musb_readl(fifo, 0);
	440	memcpy(dst, &val, len);
	441	}
	442	}
743411b3	443
f7ec9437	444	static const struct musb_platform_ops am35x_ops = {
743411b3 FB	445	.init = am35x_musb_init,
	446	.exit = am35x_musb_exit,
	447
	448	.enable = am35x_musb_enable,
	449	.disable = am35x_musb_disable,
	450
	451	.set_mode = am35x_musb_set_mode,
	452	.try_idle = am35x_musb_try_idle,
	453
	454	.set_vbus = am35x_musb_set_vbus,
	455	};
ce40c576 FB	456
	457	static u64 am35x_dmamask = DMA_BIT_MASK(32);
	458
	459	static int __init am35x_probe(struct platform_device *pdev)
	460	{
	461	struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
	462	struct platform_device *musb;
0919dfc1	463	struct am35x_glue *glue;
ce40c576	464
03491761 FB	465	struct clk *phy_clk;
	466	struct clk *clk;
	467
ce40c576 FB	468	int ret = -ENOMEM;
ce40c576 FB	469
0919dfc1 FB	470	glue = kzalloc(sizeof(*glue), GFP_KERNEL);
	471	if (!glue) {
	472	dev_err(&pdev->dev, "failed to allocate glue context\n");
	473	goto err0;
	474	}
	475
ce40c576 FB	476	musb = platform_device_alloc("musb-hdrc", -1);
	477	if (!musb) {
	478	dev_err(&pdev->dev, "failed to allocate musb device\n");
0919dfc1	479	goto err1;
ce40c576 FB	480	}
ce40c576 FB	481
03491761 FB	482	phy_clk = clk_get(&pdev->dev, "fck");
	483	if (IS_ERR(phy_clk)) {
	484	dev_err(&pdev->dev, "failed to get PHY clock\n");
	485	ret = PTR_ERR(phy_clk);
	486	goto err2;
	487	}
	488
	489	clk = clk_get(&pdev->dev, "ick");
	490	if (IS_ERR(clk)) {
	491	dev_err(&pdev->dev, "failed to get clock\n");
	492	ret = PTR_ERR(clk);
	493	goto err3;
	494	}
	495
	496	ret = clk_enable(phy_clk);
	497	if (ret) {
	498	dev_err(&pdev->dev, "failed to enable PHY clock\n");
	499	goto err4;
	500	}
	501
	502	ret = clk_enable(clk);
	503	if (ret) {
	504	dev_err(&pdev->dev, "failed to enable clock\n");
	505	goto err5;
	506	}
	507
ce40c576 FB	508	musb->dev.parent = &pdev->dev;
	509	musb->dev.dma_mask = &am35x_dmamask;
	510	musb->dev.coherent_dma_mask = am35x_dmamask;
	511
0919dfc1 FB	512	glue->dev = &pdev->dev;
0919dfc1 FB	513	glue->musb = musb;
03491761 FB	514	glue->phy_clk = phy_clk;
03491761 FB	515	glue->clk = clk;
0919dfc1	516
f7ec9437 FB	517	pdata->platform_ops = &am35x_ops;
f7ec9437 FB	518
0919dfc1	519	platform_set_drvdata(pdev, glue);
ce40c576 FB	520
	521	ret = platform_device_add_resources(musb, pdev->resource,
	522	pdev->num_resources);
	523	if (ret) {
	524	dev_err(&pdev->dev, "failed to add resources\n");
03491761	525	goto err6;
ce40c576 FB	526	}
	527
	528	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	529	if (ret) {
	530	dev_err(&pdev->dev, "failed to add platform_data\n");
03491761	531	goto err6;
ce40c576 FB	532	}
	533
	534	ret = platform_device_add(musb);
	535	if (ret) {
	536	dev_err(&pdev->dev, "failed to register musb device\n");
03491761	537	goto err6;
ce40c576 FB	538	}
	539
	540	return 0;
	541
03491761 FB	542	err6:
	543	clk_disable(clk);
	544
	545	err5:
	546	clk_disable(phy_clk);
	547
	548	err4:
	549	clk_put(clk);
	550
	551	err3:
	552	clk_put(phy_clk);
	553
0919dfc1	554	err2:
ce40c576 FB	555	platform_device_put(musb);
ce40c576 FB	556
0919dfc1 FB	557	err1:
	558	kfree(glue);
	559
ce40c576 FB	560	err0:
	561	return ret;
	562	}
	563
	564	static int __exit am35x_remove(struct platform_device *pdev)
	565	{
0919dfc1	566	struct am35x_glue *glue = platform_get_drvdata(pdev);
ce40c576	567
0919dfc1 FB	568	platform_device_del(glue->musb);
0919dfc1 FB	569	platform_device_put(glue->musb);
03491761 FB	570	clk_disable(glue->clk);
	571	clk_disable(glue->phy_clk);
	572	clk_put(glue->clk);
	573	clk_put(glue->phy_clk);
0919dfc1	574	kfree(glue);
ce40c576 FB	575
	576	return 0;
	577	}
	578
6f783e28 FB	579	#ifdef CONFIG_PM
	580	static int am35x_suspend(struct device *dev)
	581	{
	582	struct am35x_glue *glue = dev_get_drvdata(dev);
a9c03783 AKG	583	struct musb_hdrc_platform_data *plat = dev->platform_data;
	584	struct omap_musb_board_data *data = plat->board_data;
	585
	586	/* Shutdown the on-chip PHY and its PLL. */
	587	if (data->set_phy_power)
	588	data->set_phy_power(0);
6f783e28	589
6f783e28 FB	590	clk_disable(glue->phy_clk);
	591	clk_disable(glue->clk);
	592
	593	return 0;
	594	}
	595
	596	static int am35x_resume(struct device *dev)
	597	{
	598	struct am35x_glue *glue = dev_get_drvdata(dev);
a9c03783 AKG	599	struct musb_hdrc_platform_data *plat = dev->platform_data;
a9c03783 AKG	600	struct omap_musb_board_data *data = plat->board_data;
6f783e28 FB	601	int ret;
6f783e28 FB	602
a9c03783 AKG	603	/* Start the on-chip PHY and its PLL. */
	604	if (data->set_phy_power)
	605	data->set_phy_power(1);
	606
6f783e28 FB	607	ret = clk_enable(glue->phy_clk);
	608	if (ret) {
	609	dev_err(dev, "failed to enable PHY clock\n");
	610	return ret;
	611	}
	612
	613	ret = clk_enable(glue->clk);
	614	if (ret) {
	615	dev_err(dev, "failed to enable clock\n");
	616	return ret;
	617	}
	618
	619	return 0;
	620	}
	621
	622	static struct dev_pm_ops am35x_pm_ops = {
	623	.suspend = am35x_suspend,
	624	.resume = am35x_resume,
	625	};
	626
	627	#define DEV_PM_OPS &am35x_pm_ops
	628	#else
	629	#define DEV_PM_OPS NULL
	630	#endif
	631
ce40c576 FB	632	static struct platform_driver am35x_driver = {
	633	.remove = __exit_p(am35x_remove),
	634	.driver = {
	635	.name = "musb-am35x",
6f783e28	636	.pm = DEV_PM_OPS,
ce40c576 FB	637	},
	638	};
	639
	640	MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
	641	MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
	642	MODULE_LICENSE("GPL v2");
	643
	644	static int __init am35x_init(void)
	645	{
	646	return platform_driver_probe(&am35x_driver, am35x_probe);
	647	}
	648	subsys_initcall(am35x_init);
	649
	650	static void __exit am35x_exit(void)
	651	{
	652	platform_driver_unregister(&am35x_driver);
	653	}
	654	module_exit(am35x_exit);