projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
USB: usb-skeleton.c: cleanup open_count
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / host / xhci.c
CommitLineData
66d4eadd
SS		 1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
43b86af8 23#include <linux/pci.h>
66d4eadd 24#include <linux/irq.h>
8df75f42 25#include <linux/log2.h>
66d4eadd 26#include <linux/module.h>
b0567b3f 27#include <linux/moduleparam.h>
5a0e3ad6 28#include <linux/slab.h>
66d4eadd
SS		 29
30#include "xhci.h"
31
32#define DRIVER_AUTHOR "Sarah Sharp"
33#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
34
b0567b3f
SS		 35/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
36static int link_quirk;
37module_param(link_quirk, int, S_IRUGO | S_IWUSR);
38MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
39
66d4eadd
SS		 40/* TODO: copied from ehci-hcd.c - can this be refactored? */
41/*
42 * handshake - spin reading hc until handshake completes or fails
43 * @ptr: address of hc register to be read
44 * @mask: bits to look at in result of read
45 * @done: value of those bits when handshake succeeds
46 * @usec: timeout in microseconds
47 *
48 * Returns negative errno, or zero on success
49 *
50 * Success happens when the "mask" bits have the specified value (hardware
51 * handshake done). There are two failure modes: "usec" have passed (major
52 * hardware flakeout), or the register reads as all-ones (hardware removed).
53 */
54static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
55 u32 mask, u32 done, int usec)
56{
57 u32 result;
58
59 do {
60 result = xhci_readl(xhci, ptr);
61 if (result == ~(u32)0) /* card removed */
62 return -ENODEV;
63 result &= mask;
64 if (result == done)
65 return 0;
66 udelay(1);
67 usec--;
68 } while (usec > 0);
69 return -ETIMEDOUT;
70}
71
72/*
4f0f0bae 73 * Disable interrupts and begin the xHCI halting process.
66d4eadd 74 */
4f0f0bae 75void xhci_quiesce(struct xhci_hcd *xhci)
66d4eadd
SS		 76{
77 u32 halted;
78 u32 cmd;
79 u32 mask;
80
66d4eadd
SS		 81 mask = ~(XHCI_IRQS);
82 halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
83 if (!halted)
84 mask &= ~CMD_RUN;
85
86 cmd = xhci_readl(xhci, &xhci->op_regs->command);
87 cmd &= mask;
88 xhci_writel(xhci, cmd, &xhci->op_regs->command);
4f0f0bae
SS		 89}
90
91/*
92 * Force HC into halt state.
93 *
94 * Disable any IRQs and clear the run/stop bit.
95 * HC will complete any current and actively pipelined transactions, and
bdfca502 96 * should halt within 16 ms of the run/stop bit being cleared.
4f0f0bae 97 * Read HC Halted bit in the status register to see when the HC is finished.
4f0f0bae
SS		 98 */
99int xhci_halt(struct xhci_hcd *xhci)
100{
c6cc27c7 101 int ret;
4f0f0bae
SS		 102 xhci_dbg(xhci, "// Halt the HC\n");
103 xhci_quiesce(xhci);
66d4eadd 104
c6cc27c7 105 ret = handshake(xhci, &xhci->op_regs->status,
66d4eadd 106 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
c6cc27c7
SS		 107 if (!ret)
108 xhci->xhc_state |= XHCI_STATE_HALTED;
109 return ret;
66d4eadd
SS		 110}
111
ed07453f
SS		 112/*
113 * Set the run bit and wait for the host to be running.
114 */
8212a49d 115static int xhci_start(struct xhci_hcd *xhci)
ed07453f
SS		 116{
117 u32 temp;
118 int ret;
119
120 temp = xhci_readl(xhci, &xhci->op_regs->command);
121 temp |= (CMD_RUN);
122 xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
123 temp);
124 xhci_writel(xhci, temp, &xhci->op_regs->command);
125
126 /*
127 * Wait for the HCHalted Status bit to be 0 to indicate the host is
128 * running.
129 */
130 ret = handshake(xhci, &xhci->op_regs->status,
131 STS_HALT, 0, XHCI_MAX_HALT_USEC);
132 if (ret == -ETIMEDOUT)
133 xhci_err(xhci, "Host took too long to start, "
134 "waited %u microseconds.\n",
135 XHCI_MAX_HALT_USEC);
c6cc27c7
SS		 136 if (!ret)
137 xhci->xhc_state &= ~XHCI_STATE_HALTED;
ed07453f
SS		 138 return ret;
139}
140
66d4eadd 141/*
ac04e6ff 142 * Reset a halted HC.
66d4eadd
SS		 143 *
144 * This resets pipelines, timers, counters, state machines, etc.
145 * Transactions will be terminated immediately, and operational registers
146 * will be set to their defaults.
147 */
148int xhci_reset(struct xhci_hcd *xhci)
149{
150 u32 command;
151 u32 state;
2d62f3ee 152 int ret;
66d4eadd
SS		 153
154 state = xhci_readl(xhci, &xhci->op_regs->status);
d3512f63
SS		 155 if ((state & STS_HALT) == 0) {
156 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
157 return 0;
158 }
66d4eadd
SS		 159
160 xhci_dbg(xhci, "// Reset the HC\n");
161 command = xhci_readl(xhci, &xhci->op_regs->command);
162 command |= CMD_RESET;
163 xhci_writel(xhci, command, &xhci->op_regs->command);
66d4eadd 164
2d62f3ee
SS		 165 ret = handshake(xhci, &xhci->op_regs->command,
166 CMD_RESET, 0, 250 * 1000);
167 if (ret)
168 return ret;
169
170 xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
171 /*
172 * xHCI cannot write to any doorbells or operational registers other
173 * than status until the "Controller Not Ready" flag is cleared.
174 */
175 return handshake(xhci, &xhci->op_regs->status, STS_CNR, 0, 250 * 1000);
66d4eadd
SS		 176}
177
421aa841
SAS		 178#ifdef CONFIG_PCI
179static int xhci_free_msi(struct xhci_hcd *xhci)
43b86af8
DN		 180{
181 int i;
43b86af8 182
421aa841
SAS		 183 if (!xhci->msix_entries)
184 return -EINVAL;
43b86af8 185
421aa841
SAS		 186 for (i = 0; i < xhci->msix_count; i++)
187 if (xhci->msix_entries[i].vector)
188 free_irq(xhci->msix_entries[i].vector,
189 xhci_to_hcd(xhci));
190 return 0;
43b86af8
DN		 191}
192
193/*
194 * Set up MSI
195 */
196static int xhci_setup_msi(struct xhci_hcd *xhci)
66d4eadd
SS		 197{
198 int ret;
43b86af8
DN		 199 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
200
201 ret = pci_enable_msi(pdev);
202 if (ret) {
3b9783b2 203 xhci_dbg(xhci, "failed to allocate MSI entry\n");
43b86af8
DN		 204 return ret;
205 }
206
207 ret = request_irq(pdev->irq, (irq_handler_t)xhci_msi_irq,
208 0, "xhci_hcd", xhci_to_hcd(xhci));
209 if (ret) {
3b9783b2 210 xhci_dbg(xhci, "disable MSI interrupt\n");
43b86af8
DN		 211 pci_disable_msi(pdev);
212 }
213
214 return ret;
215}
216
421aa841
SAS		 217/*
218 * Free IRQs
219 * free all IRQs request
220 */
221static void xhci_free_irq(struct xhci_hcd *xhci)
222{
223 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
224 int ret;
225
226 /* return if using legacy interrupt */
227 if (xhci_to_hcd(xhci)->irq >= 0)
228 return;
229
230 ret = xhci_free_msi(xhci);
231 if (!ret)
232 return;
233 if (pdev->irq >= 0)
234 free_irq(pdev->irq, xhci_to_hcd(xhci));
235
236 return;
237}
238
43b86af8
DN		 239/*
240 * Set up MSI-X
241 */
242static int xhci_setup_msix(struct xhci_hcd *xhci)
243{
244 int i, ret = 0;
0029227f
AX		 245 struct usb_hcd *hcd = xhci_to_hcd(xhci);
246 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
66d4eadd 247
43b86af8
DN		 248 /*
249 * calculate number of msi-x vectors supported.
250 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
251 * with max number of interrupters based on the xhci HCSPARAMS1.
252 * - num_online_cpus: maximum msi-x vectors per CPUs core.
253 * Add additional 1 vector to ensure always available interrupt.
254 */
255 xhci->msix_count = min(num_online_cpus() + 1,
256 HCS_MAX_INTRS(xhci->hcs_params1));
257
258 xhci->msix_entries =
259 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
86871975 260 GFP_KERNEL);
66d4eadd
SS		 261 if (!xhci->msix_entries) {
262 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
263 return -ENOMEM;
264 }
43b86af8
DN		 265
266 for (i = 0; i < xhci->msix_count; i++) {
267 xhci->msix_entries[i].entry = i;
268 xhci->msix_entries[i].vector = 0;
269 }
66d4eadd
SS		 270
271 ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
272 if (ret) {
3b9783b2 273 xhci_dbg(xhci, "Failed to enable MSI-X\n");
66d4eadd
SS		 274 goto free_entries;
275 }
276
43b86af8
DN		 277 for (i = 0; i < xhci->msix_count; i++) {
278 ret = request_irq(xhci->msix_entries[i].vector,
279 (irq_handler_t)xhci_msi_irq,
280 0, "xhci_hcd", xhci_to_hcd(xhci));
281 if (ret)
282 goto disable_msix;
66d4eadd 283 }
43b86af8 284
0029227f 285 hcd->msix_enabled = 1;
43b86af8 286 return ret;
66d4eadd
SS		 287
288disable_msix:
3b9783b2 289 xhci_dbg(xhci, "disable MSI-X interrupt\n");
43b86af8 290 xhci_free_irq(xhci);
66d4eadd
SS		 291 pci_disable_msix(pdev);
292free_entries:
293 kfree(xhci->msix_entries);
294 xhci->msix_entries = NULL;
295 return ret;
296}
297
66d4eadd
SS		 298/* Free any IRQs and disable MSI-X */
299static void xhci_cleanup_msix(struct xhci_hcd *xhci)
300{
0029227f
AX		 301 struct usb_hcd *hcd = xhci_to_hcd(xhci);
302 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
66d4eadd 303
43b86af8
DN		 304 xhci_free_irq(xhci);
305
306 if (xhci->msix_entries) {
307 pci_disable_msix(pdev);
308 kfree(xhci->msix_entries);
309 xhci->msix_entries = NULL;
310 } else {
311 pci_disable_msi(pdev);
312 }
313
0029227f 314 hcd->msix_enabled = 0;
43b86af8 315 return;
66d4eadd 316}
66d4eadd 317
421aa841
SAS		 318static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
319{
320 int i;
321
322 if (xhci->msix_entries) {
323 for (i = 0; i < xhci->msix_count; i++)
324 synchronize_irq(xhci->msix_entries[i].vector);
325 }
326}
327
328static int xhci_try_enable_msi(struct usb_hcd *hcd)
329{
330 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
331 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
332 int ret;
333
334 /*
335 * Some Fresco Logic host controllers advertise MSI, but fail to
336 * generate interrupts. Don't even try to enable MSI.
337 */
338 if (xhci->quirks & XHCI_BROKEN_MSI)
339 return 0;
340
341 /* unregister the legacy interrupt */
342 if (hcd->irq)
343 free_irq(hcd->irq, hcd);
344 hcd->irq = -1;
345
346 ret = xhci_setup_msix(xhci);
347 if (ret)
348 /* fall back to msi*/
349 ret = xhci_setup_msi(xhci);
350
351 if (!ret)
352 /* hcd->irq is -1, we have MSI */
353 return 0;
354
355 /* fall back to legacy interrupt*/
356 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
357 hcd->irq_descr, hcd);
358 if (ret) {
359 xhci_err(xhci, "request interrupt %d failed\n",
360 pdev->irq);
361 return ret;
362 }
363 hcd->irq = pdev->irq;
364 return 0;
365}
366
367#else
368
369static int xhci_try_enable_msi(struct usb_hcd *hcd)
370{
371 return 0;
372}
373
374static void xhci_cleanup_msix(struct xhci_hcd *xhci)
375{
376}
377
378static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
379{
380}
381
382#endif
383
66d4eadd
SS		 384/*
385 * Initialize memory for HCD and xHC (one-time init).
386 *
387 * Program the PAGESIZE register, initialize the device context array, create
388 * device contexts (?), set up a command ring segment (or two?), create event
389 * ring (one for now).
390 */
391int xhci_init(struct usb_hcd *hcd)
392{
393 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
394 int retval = 0;
395
396 xhci_dbg(xhci, "xhci_init\n");
397 spin_lock_init(&xhci->lock);
d7826599 398 if (xhci->hci_version == 0x95 && link_quirk) {
b0567b3f
SS		 399 xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
400 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
401 } else {
ac9d8fe7 402 xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
b0567b3f 403 }
66d4eadd
SS		 404 retval = xhci_mem_init(xhci, GFP_KERNEL);
405 xhci_dbg(xhci, "Finished xhci_init\n");
406
407 return retval;
408}
409
7f84eef0
SS		 410/*-------------------------------------------------------------------------*/
411
7f84eef0
SS		 412
413#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
8212a49d 414static void xhci_event_ring_work(unsigned long arg)
7f84eef0
SS		 415{
416 unsigned long flags;
417 int temp;
8e595a5d 418 u64 temp_64;
7f84eef0
SS		 419 struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
420 int i, j;
421
422 xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
423
424 spin_lock_irqsave(&xhci->lock, flags);
425 temp = xhci_readl(xhci, &xhci->op_regs->status);
426 xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
7bd89b40
SS		 427 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
428 (xhci->xhc_state & XHCI_STATE_HALTED)) {
e4ab05df
SS		 429 xhci_dbg(xhci, "HW died, polling stopped.\n");
430 spin_unlock_irqrestore(&xhci->lock, flags);
431 return;
432 }
433
7f84eef0
SS		 434 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
435 xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
7f84eef0
SS		 436 xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
437 xhci->error_bitmask = 0;
438 xhci_dbg(xhci, "Event ring:\n");
439 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
440 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
8e595a5d
SS		 441 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
442 temp_64 &= ~ERST_PTR_MASK;
443 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
7f84eef0
SS		 444 xhci_dbg(xhci, "Command ring:\n");
445 xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
446 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
447 xhci_dbg_cmd_ptrs(xhci);
3ffbba95 448 for (i = 0; i < MAX_HC_SLOTS; ++i) {
63a0d9ab
SS		 449 if (!xhci->devs[i])
450 continue;
451 for (j = 0; j < 31; ++j) {
e9df17eb 452 xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
3ffbba95
SS		 453 }
454 }
7f84eef0
SS		 455 spin_unlock_irqrestore(&xhci->lock, flags);
456
457 if (!xhci->zombie)
458 mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
459 else
460 xhci_dbg(xhci, "Quit polling the event ring.\n");
461}
462#endif
463
f6ff0ac8
SS		 464static int xhci_run_finished(struct xhci_hcd *xhci)
465{
466 if (xhci_start(xhci)) {
467 xhci_halt(xhci);
468 return -ENODEV;
469 }
470 xhci->shared_hcd->state = HC_STATE_RUNNING;
471
472 if (xhci->quirks & XHCI_NEC_HOST)
473 xhci_ring_cmd_db(xhci);
474
475 xhci_dbg(xhci, "Finished xhci_run for USB3 roothub\n");
476 return 0;
477}
478
66d4eadd
SS		 479/*
480 * Start the HC after it was halted.
481 *
482 * This function is called by the USB core when the HC driver is added.
483 * Its opposite is xhci_stop().
484 *
485 * xhci_init() must be called once before this function can be called.
486 * Reset the HC, enable device slot contexts, program DCBAAP, and
487 * set command ring pointer and event ring pointer.
488 *
489 * Setup MSI-X vectors and enable interrupts.
490 */
491int xhci_run(struct usb_hcd *hcd)
492{
493 u32 temp;
8e595a5d 494 u64 temp_64;
3fd1ec58 495 int ret;
66d4eadd 496 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
66d4eadd 497
f6ff0ac8
SS		 498 /* Start the xHCI host controller running only after the USB 2.0 roothub
499 * is setup.
500 */
66d4eadd 501
0f2a7930 502 hcd->uses_new_polling = 1;
f6ff0ac8
SS		 503 if (!usb_hcd_is_primary_hcd(hcd))
504 return xhci_run_finished(xhci);
0f2a7930 505
7f84eef0 506 xhci_dbg(xhci, "xhci_run\n");
43b86af8 507
3fd1ec58 508 ret = xhci_try_enable_msi(hcd);
43b86af8 509 if (ret)
3fd1ec58 510 return ret;
66d4eadd 511
7f84eef0
SS		 512#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
513 init_timer(&xhci->event_ring_timer);
514 xhci->event_ring_timer.data = (unsigned long) xhci;
23e3be11 515 xhci->event_ring_timer.function = xhci_event_ring_work;
7f84eef0
SS		 516 /* Poll the event ring */
517 xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
518 xhci->zombie = 0;
519 xhci_dbg(xhci, "Setting event ring polling timer\n");
520 add_timer(&xhci->event_ring_timer);
521#endif
522
66e49d87
SS		 523 xhci_dbg(xhci, "Command ring memory map follows:\n");
524 xhci_debug_ring(xhci, xhci->cmd_ring);
525 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
526 xhci_dbg_cmd_ptrs(xhci);
527
528 xhci_dbg(xhci, "ERST memory map follows:\n");
529 xhci_dbg_erst(xhci, &xhci->erst);
530 xhci_dbg(xhci, "Event ring:\n");
531 xhci_debug_ring(xhci, xhci->event_ring);
532 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
533 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
534 temp_64 &= ~ERST_PTR_MASK;
535 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
536
66d4eadd
SS		 537 xhci_dbg(xhci, "// Set the interrupt modulation register\n");
538 temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
a4d88302 539 temp &= ~ER_IRQ_INTERVAL_MASK;
66d4eadd
SS		 540 temp |= (u32) 160;
541 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
542
543 /* Set the HCD state before we enable the irqs */
66d4eadd
SS		 544 temp = xhci_readl(xhci, &xhci->op_regs->command);
545 temp |= (CMD_EIE);
546 xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
547 temp);
548 xhci_writel(xhci, temp, &xhci->op_regs->command);
549
550 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
700e2052
GKH		 551 xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
552 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
66d4eadd
SS		 553 xhci_writel(xhci, ER_IRQ_ENABLE(temp),
554 &xhci->ir_set->irq_pending);
09ece30e 555 xhci_print_ir_set(xhci, 0);
66d4eadd 556
0238634d
SS		 557 if (xhci->quirks & XHCI_NEC_HOST)
558 xhci_queue_vendor_command(xhci, 0, 0, 0,
559 TRB_TYPE(TRB_NEC_GET_FW));
7f84eef0 560
f6ff0ac8
SS		 561 xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
562 return 0;
563}
ed07453f 564
f6ff0ac8
SS		 565static void xhci_only_stop_hcd(struct usb_hcd *hcd)
566{
567 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
66d4eadd 568
f6ff0ac8
SS		 569 spin_lock_irq(&xhci->lock);
570 xhci_halt(xhci);
571
572 /* The shared_hcd is going to be deallocated shortly (the USB core only
573 * calls this function when allocation fails in usb_add_hcd(), or
574 * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
575 */
576 xhci->shared_hcd = NULL;
577 spin_unlock_irq(&xhci->lock);
66d4eadd
SS		 578}
579
580/*
581 * Stop xHCI driver.
582 *
583 * This function is called by the USB core when the HC driver is removed.
584 * Its opposite is xhci_run().
585 *
586 * Disable device contexts, disable IRQs, and quiesce the HC.
587 * Reset the HC, finish any completed transactions, and cleanup memory.
588 */
589void xhci_stop(struct usb_hcd *hcd)
590{
591 u32 temp;
592 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
593
f6ff0ac8
SS		 594 if (!usb_hcd_is_primary_hcd(hcd)) {
595 xhci_only_stop_hcd(xhci->shared_hcd);
596 return;
597 }
598
66d4eadd 599 spin_lock_irq(&xhci->lock);
f6ff0ac8
SS		 600 /* Make sure the xHC is halted for a USB3 roothub
601 * (xhci_stop() could be called as part of failed init).
602 */
66d4eadd
SS		 603 xhci_halt(xhci);
604 xhci_reset(xhci);
605 spin_unlock_irq(&xhci->lock);
606
40a9fb17
ZR		 607 xhci_cleanup_msix(xhci);
608
7f84eef0
SS		 609#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
610 /* Tell the event ring poll function not to reschedule */
611 xhci->zombie = 1;
612 del_timer_sync(&xhci->event_ring_timer);
613#endif
614
c41136b0
AX		 615 if (xhci->quirks & XHCI_AMD_PLL_FIX)
616 usb_amd_dev_put();
617
66d4eadd
SS		 618 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
619 temp = xhci_readl(xhci, &xhci->op_regs->status);
620 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
621 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
622 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
623 &xhci->ir_set->irq_pending);
09ece30e 624 xhci_print_ir_set(xhci, 0);
66d4eadd
SS		 625
626 xhci_dbg(xhci, "cleaning up memory\n");
627 xhci_mem_cleanup(xhci);
628 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
629 xhci_readl(xhci, &xhci->op_regs->status));
630}
631
632/*
633 * Shutdown HC (not bus-specific)
634 *
635 * This is called when the machine is rebooting or halting. We assume that the
636 * machine will be powered off, and the HC's internal state will be reset.
637 * Don't bother to free memory.
f6ff0ac8
SS		 638 *
639 * This will only ever be called with the main usb_hcd (the USB3 roothub).
66d4eadd
SS		 640 */
641void xhci_shutdown(struct usb_hcd *hcd)
642{
643 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
644
645 spin_lock_irq(&xhci->lock);
646 xhci_halt(xhci);
43b86af8 647 spin_unlock_irq(&xhci->lock);
66d4eadd 648
40a9fb17
ZR		 649 xhci_cleanup_msix(xhci);
650
66d4eadd
SS		 651 xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
652 xhci_readl(xhci, &xhci->op_regs->status));
653}
654
b5b5c3ac 655#ifdef CONFIG_PM
5535b1d5
AX		 656static void xhci_save_registers(struct xhci_hcd *xhci)
657{
658 xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
659 xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
660 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
661 xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
662 xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
663 xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
664 xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
665 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
666 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
667}
668
669static void xhci_restore_registers(struct xhci_hcd *xhci)
670{
671 xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
672 xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
673 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
674 xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
675 xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
676 xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
677 xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
678 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
679}
680
89821320
SS		 681static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
682{
683 u64 val_64;
684
685 /* step 2: initialize command ring buffer */
686 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
687 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
688 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
689 xhci->cmd_ring->dequeue) &
690 (u64) ~CMD_RING_RSVD_BITS) |
691 xhci->cmd_ring->cycle_state;
692 xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
693 (long unsigned long) val_64);
694 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
695}
696
697/*
698 * The whole command ring must be cleared to zero when we suspend the host.
699 *
700 * The host doesn't save the command ring pointer in the suspend well, so we
701 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
702 * aligned, because of the reserved bits in the command ring dequeue pointer
703 * register. Therefore, we can't just set the dequeue pointer back in the
704 * middle of the ring (TRBs are 16-byte aligned).
705 */
706static void xhci_clear_command_ring(struct xhci_hcd *xhci)
707{
708 struct xhci_ring *ring;
709 struct xhci_segment *seg;
710
711 ring = xhci->cmd_ring;
712 seg = ring->deq_seg;
713 do {
158886cd
AX		 714 memset(seg->trbs, 0,
715 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
716 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
717 cpu_to_le32(~TRB_CYCLE);
89821320
SS		 718 seg = seg->next;
719 } while (seg != ring->deq_seg);
720
721 /* Reset the software enqueue and dequeue pointers */
722 ring->deq_seg = ring->first_seg;
723 ring->dequeue = ring->first_seg->trbs;
724 ring->enq_seg = ring->deq_seg;
725 ring->enqueue = ring->dequeue;
726
727 /*
728 * Ring is now zeroed, so the HW should look for change of ownership
729 * when the cycle bit is set to 1.
730 */
731 ring->cycle_state = 1;
732
733 /*
734 * Reset the hardware dequeue pointer.
735 * Yes, this will need to be re-written after resume, but we're paranoid
736 * and want to make sure the hardware doesn't access bogus memory
737 * because, say, the BIOS or an SMI started the host without changing
738 * the command ring pointers.
739 */
740 xhci_set_cmd_ring_deq(xhci);
741}
742
5535b1d5
AX		 743/*
744 * Stop HC (not bus-specific)
745 *
746 * This is called when the machine transition into S3/S4 mode.
747 *
748 */
749int xhci_suspend(struct xhci_hcd *xhci)
750{
751 int rc = 0;
752 struct usb_hcd *hcd = xhci_to_hcd(xhci);
753 u32 command;
754
755 spin_lock_irq(&xhci->lock);
756 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
b3209379 757 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
5535b1d5
AX		 758 /* step 1: stop endpoint */
759 /* skipped assuming that port suspend has done */
760
761 /* step 2: clear Run/Stop bit */
762 command = xhci_readl(xhci, &xhci->op_regs->command);
763 command &= ~CMD_RUN;
764 xhci_writel(xhci, command, &xhci->op_regs->command);
765 if (handshake(xhci, &xhci->op_regs->status,
766 STS_HALT, STS_HALT, 100*100)) {
767 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
768 spin_unlock_irq(&xhci->lock);
769 return -ETIMEDOUT;
770 }
89821320 771 xhci_clear_command_ring(xhci);
5535b1d5
AX		 772
773 /* step 3: save registers */
774 xhci_save_registers(xhci);
775
776 /* step 4: set CSS flag */
777 command = xhci_readl(xhci, &xhci->op_regs->command);
778 command |= CMD_CSS;
779 xhci_writel(xhci, command, &xhci->op_regs->command);
780 if (handshake(xhci, &xhci->op_regs->status, STS_SAVE, 0, 10*100)) {
781 xhci_warn(xhci, "WARN: xHC CMD_CSS timeout\n");
782 spin_unlock_irq(&xhci->lock);
783 return -ETIMEDOUT;
784 }
5535b1d5
AX		 785 spin_unlock_irq(&xhci->lock);
786
0029227f
AX		 787 /* step 5: remove core well power */
788 /* synchronize irq when using MSI-X */
421aa841 789 xhci_msix_sync_irqs(xhci);
0029227f 790
5535b1d5
AX		 791 return rc;
792}
793
794/*
795 * start xHC (not bus-specific)
796 *
797 * This is called when the machine transition from S3/S4 mode.
798 *
799 */
800int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
801{
802 u32 command, temp = 0;
803 struct usb_hcd *hcd = xhci_to_hcd(xhci);
65b22f93 804 struct usb_hcd *secondary_hcd;
f69e3120 805 int retval = 0;
5535b1d5 806
f6ff0ac8 807 /* Wait a bit if either of the roothubs need to settle from the
25985edc 808 * transition into bus suspend.
20b67cf5 809 */
f6ff0ac8
SS		 810 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
811 time_before(jiffies,
812 xhci->bus_state[1].next_statechange))
5535b1d5
AX		 813 msleep(100);
814
f69e3120
AS		 815 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
816 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
817
5535b1d5 818 spin_lock_irq(&xhci->lock);
c877b3b2
ML		 819 if (xhci->quirks & XHCI_RESET_ON_RESUME)
820 hibernated = true;
5535b1d5
AX		 821
822 if (!hibernated) {
823 /* step 1: restore register */
824 xhci_restore_registers(xhci);
825 /* step 2: initialize command ring buffer */
89821320 826 xhci_set_cmd_ring_deq(xhci);
5535b1d5
AX		 827 /* step 3: restore state and start state*/
828 /* step 3: set CRS flag */
829 command = xhci_readl(xhci, &xhci->op_regs->command);
830 command |= CMD_CRS;
831 xhci_writel(xhci, command, &xhci->op_regs->command);
832 if (handshake(xhci, &xhci->op_regs->status,
833 STS_RESTORE, 0, 10*100)) {
834 xhci_dbg(xhci, "WARN: xHC CMD_CSS timeout\n");
835 spin_unlock_irq(&xhci->lock);
836 return -ETIMEDOUT;
837 }
838 temp = xhci_readl(xhci, &xhci->op_regs->status);
839 }
840
841 /* If restore operation fails, re-initialize the HC during resume */
842 if ((temp & STS_SRE) || hibernated) {
fedd383e
SS		 843 /* Let the USB core know _both_ roothubs lost power. */
844 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
845 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
5535b1d5
AX		 846
847 xhci_dbg(xhci, "Stop HCD\n");
848 xhci_halt(xhci);
849 xhci_reset(xhci);
5535b1d5 850 spin_unlock_irq(&xhci->lock);
0029227f 851 xhci_cleanup_msix(xhci);
5535b1d5
AX		 852
853#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
854 /* Tell the event ring poll function not to reschedule */
855 xhci->zombie = 1;
856 del_timer_sync(&xhci->event_ring_timer);
857#endif
858
859 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
860 temp = xhci_readl(xhci, &xhci->op_regs->status);
861 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
862 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
863 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
864 &xhci->ir_set->irq_pending);
09ece30e 865 xhci_print_ir_set(xhci, 0);
5535b1d5
AX		 866
867 xhci_dbg(xhci, "cleaning up memory\n");
868 xhci_mem_cleanup(xhci);
869 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
870 xhci_readl(xhci, &xhci->op_regs->status));
871
65b22f93
SS		 872 /* USB core calls the PCI reinit and start functions twice:
873 * first with the primary HCD, and then with the secondary HCD.
874 * If we don't do the same, the host will never be started.
875 */
876 if (!usb_hcd_is_primary_hcd(hcd))
877 secondary_hcd = hcd;
878 else
879 secondary_hcd = xhci->shared_hcd;
880
881 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
882 retval = xhci_init(hcd->primary_hcd);
5535b1d5
AX		 883 if (retval)
884 return retval;
65b22f93
SS		 885 xhci_dbg(xhci, "Start the primary HCD\n");
886 retval = xhci_run(hcd->primary_hcd);
b3209379 887 if (!retval) {
f69e3120
AS		 888 xhci_dbg(xhci, "Start the secondary HCD\n");
889 retval = xhci_run(secondary_hcd);
b3209379 890 }
5535b1d5 891 hcd->state = HC_STATE_SUSPENDED;
b3209379 892 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
f69e3120 893 goto done;
5535b1d5
AX		 894 }
895
5535b1d5
AX		 896 /* step 4: set Run/Stop bit */
897 command = xhci_readl(xhci, &xhci->op_regs->command);
898 command |= CMD_RUN;
899 xhci_writel(xhci, command, &xhci->op_regs->command);
900 handshake(xhci, &xhci->op_regs->status, STS_HALT,
901 0, 250 * 1000);
902
903 /* step 5: walk topology and initialize portsc,
904 * portpmsc and portli
905 */
906 /* this is done in bus_resume */
907
908 /* step 6: restart each of the previously
909 * Running endpoints by ringing their doorbells
910 */
911
5535b1d5 912 spin_unlock_irq(&xhci->lock);
f69e3120
AS		 913
914 done:
915 if (retval == 0) {
916 usb_hcd_resume_root_hub(hcd);
917 usb_hcd_resume_root_hub(xhci->shared_hcd);
918 }
919 return retval;
5535b1d5 920}
b5b5c3ac
SS		 921#endif /* CONFIG_PM */
922
7f84eef0
SS		 923/*-------------------------------------------------------------------------*/
924
d0e96f5a
SS		 925/**
926 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
927 * HCDs. Find the index for an endpoint given its descriptor. Use the return
928 * value to right shift 1 for the bitmask.
929 *
930 * Index = (epnum * 2) + direction - 1,
931 * where direction = 0 for OUT, 1 for IN.
932 * For control endpoints, the IN index is used (OUT index is unused), so
933 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
934 */
935unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
936{
937 unsigned int index;
938 if (usb_endpoint_xfer_control(desc))
939 index = (unsigned int) (usb_endpoint_num(desc)*2);
940 else
941 index = (unsigned int) (usb_endpoint_num(desc)*2) +
942 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
943 return index;
944}
945
f94e0186
SS		 946/* Find the flag for this endpoint (for use in the control context). Use the
947 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
948 * bit 1, etc.
949 */
950unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
951{
952 return 1 << (xhci_get_endpoint_index(desc) + 1);
953}
954
ac9d8fe7
SS		 955/* Find the flag for this endpoint (for use in the control context). Use the
956 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
957 * bit 1, etc.
958 */
959unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
960{
961 return 1 << (ep_index + 1);
962}
963
f94e0186
SS		 964/* Compute the last valid endpoint context index. Basically, this is the
965 * endpoint index plus one. For slot contexts with more than valid endpoint,
966 * we find the most significant bit set in the added contexts flags.
967 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
968 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
969 */
ac9d8fe7 970unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
f94e0186
SS		 971{
972 return fls(added_ctxs) - 1;
973}
974
d0e96f5a
SS		 975/* Returns 1 if the arguments are OK;
976 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
977 */
8212a49d 978static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
64927730
AX		 979 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
980 const char *func) {
981 struct xhci_hcd *xhci;
982 struct xhci_virt_device *virt_dev;
983
d0e96f5a
SS		 984 if (!hcd || (check_ep && !ep) || !udev) {
985 printk(KERN_DEBUG "xHCI %s called with invalid args\n",
986 func);
987 return -EINVAL;
988 }
989 if (!udev->parent) {
990 printk(KERN_DEBUG "xHCI %s called for root hub\n",
991 func);
992 return 0;
993 }
64927730 994
7bd89b40
SS		 995 xhci = hcd_to_xhci(hcd);
996 if (xhci->xhc_state & XHCI_STATE_HALTED)
997 return -ENODEV;
998
64927730 999 if (check_virt_dev) {
73ddc247 1000 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
64927730
AX		 1001 printk(KERN_DEBUG "xHCI %s called with unaddressed "
1002 "device\n", func);
1003 return -EINVAL;
1004 }
1005
1006 virt_dev = xhci->devs[udev->slot_id];
1007 if (virt_dev->udev != udev) {
1008 printk(KERN_DEBUG "xHCI %s called with udev and "
1009 "virt_dev does not match\n", func);
1010 return -EINVAL;
1011 }
d0e96f5a 1012 }
64927730 1013
d0e96f5a
SS		 1014 return 1;
1015}
1016
2d3f1fac 1017static int xhci_configure_endpoint(struct xhci_hcd *xhci,
913a8a34
SS		 1018 struct usb_device *udev, struct xhci_command *command,
1019 bool ctx_change, bool must_succeed);
2d3f1fac
SS		 1020
1021/*
1022 * Full speed devices may have a max packet size greater than 8 bytes, but the
1023 * USB core doesn't know that until it reads the first 8 bytes of the
1024 * descriptor. If the usb_device's max packet size changes after that point,
1025 * we need to issue an evaluate context command and wait on it.
1026 */
1027static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1028 unsigned int ep_index, struct urb *urb)
1029{
1030 struct xhci_container_ctx *in_ctx;
1031 struct xhci_container_ctx *out_ctx;
1032 struct xhci_input_control_ctx *ctrl_ctx;
1033 struct xhci_ep_ctx *ep_ctx;
1034 int max_packet_size;
1035 int hw_max_packet_size;
1036 int ret = 0;
1037
1038 out_ctx = xhci->devs[slot_id]->out_ctx;
1039 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
28ccd296 1040 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
29cc8897 1041 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
2d3f1fac
SS		 1042 if (hw_max_packet_size != max_packet_size) {
1043 xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
1044 xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
1045 max_packet_size);
1046 xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
1047 hw_max_packet_size);
1048 xhci_dbg(xhci, "Issuing evaluate context command.\n");
1049
1050 /* Set up the modified control endpoint 0 */
913a8a34
SS		 1051 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1052 xhci->devs[slot_id]->out_ctx, ep_index);
2d3f1fac
SS		 1053 in_ctx = xhci->devs[slot_id]->in_ctx;
1054 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
28ccd296
ME		 1055 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1056 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
2d3f1fac
SS		 1057
1058 /* Set up the input context flags for the command */
1059 /* FIXME: This won't work if a non-default control endpoint
1060 * changes max packet sizes.
1061 */
1062 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
28ccd296 1063 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
2d3f1fac
SS		 1064 ctrl_ctx->drop_flags = 0;
1065
1066 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1067 xhci_dbg_ctx(xhci, in_ctx, ep_index);
1068 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1069 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1070
913a8a34
SS		 1071 ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
1072 true, false);
2d3f1fac
SS		 1073
1074 /* Clean up the input context for later use by bandwidth
1075 * functions.
1076 */
28ccd296 1077 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
2d3f1fac
SS		 1078 }
1079 return ret;
1080}
1081
d0e96f5a
SS		 1082/*
1083 * non-error returns are a promise to giveback() the urb later
1084 * we drop ownership so next owner (or urb unlink) can get it
1085 */
1086int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1087{
1088 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2ffdea25 1089 struct xhci_td *buffer;
d0e96f5a
SS		 1090 unsigned long flags;
1091 int ret = 0;
1092 unsigned int slot_id, ep_index;
8e51adcc
AX		 1093 struct urb_priv *urb_priv;
1094 int size, i;
2d3f1fac 1095
64927730
AX		 1096 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1097 true, true, __func__) <= 0)
d0e96f5a
SS		 1098 return -EINVAL;
1099
1100 slot_id = urb->dev->slot_id;
1101 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
d0e96f5a 1102
541c7d43 1103 if (!HCD_HW_ACCESSIBLE(hcd)) {
d0e96f5a
SS		 1104 if (!in_interrupt())
1105 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1106 ret = -ESHUTDOWN;
1107 goto exit;
1108 }
8e51adcc
AX		 1109
1110 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1111 size = urb->number_of_packets;
1112 else
1113 size = 1;
1114
1115 urb_priv = kzalloc(sizeof(struct urb_priv) +
1116 size * sizeof(struct xhci_td *), mem_flags);
1117 if (!urb_priv)
1118 return -ENOMEM;
1119
2ffdea25
AX		 1120 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1121 if (!buffer) {
1122 kfree(urb_priv);
1123 return -ENOMEM;
1124 }
1125
8e51adcc 1126 for (i = 0; i < size; i++) {
2ffdea25
AX		 1127 urb_priv->td[i] = buffer;
1128 buffer++;
8e51adcc
AX		 1129 }
1130
1131 urb_priv->length = size;
1132 urb_priv->td_cnt = 0;
1133 urb->hcpriv = urb_priv;
1134
2d3f1fac
SS		 1135 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1136 /* Check to see if the max packet size for the default control
1137 * endpoint changed during FS device enumeration
1138 */
1139 if (urb->dev->speed == USB_SPEED_FULL) {
1140 ret = xhci_check_maxpacket(xhci, slot_id,
1141 ep_index, urb);
d13565c1
SS		 1142 if (ret < 0) {
1143 xhci_urb_free_priv(xhci, urb_priv);
1144 urb->hcpriv = NULL;
2d3f1fac 1145 return ret;
d13565c1 1146 }
2d3f1fac
SS		 1147 }
1148
b11069f5
SS		 1149 /* We have a spinlock and interrupts disabled, so we must pass
1150 * atomic context to this function, which may allocate memory.
1151 */
2d3f1fac 1152 spin_lock_irqsave(&xhci->lock, flags);
6f5165cf
SS		 1153 if (xhci->xhc_state & XHCI_STATE_DYING)
1154 goto dying;
b11069f5 1155 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
23e3be11 1156 slot_id, ep_index);
d13565c1
SS		 1157 if (ret)
1158 goto free_priv;
2d3f1fac
SS		 1159 spin_unlock_irqrestore(&xhci->lock, flags);
1160 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1161 spin_lock_irqsave(&xhci->lock, flags);
6f5165cf
SS		 1162 if (xhci->xhc_state & XHCI_STATE_DYING)
1163 goto dying;
8df75f42
SS		 1164 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1165 EP_GETTING_STREAMS) {
1166 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1167 "is transitioning to using streams.\n");
1168 ret = -EINVAL;
1169 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1170 EP_GETTING_NO_STREAMS) {
1171 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1172 "is transitioning to "
1173 "not having streams.\n");
1174 ret = -EINVAL;
1175 } else {
1176 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1177 slot_id, ep_index);
1178 }
d13565c1
SS		 1179 if (ret)
1180 goto free_priv;
2d3f1fac 1181 spin_unlock_irqrestore(&xhci->lock, flags);
624defa1
SS		 1182 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1183 spin_lock_irqsave(&xhci->lock, flags);
6f5165cf
SS		 1184 if (xhci->xhc_state & XHCI_STATE_DYING)
1185 goto dying;
624defa1
SS		 1186 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1187 slot_id, ep_index);
d13565c1
SS		 1188 if (ret)
1189 goto free_priv;
624defa1 1190 spin_unlock_irqrestore(&xhci->lock, flags);
2d3f1fac 1191 } else {
787f4e5a
AX		 1192 spin_lock_irqsave(&xhci->lock, flags);
1193 if (xhci->xhc_state & XHCI_STATE_DYING)
1194 goto dying;
1195 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1196 slot_id, ep_index);
d13565c1
SS		 1197 if (ret)
1198 goto free_priv;
787f4e5a 1199 spin_unlock_irqrestore(&xhci->lock, flags);
2d3f1fac 1200 }
d0e96f5a 1201exit:
d0e96f5a 1202 return ret;
6f5165cf
SS		 1203dying:
1204 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1205 "non-responsive xHCI host.\n",
1206 urb->ep->desc.bEndpointAddress, urb);
d13565c1
SS		 1207 ret = -ESHUTDOWN;
1208free_priv:
1209 xhci_urb_free_priv(xhci, urb_priv);
1210 urb->hcpriv = NULL;
6f5165cf 1211 spin_unlock_irqrestore(&xhci->lock, flags);
d13565c1 1212 return ret;
d0e96f5a
SS		 1213}
1214
021bff91
SS		 1215/* Get the right ring for the given URB.
1216 * If the endpoint supports streams, boundary check the URB's stream ID.
1217 * If the endpoint doesn't support streams, return the singular endpoint ring.
1218 */
1219static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1220 struct urb *urb)
1221{
1222 unsigned int slot_id;
1223 unsigned int ep_index;
1224 unsigned int stream_id;
1225 struct xhci_virt_ep *ep;
1226
1227 slot_id = urb->dev->slot_id;
1228 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1229 stream_id = urb->stream_id;
1230 ep = &xhci->devs[slot_id]->eps[ep_index];
1231 /* Common case: no streams */
1232 if (!(ep->ep_state & EP_HAS_STREAMS))
1233 return ep->ring;
1234
1235 if (stream_id == 0) {
1236 xhci_warn(xhci,
1237 "WARN: Slot ID %u, ep index %u has streams, "
1238 "but URB has no stream ID.\n",
1239 slot_id, ep_index);
1240 return NULL;
1241 }
1242
1243 if (stream_id < ep->stream_info->num_streams)
1244 return ep->stream_info->stream_rings[stream_id];
1245
1246 xhci_warn(xhci,
1247 "WARN: Slot ID %u, ep index %u has "
1248 "stream IDs 1 to %u allocated, "
1249 "but stream ID %u is requested.\n",
1250 slot_id, ep_index,
1251 ep->stream_info->num_streams - 1,
1252 stream_id);
1253 return NULL;
1254}
1255
ae636747
SS		 1256/*
1257 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1258 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1259 * should pick up where it left off in the TD, unless a Set Transfer Ring
1260 * Dequeue Pointer is issued.
1261 *
1262 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1263 * the ring. Since the ring is a contiguous structure, they can't be physically
1264 * removed. Instead, there are two options:
1265 *
1266 * 1) If the HC is in the middle of processing the URB to be canceled, we
1267 * simply move the ring's dequeue pointer past those TRBs using the Set
1268 * Transfer Ring Dequeue Pointer command. This will be the common case,
1269 * when drivers timeout on the last submitted URB and attempt to cancel.
1270 *
1271 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1272 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1273 * HC will need to invalidate the any TRBs it has cached after the stop
1274 * endpoint command, as noted in the xHCI 0.95 errata.
1275 *
1276 * 3) The TD may have completed by the time the Stop Endpoint Command
1277 * completes, so software needs to handle that case too.
1278 *
1279 * This function should protect against the TD enqueueing code ringing the
1280 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1281 * It also needs to account for multiple cancellations on happening at the same
1282 * time for the same endpoint.
1283 *
1284 * Note that this function can be called in any context, or so says
1285 * usb_hcd_unlink_urb()
d0e96f5a
SS		 1286 */
1287int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1288{
ae636747 1289 unsigned long flags;
8e51adcc 1290 int ret, i;
e34b2fbf 1291 u32 temp;
ae636747 1292 struct xhci_hcd *xhci;
8e51adcc 1293 struct urb_priv *urb_priv;
ae636747
SS		 1294 struct xhci_td *td;
1295 unsigned int ep_index;
1296 struct xhci_ring *ep_ring;
63a0d9ab 1297 struct xhci_virt_ep *ep;
ae636747
SS		 1298
1299 xhci = hcd_to_xhci(hcd);
1300 spin_lock_irqsave(&xhci->lock, flags);
1301 /* Make sure the URB hasn't completed or been unlinked already */
1302 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1303 if (ret || !urb->hcpriv)
1304 goto done;
e34b2fbf 1305 temp = xhci_readl(xhci, &xhci->op_regs->status);
c6cc27c7 1306 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
e34b2fbf 1307 xhci_dbg(xhci, "HW died, freeing TD.\n");
8e51adcc 1308 urb_priv = urb->hcpriv;
585df1d9
SS		 1309 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1310 td = urb_priv->td[i];
1311 if (!list_empty(&td->td_list))
1312 list_del_init(&td->td_list);
1313 if (!list_empty(&td->cancelled_td_list))
1314 list_del_init(&td->cancelled_td_list);
1315 }
e34b2fbf
SS		 1316
1317 usb_hcd_unlink_urb_from_ep(hcd, urb);
1318 spin_unlock_irqrestore(&xhci->lock, flags);
214f76f7 1319 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
8e51adcc 1320 xhci_urb_free_priv(xhci, urb_priv);
e34b2fbf
SS		 1321 return ret;
1322 }
7bd89b40
SS		 1323 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1324 (xhci->xhc_state & XHCI_STATE_HALTED)) {
6f5165cf
SS		 1325 xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
1326 "non-responsive xHCI host.\n",
1327 urb->ep->desc.bEndpointAddress, urb);
1328 /* Let the stop endpoint command watchdog timer (which set this
1329 * state) finish cleaning up the endpoint TD lists. We must
1330 * have caught it in the middle of dropping a lock and giving
1331 * back an URB.
1332 */
1333 goto done;
1334 }
ae636747 1335
ae636747 1336 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
63a0d9ab 1337 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
e9df17eb
SS		 1338 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1339 if (!ep_ring) {
1340 ret = -EINVAL;
1341 goto done;
1342 }
1343
8e51adcc 1344 urb_priv = urb->hcpriv;
79688acf
SS		 1345 i = urb_priv->td_cnt;
1346 if (i < urb_priv->length)
1347 xhci_dbg(xhci, "Cancel URB %p, dev %s, ep 0x%x, "
1348 "starting at offset 0x%llx\n",
1349 urb, urb->dev->devpath,
1350 urb->ep->desc.bEndpointAddress,
1351 (unsigned long long) xhci_trb_virt_to_dma(
1352 urb_priv->td[i]->start_seg,
1353 urb_priv->td[i]->first_trb));
1354
1355 for (; i < urb_priv->length; i++) {
8e51adcc
AX		 1356 td = urb_priv->td[i];
1357 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1358 }
1359
ae636747
SS		 1360 /* Queue a stop endpoint command, but only if this is
1361 * the first cancellation to be handled.
1362 */
678539cf
SS		 1363 if (!(ep->ep_state & EP_HALT_PENDING)) {
1364 ep->ep_state |= EP_HALT_PENDING;
6f5165cf
SS		 1365 ep->stop_cmds_pending++;
1366 ep->stop_cmd_timer.expires = jiffies +
1367 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1368 add_timer(&ep->stop_cmd_timer);
be88fe4f 1369 xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
23e3be11 1370 xhci_ring_cmd_db(xhci);
ae636747
SS		 1371 }
1372done:
1373 spin_unlock_irqrestore(&xhci->lock, flags);
1374 return ret;
d0e96f5a
SS		 1375}
1376
f94e0186
SS		 1377/* Drop an endpoint from a new bandwidth configuration for this device.
1378 * Only one call to this function is allowed per endpoint before
1379 * check_bandwidth() or reset_bandwidth() must be called.
1380 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1381 * add the endpoint to the schedule with possibly new parameters denoted by a
1382 * different endpoint descriptor in usb_host_endpoint.
1383 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1384 * not allowed.
f88ba78d
SS		 1385 *
1386 * The USB core will not allow URBs to be queued to an endpoint that is being
1387 * disabled, so there's no need for mutual exclusion to protect
1388 * the xhci->devs[slot_id] structure.
f94e0186
SS		 1389 */
1390int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1391 struct usb_host_endpoint *ep)
1392{
f94e0186 1393 struct xhci_hcd *xhci;
d115b048
JY		 1394 struct xhci_container_ctx *in_ctx, *out_ctx;
1395 struct xhci_input_control_ctx *ctrl_ctx;
1396 struct xhci_slot_ctx *slot_ctx;
f94e0186
SS		 1397 unsigned int last_ctx;
1398 unsigned int ep_index;
1399 struct xhci_ep_ctx *ep_ctx;
1400 u32 drop_flag;
1401 u32 new_add_flags, new_drop_flags, new_slot_info;
1402 int ret;
1403
64927730 1404 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
f94e0186
SS		 1405 if (ret <= 0)
1406 return ret;
1407 xhci = hcd_to_xhci(hcd);
fe6c6c13
SS		 1408 if (xhci->xhc_state & XHCI_STATE_DYING)
1409 return -ENODEV;
f94e0186 1410
fe6c6c13 1411 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
f94e0186
SS		 1412 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1413 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1414 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1415 __func__, drop_flag);
1416 return 0;
1417 }
1418
f94e0186 1419 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
d115b048
JY		 1420 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1421 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
f94e0186 1422 ep_index = xhci_get_endpoint_index(&ep->desc);
d115b048 1423 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
f94e0186
SS		 1424 /* If the HC already knows the endpoint is disabled,
1425 * or the HCD has noted it is disabled, ignore this request
1426 */
f5960b69
ME		 1427 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1428 cpu_to_le32(EP_STATE_DISABLED)) ||
28ccd296
ME		 1429 le32_to_cpu(ctrl_ctx->drop_flags) &
1430 xhci_get_endpoint_flag(&ep->desc)) {
700e2052
GKH		 1431 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1432 __func__, ep);
f94e0186
SS		 1433 return 0;
1434 }
1435
28ccd296
ME		 1436 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1437 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
f94e0186 1438
28ccd296
ME		 1439 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1440 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
f94e0186 1441
28ccd296 1442 last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
d115b048 1443 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
f94e0186 1444 /* Update the last valid endpoint context, if we deleted the last one */
28ccd296
ME		 1445 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
1446 LAST_CTX(last_ctx)) {
1447 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1448 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
f94e0186 1449 }
28ccd296 1450 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
f94e0186
SS		 1451
1452 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1453
f94e0186
SS		 1454 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1455 (unsigned int) ep->desc.bEndpointAddress,
1456 udev->slot_id,
1457 (unsigned int) new_drop_flags,
1458 (unsigned int) new_add_flags,
1459 (unsigned int) new_slot_info);
1460 return 0;
1461}
1462
1463/* Add an endpoint to a new possible bandwidth configuration for this device.
1464 * Only one call to this function is allowed per endpoint before
1465 * check_bandwidth() or reset_bandwidth() must be called.
1466 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1467 * add the endpoint to the schedule with possibly new parameters denoted by a
1468 * different endpoint descriptor in usb_host_endpoint.
1469 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1470 * not allowed.
f88ba78d
SS		 1471 *
1472 * The USB core will not allow URBs to be queued to an endpoint until the
1473 * configuration or alt setting is installed in the device, so there's no need
1474 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
f94e0186
SS		 1475 */
1476int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1477 struct usb_host_endpoint *ep)
1478{
f94e0186 1479 struct xhci_hcd *xhci;
d115b048 1480 struct xhci_container_ctx *in_ctx, *out_ctx;
f94e0186
SS		 1481 unsigned int ep_index;
1482 struct xhci_ep_ctx *ep_ctx;
d115b048
JY		 1483 struct xhci_slot_ctx *slot_ctx;
1484 struct xhci_input_control_ctx *ctrl_ctx;
f94e0186
SS		 1485 u32 added_ctxs;
1486 unsigned int last_ctx;
1487 u32 new_add_flags, new_drop_flags, new_slot_info;
fa75ac37 1488 struct xhci_virt_device *virt_dev;
f94e0186
SS		 1489 int ret = 0;
1490
64927730 1491 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
a1587d97
SS		 1492 if (ret <= 0) {
1493 /* So we won't queue a reset ep command for a root hub */
1494 ep->hcpriv = NULL;
f94e0186 1495 return ret;
a1587d97 1496 }
f94e0186 1497 xhci = hcd_to_xhci(hcd);
fe6c6c13
SS		 1498 if (xhci->xhc_state & XHCI_STATE_DYING)
1499 return -ENODEV;
f94e0186
SS		 1500
1501 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1502 last_ctx = xhci_last_valid_endpoint(added_ctxs);
1503 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1504 /* FIXME when we have to issue an evaluate endpoint command to
1505 * deal with ep0 max packet size changing once we get the
1506 * descriptors
1507 */
1508 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1509 __func__, added_ctxs);
1510 return 0;
1511 }
1512
fa75ac37
SS		 1513 virt_dev = xhci->devs[udev->slot_id];
1514 in_ctx = virt_dev->in_ctx;
1515 out_ctx = virt_dev->out_ctx;
d115b048 1516 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
f94e0186 1517 ep_index = xhci_get_endpoint_index(&ep->desc);
d115b048 1518 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
fa75ac37
SS		 1519
1520 /* If this endpoint is already in use, and the upper layers are trying
1521 * to add it again without dropping it, reject the addition.
1522 */
1523 if (virt_dev->eps[ep_index].ring &&
1524 !(le32_to_cpu(ctrl_ctx->drop_flags) &
1525 xhci_get_endpoint_flag(&ep->desc))) {
1526 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1527 "without dropping it.\n",
1528 (unsigned int) ep->desc.bEndpointAddress);
1529 return -EINVAL;
1530 }
1531
f94e0186
SS		 1532 /* If the HCD has already noted the endpoint is enabled,
1533 * ignore this request.
1534 */
28ccd296
ME		 1535 if (le32_to_cpu(ctrl_ctx->add_flags) &
1536 xhci_get_endpoint_flag(&ep->desc)) {
700e2052
GKH		 1537 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1538 __func__, ep);
f94e0186
SS		 1539 return 0;
1540 }
1541
f88ba78d
SS		 1542 /*
1543 * Configuration and alternate setting changes must be done in
1544 * process context, not interrupt context (or so documenation
1545 * for usb_set_interface() and usb_set_configuration() claim).
1546 */
fa75ac37 1547 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
f94e0186
SS		 1548 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1549 __func__, ep->desc.bEndpointAddress);
f94e0186
SS		 1550 return -ENOMEM;
1551 }
1552
28ccd296
ME		 1553 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1554 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
f94e0186
SS		 1555
1556 /* If xhci_endpoint_disable() was called for this endpoint, but the
1557 * xHC hasn't been notified yet through the check_bandwidth() call,
1558 * this re-adds a new state for the endpoint from the new endpoint
1559 * descriptors. We must drop and re-add this endpoint, so we leave the
1560 * drop flags alone.
1561 */
28ccd296 1562 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
f94e0186 1563
d115b048 1564 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
f94e0186 1565 /* Update the last valid endpoint context, if we just added one past */
28ccd296
ME		 1566 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
1567 LAST_CTX(last_ctx)) {
1568 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1569 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
f94e0186 1570 }
28ccd296 1571 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
f94e0186 1572
a1587d97
SS		 1573 /* Store the usb_device pointer for later use */
1574 ep->hcpriv = udev;
1575
f94e0186
SS		 1576 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1577 (unsigned int) ep->desc.bEndpointAddress,
1578 udev->slot_id,
1579 (unsigned int) new_drop_flags,
1580 (unsigned int) new_add_flags,
1581 (unsigned int) new_slot_info);
1582 return 0;
1583}
1584
d115b048 1585static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
f94e0186 1586{
d115b048 1587 struct xhci_input_control_ctx *ctrl_ctx;
f94e0186 1588 struct xhci_ep_ctx *ep_ctx;
d115b048 1589 struct xhci_slot_ctx *slot_ctx;
f94e0186
SS		 1590 int i;
1591
1592 /* When a device's add flag and drop flag are zero, any subsequent
1593 * configure endpoint command will leave that endpoint's state
1594 * untouched. Make sure we don't leave any old state in the input
1595 * endpoint contexts.
1596 */
d115b048
JY		 1597 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1598 ctrl_ctx->drop_flags = 0;
1599 ctrl_ctx->add_flags = 0;
1600 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
28ccd296 1601 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
f94e0186 1602 /* Endpoint 0 is always valid */
28ccd296 1603 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
f94e0186 1604 for (i = 1; i < 31; ++i) {
d115b048 1605 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
f94e0186
SS		 1606 ep_ctx->ep_info = 0;
1607 ep_ctx->ep_info2 = 0;
8e595a5d 1608 ep_ctx->deq = 0;
f94e0186
SS		 1609 ep_ctx->tx_info = 0;
1610 }
1611}
1612
f2217e8e 1613static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
00161f7d 1614 struct usb_device *udev, u32 *cmd_status)
f2217e8e
SS		 1615{
1616 int ret;
1617
913a8a34 1618 switch (*cmd_status) {
f2217e8e
SS		 1619 case COMP_ENOMEM:
1620 dev_warn(&udev->dev, "Not enough host controller resources "
1621 "for new device state.\n");
1622 ret = -ENOMEM;
1623 /* FIXME: can we allocate more resources for the HC? */
1624 break;
1625 case COMP_BW_ERR:
1626 dev_warn(&udev->dev, "Not enough bandwidth "
1627 "for new device state.\n");
1628 ret = -ENOSPC;
1629 /* FIXME: can we go back to the old state? */
1630 break;
1631 case COMP_TRB_ERR:
1632 /* the HCD set up something wrong */
1633 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1634 "add flag = 1, "
1635 "and endpoint is not disabled.\n");
1636 ret = -EINVAL;
1637 break;
f6ba6fe2
AH		 1638 case COMP_DEV_ERR:
1639 dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint "
1640 "configure command.\n");
1641 ret = -ENODEV;
1642 break;
f2217e8e
SS		 1643 case COMP_SUCCESS:
1644 dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
1645 ret = 0;
1646 break;
1647 default:
1648 xhci_err(xhci, "ERROR: unexpected command completion "
913a8a34 1649 "code 0x%x.\n", *cmd_status);
f2217e8e
SS		 1650 ret = -EINVAL;
1651 break;
1652 }
1653 return ret;
1654}
1655
1656static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
00161f7d 1657 struct usb_device *udev, u32 *cmd_status)
f2217e8e
SS		 1658{
1659 int ret;
913a8a34 1660 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
f2217e8e 1661
913a8a34 1662 switch (*cmd_status) {
f2217e8e
SS		 1663 case COMP_EINVAL:
1664 dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
1665 "context command.\n");
1666 ret = -EINVAL;
1667 break;
1668 case COMP_EBADSLT:
1669 dev_warn(&udev->dev, "WARN: slot not enabled for"
1670 "evaluate context command.\n");
1671 case COMP_CTX_STATE:
1672 dev_warn(&udev->dev, "WARN: invalid context state for "
1673 "evaluate context command.\n");
1674 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1675 ret = -EINVAL;
1676 break;
f6ba6fe2
AH		 1677 case COMP_DEV_ERR:
1678 dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate "
1679 "context command.\n");
1680 ret = -ENODEV;
1681 break;
1bb73a88
AH		 1682 case COMP_MEL_ERR:
1683 /* Max Exit Latency too large error */
1684 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1685 ret = -EINVAL;
1686 break;
f2217e8e
SS		 1687 case COMP_SUCCESS:
1688 dev_dbg(&udev->dev, "Successful evaluate context command\n");
1689 ret = 0;
1690 break;
1691 default:
1692 xhci_err(xhci, "ERROR: unexpected command completion "
913a8a34 1693 "code 0x%x.\n", *cmd_status);
f2217e8e
SS		 1694 ret = -EINVAL;
1695 break;
1696 }
1697 return ret;
1698}
1699
2cf95c18
SS		 1700static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1701 struct xhci_container_ctx *in_ctx)
1702{
1703 struct xhci_input_control_ctx *ctrl_ctx;
1704 u32 valid_add_flags;
1705 u32 valid_drop_flags;
1706
1707 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1708 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1709 * (bit 1). The default control endpoint is added during the Address
1710 * Device command and is never removed until the slot is disabled.
1711 */
1712 valid_add_flags = ctrl_ctx->add_flags >> 2;
1713 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1714
1715 /* Use hweight32 to count the number of ones in the add flags, or
1716 * number of endpoints added. Don't count endpoints that are changed
1717 * (both added and dropped).
1718 */
1719 return hweight32(valid_add_flags) -
1720 hweight32(valid_add_flags & valid_drop_flags);
1721}
1722
1723static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1724 struct xhci_container_ctx *in_ctx)
1725{
1726 struct xhci_input_control_ctx *ctrl_ctx;
1727 u32 valid_add_flags;
1728 u32 valid_drop_flags;
1729
1730 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1731 valid_add_flags = ctrl_ctx->add_flags >> 2;
1732 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1733
1734 return hweight32(valid_drop_flags) -
1735 hweight32(valid_add_flags & valid_drop_flags);
1736}
1737
1738/*
1739 * We need to reserve the new number of endpoints before the configure endpoint
1740 * command completes. We can't subtract the dropped endpoints from the number
1741 * of active endpoints until the command completes because we can oversubscribe
1742 * the host in this case:
1743 *
1744 * - the first configure endpoint command drops more endpoints than it adds
1745 * - a second configure endpoint command that adds more endpoints is queued
1746 * - the first configure endpoint command fails, so the config is unchanged
1747 * - the second command may succeed, even though there isn't enough resources
1748 *
1749 * Must be called with xhci->lock held.
1750 */
1751static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1752 struct xhci_container_ctx *in_ctx)
1753{
1754 u32 added_eps;
1755
1756 added_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1757 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1758 xhci_dbg(xhci, "Not enough ep ctxs: "
1759 "%u active, need to add %u, limit is %u.\n",
1760 xhci->num_active_eps, added_eps,
1761 xhci->limit_active_eps);
1762 return -ENOMEM;
1763 }
1764 xhci->num_active_eps += added_eps;
1765 xhci_dbg(xhci, "Adding %u ep ctxs, %u now active.\n", added_eps,
1766 xhci->num_active_eps);
1767 return 0;
1768}
1769
1770/*
1771 * The configure endpoint was failed by the xHC for some other reason, so we
1772 * need to revert the resources that failed configuration would have used.
1773 *
1774 * Must be called with xhci->lock held.
1775 */
1776static void xhci_free_host_resources(struct xhci_hcd *xhci,
1777 struct xhci_container_ctx *in_ctx)
1778{
1779 u32 num_failed_eps;
1780
1781 num_failed_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1782 xhci->num_active_eps -= num_failed_eps;
1783 xhci_dbg(xhci, "Removing %u failed ep ctxs, %u now active.\n",
1784 num_failed_eps,
1785 xhci->num_active_eps);
1786}
1787
1788/*
1789 * Now that the command has completed, clean up the active endpoint count by
1790 * subtracting out the endpoints that were dropped (but not changed).
1791 *
1792 * Must be called with xhci->lock held.
1793 */
1794static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
1795 struct xhci_container_ctx *in_ctx)
1796{
1797 u32 num_dropped_eps;
1798
1799 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, in_ctx);
1800 xhci->num_active_eps -= num_dropped_eps;
1801 if (num_dropped_eps)
1802 xhci_dbg(xhci, "Removing %u dropped ep ctxs, %u now active.\n",
1803 num_dropped_eps,
1804 xhci->num_active_eps);
1805}
1806
c29eea62
SS		 1807unsigned int xhci_get_block_size(struct usb_device *udev)
1808{
1809 switch (udev->speed) {
1810 case USB_SPEED_LOW:
1811 case USB_SPEED_FULL:
1812 return FS_BLOCK;
1813 case USB_SPEED_HIGH:
1814 return HS_BLOCK;
1815 case USB_SPEED_SUPER:
1816 return SS_BLOCK;
1817 case USB_SPEED_UNKNOWN:
1818 case USB_SPEED_WIRELESS:
1819 default:
1820 /* Should never happen */
1821 return 1;
1822 }
1823}
1824
1825unsigned int xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
1826{
1827 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
1828 return LS_OVERHEAD;
1829 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
1830 return FS_OVERHEAD;
1831 return HS_OVERHEAD;
1832}
1833
1834/* If we are changing a LS/FS device under a HS hub,
1835 * make sure (if we are activating a new TT) that the HS bus has enough
1836 * bandwidth for this new TT.
1837 */
1838static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
1839 struct xhci_virt_device *virt_dev,
1840 int old_active_eps)
1841{
1842 struct xhci_interval_bw_table *bw_table;
1843 struct xhci_tt_bw_info *tt_info;
1844
1845 /* Find the bandwidth table for the root port this TT is attached to. */
1846 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
1847 tt_info = virt_dev->tt_info;
1848 /* If this TT already had active endpoints, the bandwidth for this TT
1849 * has already been added. Removing all periodic endpoints (and thus
1850 * making the TT enactive) will only decrease the bandwidth used.
1851 */
1852 if (old_active_eps)
1853 return 0;
1854 if (old_active_eps == 0 && tt_info->active_eps != 0) {
1855 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
1856 return -ENOMEM;
1857 return 0;
1858 }
1859 /* Not sure why we would have no new active endpoints...
1860 *
1861 * Maybe because of an Evaluate Context change for a hub update or a
1862 * control endpoint 0 max packet size change?
1863 * FIXME: skip the bandwidth calculation in that case.
1864 */
1865 return 0;
1866}
1867
2b698999
SS		 1868static int xhci_check_ss_bw(struct xhci_hcd *xhci,
1869 struct xhci_virt_device *virt_dev)
1870{
1871 unsigned int bw_reserved;
1872
1873 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
1874 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
1875 return -ENOMEM;
1876
1877 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
1878 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
1879 return -ENOMEM;
1880
1881 return 0;
1882}
1883
c29eea62
SS		 1884/*
1885 * This algorithm is a very conservative estimate of the worst-case scheduling
1886 * scenario for any one interval. The hardware dynamically schedules the
1887 * packets, so we can't tell which microframe could be the limiting factor in
1888 * the bandwidth scheduling. This only takes into account periodic endpoints.
1889 *
1890 * Obviously, we can't solve an NP complete problem to find the minimum worst
1891 * case scenario. Instead, we come up with an estimate that is no less than
1892 * the worst case bandwidth used for any one microframe, but may be an
1893 * over-estimate.
1894 *
1895 * We walk the requirements for each endpoint by interval, starting with the
1896 * smallest interval, and place packets in the schedule where there is only one
1897 * possible way to schedule packets for that interval. In order to simplify
1898 * this algorithm, we record the largest max packet size for each interval, and
1899 * assume all packets will be that size.
1900 *
1901 * For interval 0, we obviously must schedule all packets for each interval.
1902 * The bandwidth for interval 0 is just the amount of data to be transmitted
1903 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
1904 * the number of packets).
1905 *
1906 * For interval 1, we have two possible microframes to schedule those packets
1907 * in. For this algorithm, if we can schedule the same number of packets for
1908 * each possible scheduling opportunity (each microframe), we will do so. The
1909 * remaining number of packets will be saved to be transmitted in the gaps in
1910 * the next interval's scheduling sequence.
1911 *
1912 * As we move those remaining packets to be scheduled with interval 2 packets,
1913 * we have to double the number of remaining packets to transmit. This is
1914 * because the intervals are actually powers of 2, and we would be transmitting
1915 * the previous interval's packets twice in this interval. We also have to be
1916 * sure that when we look at the largest max packet size for this interval, we
1917 * also look at the largest max packet size for the remaining packets and take
1918 * the greater of the two.
1919 *
1920 * The algorithm continues to evenly distribute packets in each scheduling
1921 * opportunity, and push the remaining packets out, until we get to the last
1922 * interval. Then those packets and their associated overhead are just added
1923 * to the bandwidth used.
2e27980e
SS		 1924 */
1925static int xhci_check_bw_table(struct xhci_hcd *xhci,
1926 struct xhci_virt_device *virt_dev,
1927 int old_active_eps)
1928{
c29eea62
SS		 1929 unsigned int bw_reserved;
1930 unsigned int max_bandwidth;
1931 unsigned int bw_used;
1932 unsigned int block_size;
1933 struct xhci_interval_bw_table *bw_table;
1934 unsigned int packet_size = 0;
1935 unsigned int overhead = 0;
1936 unsigned int packets_transmitted = 0;
1937 unsigned int packets_remaining = 0;
1938 unsigned int i;
1939
2b698999
SS		 1940 if (virt_dev->udev->speed == USB_SPEED_SUPER)
1941 return xhci_check_ss_bw(xhci, virt_dev);
1942
c29eea62
SS		 1943 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
1944 max_bandwidth = HS_BW_LIMIT;
1945 /* Convert percent of bus BW reserved to blocks reserved */
1946 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
1947 } else {
1948 max_bandwidth = FS_BW_LIMIT;
1949 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
1950 }
1951
1952 bw_table = virt_dev->bw_table;
1953 /* We need to translate the max packet size and max ESIT payloads into
1954 * the units the hardware uses.
1955 */
1956 block_size = xhci_get_block_size(virt_dev->udev);
1957
1958 /* If we are manipulating a LS/FS device under a HS hub, double check
1959 * that the HS bus has enough bandwidth if we are activing a new TT.
1960 */
1961 if (virt_dev->tt_info) {
1962 xhci_dbg(xhci, "Recalculating BW for rootport %u\n",
1963 virt_dev->real_port);
1964 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
1965 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
1966 "newly activated TT.\n");
1967 return -ENOMEM;
1968 }
1969 xhci_dbg(xhci, "Recalculating BW for TT slot %u port %u\n",
1970 virt_dev->tt_info->slot_id,
1971 virt_dev->tt_info->ttport);
1972 } else {
1973 xhci_dbg(xhci, "Recalculating BW for rootport %u\n",
1974 virt_dev->real_port);
1975 }
1976
1977 /* Add in how much bandwidth will be used for interval zero, or the
1978 * rounded max ESIT payload + number of packets * largest overhead.
1979 */
1980 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
1981 bw_table->interval_bw[0].num_packets *
1982 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
1983
1984 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
1985 unsigned int bw_added;
1986 unsigned int largest_mps;
1987 unsigned int interval_overhead;
1988
1989 /*
1990 * How many packets could we transmit in this interval?
1991 * If packets didn't fit in the previous interval, we will need
1992 * to transmit that many packets twice within this interval.
1993 */
1994 packets_remaining = 2 * packets_remaining +
1995 bw_table->interval_bw[i].num_packets;
1996
1997 /* Find the largest max packet size of this or the previous
1998 * interval.
1999 */
2000 if (list_empty(&bw_table->interval_bw[i].endpoints))
2001 largest_mps = 0;
2002 else {
2003 struct xhci_virt_ep *virt_ep;
2004 struct list_head *ep_entry;
2005
2006 ep_entry = bw_table->interval_bw[i].endpoints.next;
2007 virt_ep = list_entry(ep_entry,
2008 struct xhci_virt_ep, bw_endpoint_list);
2009 /* Convert to blocks, rounding up */
2010 largest_mps = DIV_ROUND_UP(
2011 virt_ep->bw_info.max_packet_size,
2012 block_size);
2013 }
2014 if (largest_mps > packet_size)
2015 packet_size = largest_mps;
2016
2017 /* Use the larger overhead of this or the previous interval. */
2018 interval_overhead = xhci_get_largest_overhead(
2019 &bw_table->interval_bw[i]);
2020 if (interval_overhead > overhead)
2021 overhead = interval_overhead;
2022
2023 /* How many packets can we evenly distribute across
2024 * (1 << (i + 1)) possible scheduling opportunities?
2025 */
2026 packets_transmitted = packets_remaining >> (i + 1);
2027
2028 /* Add in the bandwidth used for those scheduled packets */
2029 bw_added = packets_transmitted * (overhead + packet_size);
2030
2031 /* How many packets do we have remaining to transmit? */
2032 packets_remaining = packets_remaining % (1 << (i + 1));
2033
2034 /* What largest max packet size should those packets have? */
2035 /* If we've transmitted all packets, don't carry over the
2036 * largest packet size.
2037 */
2038 if (packets_remaining == 0) {
2039 packet_size = 0;
2040 overhead = 0;
2041 } else if (packets_transmitted > 0) {
2042 /* Otherwise if we do have remaining packets, and we've
2043 * scheduled some packets in this interval, take the
2044 * largest max packet size from endpoints with this
2045 * interval.
2046 */
2047 packet_size = largest_mps;
2048 overhead = interval_overhead;
2049 }
2050 /* Otherwise carry over packet_size and overhead from the last
2051 * time we had a remainder.
2052 */
2053 bw_used += bw_added;
2054 if (bw_used > max_bandwidth) {
2055 xhci_warn(xhci, "Not enough bandwidth. "
2056 "Proposed: %u, Max: %u\n",
2057 bw_used, max_bandwidth);
2058 return -ENOMEM;
2059 }
2060 }
2061 /*
2062 * Ok, we know we have some packets left over after even-handedly
2063 * scheduling interval 15. We don't know which microframes they will
2064 * fit into, so we over-schedule and say they will be scheduled every
2065 * microframe.
2066 */
2067 if (packets_remaining > 0)
2068 bw_used += overhead + packet_size;
2069
2070 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2071 unsigned int port_index = virt_dev->real_port - 1;
2072
2073 /* OK, we're manipulating a HS device attached to a
2074 * root port bandwidth domain. Include the number of active TTs
2075 * in the bandwidth used.
2076 */
2077 bw_used += TT_HS_OVERHEAD *
2078 xhci->rh_bw[port_index].num_active_tts;
2079 }
2080
2081 xhci_dbg(xhci, "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2082 "Available: %u " "percent\n",
2083 bw_used, max_bandwidth, bw_reserved,
2084 (max_bandwidth - bw_used - bw_reserved) * 100 /
2085 max_bandwidth);
2086
2087 bw_used += bw_reserved;
2088 if (bw_used > max_bandwidth) {
2089 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2090 bw_used, max_bandwidth);
2091 return -ENOMEM;
2092 }
2093
2094 bw_table->bw_used = bw_used;
2e27980e
SS		 2095 return 0;
2096}
2097
2098static bool xhci_is_async_ep(unsigned int ep_type)
2099{
2100 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2101 ep_type != ISOC_IN_EP &&
2102 ep_type != INT_IN_EP);
2103}
2104
2b698999
SS		 2105static bool xhci_is_sync_in_ep(unsigned int ep_type)
2106{
2107 return (ep_type == ISOC_IN_EP || ep_type != INT_IN_EP);
2108}
2109
2110static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2111{
2112 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2113
2114 if (ep_bw->ep_interval == 0)
2115 return SS_OVERHEAD_BURST +
2116 (ep_bw->mult * ep_bw->num_packets *
2117 (SS_OVERHEAD + mps));
2118 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2119 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2120 1 << ep_bw->ep_interval);
2121
2122}
2123
2e27980e
SS		 2124void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2125 struct xhci_bw_info *ep_bw,
2126 struct xhci_interval_bw_table *bw_table,
2127 struct usb_device *udev,
2128 struct xhci_virt_ep *virt_ep,
2129 struct xhci_tt_bw_info *tt_info)
2130{
2131 struct xhci_interval_bw *interval_bw;
2132 int normalized_interval;
2133
2b698999 2134 if (xhci_is_async_ep(ep_bw->type))
2e27980e
SS		 2135 return;
2136
2b698999
SS		 2137 if (udev->speed == USB_SPEED_SUPER) {
2138 if (xhci_is_sync_in_ep(ep_bw->type))
2139 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2140 xhci_get_ss_bw_consumed(ep_bw);
2141 else
2142 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2143 xhci_get_ss_bw_consumed(ep_bw);
2144 return;
2145 }
2146
2147 /* SuperSpeed endpoints never get added to intervals in the table, so
2148 * this check is only valid for HS/FS/LS devices.
2149 */
2150 if (list_empty(&virt_ep->bw_endpoint_list))
2151 return;
2e27980e
SS		 2152 /* For LS/FS devices, we need to translate the interval expressed in
2153 * microframes to frames.
2154 */
2155 if (udev->speed == USB_SPEED_HIGH)
2156 normalized_interval = ep_bw->ep_interval;
2157 else
2158 normalized_interval = ep_bw->ep_interval - 3;
2159
2160 if (normalized_interval == 0)
2161 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2162 interval_bw = &bw_table->interval_bw[normalized_interval];
2163 interval_bw->num_packets -= ep_bw->num_packets;
2164 switch (udev->speed) {
2165 case USB_SPEED_LOW:
2166 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2167 break;
2168 case USB_SPEED_FULL:
2169 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2170 break;
2171 case USB_SPEED_HIGH:
2172 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2173 break;
2174 case USB_SPEED_SUPER:
2175 case USB_SPEED_UNKNOWN:
2176 case USB_SPEED_WIRELESS:
2177 /* Should never happen because only LS/FS/HS endpoints will get
2178 * added to the endpoint list.
2179 */
2180 return;
2181 }
2182 if (tt_info)
2183 tt_info->active_eps -= 1;
2184 list_del_init(&virt_ep->bw_endpoint_list);
2185}
2186
2187static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2188 struct xhci_bw_info *ep_bw,
2189 struct xhci_interval_bw_table *bw_table,
2190 struct usb_device *udev,
2191 struct xhci_virt_ep *virt_ep,
2192 struct xhci_tt_bw_info *tt_info)
2193{
2194 struct xhci_interval_bw *interval_bw;
2195 struct xhci_virt_ep *smaller_ep;
2196 int normalized_interval;
2197
2198 if (xhci_is_async_ep(ep_bw->type))
2199 return;
2200
2b698999
SS		 2201 if (udev->speed == USB_SPEED_SUPER) {
2202 if (xhci_is_sync_in_ep(ep_bw->type))
2203 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2204 xhci_get_ss_bw_consumed(ep_bw);
2205 else
2206 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2207 xhci_get_ss_bw_consumed(ep_bw);
2208 return;
2209 }
2210
2e27980e
SS		 2211 /* For LS/FS devices, we need to translate the interval expressed in
2212 * microframes to frames.
2213 */
2214 if (udev->speed == USB_SPEED_HIGH)
2215 normalized_interval = ep_bw->ep_interval;
2216 else
2217 normalized_interval = ep_bw->ep_interval - 3;
2218
2219 if (normalized_interval == 0)
2220 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2221 interval_bw = &bw_table->interval_bw[normalized_interval];
2222 interval_bw->num_packets += ep_bw->num_packets;
2223 switch (udev->speed) {
2224 case USB_SPEED_LOW:
2225 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2226 break;
2227 case USB_SPEED_FULL:
2228 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2229 break;
2230 case USB_SPEED_HIGH:
2231 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2232 break;
2233 case USB_SPEED_SUPER:
2234 case USB_SPEED_UNKNOWN:
2235 case USB_SPEED_WIRELESS:
2236 /* Should never happen because only LS/FS/HS endpoints will get
2237 * added to the endpoint list.
2238 */
2239 return;
2240 }
2241
2242 if (tt_info)
2243 tt_info->active_eps += 1;
2244 /* Insert the endpoint into the list, largest max packet size first. */
2245 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2246 bw_endpoint_list) {
2247 if (ep_bw->max_packet_size >=
2248 smaller_ep->bw_info.max_packet_size) {
2249 /* Add the new ep before the smaller endpoint */
2250 list_add_tail(&virt_ep->bw_endpoint_list,
2251 &smaller_ep->bw_endpoint_list);
2252 return;
2253 }
2254 }
2255 /* Add the new endpoint at the end of the list. */
2256 list_add_tail(&virt_ep->bw_endpoint_list,
2257 &interval_bw->endpoints);
2258}
2259
2260void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2261 struct xhci_virt_device *virt_dev,
2262 int old_active_eps)
2263{
2264 struct xhci_root_port_bw_info *rh_bw_info;
2265 if (!virt_dev->tt_info)
2266 return;
2267
2268 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2269 if (old_active_eps == 0 &&
2270 virt_dev->tt_info->active_eps != 0) {
2271 rh_bw_info->num_active_tts += 1;
c29eea62 2272 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2e27980e
SS		 2273 } else if (old_active_eps != 0 &&
2274 virt_dev->tt_info->active_eps == 0) {
2275 rh_bw_info->num_active_tts -= 1;
c29eea62 2276 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2e27980e
SS		 2277 }
2278}
2279
2280static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2281 struct xhci_virt_device *virt_dev,
2282 struct xhci_container_ctx *in_ctx)
2283{
2284 struct xhci_bw_info ep_bw_info[31];
2285 int i;
2286 struct xhci_input_control_ctx *ctrl_ctx;
2287 int old_active_eps = 0;
2288
2e27980e
SS		 2289 if (virt_dev->tt_info)
2290 old_active_eps = virt_dev->tt_info->active_eps;
2291
2292 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2293
2294 for (i = 0; i < 31; i++) {
2295 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2296 continue;
2297
2298 /* Make a copy of the BW info in case we need to revert this */
2299 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2300 sizeof(ep_bw_info[i]));
2301 /* Drop the endpoint from the interval table if the endpoint is
2302 * being dropped or changed.
2303 */
2304 if (EP_IS_DROPPED(ctrl_ctx, i))
2305 xhci_drop_ep_from_interval_table(xhci,
2306 &virt_dev->eps[i].bw_info,
2307 virt_dev->bw_table,
2308 virt_dev->udev,
2309 &virt_dev->eps[i],
2310 virt_dev->tt_info);
2311 }
2312 /* Overwrite the information stored in the endpoints' bw_info */
2313 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2314 for (i = 0; i < 31; i++) {
2315 /* Add any changed or added endpoints to the interval table */
2316 if (EP_IS_ADDED(ctrl_ctx, i))
2317 xhci_add_ep_to_interval_table(xhci,
2318 &virt_dev->eps[i].bw_info,
2319 virt_dev->bw_table,
2320 virt_dev->udev,
2321 &virt_dev->eps[i],
2322 virt_dev->tt_info);
2323 }
2324
2325 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2326 /* Ok, this fits in the bandwidth we have.
2327 * Update the number of active TTs.
2328 */
2329 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2330 return 0;
2331 }
2332
2333 /* We don't have enough bandwidth for this, revert the stored info. */
2334 for (i = 0; i < 31; i++) {
2335 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2336 continue;
2337
2338 /* Drop the new copies of any added or changed endpoints from
2339 * the interval table.
2340 */
2341 if (EP_IS_ADDED(ctrl_ctx, i)) {
2342 xhci_drop_ep_from_interval_table(xhci,
2343 &virt_dev->eps[i].bw_info,
2344 virt_dev->bw_table,
2345 virt_dev->udev,
2346 &virt_dev->eps[i],
2347 virt_dev->tt_info);
2348 }
2349 /* Revert the endpoint back to its old information */
2350 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2351 sizeof(ep_bw_info[i]));
2352 /* Add any changed or dropped endpoints back into the table */
2353 if (EP_IS_DROPPED(ctrl_ctx, i))
2354 xhci_add_ep_to_interval_table(xhci,
2355 &virt_dev->eps[i].bw_info,
2356 virt_dev->bw_table,
2357 virt_dev->udev,
2358 &virt_dev->eps[i],
2359 virt_dev->tt_info);
2360 }
2361 return -ENOMEM;
2362}
2363
2364
f2217e8e
SS		 2365/* Issue a configure endpoint command or evaluate context command
2366 * and wait for it to finish.
2367 */
2368static int xhci_configure_endpoint(struct xhci_hcd *xhci,
913a8a34
SS		 2369 struct usb_device *udev,
2370 struct xhci_command *command,
2371 bool ctx_change, bool must_succeed)
f2217e8e
SS		 2372{
2373 int ret;
2374 int timeleft;
2375 unsigned long flags;
913a8a34
SS		 2376 struct xhci_container_ctx *in_ctx;
2377 struct completion *cmd_completion;
28ccd296 2378 u32 *cmd_status;
913a8a34 2379 struct xhci_virt_device *virt_dev;
f2217e8e
SS		 2380
2381 spin_lock_irqsave(&xhci->lock, flags);
913a8a34 2382 virt_dev = xhci->devs[udev->slot_id];
750645f8
SS		 2383
2384 if (command)
913a8a34 2385 in_ctx = command->in_ctx;
750645f8
SS		 2386 else
2387 in_ctx = virt_dev->in_ctx;
2cf95c18 2388
750645f8
SS		 2389 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2390 xhci_reserve_host_resources(xhci, in_ctx)) {
2391 spin_unlock_irqrestore(&xhci->lock, flags);
2392 xhci_warn(xhci, "Not enough host resources, "
2393 "active endpoint contexts = %u\n",
2394 xhci->num_active_eps);
2395 return -ENOMEM;
2396 }
2e27980e
SS		 2397 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2398 xhci_reserve_bandwidth(xhci, virt_dev, in_ctx)) {
2399 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2400 xhci_free_host_resources(xhci, in_ctx);
2401 spin_unlock_irqrestore(&xhci->lock, flags);
2402 xhci_warn(xhci, "Not enough bandwidth\n");
2403 return -ENOMEM;
2404 }
750645f8
SS		 2405
2406 if (command) {
913a8a34
SS		 2407 cmd_completion = command->completion;
2408 cmd_status = &command->status;
2409 command->command_trb = xhci->cmd_ring->enqueue;
7a3783ef
PZ		 2410
2411 /* Enqueue pointer can be left pointing to the link TRB,
2412 * we must handle that
2413 */
f5960b69 2414 if (TRB_TYPE_LINK_LE32(command->command_trb->link.control))
7a3783ef
PZ		 2415 command->command_trb =
2416 xhci->cmd_ring->enq_seg->next->trbs;
2417
913a8a34
SS		 2418 list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
2419 } else {
913a8a34
SS		 2420 cmd_completion = &virt_dev->cmd_completion;
2421 cmd_status = &virt_dev->cmd_status;
2422 }
1d68064a 2423 init_completion(cmd_completion);
913a8a34 2424
f2217e8e 2425 if (!ctx_change)
913a8a34
SS		 2426 ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
2427 udev->slot_id, must_succeed);
f2217e8e 2428 else
913a8a34 2429 ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
f2217e8e
SS		 2430 udev->slot_id);
2431 if (ret < 0) {
c01591bd
SS		 2432 if (command)
2433 list_del(&command->cmd_list);
2cf95c18
SS		 2434 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2435 xhci_free_host_resources(xhci, in_ctx);
f2217e8e
SS		 2436 spin_unlock_irqrestore(&xhci->lock, flags);
2437 xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
2438 return -ENOMEM;
2439 }
2440 xhci_ring_cmd_db(xhci);
2441 spin_unlock_irqrestore(&xhci->lock, flags);
2442
2443 /* Wait for the configure endpoint command to complete */
2444 timeleft = wait_for_completion_interruptible_timeout(
913a8a34 2445 cmd_completion,
f2217e8e
SS		 2446 USB_CTRL_SET_TIMEOUT);
2447 if (timeleft <= 0) {
2448 xhci_warn(xhci, "%s while waiting for %s command\n",
2449 timeleft == 0 ? "Timeout" : "Signal",
2450 ctx_change == 0 ?
2451 "configure endpoint" :
2452 "evaluate context");
2453 /* FIXME cancel the configure endpoint command */
2454 return -ETIME;
2455 }
2456
2457 if (!ctx_change)
2cf95c18
SS		 2458 ret = xhci_configure_endpoint_result(xhci, udev, cmd_status);
2459 else
2460 ret = xhci_evaluate_context_result(xhci, udev, cmd_status);
2461
2462 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2463 spin_lock_irqsave(&xhci->lock, flags);
2464 /* If the command failed, remove the reserved resources.
2465 * Otherwise, clean up the estimate to include dropped eps.
2466 */
2467 if (ret)
2468 xhci_free_host_resources(xhci, in_ctx);
2469 else
2470 xhci_finish_resource_reservation(xhci, in_ctx);
2471 spin_unlock_irqrestore(&xhci->lock, flags);
2472 }
2473 return ret;
f2217e8e
SS		 2474}
2475
f88ba78d
SS		 2476/* Called after one or more calls to xhci_add_endpoint() or
2477 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2478 * to call xhci_reset_bandwidth().
2479 *
2480 * Since we are in the middle of changing either configuration or
2481 * installing a new alt setting, the USB core won't allow URBs to be
2482 * enqueued for any endpoint on the old config or interface. Nothing
2483 * else should be touching the xhci->devs[slot_id] structure, so we
2484 * don't need to take the xhci->lock for manipulating that.
2485 */
f94e0186
SS		 2486int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2487{
2488 int i;
2489 int ret = 0;
f94e0186
SS		 2490 struct xhci_hcd *xhci;
2491 struct xhci_virt_device *virt_dev;
d115b048
JY		 2492 struct xhci_input_control_ctx *ctrl_ctx;
2493 struct xhci_slot_ctx *slot_ctx;
f94e0186 2494
64927730 2495 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
f94e0186
SS		 2496 if (ret <= 0)
2497 return ret;
2498 xhci = hcd_to_xhci(hcd);
fe6c6c13
SS		 2499 if (xhci->xhc_state & XHCI_STATE_DYING)
2500 return -ENODEV;
f94e0186 2501
700e2052 2502 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
f94e0186
SS		 2503 virt_dev = xhci->devs[udev->slot_id];
2504
2505 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
d115b048 2506 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
28ccd296
ME		 2507 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2508 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2509 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2dc37539
SS		 2510
2511 /* Don't issue the command if there's no endpoints to update. */
2512 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2513 ctrl_ctx->drop_flags == 0)
2514 return 0;
2515
f94e0186 2516 xhci_dbg(xhci, "New Input Control Context:\n");
d115b048
JY		 2517 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2518 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
28ccd296 2519 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
f94e0186 2520
913a8a34
SS		 2521 ret = xhci_configure_endpoint(xhci, udev, NULL,
2522 false, false);
f94e0186
SS		 2523 if (ret) {
2524 /* Callee should call reset_bandwidth() */
f94e0186
SS		 2525 return ret;
2526 }
2527
2528 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
d115b048 2529 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
28ccd296 2530 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
f94e0186 2531
834cb0fc
SS		 2532 /* Free any rings that were dropped, but not changed. */
2533 for (i = 1; i < 31; ++i) {
4819fef5
ME		 2534 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2535 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))))
834cb0fc
SS		 2536 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2537 }
d115b048 2538 xhci_zero_in_ctx(xhci, virt_dev);
834cb0fc
SS		 2539 /*
2540 * Install any rings for completely new endpoints or changed endpoints,
2541 * and free or cache any old rings from changed endpoints.
2542 */
f94e0186 2543 for (i = 1; i < 31; ++i) {
74f9fe21
SS		 2544 if (!virt_dev->eps[i].new_ring)
2545 continue;
2546 /* Only cache or free the old ring if it exists.
2547 * It may not if this is the first add of an endpoint.
2548 */
2549 if (virt_dev->eps[i].ring) {
412566bd 2550 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
f94e0186 2551 }
74f9fe21
SS		 2552 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2553 virt_dev->eps[i].new_ring = NULL;
f94e0186
SS		 2554 }
2555
f94e0186
SS		 2556 return ret;
2557}
2558
2559void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2560{
f94e0186
SS		 2561 struct xhci_hcd *xhci;
2562 struct xhci_virt_device *virt_dev;
2563 int i, ret;
2564
64927730 2565 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
f94e0186
SS		 2566 if (ret <= 0)
2567 return;
2568 xhci = hcd_to_xhci(hcd);
2569
700e2052 2570 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
f94e0186
SS		 2571 virt_dev = xhci->devs[udev->slot_id];
2572 /* Free any rings allocated for added endpoints */
2573 for (i = 0; i < 31; ++i) {
63a0d9ab
SS		 2574 if (virt_dev->eps[i].new_ring) {
2575 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2576 virt_dev->eps[i].new_ring = NULL;
f94e0186
SS		 2577 }
2578 }
d115b048 2579 xhci_zero_in_ctx(xhci, virt_dev);
f94e0186
SS		 2580}
2581
5270b951 2582static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
913a8a34
SS		 2583 struct xhci_container_ctx *in_ctx,
2584 struct xhci_container_ctx *out_ctx,
2585 u32 add_flags, u32 drop_flags)
5270b951
SS		 2586{
2587 struct xhci_input_control_ctx *ctrl_ctx;
913a8a34 2588 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
28ccd296
ME		 2589 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2590 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
913a8a34 2591 xhci_slot_copy(xhci, in_ctx, out_ctx);
28ccd296 2592 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5270b951 2593
913a8a34
SS		 2594 xhci_dbg(xhci, "Input Context:\n");
2595 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
5270b951
SS		 2596}
2597
8212a49d 2598static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
ac9d8fe7
SS		 2599 unsigned int slot_id, unsigned int ep_index,
2600 struct xhci_dequeue_state *deq_state)
2601{
2602 struct xhci_container_ctx *in_ctx;
ac9d8fe7
SS		 2603 struct xhci_ep_ctx *ep_ctx;
2604 u32 added_ctxs;
2605 dma_addr_t addr;
2606
913a8a34
SS		 2607 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2608 xhci->devs[slot_id]->out_ctx, ep_index);
ac9d8fe7
SS		 2609 in_ctx = xhci->devs[slot_id]->in_ctx;
2610 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2611 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2612 deq_state->new_deq_ptr);
2613 if (addr == 0) {
2614 xhci_warn(xhci, "WARN Cannot submit config ep after "
2615 "reset ep command\n");
2616 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2617 deq_state->new_deq_seg,
2618 deq_state->new_deq_ptr);
2619 return;
2620 }
28ccd296 2621 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
ac9d8fe7 2622
ac9d8fe7 2623 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
913a8a34
SS		 2624 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2625 xhci->devs[slot_id]->out_ctx, added_ctxs, added_ctxs);
ac9d8fe7
SS		 2626}
2627
82d1009f 2628void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
63a0d9ab 2629 struct usb_device *udev, unsigned int ep_index)
82d1009f
SS		 2630{
2631 struct xhci_dequeue_state deq_state;
63a0d9ab 2632 struct xhci_virt_ep *ep;
82d1009f
SS		 2633
2634 xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
63a0d9ab 2635 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
82d1009f
SS		 2636 /* We need to move the HW's dequeue pointer past this TD,
2637 * or it will attempt to resend it on the next doorbell ring.
2638 */
2639 xhci_find_new_dequeue_state(xhci, udev->slot_id,
e9df17eb 2640 ep_index, ep->stopped_stream, ep->stopped_td,
ac9d8fe7 2641 &deq_state);
82d1009f 2642
ac9d8fe7
SS		 2643 /* HW with the reset endpoint quirk will use the saved dequeue state to
2644 * issue a configure endpoint command later.
2645 */
2646 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2647 xhci_dbg(xhci, "Queueing new dequeue state\n");
63a0d9ab 2648 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
e9df17eb 2649 ep_index, ep->stopped_stream, &deq_state);
ac9d8fe7
SS		 2650 } else {
2651 /* Better hope no one uses the input context between now and the
2652 * reset endpoint completion!
e9df17eb
SS		 2653 * XXX: No idea how this hardware will react when stream rings
2654 * are enabled.
ac9d8fe7
SS		 2655 */
2656 xhci_dbg(xhci, "Setting up input context for "
2657 "configure endpoint command\n");
2658 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2659 ep_index, &deq_state);
2660 }
82d1009f
SS		 2661}
2662
a1587d97
SS		 2663/* Deal with stalled endpoints. The core should have sent the control message
2664 * to clear the halt condition. However, we need to make the xHCI hardware
2665 * reset its sequence number, since a device will expect a sequence number of
2666 * zero after the halt condition is cleared.
2667 * Context: in_interrupt
2668 */
2669void xhci_endpoint_reset(struct usb_hcd *hcd,
2670 struct usb_host_endpoint *ep)
2671{
2672 struct xhci_hcd *xhci;
2673 struct usb_device *udev;
2674 unsigned int ep_index;
2675 unsigned long flags;
2676 int ret;
63a0d9ab 2677 struct xhci_virt_ep *virt_ep;
a1587d97
SS		 2678
2679 xhci = hcd_to_xhci(hcd);
2680 udev = (struct usb_device *) ep->hcpriv;
2681 /* Called with a root hub endpoint (or an endpoint that wasn't added
2682 * with xhci_add_endpoint()
2683 */
2684 if (!ep->hcpriv)
2685 return;
2686 ep_index = xhci_get_endpoint_index(&ep->desc);
63a0d9ab
SS		 2687 virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2688 if (!virt_ep->stopped_td) {
c92bcfa7
SS		 2689 xhci_dbg(xhci, "Endpoint 0x%x not halted, refusing to reset.\n",
2690 ep->desc.bEndpointAddress);
2691 return;
2692 }
82d1009f
SS		 2693 if (usb_endpoint_xfer_control(&ep->desc)) {
2694 xhci_dbg(xhci, "Control endpoint stall already handled.\n");
2695 return;
2696 }
a1587d97
SS		 2697
2698 xhci_dbg(xhci, "Queueing reset endpoint command\n");
2699 spin_lock_irqsave(&xhci->lock, flags);
2700 ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
c92bcfa7
SS		 2701 /*
2702 * Can't change the ring dequeue pointer until it's transitioned to the
2703 * stopped state, which is only upon a successful reset endpoint
2704 * command. Better hope that last command worked!
2705 */
a1587d97 2706 if (!ret) {
63a0d9ab
SS		 2707 xhci_cleanup_stalled_ring(xhci, udev, ep_index);
2708 kfree(virt_ep->stopped_td);
a1587d97
SS		 2709 xhci_ring_cmd_db(xhci);
2710 }
1624ae1c
SS		 2711 virt_ep->stopped_td = NULL;
2712 virt_ep->stopped_trb = NULL;
5e5cf6fc 2713 virt_ep->stopped_stream = 0;
a1587d97
SS		 2714 spin_unlock_irqrestore(&xhci->lock, flags);
2715
2716 if (ret)
2717 xhci_warn(xhci, "FIXME allocate a new ring segment\n");
2718}
2719
8df75f42
SS		 2720static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2721 struct usb_device *udev, struct usb_host_endpoint *ep,
2722 unsigned int slot_id)
2723{
2724 int ret;
2725 unsigned int ep_index;
2726 unsigned int ep_state;
2727
2728 if (!ep)
2729 return -EINVAL;
64927730 2730 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
8df75f42
SS		 2731 if (ret <= 0)
2732 return -EINVAL;
842f1690 2733 if (ep->ss_ep_comp.bmAttributes == 0) {
8df75f42
SS		 2734 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2735 " descriptor for ep 0x%x does not support streams\n",
2736 ep->desc.bEndpointAddress);
2737 return -EINVAL;
2738 }
2739
2740 ep_index = xhci_get_endpoint_index(&ep->desc);
2741 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2742 if (ep_state & EP_HAS_STREAMS ||
2743 ep_state & EP_GETTING_STREAMS) {
2744 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2745 "already has streams set up.\n",
2746 ep->desc.bEndpointAddress);
2747 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2748 "dynamic stream context array reallocation.\n");
2749 return -EINVAL;
2750 }
2751 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2752 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2753 "endpoint 0x%x; URBs are pending.\n",
2754 ep->desc.bEndpointAddress);
2755 return -EINVAL;
2756 }
2757 return 0;
2758}
2759
2760static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
2761 unsigned int *num_streams, unsigned int *num_stream_ctxs)
2762{
2763 unsigned int max_streams;
2764
2765 /* The stream context array size must be a power of two */
2766 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
2767 /*
2768 * Find out how many primary stream array entries the host controller
2769 * supports. Later we may use secondary stream arrays (similar to 2nd
2770 * level page entries), but that's an optional feature for xHCI host
2771 * controllers. xHCs must support at least 4 stream IDs.
2772 */
2773 max_streams = HCC_MAX_PSA(xhci->hcc_params);
2774 if (*num_stream_ctxs > max_streams) {
2775 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
2776 max_streams);
2777 *num_stream_ctxs = max_streams;
2778 *num_streams = max_streams;
2779 }
2780}
2781
2782/* Returns an error code if one of the endpoint already has streams.
2783 * This does not change any data structures, it only checks and gathers
2784 * information.
2785 */
2786static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
2787 struct usb_device *udev,
2788 struct usb_host_endpoint **eps, unsigned int num_eps,
2789 unsigned int *num_streams, u32 *changed_ep_bitmask)
2790{
8df75f42
SS		 2791 unsigned int max_streams;
2792 unsigned int endpoint_flag;
2793 int i;
2794 int ret;
2795
2796 for (i = 0; i < num_eps; i++) {
2797 ret = xhci_check_streams_endpoint(xhci, udev,
2798 eps[i], udev->slot_id);
2799 if (ret < 0)
2800 return ret;
2801
842f1690
AS		 2802 max_streams = USB_SS_MAX_STREAMS(
2803 eps[i]->ss_ep_comp.bmAttributes);
8df75f42
SS		 2804 if (max_streams < (*num_streams - 1)) {
2805 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
2806 eps[i]->desc.bEndpointAddress,
2807 max_streams);
2808 *num_streams = max_streams+1;
2809 }
2810
2811 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
2812 if (*changed_ep_bitmask & endpoint_flag)
2813 return -EINVAL;
2814 *changed_ep_bitmask |= endpoint_flag;
2815 }
2816 return 0;
2817}
2818
2819static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
2820 struct usb_device *udev,
2821 struct usb_host_endpoint **eps, unsigned int num_eps)
2822{
2823 u32 changed_ep_bitmask = 0;
2824 unsigned int slot_id;
2825 unsigned int ep_index;
2826 unsigned int ep_state;
2827 int i;
2828
2829 slot_id = udev->slot_id;
2830 if (!xhci->devs[slot_id])
2831 return 0;
2832
2833 for (i = 0; i < num_eps; i++) {
2834 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2835 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2836 /* Are streams already being freed for the endpoint? */
2837 if (ep_state & EP_GETTING_NO_STREAMS) {
2838 xhci_warn(xhci, "WARN Can't disable streams for "
2839 "endpoint 0x%x\n, "
2840 "streams are being disabled already.",
2841 eps[i]->desc.bEndpointAddress);
2842 return 0;
2843 }
2844 /* Are there actually any streams to free? */
2845 if (!(ep_state & EP_HAS_STREAMS) &&
2846 !(ep_state & EP_GETTING_STREAMS)) {
2847 xhci_warn(xhci, "WARN Can't disable streams for "
2848 "endpoint 0x%x\n, "
2849 "streams are already disabled!",
2850 eps[i]->desc.bEndpointAddress);
2851 xhci_warn(xhci, "WARN xhci_free_streams() called "
2852 "with non-streams endpoint\n");
2853 return 0;
2854 }
2855 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
2856 }
2857 return changed_ep_bitmask;
2858}
2859
2860/*
2861 * The USB device drivers use this function (though the HCD interface in USB
2862 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
2863 * coordinate mass storage command queueing across multiple endpoints (basically
2864 * a stream ID == a task ID).
2865 *
2866 * Setting up streams involves allocating the same size stream context array
2867 * for each endpoint and issuing a configure endpoint command for all endpoints.
2868 *
2869 * Don't allow the call to succeed if one endpoint only supports one stream
2870 * (which means it doesn't support streams at all).
2871 *
2872 * Drivers may get less stream IDs than they asked for, if the host controller
2873 * hardware or endpoints claim they can't support the number of requested
2874 * stream IDs.
2875 */
2876int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
2877 struct usb_host_endpoint **eps, unsigned int num_eps,
2878 unsigned int num_streams, gfp_t mem_flags)
2879{
2880 int i, ret;
2881 struct xhci_hcd *xhci;
2882 struct xhci_virt_device *vdev;
2883 struct xhci_command *config_cmd;
2884 unsigned int ep_index;
2885 unsigned int num_stream_ctxs;
2886 unsigned long flags;
2887 u32 changed_ep_bitmask = 0;
2888
2889 if (!eps)
2890 return -EINVAL;
2891
2892 /* Add one to the number of streams requested to account for
2893 * stream 0 that is reserved for xHCI usage.
2894 */
2895 num_streams += 1;
2896 xhci = hcd_to_xhci(hcd);
2897 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
2898 num_streams);
2899
2900 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
2901 if (!config_cmd) {
2902 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
2903 return -ENOMEM;
2904 }
2905
2906 /* Check to make sure all endpoints are not already configured for
2907 * streams. While we're at it, find the maximum number of streams that
2908 * all the endpoints will support and check for duplicate endpoints.
2909 */
2910 spin_lock_irqsave(&xhci->lock, flags);
2911 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
2912 num_eps, &num_streams, &changed_ep_bitmask);
2913 if (ret < 0) {
2914 xhci_free_command(xhci, config_cmd);
2915 spin_unlock_irqrestore(&xhci->lock, flags);
2916 return ret;
2917 }
2918 if (num_streams <= 1) {
2919 xhci_warn(xhci, "WARN: endpoints can't handle "
2920 "more than one stream.\n");
2921 xhci_free_command(xhci, config_cmd);
2922 spin_unlock_irqrestore(&xhci->lock, flags);
2923 return -EINVAL;
2924 }
2925 vdev = xhci->devs[udev->slot_id];
25985edc 2926 /* Mark each endpoint as being in transition, so
8df75f42
SS		 2927 * xhci_urb_enqueue() will reject all URBs.
2928 */
2929 for (i = 0; i < num_eps; i++) {
2930 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2931 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
2932 }
2933 spin_unlock_irqrestore(&xhci->lock, flags);
2934
2935 /* Setup internal data structures and allocate HW data structures for
2936 * streams (but don't install the HW structures in the input context
2937 * until we're sure all memory allocation succeeded).
2938 */
2939 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
2940 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
2941 num_stream_ctxs, num_streams);
2942
2943 for (i = 0; i < num_eps; i++) {
2944 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2945 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
2946 num_stream_ctxs,
2947 num_streams, mem_flags);
2948 if (!vdev->eps[ep_index].stream_info)
2949 goto cleanup;
2950 /* Set maxPstreams in endpoint context and update deq ptr to
2951 * point to stream context array. FIXME
2952 */
2953 }
2954
2955 /* Set up the input context for a configure endpoint command. */
2956 for (i = 0; i < num_eps; i++) {
2957 struct xhci_ep_ctx *ep_ctx;
2958
2959 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2960 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
2961
2962 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
2963 vdev->out_ctx, ep_index);
2964 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
2965 vdev->eps[ep_index].stream_info);
2966 }
2967 /* Tell the HW to drop its old copy of the endpoint context info
2968 * and add the updated copy from the input context.
2969 */
2970 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
2971 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
2972
2973 /* Issue and wait for the configure endpoint command */
2974 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
2975 false, false);
2976
2977 /* xHC rejected the configure endpoint command for some reason, so we
2978 * leave the old ring intact and free our internal streams data
2979 * structure.
2980 */
2981 if (ret < 0)
2982 goto cleanup;
2983
2984 spin_lock_irqsave(&xhci->lock, flags);
2985 for (i = 0; i < num_eps; i++) {
2986 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
2987 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
2988 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
2989 udev->slot_id, ep_index);
2990 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
2991 }
2992 xhci_free_command(xhci, config_cmd);
2993 spin_unlock_irqrestore(&xhci->lock, flags);
2994
2995 /* Subtract 1 for stream 0, which drivers can't use */
2996 return num_streams - 1;
2997
2998cleanup:
2999 /* If it didn't work, free the streams! */
3000 for (i = 0; i < num_eps; i++) {
3001 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3002 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
8a007748 3003 vdev->eps[ep_index].stream_info = NULL;
8df75f42
SS		 3004 /* FIXME Unset maxPstreams in endpoint context and
3005 * update deq ptr to point to normal string ring.
3006 */
3007 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3008 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3009 xhci_endpoint_zero(xhci, vdev, eps[i]);
3010 }
3011 xhci_free_command(xhci, config_cmd);
3012 return -ENOMEM;
3013}
3014
3015/* Transition the endpoint from using streams to being a "normal" endpoint
3016 * without streams.
3017 *
3018 * Modify the endpoint context state, submit a configure endpoint command,
3019 * and free all endpoint rings for streams if that completes successfully.
3020 */
3021int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3022 struct usb_host_endpoint **eps, unsigned int num_eps,
3023 gfp_t mem_flags)
3024{
3025 int i, ret;
3026 struct xhci_hcd *xhci;
3027 struct xhci_virt_device *vdev;
3028 struct xhci_command *command;
3029 unsigned int ep_index;
3030 unsigned long flags;
3031 u32 changed_ep_bitmask;
3032
3033 xhci = hcd_to_xhci(hcd);
3034 vdev = xhci->devs[udev->slot_id];
3035
3036 /* Set up a configure endpoint command to remove the streams rings */
3037 spin_lock_irqsave(&xhci->lock, flags);
3038 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3039 udev, eps, num_eps);
3040 if (changed_ep_bitmask == 0) {
3041 spin_unlock_irqrestore(&xhci->lock, flags);
3042 return -EINVAL;
3043 }
3044
3045 /* Use the xhci_command structure from the first endpoint. We may have
3046 * allocated too many, but the driver may call xhci_free_streams() for
3047 * each endpoint it grouped into one call to xhci_alloc_streams().
3048 */
3049 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3050 command = vdev->eps[ep_index].stream_info->free_streams_command;
3051 for (i = 0; i < num_eps; i++) {
3052 struct xhci_ep_ctx *ep_ctx;
3053
3054 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3055 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3056 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3057 EP_GETTING_NO_STREAMS;
3058
3059 xhci_endpoint_copy(xhci, command->in_ctx,
3060 vdev->out_ctx, ep_index);
3061 xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
3062 &vdev->eps[ep_index]);
3063 }
3064 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3065 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
3066 spin_unlock_irqrestore(&xhci->lock, flags);
3067
3068 /* Issue and wait for the configure endpoint command,
3069 * which must succeed.
3070 */
3071 ret = xhci_configure_endpoint(xhci, udev, command,
3072 false, true);
3073
3074 /* xHC rejected the configure endpoint command for some reason, so we
3075 * leave the streams rings intact.
3076 */
3077 if (ret < 0)
3078 return ret;
3079
3080 spin_lock_irqsave(&xhci->lock, flags);
3081 for (i = 0; i < num_eps; i++) {
3082 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3083 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
8a007748 3084 vdev->eps[ep_index].stream_info = NULL;
8df75f42
SS		 3085 /* FIXME Unset maxPstreams in endpoint context and
3086 * update deq ptr to point to normal string ring.
3087 */
3088 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3089 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3090 }
3091 spin_unlock_irqrestore(&xhci->lock, flags);
3092
3093 return 0;
3094}
3095
2cf95c18
SS		 3096/*
3097 * Deletes endpoint resources for endpoints that were active before a Reset
3098 * Device command, or a Disable Slot command. The Reset Device command leaves
3099 * the control endpoint intact, whereas the Disable Slot command deletes it.
3100 *
3101 * Must be called with xhci->lock held.
3102 */
3103void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3104 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3105{
3106 int i;
3107 unsigned int num_dropped_eps = 0;
3108 unsigned int drop_flags = 0;
3109
3110 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3111 if (virt_dev->eps[i].ring) {
3112 drop_flags |= 1 << i;
3113 num_dropped_eps++;
3114 }
3115 }
3116 xhci->num_active_eps -= num_dropped_eps;
3117 if (num_dropped_eps)
3118 xhci_dbg(xhci, "Dropped %u ep ctxs, flags = 0x%x, "
3119 "%u now active.\n",
3120 num_dropped_eps, drop_flags,
3121 xhci->num_active_eps);
3122}
3123
2a8f82c4
SS		 3124/*
3125 * This submits a Reset Device Command, which will set the device state to 0,
3126 * set the device address to 0, and disable all the endpoints except the default
3127 * control endpoint. The USB core should come back and call
3128 * xhci_address_device(), and then re-set up the configuration. If this is
3129 * called because of a usb_reset_and_verify_device(), then the old alternate
3130 * settings will be re-installed through the normal bandwidth allocation
3131 * functions.
3132 *
3133 * Wait for the Reset Device command to finish. Remove all structures
3134 * associated with the endpoints that were disabled. Clear the input device
3135 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
f0615c45
AX		 3136 *
3137 * If the virt_dev to be reset does not exist or does not match the udev,
3138 * it means the device is lost, possibly due to the xHC restore error and
3139 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3140 * re-allocate the device.
2a8f82c4 3141 */
f0615c45 3142int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
2a8f82c4
SS		 3143{
3144 int ret, i;
3145 unsigned long flags;
3146 struct xhci_hcd *xhci;
3147 unsigned int slot_id;
3148 struct xhci_virt_device *virt_dev;
3149 struct xhci_command *reset_device_cmd;
3150 int timeleft;
3151 int last_freed_endpoint;
001fd382 3152 struct xhci_slot_ctx *slot_ctx;
2e27980e 3153 int old_active_eps = 0;
2a8f82c4 3154
f0615c45 3155 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
2a8f82c4
SS		 3156 if (ret <= 0)
3157 return ret;
3158 xhci = hcd_to_xhci(hcd);
3159 slot_id = udev->slot_id;
3160 virt_dev = xhci->devs[slot_id];
f0615c45
AX		 3161 if (!virt_dev) {
3162 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3163 "not exist. Re-allocate the device\n", slot_id);
3164 ret = xhci_alloc_dev(hcd, udev);
3165 if (ret == 1)
3166 return 0;
3167 else
3168 return -EINVAL;
3169 }
3170
3171 if (virt_dev->udev != udev) {
3172 /* If the virt_dev and the udev does not match, this virt_dev
3173 * may belong to another udev.
3174 * Re-allocate the device.
3175 */
3176 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3177 "not match the udev. Re-allocate the device\n",
3178 slot_id);
3179 ret = xhci_alloc_dev(hcd, udev);
3180 if (ret == 1)
3181 return 0;
3182 else
3183 return -EINVAL;
3184 }
2a8f82c4 3185
001fd382
ML		 3186 /* If device is not setup, there is no point in resetting it */
3187 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3188 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3189 SLOT_STATE_DISABLED)
3190 return 0;
3191
2a8f82c4
SS		 3192 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3193 /* Allocate the command structure that holds the struct completion.
3194 * Assume we're in process context, since the normal device reset
3195 * process has to wait for the device anyway. Storage devices are
3196 * reset as part of error handling, so use GFP_NOIO instead of
3197 * GFP_KERNEL.
3198 */
3199 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3200 if (!reset_device_cmd) {
3201 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3202 return -ENOMEM;
3203 }
3204
3205 /* Attempt to submit the Reset Device command to the command ring */
3206 spin_lock_irqsave(&xhci->lock, flags);
3207 reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
7a3783ef
PZ		 3208
3209 /* Enqueue pointer can be left pointing to the link TRB,
3210 * we must handle that
3211 */
f5960b69 3212 if (TRB_TYPE_LINK_LE32(reset_device_cmd->command_trb->link.control))
7a3783ef
PZ		 3213 reset_device_cmd->command_trb =
3214 xhci->cmd_ring->enq_seg->next->trbs;
3215
2a8f82c4
SS		 3216 list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
3217 ret = xhci_queue_reset_device(xhci, slot_id);
3218 if (ret) {
3219 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3220 list_del(&reset_device_cmd->cmd_list);
3221 spin_unlock_irqrestore(&xhci->lock, flags);
3222 goto command_cleanup;
3223 }
3224 xhci_ring_cmd_db(xhci);
3225 spin_unlock_irqrestore(&xhci->lock, flags);
3226
3227 /* Wait for the Reset Device command to finish */
3228 timeleft = wait_for_completion_interruptible_timeout(
3229 reset_device_cmd->completion,
3230 USB_CTRL_SET_TIMEOUT);
3231 if (timeleft <= 0) {
3232 xhci_warn(xhci, "%s while waiting for reset device command\n",
3233 timeleft == 0 ? "Timeout" : "Signal");
3234 spin_lock_irqsave(&xhci->lock, flags);
3235 /* The timeout might have raced with the event ring handler, so
3236 * only delete from the list if the item isn't poisoned.
3237 */
3238 if (reset_device_cmd->cmd_list.next != LIST_POISON1)
3239 list_del(&reset_device_cmd->cmd_list);
3240 spin_unlock_irqrestore(&xhci->lock, flags);
3241 ret = -ETIME;
3242 goto command_cleanup;
3243 }
3244
3245 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3246 * unless we tried to reset a slot ID that wasn't enabled,
3247 * or the device wasn't in the addressed or configured state.
3248 */
3249 ret = reset_device_cmd->status;
3250 switch (ret) {
3251 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3252 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3253 xhci_info(xhci, "Can't reset device (slot ID %u) in %s state\n",
3254 slot_id,
3255 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3256 xhci_info(xhci, "Not freeing device rings.\n");
3257 /* Don't treat this as an error. May change my mind later. */
3258 ret = 0;
3259 goto command_cleanup;
3260 case COMP_SUCCESS:
3261 xhci_dbg(xhci, "Successful reset device command.\n");
3262 break;
3263 default:
3264 if (xhci_is_vendor_info_code(xhci, ret))
3265 break;
3266 xhci_warn(xhci, "Unknown completion code %u for "
3267 "reset device command.\n", ret);
3268 ret = -EINVAL;
3269 goto command_cleanup;
3270 }
3271
2cf95c18
SS		 3272 /* Free up host controller endpoint resources */
3273 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3274 spin_lock_irqsave(&xhci->lock, flags);
3275 /* Don't delete the default control endpoint resources */
3276 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3277 spin_unlock_irqrestore(&xhci->lock, flags);
3278 }
3279
2a8f82c4
SS		 3280 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3281 last_freed_endpoint = 1;
3282 for (i = 1; i < 31; ++i) {
2dea75d9
DT		 3283 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3284
3285 if (ep->ep_state & EP_HAS_STREAMS) {
3286 xhci_free_stream_info(xhci, ep->stream_info);
3287 ep->stream_info = NULL;
3288 ep->ep_state &= ~EP_HAS_STREAMS;
3289 }
3290
3291 if (ep->ring) {
3292 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3293 last_freed_endpoint = i;
3294 }
2e27980e
SS		 3295 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3296 xhci_drop_ep_from_interval_table(xhci,
3297 &virt_dev->eps[i].bw_info,
3298 virt_dev->bw_table,
3299 udev,
3300 &virt_dev->eps[i],
3301 virt_dev->tt_info);
9af5d71d 3302 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
2a8f82c4 3303 }
2e27980e
SS		 3304 /* If necessary, update the number of active TTs on this root port */
3305 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3306
2a8f82c4
SS		 3307 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3308 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3309 ret = 0;
3310
3311command_cleanup:
3312 xhci_free_command(xhci, reset_device_cmd);
3313 return ret;
3314}
3315
3ffbba95
SS		 3316/*
3317 * At this point, the struct usb_device is about to go away, the device has
3318 * disconnected, and all traffic has been stopped and the endpoints have been
3319 * disabled. Free any HC data structures associated with that device.
3320 */
3321void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3322{
3323 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
6f5165cf 3324 struct xhci_virt_device *virt_dev;
3ffbba95 3325 unsigned long flags;
c526d0d4 3326 u32 state;
64927730 3327 int i, ret;
3ffbba95 3328
64927730 3329 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
7bd89b40
SS		 3330 /* If the host is halted due to driver unload, we still need to free the
3331 * device.
3332 */
3333 if (ret <= 0 && ret != -ENODEV)
3ffbba95 3334 return;
64927730 3335
6f5165cf 3336 virt_dev = xhci->devs[udev->slot_id];
6f5165cf
SS		 3337
3338 /* Stop any wayward timer functions (which may grab the lock) */
3339 for (i = 0; i < 31; ++i) {
3340 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3341 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3342 }
3ffbba95 3343
65580b43
AX		 3344 if (udev->usb2_hw_lpm_enabled) {
3345 xhci_set_usb2_hardware_lpm(hcd, udev, 0);
3346 udev->usb2_hw_lpm_enabled = 0;
3347 }
3348
3ffbba95 3349 spin_lock_irqsave(&xhci->lock, flags);
c526d0d4
SS		 3350 /* Don't disable the slot if the host controller is dead. */
3351 state = xhci_readl(xhci, &xhci->op_regs->status);
7bd89b40
SS		 3352 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3353 (xhci->xhc_state & XHCI_STATE_HALTED)) {
c526d0d4
SS		 3354 xhci_free_virt_device(xhci, udev->slot_id);
3355 spin_unlock_irqrestore(&xhci->lock, flags);
3356 return;
3357 }
3358
23e3be11 3359 if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
3ffbba95
SS		 3360 spin_unlock_irqrestore(&xhci->lock, flags);
3361 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3362 return;
3363 }
23e3be11 3364 xhci_ring_cmd_db(xhci);
3ffbba95
SS		 3365 spin_unlock_irqrestore(&xhci->lock, flags);
3366 /*
3367 * Event command completion handler will free any data structures
f88ba78d 3368 * associated with the slot. XXX Can free sleep?
3ffbba95
SS		 3369 */
3370}
3371
2cf95c18
SS		 3372/*
3373 * Checks if we have enough host controller resources for the default control
3374 * endpoint.
3375 *
3376 * Must be called with xhci->lock held.
3377 */
3378static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3379{
3380 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3381 xhci_dbg(xhci, "Not enough ep ctxs: "
3382 "%u active, need to add 1, limit is %u.\n",
3383 xhci->num_active_eps, xhci->limit_active_eps);
3384 return -ENOMEM;
3385 }
3386 xhci->num_active_eps += 1;
3387 xhci_dbg(xhci, "Adding 1 ep ctx, %u now active.\n",
3388 xhci->num_active_eps);
3389 return 0;
3390}
3391
3392
3ffbba95
SS		 3393/*
3394 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3395 * timed out, or allocating memory failed. Returns 1 on success.
3396 */
3397int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3398{
3399 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3400 unsigned long flags;
3401 int timeleft;
3402 int ret;
3403
3404 spin_lock_irqsave(&xhci->lock, flags);
23e3be11 3405 ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
3ffbba95
SS		 3406 if (ret) {
3407 spin_unlock_irqrestore(&xhci->lock, flags);
3408 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3409 return 0;
3410 }
23e3be11 3411 xhci_ring_cmd_db(xhci);
3ffbba95
SS		 3412 spin_unlock_irqrestore(&xhci->lock, flags);
3413
3414 /* XXX: how much time for xHC slot assignment? */
3415 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
3416 USB_CTRL_SET_TIMEOUT);
3417 if (timeleft <= 0) {
3418 xhci_warn(xhci, "%s while waiting for a slot\n",
3419 timeleft == 0 ? "Timeout" : "Signal");
3420 /* FIXME cancel the enable slot request */
3421 return 0;
3422 }
3423
3ffbba95
SS		 3424 if (!xhci->slot_id) {
3425 xhci_err(xhci, "Error while assigning device slot ID\n");
3ffbba95
SS		 3426 return 0;
3427 }
2cf95c18
SS		 3428
3429 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3430 spin_lock_irqsave(&xhci->lock, flags);
3431 ret = xhci_reserve_host_control_ep_resources(xhci);
3432 if (ret) {
3433 spin_unlock_irqrestore(&xhci->lock, flags);
3434 xhci_warn(xhci, "Not enough host resources, "
3435 "active endpoint contexts = %u\n",
3436 xhci->num_active_eps);
3437 goto disable_slot;
3438 }
3439 spin_unlock_irqrestore(&xhci->lock, flags);
3440 }
3441 /* Use GFP_NOIO, since this function can be called from
a6d940dd
SS		 3442 * xhci_discover_or_reset_device(), which may be called as part of
3443 * mass storage driver error handling.
3444 */
3445 if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
3ffbba95 3446 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
2cf95c18 3447 goto disable_slot;
3ffbba95
SS		 3448 }
3449 udev->slot_id = xhci->slot_id;
3450 /* Is this a LS or FS device under a HS hub? */
3451 /* Hub or peripherial? */
3ffbba95 3452 return 1;
2cf95c18
SS		 3453
3454disable_slot:
3455 /* Disable slot, if we can do it without mem alloc */
3456 spin_lock_irqsave(&xhci->lock, flags);
3457 if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
3458 xhci_ring_cmd_db(xhci);
3459 spin_unlock_irqrestore(&xhci->lock, flags);
3460 return 0;
3ffbba95
SS		 3461}
3462
3463/*
3464 * Issue an Address Device command (which will issue a SetAddress request to
3465 * the device).
3466 * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
3467 * we should only issue and wait on one address command at the same time.
3468 *
3469 * We add one to the device address issued by the hardware because the USB core
3470 * uses address 1 for the root hubs (even though they're not really devices).
3471 */
3472int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3473{
3474 unsigned long flags;
3475 int timeleft;
3476 struct xhci_virt_device *virt_dev;
3477 int ret = 0;
3478 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
d115b048
JY		 3479 struct xhci_slot_ctx *slot_ctx;
3480 struct xhci_input_control_ctx *ctrl_ctx;
8e595a5d 3481 u64 temp_64;
3ffbba95
SS		 3482
3483 if (!udev->slot_id) {
3484 xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
3485 return -EINVAL;
3486 }
3487
3ffbba95
SS		 3488 virt_dev = xhci->devs[udev->slot_id];
3489
7ed603ec
ME		 3490 if (WARN_ON(!virt_dev)) {
3491 /*
3492 * In plug/unplug torture test with an NEC controller,
3493 * a zero-dereference was observed once due to virt_dev = 0.
3494 * Print useful debug rather than crash if it is observed again!
3495 */
3496 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3497 udev->slot_id);
3498 return -EINVAL;
3499 }
3500
f0615c45
AX		 3501 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3502 /*
3503 * If this is the first Set Address since device plug-in or
3504 * virt_device realloaction after a resume with an xHCI power loss,
3505 * then set up the slot context.
3506 */
3507 if (!slot_ctx->dev_info)
3ffbba95 3508 xhci_setup_addressable_virt_dev(xhci, udev);
f0615c45 3509 /* Otherwise, update the control endpoint ring enqueue pointer. */
2d1ee590
SS		 3510 else
3511 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
d31c285b
SS		 3512 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
3513 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3514 ctrl_ctx->drop_flags = 0;
3515
66e49d87 3516 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
d115b048 3517 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3ffbba95 3518
f88ba78d 3519 spin_lock_irqsave(&xhci->lock, flags);
d115b048
JY		 3520 ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
3521 udev->slot_id);
3ffbba95
SS		 3522 if (ret) {
3523 spin_unlock_irqrestore(&xhci->lock, flags);
3524 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3525 return ret;
3526 }
23e3be11 3527 xhci_ring_cmd_db(xhci);
3ffbba95
SS		 3528 spin_unlock_irqrestore(&xhci->lock, flags);
3529
3530 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3531 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
3532 USB_CTRL_SET_TIMEOUT);
3533 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3534 * the SetAddress() "recovery interval" required by USB and aborting the
3535 * command on a timeout.
3536 */
3537 if (timeleft <= 0) {
cd68176a 3538 xhci_warn(xhci, "%s while waiting for address device command\n",
3ffbba95
SS		 3539 timeleft == 0 ? "Timeout" : "Signal");
3540 /* FIXME cancel the address device command */
3541 return -ETIME;
3542 }
3543
3ffbba95
SS		 3544 switch (virt_dev->cmd_status) {
3545 case COMP_CTX_STATE:
3546 case COMP_EBADSLT:
3547 xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
3548 udev->slot_id);
3549 ret = -EINVAL;
3550 break;
3551 case COMP_TX_ERR:
3552 dev_warn(&udev->dev, "Device not responding to set address.\n");
3553 ret = -EPROTO;
3554 break;
f6ba6fe2
AH		 3555 case COMP_DEV_ERR:
3556 dev_warn(&udev->dev, "ERROR: Incompatible device for address "
3557 "device command.\n");
3558 ret = -ENODEV;
3559 break;
3ffbba95
SS		 3560 case COMP_SUCCESS:
3561 xhci_dbg(xhci, "Successful Address Device command\n");
3562 break;
3563 default:
3564 xhci_err(xhci, "ERROR: unexpected command completion "
3565 "code 0x%x.\n", virt_dev->cmd_status);
66e49d87 3566 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
d115b048 3567 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3ffbba95
SS		 3568 ret = -EINVAL;
3569 break;
3570 }
3571 if (ret) {
3ffbba95
SS		 3572 return ret;
3573 }
8e595a5d
SS		 3574 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3575 xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
3576 xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
28ccd296
ME		 3577 udev->slot_id,
3578 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3579 (unsigned long long)
3580 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
700e2052 3581 xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
d115b048 3582 (unsigned long long)virt_dev->out_ctx->dma);
3ffbba95 3583 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
d115b048 3584 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3ffbba95 3585 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
d115b048 3586 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3ffbba95
SS		 3587 /*
3588 * USB core uses address 1 for the roothubs, so we add one to the
3589 * address given back to us by the HC.
3590 */
d115b048 3591 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
c8d4af8e
AX		 3592 /* Use kernel assigned address for devices; store xHC assigned
3593 * address locally. */
28ccd296
ME		 3594 virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK)
3595 + 1;
f94e0186 3596 /* Zero the input context control for later use */
d115b048
JY		 3597 ctrl_ctx->add_flags = 0;
3598 ctrl_ctx->drop_flags = 0;
3ffbba95 3599
c8d4af8e 3600 xhci_dbg(xhci, "Internal device address = %d\n", virt_dev->address);
3ffbba95
SS		 3601
3602 return 0;
3603}
3604
9574323c
AX		 3605#ifdef CONFIG_USB_SUSPEND
3606
3607/* BESL to HIRD Encoding array for USB2 LPM */
3608static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
3609 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
3610
3611/* Calculate HIRD/BESL for USB2 PORTPMSC*/
3612static int xhci_calculate_hird_besl(int u2del, bool use_besl)
3613{
3614 int hird;
3615
3616 if (use_besl) {
3617 for (hird = 0; hird < 16; hird++) {
3618 if (xhci_besl_encoding[hird] >= u2del)
3619 break;
3620 }
3621 } else {
3622 if (u2del <= 50)
3623 hird = 0;
3624 else
3625 hird = (u2del - 51) / 75 + 1;
3626
3627 if (hird > 15)
3628 hird = 15;
3629 }
3630
3631 return hird;
3632}
3633
3634static int xhci_usb2_software_lpm_test(struct usb_hcd *hcd,
3635 struct usb_device *udev)
3636{
3637 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3638 struct dev_info *dev_info;
3639 __le32 __iomem **port_array;
3640 __le32 __iomem *addr, *pm_addr;
3641 u32 temp, dev_id;
3642 unsigned int port_num;
3643 unsigned long flags;
3644 int u2del, hird;
3645 int ret;
3646
3647 if (hcd->speed == HCD_USB3 || !xhci->sw_lpm_support ||
3648 !udev->lpm_capable)
3649 return -EINVAL;
3650
3651 /* we only support lpm for non-hub device connected to root hub yet */
3652 if (!udev->parent || udev->parent->parent ||
3653 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
3654 return -EINVAL;
3655
3656 spin_lock_irqsave(&xhci->lock, flags);
3657
3658 /* Look for devices in lpm_failed_devs list */
3659 dev_id = le16_to_cpu(udev->descriptor.idVendor) << 16 |
3660 le16_to_cpu(udev->descriptor.idProduct);
3661 list_for_each_entry(dev_info, &xhci->lpm_failed_devs, list) {
3662 if (dev_info->dev_id == dev_id) {
3663 ret = -EINVAL;
3664 goto finish;
3665 }
3666 }
3667
3668 port_array = xhci->usb2_ports;
3669 port_num = udev->portnum - 1;
3670
3671 if (port_num > HCS_MAX_PORTS(xhci->hcs_params1)) {
3672 xhci_dbg(xhci, "invalid port number %d\n", udev->portnum);
3673 ret = -EINVAL;
3674 goto finish;
3675 }
3676
3677 /*
3678 * Test USB 2.0 software LPM.
3679 * FIXME: some xHCI 1.0 hosts may implement a new register to set up
3680 * hardware-controlled USB 2.0 LPM. See section 5.4.11 and 4.23.5.1.1.1
3681 * in the June 2011 errata release.
3682 */
3683 xhci_dbg(xhci, "test port %d software LPM\n", port_num);
3684 /*
3685 * Set L1 Device Slot and HIRD/BESL.
3686 * Check device's USB 2.0 extension descriptor to determine whether
3687 * HIRD or BESL shoule be used. See USB2.0 LPM errata.
3688 */
3689 pm_addr = port_array[port_num] + 1;
3690 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
3691 if (le32_to_cpu(udev->bos->ext_cap->bmAttributes) & (1 << 2))
3692 hird = xhci_calculate_hird_besl(u2del, 1);
3693 else
3694 hird = xhci_calculate_hird_besl(u2del, 0);
3695
3696 temp = PORT_L1DS(udev->slot_id) | PORT_HIRD(hird);
3697 xhci_writel(xhci, temp, pm_addr);
3698
3699 /* Set port link state to U2(L1) */
3700 addr = port_array[port_num];
3701 xhci_set_link_state(xhci, port_array, port_num, XDEV_U2);
3702
3703 /* wait for ACK */
3704 spin_unlock_irqrestore(&xhci->lock, flags);
3705 msleep(10);
3706 spin_lock_irqsave(&xhci->lock, flags);
3707
3708 /* Check L1 Status */
3709 ret = handshake(xhci, pm_addr, PORT_L1S_MASK, PORT_L1S_SUCCESS, 125);
3710 if (ret != -ETIMEDOUT) {
3711 /* enter L1 successfully */
3712 temp = xhci_readl(xhci, addr);
3713 xhci_dbg(xhci, "port %d entered L1 state, port status 0x%x\n",
3714 port_num, temp);
3715 ret = 0;
3716 } else {
3717 temp = xhci_readl(xhci, pm_addr);
3718 xhci_dbg(xhci, "port %d software lpm failed, L1 status %d\n",
3719 port_num, temp & PORT_L1S_MASK);
3720 ret = -EINVAL;
3721 }
3722
3723 /* Resume the port */
3724 xhci_set_link_state(xhci, port_array, port_num, XDEV_U0);
3725
3726 spin_unlock_irqrestore(&xhci->lock, flags);
3727 msleep(10);
3728 spin_lock_irqsave(&xhci->lock, flags);
3729
3730 /* Clear PLC */
3731 xhci_test_and_clear_bit(xhci, port_array, port_num, PORT_PLC);
3732
3733 /* Check PORTSC to make sure the device is in the right state */
3734 if (!ret) {
3735 temp = xhci_readl(xhci, addr);
3736 xhci_dbg(xhci, "resumed port %d status 0x%x\n", port_num, temp);
3737 if (!(temp & PORT_CONNECT) || !(temp & PORT_PE) ||
3738 (temp & PORT_PLS_MASK) != XDEV_U0) {
3739 xhci_dbg(xhci, "port L1 resume fail\n");
3740 ret = -EINVAL;
3741 }
3742 }
3743
3744 if (ret) {
3745 /* Insert dev to lpm_failed_devs list */
3746 xhci_warn(xhci, "device LPM test failed, may disconnect and "
3747 "re-enumerate\n");
3748 dev_info = kzalloc(sizeof(struct dev_info), GFP_ATOMIC);
3749 if (!dev_info) {
3750 ret = -ENOMEM;
3751 goto finish;
3752 }
3753 dev_info->dev_id = dev_id;
3754 INIT_LIST_HEAD(&dev_info->list);
3755 list_add(&dev_info->list, &xhci->lpm_failed_devs);
3756 } else {
3757 xhci_ring_device(xhci, udev->slot_id);
3758 }
3759
3760finish:
3761 spin_unlock_irqrestore(&xhci->lock, flags);
3762 return ret;
3763}
3764
65580b43
AX		 3765int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
3766 struct usb_device *udev, int enable)
3767{
3768 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3769 __le32 __iomem **port_array;
3770 __le32 __iomem *pm_addr;
3771 u32 temp;
3772 unsigned int port_num;
3773 unsigned long flags;
3774 int u2del, hird;
3775
3776 if (hcd->speed == HCD_USB3 || !xhci->hw_lpm_support ||
3777 !udev->lpm_capable)
3778 return -EPERM;
3779
3780 if (!udev->parent || udev->parent->parent ||
3781 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
3782 return -EPERM;
3783
3784 if (udev->usb2_hw_lpm_capable != 1)
3785 return -EPERM;
3786
3787 spin_lock_irqsave(&xhci->lock, flags);
3788
3789 port_array = xhci->usb2_ports;
3790 port_num = udev->portnum - 1;
3791 pm_addr = port_array[port_num] + 1;
3792 temp = xhci_readl(xhci, pm_addr);
3793
3794 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
3795 enable ? "enable" : "disable", port_num);
3796
3797 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
3798 if (le32_to_cpu(udev->bos->ext_cap->bmAttributes) & (1 << 2))
3799 hird = xhci_calculate_hird_besl(u2del, 1);
3800 else
3801 hird = xhci_calculate_hird_besl(u2del, 0);
3802
3803 if (enable) {
3804 temp &= ~PORT_HIRD_MASK;
3805 temp |= PORT_HIRD(hird) | PORT_RWE;
3806 xhci_writel(xhci, temp, pm_addr);
3807 temp = xhci_readl(xhci, pm_addr);
3808 temp |= PORT_HLE;
3809 xhci_writel(xhci, temp, pm_addr);
3810 } else {
3811 temp &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK);
3812 xhci_writel(xhci, temp, pm_addr);
3813 }
3814
3815 spin_unlock_irqrestore(&xhci->lock, flags);
3816 return 0;
3817}
3818
9574323c
AX		 3819int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
3820{
3821 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3822 int ret;
3823
3824 ret = xhci_usb2_software_lpm_test(hcd, udev);
65580b43 3825 if (!ret) {
9574323c 3826 xhci_dbg(xhci, "software LPM test succeed\n");
65580b43
AX		 3827 if (xhci->hw_lpm_support == 1) {
3828 udev->usb2_hw_lpm_capable = 1;
3829 ret = xhci_set_usb2_hardware_lpm(hcd, udev, 1);
3830 if (!ret)
3831 udev->usb2_hw_lpm_enabled = 1;
3832 }
3833 }
9574323c
AX		 3834
3835 return 0;
3836}
3837
3838#else
3839
65580b43
AX		 3840int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
3841 struct usb_device *udev, int enable)
3842{
3843 return 0;
3844}
3845
9574323c
AX		 3846int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
3847{
3848 return 0;
3849}
3850
3851#endif /* CONFIG_USB_SUSPEND */
3852
ac1c1b7f
SS		 3853/* Once a hub descriptor is fetched for a device, we need to update the xHC's
3854 * internal data structures for the device.
3855 */
3856int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
3857 struct usb_tt *tt, gfp_t mem_flags)
3858{
3859 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3860 struct xhci_virt_device *vdev;
3861 struct xhci_command *config_cmd;
3862 struct xhci_input_control_ctx *ctrl_ctx;
3863 struct xhci_slot_ctx *slot_ctx;
3864 unsigned long flags;
3865 unsigned think_time;
3866 int ret;
3867
3868 /* Ignore root hubs */
3869 if (!hdev->parent)
3870 return 0;
3871
3872 vdev = xhci->devs[hdev->slot_id];
3873 if (!vdev) {
3874 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
3875 return -EINVAL;
3876 }
a1d78c16 3877 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
ac1c1b7f
SS		 3878 if (!config_cmd) {
3879 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3880 return -ENOMEM;
3881 }
3882
3883 spin_lock_irqsave(&xhci->lock, flags);
839c817c
SS		 3884 if (hdev->speed == USB_SPEED_HIGH &&
3885 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
3886 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
3887 xhci_free_command(xhci, config_cmd);
3888 spin_unlock_irqrestore(&xhci->lock, flags);
3889 return -ENOMEM;
3890 }
3891
ac1c1b7f
SS		 3892 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
3893 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
28ccd296 3894 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
ac1c1b7f 3895 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
28ccd296 3896 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
ac1c1b7f 3897 if (tt->multi)
28ccd296 3898 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
ac1c1b7f
SS		 3899 if (xhci->hci_version > 0x95) {
3900 xhci_dbg(xhci, "xHCI version %x needs hub "
3901 "TT think time and number of ports\n",
3902 (unsigned int) xhci->hci_version);
28ccd296 3903 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
ac1c1b7f
SS		 3904 /* Set TT think time - convert from ns to FS bit times.
3905 * 0 = 8 FS bit times, 1 = 16 FS bit times,
3906 * 2 = 24 FS bit times, 3 = 32 FS bit times.
700b4173
AX		 3907 *
3908 * xHCI 1.0: this field shall be 0 if the device is not a
3909 * High-spped hub.
ac1c1b7f
SS		 3910 */
3911 think_time = tt->think_time;
3912 if (think_time != 0)
3913 think_time = (think_time / 666) - 1;
700b4173
AX		 3914 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
3915 slot_ctx->tt_info |=
3916 cpu_to_le32(TT_THINK_TIME(think_time));
ac1c1b7f
SS		 3917 } else {
3918 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
3919 "TT think time or number of ports\n",
3920 (unsigned int) xhci->hci_version);
3921 }
3922 slot_ctx->dev_state = 0;
3923 spin_unlock_irqrestore(&xhci->lock, flags);
3924
3925 xhci_dbg(xhci, "Set up %s for hub device.\n",
3926 (xhci->hci_version > 0x95) ?
3927 "configure endpoint" : "evaluate context");
3928 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
3929 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
3930
3931 /* Issue and wait for the configure endpoint or
3932 * evaluate context command.
3933 */
3934 if (xhci->hci_version > 0x95)
3935 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
3936 false, false);
3937 else
3938 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
3939 true, false);
3940
3941 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
3942 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
3943
3944 xhci_free_command(xhci, config_cmd);
3945 return ret;
3946}
3947
66d4eadd
SS		 3948int xhci_get_frame(struct usb_hcd *hcd)
3949{
3950 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3951 /* EHCI mods by the periodic size. Why? */
3952 return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
3953}
3954
552e0c4f
SAS		 3955int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
3956{
3957 struct xhci_hcd *xhci;
3958 struct device *dev = hcd->self.controller;
3959 int retval;
3960 u32 temp;
3961
3962 hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
3963
3964 if (usb_hcd_is_primary_hcd(hcd)) {
3965 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
3966 if (!xhci)
3967 return -ENOMEM;
3968 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
3969 xhci->main_hcd = hcd;
3970 /* Mark the first roothub as being USB 2.0.
3971 * The xHCI driver will register the USB 3.0 roothub.
3972 */
3973 hcd->speed = HCD_USB2;
3974 hcd->self.root_hub->speed = USB_SPEED_HIGH;
3975 /*
3976 * USB 2.0 roothub under xHCI has an integrated TT,
3977 * (rate matching hub) as opposed to having an OHCI/UHCI
3978 * companion controller.
3979 */
3980 hcd->has_tt = 1;
3981 } else {
3982 /* xHCI private pointer was set in xhci_pci_probe for the second
3983 * registered roothub.
3984 */
3985 xhci = hcd_to_xhci(hcd);
3986 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
3987 if (HCC_64BIT_ADDR(temp)) {
3988 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
3989 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
3990 } else {
3991 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
3992 }
3993 return 0;
3994 }
3995
3996 xhci->cap_regs = hcd->regs;
3997 xhci->op_regs = hcd->regs +
3998 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
3999 xhci->run_regs = hcd->regs +
4000 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4001 /* Cache read-only capability registers */
4002 xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
4003 xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
4004 xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
4005 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
4006 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4007 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4008 xhci_print_registers(xhci);
4009
4010 get_quirks(dev, xhci);
4011
4012 /* Make sure the HC is halted. */
4013 retval = xhci_halt(xhci);
4014 if (retval)
4015 goto error;
4016
4017 xhci_dbg(xhci, "Resetting HCD\n");
4018 /* Reset the internal HC memory state and registers. */
4019 retval = xhci_reset(xhci);
4020 if (retval)
4021 goto error;
4022 xhci_dbg(xhci, "Reset complete\n");
4023
4024 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4025 if (HCC_64BIT_ADDR(temp)) {
4026 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4027 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
4028 } else {
4029 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
4030 }
4031
4032 xhci_dbg(xhci, "Calling HCD init\n");
4033 /* Initialize HCD and host controller data structures. */
4034 retval = xhci_init(hcd);
4035 if (retval)
4036 goto error;
4037 xhci_dbg(xhci, "Called HCD init\n");
4038 return 0;
4039error:
4040 kfree(xhci);
4041 return retval;
4042}
4043
66d4eadd
SS		 4044MODULE_DESCRIPTION(DRIVER_DESC);
4045MODULE_AUTHOR(DRIVER_AUTHOR);
4046MODULE_LICENSE("GPL");
4047
4048static int __init xhci_hcd_init(void)
4049{
0cc47d54 4050 int retval;
66d4eadd
SS		 4051
4052 retval = xhci_register_pci();
66d4eadd
SS		 4053 if (retval < 0) {
4054 printk(KERN_DEBUG "Problem registering PCI driver.");
4055 return retval;
4056 }
98441973
SS		 4057 /*
4058 * Check the compiler generated sizes of structures that must be laid
4059 * out in specific ways for hardware access.
4060 */
4061 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
4062 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
4063 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
4064 /* xhci_device_control has eight fields, and also
4065 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
4066 */
98441973
SS		 4067 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
4068 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
4069 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
4070 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
4071 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
4072 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
4073 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
4074 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
66d4eadd
SS		 4075 return 0;
4076}
4077module_init(xhci_hcd_init);
4078
4079static void __exit xhci_hcd_cleanup(void)
4080{
66d4eadd 4081 xhci_unregister_pci();
66d4eadd
SS		 4082}
4083module_exit(xhci_hcd_cleanup);
kernel source for telekom puls (alcatel/mediatek)