[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / host / r8a66597.h

/*
 * R8A66597 HCD (Host Controller Driver)
 *
 * Copyright (C) 2006-2007 Renesas Solutions Corp.
 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
 * Portions Copyright (C) 2004-2005 David Brownell
 * Portions Copyright (C) 1999 Roman Weissgaerber
 *
 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 *
 */

#ifndef __R8A66597_H__
#define __R8A66597_H__

#include <linux/clk.h>
#include <linux/usb/r8a66597.h>

#define R8A66597_MAX_NUM_PIPE		10
#define R8A66597_BUF_BSIZE		8
#define R8A66597_MAX_DEVICE		10
#define R8A66597_MAX_ROOT_HUB		2
#define R8A66597_MAX_SAMPLING		5
#define R8A66597_RH_POLL_TIME		10
#define R8A66597_MAX_DMA_CHANNEL	2
#define R8A66597_PIPE_NO_DMA		R8A66597_MAX_DMA_CHANNEL
#define check_bulk_or_isoc(pipenum)	((pipenum >= 1 && pipenum <= 5))
#define check_interrupt(pipenum)	((pipenum >= 6 && pipenum <= 9))
#define make_devsel(addr)		(addr << 12)

struct r8a66597_pipe_info {
	unsigned long timer_interval;
	u16 pipenum;
	u16 address;	/* R8A66597 HCD usb address */
	u16 epnum;
	u16 maxpacket;
	u16 type;
	u16 bufnum;
	u16 buf_bsize;
	u16 interval;
	u16 dir_in;
};

struct r8a66597_pipe {
	struct r8a66597_pipe_info info;

	unsigned long fifoaddr;
	unsigned long fifosel;
	unsigned long fifoctr;
	unsigned long pipectr;
	unsigned long pipetre;
	unsigned long pipetrn;
};

struct r8a66597_td {
	struct r8a66597_pipe *pipe;
	struct urb *urb;
	struct list_head queue;

	u16 type;
	u16 pipenum;
	int iso_cnt;

	u16 address;		/* R8A66597's USB address */
	u16 maxpacket;

	unsigned zero_packet:1;
	unsigned short_packet:1;
	unsigned set_address:1;
};

struct r8a66597_device {
	u16	address;	/* R8A66597's USB address */
	u16	hub_port;
	u16	root_port;

	unsigned short ep_in_toggle;
	unsigned short ep_out_toggle;
	unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
	unsigned char dma_map;

	enum usb_device_state state;

	struct usb_device *udev;
	int usb_address;
	struct list_head device_list;
};

struct r8a66597_root_hub {
	u32 port;
	u16 old_syssts;
	int scount;

	struct r8a66597_device	*dev;
};

struct r8a66597 {
	spinlock_t lock;
	void __iomem *reg;
	struct clk *clk;
	struct r8a66597_platdata	*pdata;
	struct r8a66597_device		device0;
	struct r8a66597_root_hub	root_hub[R8A66597_MAX_ROOT_HUB];
	struct list_head		pipe_queue[R8A66597_MAX_NUM_PIPE];

	struct timer_list rh_timer;
	struct timer_list td_timer[R8A66597_MAX_NUM_PIPE];
	struct timer_list interval_timer[R8A66597_MAX_NUM_PIPE];

	unsigned short address_map;
	unsigned short timeout_map;
	unsigned short interval_map;
	unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
	unsigned char dma_map;
	unsigned int max_root_hub;

	struct list_head child_device;
	unsigned long child_connect_map[4];

	unsigned bus_suspended:1;
	unsigned irq_sense_low:1;
};

static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
{
	return (struct r8a66597 *)(hcd->hcd_priv);
}

static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
{
	return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
}

static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
						  u16 pipenum)
{
	if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
		return NULL;

	return list_entry(r8a66597->pipe_queue[pipenum].next,
			  struct r8a66597_td, queue);
}

static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
					   u16 pipenum)
{
	struct r8a66597_td *td;

	td = r8a66597_get_td(r8a66597, pipenum);
	return (td ? td->urb : NULL);
}

static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
{
	return ioread16(r8a66597->reg + offset);
}

static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
				      unsigned long offset, u16 *buf,
				      int len)
{
	void __iomem *fifoaddr = r8a66597->reg + offset;
	unsigned long count;

	if (r8a66597->pdata->on_chip) {
		count = len / 4;
		ioread32_rep(fifoaddr, buf, count);

		if (len & 0x00000003) {
			unsigned long tmp = ioread32(fifoaddr);
			memcpy((unsigned char *)buf + count * 4, &tmp,
			       len & 0x03);
		}
	} else {
		len = (len + 1) / 2;
		ioread16_rep(fifoaddr, buf, len);
	}
}

static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
				  unsigned long offset)
{
	iowrite16(val, r8a66597->reg + offset);
}

static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
				 u16 val, u16 pat, unsigned long offset)
{
	u16 tmp;
	tmp = r8a66597_read(r8a66597, offset);
	tmp = tmp & (~pat);
	tmp = tmp | val;
	r8a66597_write(r8a66597, tmp, offset);
}

#define r8a66597_bclr(r8a66597, val, offset)	\
			r8a66597_mdfy(r8a66597, 0, val, offset)
#define r8a66597_bset(r8a66597, val, offset)	\
			r8a66597_mdfy(r8a66597, val, 0, offset)

static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
				       struct r8a66597_pipe *pipe, u16 *buf,
				       int len)
{
	void __iomem *fifoaddr = r8a66597->reg + pipe->fifoaddr;
	unsigned long count;
	unsigned char *pb;
	int i;

	if (r8a66597->pdata->on_chip) {
		count = len / 4;
		iowrite32_rep(fifoaddr, buf, count);

		if (len & 0x00000003) {
			pb = (unsigned char *)buf + count * 4;
			for (i = 0; i < (len & 0x00000003); i++) {
				if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
					iowrite8(pb[i], fifoaddr + i);
				else
					iowrite8(pb[i], fifoaddr + 3 - i);
			}
		}
	} else {
		int odd = len & 0x0001;

		len = len / 2;
		iowrite16_rep(fifoaddr, buf, len);
		if (unlikely(odd)) {
			buf = &buf[len];
			if (r8a66597->pdata->wr0_shorted_to_wr1)
				r8a66597_bclr(r8a66597, MBW_16, pipe->fifosel);
			iowrite8((unsigned char)*buf, fifoaddr);
			if (r8a66597->pdata->wr0_shorted_to_wr1)
				r8a66597_bset(r8a66597, MBW_16, pipe->fifosel);
		}
	}
}

static inline unsigned long get_syscfg_reg(int port)
{
	return port == 0 ? SYSCFG0 : SYSCFG1;
}

static inline unsigned long get_syssts_reg(int port)
{
	return port == 0 ? SYSSTS0 : SYSSTS1;
}

static inline unsigned long get_dvstctr_reg(int port)
{
	return port == 0 ? DVSTCTR0 : DVSTCTR1;
}

static inline unsigned long get_dmacfg_reg(int port)
{
	return port == 0 ? DMA0CFG : DMA1CFG;
}

static inline unsigned long get_intenb_reg(int port)
{
	return port == 0 ? INTENB1 : INTENB2;
}

static inline unsigned long get_intsts_reg(int port)
{
	return port == 0 ? INTSTS1 : INTSTS2;
}

static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
{
	unsigned long dvstctr_reg = get_dvstctr_reg(port);

	return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
}

static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
				       int power)
{
	unsigned long dvstctr_reg = get_dvstctr_reg(port);

	if (r8a66597->pdata->port_power) {
		r8a66597->pdata->port_power(port, power);
	} else {
		if (power)
			r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
		else
			r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
	}
}

static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
{
	u16 clock = 0;

	switch (pdata->xtal) {
	case R8A66597_PLATDATA_XTAL_12MHZ:
		clock = XTAL12;
		break;
	case R8A66597_PLATDATA_XTAL_24MHZ:
		clock = XTAL24;
		break;
	case R8A66597_PLATDATA_XTAL_48MHZ:
		clock = XTAL48;
		break;
	default:
		printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
		break;
	}

	return clock;
}

#define get_pipectr_addr(pipenum)	(PIPE1CTR + (pipenum - 1) * 2)
#define get_pipetre_addr(pipenum)	(PIPE1TRE + (pipenum - 1) * 4)
#define get_pipetrn_addr(pipenum)	(PIPE1TRN + (pipenum - 1) * 4)
#define get_devadd_addr(address)	(DEVADD0 + address * 2)

#define enable_irq_ready(r8a66597, pipenum)	\
	enable_pipe_irq(r8a66597, pipenum, BRDYENB)
#define disable_irq_ready(r8a66597, pipenum)	\
	disable_pipe_irq(r8a66597, pipenum, BRDYENB)
#define enable_irq_empty(r8a66597, pipenum)	\
	enable_pipe_irq(r8a66597, pipenum, BEMPENB)
#define disable_irq_empty(r8a66597, pipenum)	\
	disable_pipe_irq(r8a66597, pipenum, BEMPENB)
#define enable_irq_nrdy(r8a66597, pipenum)	\
	enable_pipe_irq(r8a66597, pipenum, NRDYENB)
#define disable_irq_nrdy(r8a66597, pipenum)	\
	disable_pipe_irq(r8a66597, pipenum, NRDYENB)

#endif	/* __R8A66597_H__ */
Commit	Line	Data
5d304358 YS	1	/*
	2	* R8A66597 HCD (Host Controller Driver)
	3	*
	4	* Copyright (C) 2006-2007 Renesas Solutions Corp.
	5	* Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
	6	* Portions Copyright (C) 2004-2005 David Brownell
	7	* Portions Copyright (C) 1999 Roman Weissgaerber
	8	*
	9	* Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; version 2 of the License.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	23	*
	24	*/
	25
	26	#ifndef __R8A66597_H__
	27	#define __R8A66597_H__
	28
765786e0	29	#include <linux/clk.h>
5effabbe YS	30	#include <linux/usb/r8a66597.h>
5effabbe YS	31
5d304358 YS	32	#define R8A66597_MAX_NUM_PIPE 10
	33	#define R8A66597_BUF_BSIZE 8
	34	#define R8A66597_MAX_DEVICE 10
	35	#define R8A66597_MAX_ROOT_HUB 2
29fab0cd YS	36	#define R8A66597_MAX_SAMPLING 5
29fab0cd YS	37	#define R8A66597_RH_POLL_TIME 10
5d304358 YS	38	#define R8A66597_MAX_DMA_CHANNEL 2
	39	#define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
	40	#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
	41	#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
	42	#define make_devsel(addr) (addr << 12)
	43
	44	struct r8a66597_pipe_info {
6d879107	45	unsigned long timer_interval;
e294531d	46	u16 pipenum;
dc0d5c1e	47	u16 address; /* R8A66597 HCD usb address */
e294531d YS	48	u16 epnum;
	49	u16 maxpacket;
	50	u16 type;
	51	u16 bufnum;
	52	u16 buf_bsize;
	53	u16 interval;
	54	u16 dir_in;
5d304358 YS	55	};
	56
	57	struct r8a66597_pipe {
	58	struct r8a66597_pipe_info info;
	59
	60	unsigned long fifoaddr;
	61	unsigned long fifosel;
	62	unsigned long fifoctr;
	63	unsigned long pipectr;
	64	unsigned long pipetre;
	65	unsigned long pipetrn;
	66	};
	67
	68	struct r8a66597_td {
	69	struct r8a66597_pipe *pipe;
	70	struct urb *urb;
	71	struct list_head queue;
	72
	73	u16 type;
	74	u16 pipenum;
	75	int iso_cnt;
	76
	77	u16 address; /* R8A66597's USB address */
	78	u16 maxpacket;
	79
	80	unsigned zero_packet:1;
	81	unsigned short_packet:1;
	82	unsigned set_address:1;
	83	};
	84
	85	struct r8a66597_device {
	86	u16 address; /* R8A66597's USB address */
	87	u16 hub_port;
	88	u16 root_port;
	89
	90	unsigned short ep_in_toggle;
	91	unsigned short ep_out_toggle;
	92	unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
	93	unsigned char dma_map;
	94
	95	enum usb_device_state state;
	96
	97	struct usb_device *udev;
	98	int usb_address;
	99	struct list_head device_list;
	100	};
	101
	102	struct r8a66597_root_hub {
	103	u32 port;
	104	u16 old_syssts;
	105	int scount;
	106
	107	struct r8a66597_device *dev;
	108	};
	109
	110	struct r8a66597 {
	111	spinlock_t lock;
1c98347e	112	void __iomem *reg;
765786e0	113	struct clk *clk;
5effabbe	114	struct r8a66597_platdata *pdata;
5d304358 YS	115	struct r8a66597_device device0;
	116	struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB];
	117	struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE];
	118
	119	struct timer_list rh_timer;
	120	struct timer_list td_timer[R8A66597_MAX_NUM_PIPE];
6d879107	121	struct timer_list interval_timer[R8A66597_MAX_NUM_PIPE];
5d304358 YS	122
	123	unsigned short address_map;
	124	unsigned short timeout_map;
6d879107	125	unsigned short interval_map;
5d304358 YS	126	unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
5d304358 YS	127	unsigned char dma_map;
719a72b7	128	unsigned int max_root_hub;
5d304358 YS	129
	130	struct list_head child_device;
	131	unsigned long child_connect_map[4];
e1e609be YS	132
e1e609be YS	133	unsigned bus_suspended:1;
5effabbe	134	unsigned irq_sense_low:1;
5d304358 YS	135	};
	136
	137	static inline struct r8a66597 hcd_to_r8a66597(struct usb_hcd hcd)
	138	{
	139	return (struct r8a66597 *)(hcd->hcd_priv);
	140	}
	141
	142	static inline struct usb_hcd r8a66597_to_hcd(struct r8a66597 r8a66597)
	143	{
	144	return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
	145	}
	146
	147	static inline struct r8a66597_td r8a66597_get_td(struct r8a66597 r8a66597,
	148	u16 pipenum)
	149	{
	150	if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
	151	return NULL;
	152
	153	return list_entry(r8a66597->pipe_queue[pipenum].next,
	154	struct r8a66597_td, queue);
	155	}
	156
	157	static inline struct urb r8a66597_get_urb(struct r8a66597 r8a66597,
	158	u16 pipenum)
	159	{
	160	struct r8a66597_td *td;
	161
	162	td = r8a66597_get_td(r8a66597, pipenum);
	163	return (td ? td->urb : NULL);
	164	}
	165
	166	static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
	167	{
1c98347e	168	return ioread16(r8a66597->reg + offset);
5d304358 YS	169	}
	170
	171	static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
	172	unsigned long offset, u16 *buf,
	173	int len)
	174	{
1c98347e	175	void __iomem *fifoaddr = r8a66597->reg + offset;
9424ea29 YS	176	unsigned long count;
9424ea29 YS	177
719a72b7 MD	178	if (r8a66597->pdata->on_chip) {
719a72b7 MD	179	count = len / 4;
1c98347e	180	ioread32_rep(fifoaddr, buf, count);
9424ea29	181
719a72b7	182	if (len & 0x00000003) {
1c98347e	183	unsigned long tmp = ioread32(fifoaddr);
719a72b7 MD	184	memcpy((unsigned char )buf + count 4, &tmp,
	185	len & 0x03);
	186	}
	187	} else {
	188	len = (len + 1) / 2;
1c98347e	189	ioread16_rep(fifoaddr, buf, len);
9424ea29	190	}
5d304358 YS	191	}
	192
	193	static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
	194	unsigned long offset)
	195	{
1c98347e	196	iowrite16(val, r8a66597->reg + offset);
5d304358 YS	197	}
5d304358 YS	198
f2e9039a YS	199	static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
	200	u16 val, u16 pat, unsigned long offset)
	201	{
	202	u16 tmp;
	203	tmp = r8a66597_read(r8a66597, offset);
	204	tmp = tmp & (~pat);
	205	tmp = tmp \| val;
	206	r8a66597_write(r8a66597, tmp, offset);
	207	}
	208
	209	#define r8a66597_bclr(r8a66597, val, offset) \
	210	r8a66597_mdfy(r8a66597, 0, val, offset)
	211	#define r8a66597_bset(r8a66597, val, offset) \
	212	r8a66597_mdfy(r8a66597, val, 0, offset)
	213
5d304358	214	static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
f2e9039a	215	struct r8a66597_pipe pipe, u16 buf,
5d304358 YS	216	int len)
5d304358 YS	217	{
f2e9039a	218	void __iomem *fifoaddr = r8a66597->reg + pipe->fifoaddr;
9424ea29 YS	219	unsigned long count;
	220	unsigned char *pb;
	221	int i;
	222
719a72b7 MD	223	if (r8a66597->pdata->on_chip) {
719a72b7 MD	224	count = len / 4;
1c98347e	225	iowrite32_rep(fifoaddr, buf, count);
719a72b7 MD	226
	227	if (len & 0x00000003) {
	228	pb = (unsigned char )buf + count 4;
	229	for (i = 0; i < (len & 0x00000003); i++) {
	230	if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
1c98347e	231	iowrite8(pb[i], fifoaddr + i);
719a72b7	232	else
1c98347e	233	iowrite8(pb[i], fifoaddr + 3 - i);
719a72b7 MD	234	}
	235	}
	236	} else {
	237	int odd = len & 0x0001;
	238
	239	len = len / 2;
ac9dfe9c	240	iowrite16_rep(fifoaddr, buf, len);
719a72b7 MD	241	if (unlikely(odd)) {
719a72b7 MD	242	buf = &buf[len];
f2e9039a YS	243	if (r8a66597->pdata->wr0_shorted_to_wr1)
f2e9039a YS	244	r8a66597_bclr(r8a66597, MBW_16, pipe->fifosel);
1c98347e	245	iowrite8((unsigned char)*buf, fifoaddr);
f2e9039a YS	246	if (r8a66597->pdata->wr0_shorted_to_wr1)
f2e9039a YS	247	r8a66597_bset(r8a66597, MBW_16, pipe->fifosel);
9424ea29 YS	248	}
9424ea29 YS	249	}
5d304358 YS	250	}
5d304358 YS	251
5d304358 YS	252	static inline unsigned long get_syscfg_reg(int port)
	253	{
	254	return port == 0 ? SYSCFG0 : SYSCFG1;
	255	}
	256
	257	static inline unsigned long get_syssts_reg(int port)
	258	{
	259	return port == 0 ? SYSSTS0 : SYSSTS1;
	260	}
	261
	262	static inline unsigned long get_dvstctr_reg(int port)
	263	{
	264	return port == 0 ? DVSTCTR0 : DVSTCTR1;
	265	}
	266
9424ea29 YS	267	static inline unsigned long get_dmacfg_reg(int port)
	268	{
	269	return port == 0 ? DMA0CFG : DMA1CFG;
	270	}
	271
5d304358 YS	272	static inline unsigned long get_intenb_reg(int port)
	273	{
	274	return port == 0 ? INTENB1 : INTENB2;
	275	}
	276
	277	static inline unsigned long get_intsts_reg(int port)
	278	{
	279	return port == 0 ? INTSTS1 : INTSTS2;
	280	}
	281
	282	static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
	283	{
	284	unsigned long dvstctr_reg = get_dvstctr_reg(port);
	285
	286	return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
	287	}
	288
	289	static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
	290	int power)
	291	{
	292	unsigned long dvstctr_reg = get_dvstctr_reg(port);
	293
5effabbe YS	294	if (r8a66597->pdata->port_power) {
	295	r8a66597->pdata->port_power(port, power);
	296	} else {
	297	if (power)
	298	r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
	299	else
	300	r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
	301	}
	302	}
	303
	304	static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
	305	{
	306	u16 clock = 0;
	307
	308	switch (pdata->xtal) {
	309	case R8A66597_PLATDATA_XTAL_12MHZ:
	310	clock = XTAL12;
	311	break;
	312	case R8A66597_PLATDATA_XTAL_24MHZ:
	313	clock = XTAL24;
	314	break;
	315	case R8A66597_PLATDATA_XTAL_48MHZ:
	316	clock = XTAL48;
	317	break;
	318	default:
	319	printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
	320	break;
	321	}
	322
	323	return clock;
5d304358 YS	324	}
	325
	326	#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
	327	#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
	328	#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
	329	#define get_devadd_addr(address) (DEVADD0 + address * 2)
	330
	331	#define enable_irq_ready(r8a66597, pipenum) \
	332	enable_pipe_irq(r8a66597, pipenum, BRDYENB)
	333	#define disable_irq_ready(r8a66597, pipenum) \
	334	disable_pipe_irq(r8a66597, pipenum, BRDYENB)
	335	#define enable_irq_empty(r8a66597, pipenum) \
	336	enable_pipe_irq(r8a66597, pipenum, BEMPENB)
	337	#define disable_irq_empty(r8a66597, pipenum) \
	338	disable_pipe_irq(r8a66597, pipenum, BEMPENB)
	339	#define enable_irq_nrdy(r8a66597, pipenum) \
	340	enable_pipe_irq(r8a66597, pipenum, NRDYENB)
	341	#define disable_irq_nrdy(r8a66597, pipenum) \
	342	disable_pipe_irq(r8a66597, pipenum, NRDYENB)
	343
	344	#endif /* __R8A66597_H__ */
	345