Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * OHCI HCD (Host Controller Driver) for USB. | |
dd9048af | 3 | * |
1da177e4 LT |
4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> |
5 | * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> | |
dd9048af | 6 | * |
1da177e4 LT |
7 | * This file is licenced under the GPL. |
8 | */ | |
9 | ||
7d12e780 | 10 | #include <linux/irq.h> |
5a0e3ad6 | 11 | #include <linux/slab.h> |
7d12e780 | 12 | |
1da177e4 LT |
13 | static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv) |
14 | { | |
15 | int last = urb_priv->length - 1; | |
16 | ||
17 | if (last >= 0) { | |
18 | int i; | |
19 | struct td *td; | |
20 | ||
21 | for (i = 0; i <= last; i++) { | |
22 | td = urb_priv->td [i]; | |
23 | if (td) | |
24 | td_free (hc, td); | |
25 | } | |
26 | } | |
27 | ||
28 | list_del (&urb_priv->pending); | |
29 | kfree (urb_priv); | |
30 | } | |
31 | ||
32 | /*-------------------------------------------------------------------------*/ | |
33 | ||
34 | /* | |
35 | * URB goes back to driver, and isn't reissued. | |
36 | * It's completely gone from HC data structures. | |
37 | * PRECONDITION: ohci lock held, irqs blocked. | |
38 | */ | |
39 | static void | |
55d84968 | 40 | finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status) |
1da177e4 LT |
41 | __releases(ohci->lock) |
42 | __acquires(ohci->lock) | |
43 | { | |
7ca9229c AS |
44 | struct usb_host_endpoint *ep = urb->ep; |
45 | struct urb_priv *urb_priv; | |
46 | ||
1da177e4 LT |
47 | // ASSERT (urb->hcpriv != 0); |
48 | ||
7ca9229c | 49 | restart: |
1da177e4 | 50 | urb_free_priv (ohci, urb->hcpriv); |
ece1d77e | 51 | urb->hcpriv = NULL; |
55d84968 AS |
52 | if (likely(status == -EINPROGRESS)) |
53 | status = 0; | |
1da177e4 LT |
54 | |
55 | switch (usb_pipetype (urb->pipe)) { | |
56 | case PIPE_ISOCHRONOUS: | |
57 | ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--; | |
a1f17a87 LY |
58 | if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) { |
59 | if (quirk_amdiso(ohci)) | |
ad93562b | 60 | usb_amd_quirk_pll_enable(); |
a1f17a87 LY |
61 | if (quirk_amdprefetch(ohci)) |
62 | sb800_prefetch(ohci, 0); | |
63 | } | |
1da177e4 LT |
64 | break; |
65 | case PIPE_INTERRUPT: | |
66 | ohci_to_hcd(ohci)->self.bandwidth_int_reqs--; | |
67 | break; | |
68 | } | |
69 | ||
70 | #ifdef OHCI_VERBOSE_DEBUG | |
55d84968 | 71 | urb_print(urb, "RET", usb_pipeout (urb->pipe), status); |
1da177e4 LT |
72 | #endif |
73 | ||
74 | /* urb->complete() can reenter this HCD */ | |
e9df41c5 | 75 | usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb); |
1da177e4 | 76 | spin_unlock (&ohci->lock); |
4a00027d | 77 | usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status); |
1da177e4 LT |
78 | spin_lock (&ohci->lock); |
79 | ||
80 | /* stop periodic dma if it's not needed */ | |
81 | if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0 | |
82 | && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) { | |
83 | ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE); | |
84 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
85 | } | |
7ca9229c AS |
86 | |
87 | /* | |
88 | * An isochronous URB that is sumitted too late won't have any TDs | |
89 | * (marked by the fact that the td_cnt value is larger than the | |
90 | * actual number of TDs). If the next URB on this endpoint is like | |
91 | * that, give it back now. | |
92 | */ | |
93 | if (!list_empty(&ep->urb_list)) { | |
94 | urb = list_first_entry(&ep->urb_list, struct urb, urb_list); | |
95 | urb_priv = urb->hcpriv; | |
96 | if (urb_priv->td_cnt > urb_priv->length) { | |
97 | status = 0; | |
98 | goto restart; | |
99 | } | |
100 | } | |
1da177e4 LT |
101 | } |
102 | ||
103 | ||
104 | /*-------------------------------------------------------------------------* | |
105 | * ED handling functions | |
dd9048af | 106 | *-------------------------------------------------------------------------*/ |
1da177e4 LT |
107 | |
108 | /* search for the right schedule branch to use for a periodic ed. | |
109 | * does some load balancing; returns the branch, or negative errno. | |
110 | */ | |
111 | static int balance (struct ohci_hcd *ohci, int interval, int load) | |
112 | { | |
113 | int i, branch = -ENOSPC; | |
114 | ||
115 | /* iso periods can be huge; iso tds specify frame numbers */ | |
116 | if (interval > NUM_INTS) | |
117 | interval = NUM_INTS; | |
118 | ||
119 | /* search for the least loaded schedule branch of that period | |
120 | * that has enough bandwidth left unreserved. | |
121 | */ | |
122 | for (i = 0; i < interval ; i++) { | |
123 | if (branch < 0 || ohci->load [branch] > ohci->load [i]) { | |
1da177e4 LT |
124 | int j; |
125 | ||
126 | /* usb 1.1 says 90% of one frame */ | |
127 | for (j = i; j < NUM_INTS; j += interval) { | |
128 | if ((ohci->load [j] + load) > 900) | |
129 | break; | |
130 | } | |
131 | if (j < NUM_INTS) | |
132 | continue; | |
dd9048af | 133 | branch = i; |
1da177e4 LT |
134 | } |
135 | } | |
136 | return branch; | |
137 | } | |
138 | ||
139 | /*-------------------------------------------------------------------------*/ | |
140 | ||
141 | /* both iso and interrupt requests have periods; this routine puts them | |
142 | * into the schedule tree in the apppropriate place. most iso devices use | |
143 | * 1msec periods, but that's not required. | |
144 | */ | |
145 | static void periodic_link (struct ohci_hcd *ohci, struct ed *ed) | |
146 | { | |
147 | unsigned i; | |
148 | ||
149 | ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n", | |
150 | (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "", | |
151 | ed, ed->branch, ed->load, ed->interval); | |
152 | ||
153 | for (i = ed->branch; i < NUM_INTS; i += ed->interval) { | |
154 | struct ed **prev = &ohci->periodic [i]; | |
155 | __hc32 *prev_p = &ohci->hcca->int_table [i]; | |
156 | struct ed *here = *prev; | |
157 | ||
158 | /* sorting each branch by period (slow before fast) | |
159 | * lets us share the faster parts of the tree. | |
160 | * (plus maybe: put interrupt eds before iso) | |
161 | */ | |
162 | while (here && ed != here) { | |
163 | if (ed->interval > here->interval) | |
164 | break; | |
165 | prev = &here->ed_next; | |
166 | prev_p = &here->hwNextED; | |
167 | here = *prev; | |
168 | } | |
169 | if (ed != here) { | |
170 | ed->ed_next = here; | |
171 | if (here) | |
172 | ed->hwNextED = *prev_p; | |
173 | wmb (); | |
174 | *prev = ed; | |
175 | *prev_p = cpu_to_hc32(ohci, ed->dma); | |
176 | wmb(); | |
177 | } | |
178 | ohci->load [i] += ed->load; | |
179 | } | |
180 | ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval; | |
181 | } | |
182 | ||
183 | /* link an ed into one of the HC chains */ | |
184 | ||
185 | static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed) | |
dd9048af | 186 | { |
1da177e4 LT |
187 | int branch; |
188 | ||
1da177e4 LT |
189 | ed->state = ED_OPER; |
190 | ed->ed_prev = NULL; | |
191 | ed->ed_next = NULL; | |
192 | ed->hwNextED = 0; | |
89a0fd18 MN |
193 | if (quirk_zfmicro(ohci) |
194 | && (ed->type == PIPE_INTERRUPT) | |
195 | && !(ohci->eds_scheduled++)) | |
9cebcdc7 | 196 | mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ)); |
1da177e4 LT |
197 | wmb (); |
198 | ||
199 | /* we care about rm_list when setting CLE/BLE in case the HC was at | |
200 | * work on some TD when CLE/BLE was turned off, and isn't quiesced | |
201 | * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF. | |
202 | * | |
203 | * control and bulk EDs are doubly linked (ed_next, ed_prev), but | |
204 | * periodic ones are singly linked (ed_next). that's because the | |
205 | * periodic schedule encodes a tree like figure 3-5 in the ohci | |
206 | * spec: each qh can have several "previous" nodes, and the tree | |
207 | * doesn't have unused/idle descriptors. | |
208 | */ | |
209 | switch (ed->type) { | |
210 | case PIPE_CONTROL: | |
211 | if (ohci->ed_controltail == NULL) { | |
212 | WARN_ON (ohci->hc_control & OHCI_CTRL_CLE); | |
213 | ohci_writel (ohci, ed->dma, | |
214 | &ohci->regs->ed_controlhead); | |
215 | } else { | |
216 | ohci->ed_controltail->ed_next = ed; | |
217 | ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci, | |
218 | ed->dma); | |
219 | } | |
220 | ed->ed_prev = ohci->ed_controltail; | |
221 | if (!ohci->ed_controltail && !ohci->ed_rm_list) { | |
222 | wmb(); | |
223 | ohci->hc_control |= OHCI_CTRL_CLE; | |
224 | ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent); | |
225 | ohci_writel (ohci, ohci->hc_control, | |
226 | &ohci->regs->control); | |
227 | } | |
228 | ohci->ed_controltail = ed; | |
229 | break; | |
230 | ||
231 | case PIPE_BULK: | |
232 | if (ohci->ed_bulktail == NULL) { | |
233 | WARN_ON (ohci->hc_control & OHCI_CTRL_BLE); | |
234 | ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead); | |
235 | } else { | |
236 | ohci->ed_bulktail->ed_next = ed; | |
237 | ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci, | |
238 | ed->dma); | |
239 | } | |
240 | ed->ed_prev = ohci->ed_bulktail; | |
241 | if (!ohci->ed_bulktail && !ohci->ed_rm_list) { | |
242 | wmb(); | |
243 | ohci->hc_control |= OHCI_CTRL_BLE; | |
244 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent); | |
245 | ohci_writel (ohci, ohci->hc_control, | |
246 | &ohci->regs->control); | |
247 | } | |
248 | ohci->ed_bulktail = ed; | |
249 | break; | |
250 | ||
251 | // case PIPE_INTERRUPT: | |
252 | // case PIPE_ISOCHRONOUS: | |
253 | default: | |
254 | branch = balance (ohci, ed->interval, ed->load); | |
255 | if (branch < 0) { | |
256 | ohci_dbg (ohci, | |
257 | "ERR %d, interval %d msecs, load %d\n", | |
258 | branch, ed->interval, ed->load); | |
259 | // FIXME if there are TDs queued, fail them! | |
260 | return branch; | |
261 | } | |
262 | ed->branch = branch; | |
263 | periodic_link (ohci, ed); | |
dd9048af | 264 | } |
1da177e4 LT |
265 | |
266 | /* the HC may not see the schedule updates yet, but if it does | |
267 | * then they'll be properly ordered. | |
268 | */ | |
269 | return 0; | |
270 | } | |
271 | ||
272 | /*-------------------------------------------------------------------------*/ | |
273 | ||
274 | /* scan the periodic table to find and unlink this ED */ | |
275 | static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed) | |
276 | { | |
277 | int i; | |
278 | ||
279 | for (i = ed->branch; i < NUM_INTS; i += ed->interval) { | |
280 | struct ed *temp; | |
281 | struct ed **prev = &ohci->periodic [i]; | |
282 | __hc32 *prev_p = &ohci->hcca->int_table [i]; | |
283 | ||
284 | while (*prev && (temp = *prev) != ed) { | |
285 | prev_p = &temp->hwNextED; | |
286 | prev = &temp->ed_next; | |
287 | } | |
288 | if (*prev) { | |
289 | *prev_p = ed->hwNextED; | |
290 | *prev = ed->ed_next; | |
291 | } | |
292 | ohci->load [i] -= ed->load; | |
dd9048af | 293 | } |
1da177e4 LT |
294 | ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval; |
295 | ||
296 | ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n", | |
297 | (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "", | |
298 | ed, ed->branch, ed->load, ed->interval); | |
299 | } | |
300 | ||
dd9048af | 301 | /* unlink an ed from one of the HC chains. |
1da177e4 LT |
302 | * just the link to the ed is unlinked. |
303 | * the link from the ed still points to another operational ed or 0 | |
304 | * so the HC can eventually finish the processing of the unlinked ed | |
305 | * (assuming it already started that, which needn't be true). | |
306 | * | |
307 | * ED_UNLINK is a transient state: the HC may still see this ED, but soon | |
308 | * it won't. ED_SKIP means the HC will finish its current transaction, | |
309 | * but won't start anything new. The TD queue may still grow; device | |
310 | * drivers don't know about this HCD-internal state. | |
311 | * | |
312 | * When the HC can't see the ED, something changes ED_UNLINK to one of: | |
313 | * | |
314 | * - ED_OPER: when there's any request queued, the ED gets rescheduled | |
315 | * immediately. HC should be working on them. | |
316 | * | |
e7b094f8 | 317 | * - ED_IDLE: when there's no TD queue or the HC isn't running. |
1da177e4 LT |
318 | * |
319 | * When finish_unlinks() runs later, after SOF interrupt, it will often | |
320 | * complete one or more URB unlinks before making that state change. | |
321 | */ | |
dd9048af | 322 | static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed) |
1da177e4 LT |
323 | { |
324 | ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP); | |
325 | wmb (); | |
326 | ed->state = ED_UNLINK; | |
327 | ||
328 | /* To deschedule something from the control or bulk list, just | |
329 | * clear CLE/BLE and wait. There's no safe way to scrub out list | |
330 | * head/current registers until later, and "later" isn't very | |
331 | * tightly specified. Figure 6-5 and Section 6.4.2.2 show how | |
332 | * the HC is reading the ED queues (while we modify them). | |
333 | * | |
334 | * For now, ed_schedule() is "later". It might be good paranoia | |
335 | * to scrub those registers in finish_unlinks(), in case of bugs | |
336 | * that make the HC try to use them. | |
337 | */ | |
338 | switch (ed->type) { | |
339 | case PIPE_CONTROL: | |
340 | /* remove ED from the HC's list: */ | |
341 | if (ed->ed_prev == NULL) { | |
342 | if (!ed->hwNextED) { | |
343 | ohci->hc_control &= ~OHCI_CTRL_CLE; | |
344 | ohci_writel (ohci, ohci->hc_control, | |
345 | &ohci->regs->control); | |
346 | // a ohci_readl() later syncs CLE with the HC | |
347 | } else | |
348 | ohci_writel (ohci, | |
349 | hc32_to_cpup (ohci, &ed->hwNextED), | |
350 | &ohci->regs->ed_controlhead); | |
351 | } else { | |
352 | ed->ed_prev->ed_next = ed->ed_next; | |
353 | ed->ed_prev->hwNextED = ed->hwNextED; | |
354 | } | |
355 | /* remove ED from the HCD's list: */ | |
356 | if (ohci->ed_controltail == ed) { | |
357 | ohci->ed_controltail = ed->ed_prev; | |
358 | if (ohci->ed_controltail) | |
359 | ohci->ed_controltail->ed_next = NULL; | |
360 | } else if (ed->ed_next) { | |
361 | ed->ed_next->ed_prev = ed->ed_prev; | |
362 | } | |
363 | break; | |
364 | ||
365 | case PIPE_BULK: | |
366 | /* remove ED from the HC's list: */ | |
367 | if (ed->ed_prev == NULL) { | |
368 | if (!ed->hwNextED) { | |
369 | ohci->hc_control &= ~OHCI_CTRL_BLE; | |
370 | ohci_writel (ohci, ohci->hc_control, | |
371 | &ohci->regs->control); | |
372 | // a ohci_readl() later syncs BLE with the HC | |
373 | } else | |
374 | ohci_writel (ohci, | |
375 | hc32_to_cpup (ohci, &ed->hwNextED), | |
376 | &ohci->regs->ed_bulkhead); | |
377 | } else { | |
378 | ed->ed_prev->ed_next = ed->ed_next; | |
379 | ed->ed_prev->hwNextED = ed->hwNextED; | |
380 | } | |
381 | /* remove ED from the HCD's list: */ | |
382 | if (ohci->ed_bulktail == ed) { | |
383 | ohci->ed_bulktail = ed->ed_prev; | |
384 | if (ohci->ed_bulktail) | |
385 | ohci->ed_bulktail->ed_next = NULL; | |
386 | } else if (ed->ed_next) { | |
387 | ed->ed_next->ed_prev = ed->ed_prev; | |
388 | } | |
389 | break; | |
390 | ||
391 | // case PIPE_INTERRUPT: | |
392 | // case PIPE_ISOCHRONOUS: | |
393 | default: | |
394 | periodic_unlink (ohci, ed); | |
395 | break; | |
396 | } | |
397 | } | |
398 | ||
399 | ||
400 | /*-------------------------------------------------------------------------*/ | |
401 | ||
402 | /* get and maybe (re)init an endpoint. init _should_ be done only as part | |
403 | * of enumeration, usb_set_configuration() or usb_set_interface(). | |
404 | */ | |
405 | static struct ed *ed_get ( | |
406 | struct ohci_hcd *ohci, | |
407 | struct usb_host_endpoint *ep, | |
408 | struct usb_device *udev, | |
409 | unsigned int pipe, | |
410 | int interval | |
411 | ) { | |
dd9048af | 412 | struct ed *ed; |
1da177e4 LT |
413 | unsigned long flags; |
414 | ||
415 | spin_lock_irqsave (&ohci->lock, flags); | |
416 | ||
417 | if (!(ed = ep->hcpriv)) { | |
418 | struct td *td; | |
419 | int is_out; | |
420 | u32 info; | |
421 | ||
422 | ed = ed_alloc (ohci, GFP_ATOMIC); | |
423 | if (!ed) { | |
424 | /* out of memory */ | |
425 | goto done; | |
426 | } | |
427 | ||
dd9048af | 428 | /* dummy td; end of td list for ed */ |
1da177e4 | 429 | td = td_alloc (ohci, GFP_ATOMIC); |
dd9048af | 430 | if (!td) { |
1da177e4 LT |
431 | /* out of memory */ |
432 | ed_free (ohci, ed); | |
433 | ed = NULL; | |
434 | goto done; | |
435 | } | |
436 | ed->dummy = td; | |
437 | ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma); | |
438 | ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */ | |
439 | ed->state = ED_IDLE; | |
440 | ||
441 | is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN); | |
442 | ||
443 | /* FIXME usbcore changes dev->devnum before SET_ADDRESS | |
4b26d50b | 444 | * succeeds ... otherwise we wouldn't need "pipe". |
1da177e4 LT |
445 | */ |
446 | info = usb_pipedevice (pipe); | |
447 | ed->type = usb_pipetype(pipe); | |
448 | ||
449 | info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7; | |
29cc8897 | 450 | info |= usb_endpoint_maxp(&ep->desc) << 16; |
1da177e4 LT |
451 | if (udev->speed == USB_SPEED_LOW) |
452 | info |= ED_LOWSPEED; | |
453 | /* only control transfers store pids in tds */ | |
454 | if (ed->type != PIPE_CONTROL) { | |
455 | info |= is_out ? ED_OUT : ED_IN; | |
456 | if (ed->type != PIPE_BULK) { | |
457 | /* periodic transfers... */ | |
458 | if (ed->type == PIPE_ISOCHRONOUS) | |
459 | info |= ED_ISO; | |
460 | else if (interval > 32) /* iso can be bigger */ | |
461 | interval = 32; | |
462 | ed->interval = interval; | |
463 | ed->load = usb_calc_bus_time ( | |
464 | udev->speed, !is_out, | |
465 | ed->type == PIPE_ISOCHRONOUS, | |
29cc8897 | 466 | usb_endpoint_maxp(&ep->desc)) |
1da177e4 LT |
467 | / 1000; |
468 | } | |
469 | } | |
470 | ed->hwINFO = cpu_to_hc32(ohci, info); | |
471 | ||
472 | ep->hcpriv = ed; | |
473 | } | |
474 | ||
475 | done: | |
476 | spin_unlock_irqrestore (&ohci->lock, flags); | |
dd9048af | 477 | return ed; |
1da177e4 LT |
478 | } |
479 | ||
480 | /*-------------------------------------------------------------------------*/ | |
481 | ||
482 | /* request unlinking of an endpoint from an operational HC. | |
483 | * put the ep on the rm_list | |
484 | * real work is done at the next start frame (SF) hardware interrupt | |
485 | * caller guarantees HCD is running, so hardware access is safe, | |
486 | * and that ed->state is ED_OPER | |
487 | */ | |
488 | static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed) | |
dd9048af | 489 | { |
1da177e4 LT |
490 | ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE); |
491 | ed_deschedule (ohci, ed); | |
492 | ||
493 | /* rm_list is just singly linked, for simplicity */ | |
494 | ed->ed_next = ohci->ed_rm_list; | |
495 | ed->ed_prev = NULL; | |
496 | ohci->ed_rm_list = ed; | |
497 | ||
498 | /* enable SOF interrupt */ | |
499 | ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus); | |
500 | ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable); | |
501 | // flush those writes, and get latest HCCA contents | |
502 | (void) ohci_readl (ohci, &ohci->regs->control); | |
503 | ||
504 | /* SF interrupt might get delayed; record the frame counter value that | |
505 | * indicates when the HC isn't looking at it, so concurrent unlinks | |
506 | * behave. frame_no wraps every 2^16 msec, and changes right before | |
507 | * SF is triggered. | |
508 | */ | |
509 | ed->tick = ohci_frame_no(ohci) + 1; | |
510 | ||
511 | } | |
512 | ||
513 | /*-------------------------------------------------------------------------* | |
514 | * TD handling functions | |
515 | *-------------------------------------------------------------------------*/ | |
516 | ||
517 | /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ | |
518 | ||
519 | static void | |
520 | td_fill (struct ohci_hcd *ohci, u32 info, | |
521 | dma_addr_t data, int len, | |
522 | struct urb *urb, int index) | |
523 | { | |
524 | struct td *td, *td_pt; | |
525 | struct urb_priv *urb_priv = urb->hcpriv; | |
526 | int is_iso = info & TD_ISO; | |
527 | int hash; | |
528 | ||
529 | // ASSERT (index < urb_priv->length); | |
530 | ||
531 | /* aim for only one interrupt per urb. mostly applies to control | |
532 | * and iso; other urbs rarely need more than one TD per urb. | |
533 | * this way, only final tds (or ones with an error) cause IRQs. | |
534 | * at least immediately; use DI=6 in case any control request is | |
535 | * tempted to die part way through. (and to force the hc to flush | |
536 | * its donelist soonish, even on unlink paths.) | |
537 | * | |
538 | * NOTE: could delay interrupts even for the last TD, and get fewer | |
539 | * interrupts ... increasing per-urb latency by sharing interrupts. | |
540 | * Drivers that queue bulk urbs may request that behavior. | |
541 | */ | |
542 | if (index != (urb_priv->length - 1) | |
543 | || (urb->transfer_flags & URB_NO_INTERRUPT)) | |
544 | info |= TD_DI_SET (6); | |
545 | ||
546 | /* use this td as the next dummy */ | |
547 | td_pt = urb_priv->td [index]; | |
548 | ||
549 | /* fill the old dummy TD */ | |
550 | td = urb_priv->td [index] = urb_priv->ed->dummy; | |
551 | urb_priv->ed->dummy = td_pt; | |
552 | ||
553 | td->ed = urb_priv->ed; | |
554 | td->next_dl_td = NULL; | |
555 | td->index = index; | |
dd9048af | 556 | td->urb = urb; |
1da177e4 LT |
557 | td->data_dma = data; |
558 | if (!len) | |
559 | data = 0; | |
560 | ||
561 | td->hwINFO = cpu_to_hc32 (ohci, info); | |
562 | if (is_iso) { | |
563 | td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000); | |
564 | *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci, | |
565 | (data & 0x0FFF) | 0xE000); | |
1da177e4 | 566 | } else { |
dd9048af DB |
567 | td->hwCBP = cpu_to_hc32 (ohci, data); |
568 | } | |
1da177e4 LT |
569 | if (data) |
570 | td->hwBE = cpu_to_hc32 (ohci, data + len - 1); | |
571 | else | |
572 | td->hwBE = 0; | |
573 | td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma); | |
574 | ||
575 | /* append to queue */ | |
576 | list_add_tail (&td->td_list, &td->ed->td_list); | |
577 | ||
578 | /* hash it for later reverse mapping */ | |
579 | hash = TD_HASH_FUNC (td->td_dma); | |
580 | td->td_hash = ohci->td_hash [hash]; | |
581 | ohci->td_hash [hash] = td; | |
582 | ||
583 | /* HC might read the TD (or cachelines) right away ... */ | |
584 | wmb (); | |
585 | td->ed->hwTailP = td->hwNextTD; | |
586 | } | |
587 | ||
588 | /*-------------------------------------------------------------------------*/ | |
589 | ||
590 | /* Prepare all TDs of a transfer, and queue them onto the ED. | |
591 | * Caller guarantees HC is active. | |
592 | * Usually the ED is already on the schedule, so TDs might be | |
593 | * processed as soon as they're queued. | |
594 | */ | |
595 | static void td_submit_urb ( | |
596 | struct ohci_hcd *ohci, | |
597 | struct urb *urb | |
598 | ) { | |
599 | struct urb_priv *urb_priv = urb->hcpriv; | |
600 | dma_addr_t data; | |
601 | int data_len = urb->transfer_buffer_length; | |
602 | int cnt = 0; | |
603 | u32 info = 0; | |
604 | int is_out = usb_pipeout (urb->pipe); | |
605 | int periodic = 0; | |
606 | ||
607 | /* OHCI handles the bulk/interrupt data toggles itself. We just | |
608 | * use the device toggle bits for resetting, and rely on the fact | |
609 | * that resetting toggle is meaningless if the endpoint is active. | |
610 | */ | |
dd9048af | 611 | if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) { |
1da177e4 LT |
612 | usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), |
613 | is_out, 1); | |
614 | urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C); | |
615 | } | |
616 | ||
1da177e4 LT |
617 | list_add (&urb_priv->pending, &ohci->pending); |
618 | ||
619 | if (data_len) | |
620 | data = urb->transfer_dma; | |
621 | else | |
622 | data = 0; | |
623 | ||
624 | /* NOTE: TD_CC is set so we can tell which TDs the HC processed by | |
625 | * using TD_CC_GET, as well as by seeing them on the done list. | |
626 | * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.) | |
627 | */ | |
628 | switch (urb_priv->ed->type) { | |
629 | ||
630 | /* Bulk and interrupt are identical except for where in the schedule | |
631 | * their EDs live. | |
632 | */ | |
633 | case PIPE_INTERRUPT: | |
634 | /* ... and periodic urbs have extra accounting */ | |
635 | periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0 | |
636 | && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0; | |
637 | /* FALLTHROUGH */ | |
638 | case PIPE_BULK: | |
639 | info = is_out | |
640 | ? TD_T_TOGGLE | TD_CC | TD_DP_OUT | |
641 | : TD_T_TOGGLE | TD_CC | TD_DP_IN; | |
642 | /* TDs _could_ transfer up to 8K each */ | |
643 | while (data_len > 4096) { | |
644 | td_fill (ohci, info, data, 4096, urb, cnt); | |
645 | data += 4096; | |
646 | data_len -= 4096; | |
647 | cnt++; | |
648 | } | |
649 | /* maybe avoid ED halt on final TD short read */ | |
650 | if (!(urb->transfer_flags & URB_SHORT_NOT_OK)) | |
651 | info |= TD_R; | |
652 | td_fill (ohci, info, data, data_len, urb, cnt); | |
653 | cnt++; | |
654 | if ((urb->transfer_flags & URB_ZERO_PACKET) | |
655 | && cnt < urb_priv->length) { | |
656 | td_fill (ohci, info, 0, 0, urb, cnt); | |
657 | cnt++; | |
658 | } | |
659 | /* maybe kickstart bulk list */ | |
660 | if (urb_priv->ed->type == PIPE_BULK) { | |
661 | wmb (); | |
662 | ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus); | |
663 | } | |
664 | break; | |
665 | ||
666 | /* control manages DATA0/DATA1 toggle per-request; SETUP resets it, | |
667 | * any DATA phase works normally, and the STATUS ack is special. | |
668 | */ | |
669 | case PIPE_CONTROL: | |
670 | info = TD_CC | TD_DP_SETUP | TD_T_DATA0; | |
671 | td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++); | |
672 | if (data_len > 0) { | |
673 | info = TD_CC | TD_R | TD_T_DATA1; | |
674 | info |= is_out ? TD_DP_OUT : TD_DP_IN; | |
675 | /* NOTE: mishandles transfers >8K, some >4K */ | |
676 | td_fill (ohci, info, data, data_len, urb, cnt++); | |
677 | } | |
678 | info = (is_out || data_len == 0) | |
679 | ? TD_CC | TD_DP_IN | TD_T_DATA1 | |
680 | : TD_CC | TD_DP_OUT | TD_T_DATA1; | |
681 | td_fill (ohci, info, data, 0, urb, cnt++); | |
682 | /* maybe kickstart control list */ | |
683 | wmb (); | |
684 | ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus); | |
685 | break; | |
686 | ||
687 | /* ISO has no retransmit, so no toggle; and it uses special TDs. | |
688 | * Each TD could handle multiple consecutive frames (interval 1); | |
689 | * we could often reduce the number of TDs here. | |
690 | */ | |
691 | case PIPE_ISOCHRONOUS: | |
6a41b4d3 AS |
692 | for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets; |
693 | cnt++) { | |
1da177e4 LT |
694 | int frame = urb->start_frame; |
695 | ||
696 | // FIXME scheduling should handle frame counter | |
697 | // roll-around ... exotic case (and OHCI has | |
698 | // a 2^16 iso range, vs other HCs max of 2^10) | |
699 | frame += cnt * urb->interval; | |
700 | frame &= 0xffff; | |
701 | td_fill (ohci, TD_CC | TD_ISO | frame, | |
702 | data + urb->iso_frame_desc [cnt].offset, | |
703 | urb->iso_frame_desc [cnt].length, urb, cnt); | |
704 | } | |
a1f17a87 LY |
705 | if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) { |
706 | if (quirk_amdiso(ohci)) | |
ad93562b | 707 | usb_amd_quirk_pll_disable(); |
a1f17a87 LY |
708 | if (quirk_amdprefetch(ohci)) |
709 | sb800_prefetch(ohci, 1); | |
710 | } | |
1da177e4 LT |
711 | periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0 |
712 | && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0; | |
713 | break; | |
714 | } | |
715 | ||
716 | /* start periodic dma if needed */ | |
717 | if (periodic) { | |
718 | wmb (); | |
719 | ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE; | |
720 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
721 | } | |
722 | ||
723 | // ASSERT (urb_priv->length == cnt); | |
724 | } | |
725 | ||
726 | /*-------------------------------------------------------------------------* | |
727 | * Done List handling functions | |
728 | *-------------------------------------------------------------------------*/ | |
729 | ||
55d84968 AS |
730 | /* calculate transfer length/status and update the urb */ |
731 | static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td) | |
1da177e4 LT |
732 | { |
733 | u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO); | |
734 | int cc = 0; | |
55d84968 | 735 | int status = -EINPROGRESS; |
1da177e4 LT |
736 | |
737 | list_del (&td->td_list); | |
738 | ||
739 | /* ISO ... drivers see per-TD length/status */ | |
dd9048af | 740 | if (tdINFO & TD_ISO) { |
55d84968 | 741 | u16 tdPSW = ohci_hwPSW(ohci, td, 0); |
1da177e4 LT |
742 | int dlen = 0; |
743 | ||
744 | /* NOTE: assumes FC in tdINFO == 0, and that | |
745 | * only the first of 0..MAXPSW psws is used. | |
746 | */ | |
747 | ||
dd9048af DB |
748 | cc = (tdPSW >> 12) & 0xF; |
749 | if (tdINFO & TD_CC) /* hc didn't touch? */ | |
55d84968 | 750 | return status; |
1da177e4 LT |
751 | |
752 | if (usb_pipeout (urb->pipe)) | |
753 | dlen = urb->iso_frame_desc [td->index].length; | |
754 | else { | |
755 | /* short reads are always OK for ISO */ | |
756 | if (cc == TD_DATAUNDERRUN) | |
757 | cc = TD_CC_NOERROR; | |
758 | dlen = tdPSW & 0x3ff; | |
759 | } | |
760 | urb->actual_length += dlen; | |
761 | urb->iso_frame_desc [td->index].actual_length = dlen; | |
762 | urb->iso_frame_desc [td->index].status = cc_to_error [cc]; | |
763 | ||
764 | if (cc != TD_CC_NOERROR) | |
765 | ohci_vdbg (ohci, | |
766 | "urb %p iso td %p (%d) len %d cc %d\n", | |
767 | urb, td, 1 + td->index, dlen, cc); | |
768 | ||
769 | /* BULK, INT, CONTROL ... drivers see aggregate length/status, | |
770 | * except that "setup" bytes aren't counted and "short" transfers | |
771 | * might not be reported as errors. | |
772 | */ | |
773 | } else { | |
774 | int type = usb_pipetype (urb->pipe); | |
775 | u32 tdBE = hc32_to_cpup (ohci, &td->hwBE); | |
776 | ||
dd9048af | 777 | cc = TD_CC_GET (tdINFO); |
1da177e4 LT |
778 | |
779 | /* update packet status if needed (short is normally ok) */ | |
780 | if (cc == TD_DATAUNDERRUN | |
781 | && !(urb->transfer_flags & URB_SHORT_NOT_OK)) | |
782 | cc = TD_CC_NOERROR; | |
55d84968 AS |
783 | if (cc != TD_CC_NOERROR && cc < 0x0E) |
784 | status = cc_to_error[cc]; | |
1da177e4 LT |
785 | |
786 | /* count all non-empty packets except control SETUP packet */ | |
787 | if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) { | |
788 | if (td->hwCBP == 0) | |
789 | urb->actual_length += tdBE - td->data_dma + 1; | |
790 | else | |
791 | urb->actual_length += | |
792 | hc32_to_cpup (ohci, &td->hwCBP) | |
793 | - td->data_dma; | |
794 | } | |
795 | ||
796 | if (cc != TD_CC_NOERROR && cc < 0x0E) | |
797 | ohci_vdbg (ohci, | |
798 | "urb %p td %p (%d) cc %d, len=%d/%d\n", | |
799 | urb, td, 1 + td->index, cc, | |
800 | urb->actual_length, | |
801 | urb->transfer_buffer_length); | |
dd9048af | 802 | } |
55d84968 | 803 | return status; |
1da177e4 LT |
804 | } |
805 | ||
806 | /*-------------------------------------------------------------------------*/ | |
807 | ||
6e8fe43b | 808 | static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc) |
1da177e4 | 809 | { |
dd9048af | 810 | struct urb *urb = td->urb; |
6e8fe43b | 811 | urb_priv_t *urb_priv = urb->hcpriv; |
1da177e4 LT |
812 | struct ed *ed = td->ed; |
813 | struct list_head *tmp = td->td_list.next; | |
814 | __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C); | |
815 | ||
816 | /* clear ed halt; this is the td that caused it, but keep it inactive | |
817 | * until its urb->complete() has a chance to clean up. | |
818 | */ | |
819 | ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP); | |
820 | wmb (); | |
dd9048af | 821 | ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H); |
1da177e4 | 822 | |
6e8fe43b AS |
823 | /* Get rid of all later tds from this urb. We don't have |
824 | * to be careful: no errors and nothing was transferred. | |
825 | * Also patch the ed so it looks as if those tds completed normally. | |
1da177e4 LT |
826 | */ |
827 | while (tmp != &ed->td_list) { | |
828 | struct td *next; | |
1da177e4 LT |
829 | |
830 | next = list_entry (tmp, struct td, td_list); | |
831 | tmp = next->td_list.next; | |
832 | ||
833 | if (next->urb != urb) | |
834 | break; | |
835 | ||
836 | /* NOTE: if multi-td control DATA segments get supported, | |
837 | * this urb had one of them, this td wasn't the last td | |
838 | * in that segment (TD_R clear), this ed halted because | |
839 | * of a short read, _and_ URB_SHORT_NOT_OK is clear ... | |
840 | * then we need to leave the control STATUS packet queued | |
841 | * and clear ED_SKIP. | |
842 | */ | |
1da177e4 | 843 | |
6e8fe43b AS |
844 | list_del(&next->td_list); |
845 | urb_priv->td_cnt++; | |
1da177e4 LT |
846 | ed->hwHeadP = next->hwNextTD | toggle; |
847 | } | |
848 | ||
849 | /* help for troubleshooting: report anything that | |
850 | * looks odd ... that doesn't include protocol stalls | |
851 | * (or maybe some other things) | |
852 | */ | |
853 | switch (cc) { | |
854 | case TD_DATAUNDERRUN: | |
855 | if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0) | |
856 | break; | |
857 | /* fallthrough */ | |
858 | case TD_CC_STALL: | |
859 | if (usb_pipecontrol (urb->pipe)) | |
860 | break; | |
861 | /* fallthrough */ | |
862 | default: | |
863 | ohci_dbg (ohci, | |
864 | "urb %p path %s ep%d%s %08x cc %d --> status %d\n", | |
865 | urb, urb->dev->devpath, | |
866 | usb_pipeendpoint (urb->pipe), | |
867 | usb_pipein (urb->pipe) ? "in" : "out", | |
868 | hc32_to_cpu (ohci, td->hwINFO), | |
869 | cc, cc_to_error [cc]); | |
870 | } | |
1da177e4 LT |
871 | } |
872 | ||
873 | /* replies to the request have to be on a FIFO basis so | |
874 | * we unreverse the hc-reversed done-list | |
875 | */ | |
876 | static struct td *dl_reverse_done_list (struct ohci_hcd *ohci) | |
877 | { | |
878 | u32 td_dma; | |
879 | struct td *td_rev = NULL; | |
880 | struct td *td = NULL; | |
881 | ||
882 | td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head); | |
883 | ohci->hcca->done_head = 0; | |
884 | wmb(); | |
885 | ||
886 | /* get TD from hc's singly linked list, and | |
887 | * prepend to ours. ed->td_list changes later. | |
888 | */ | |
dd9048af DB |
889 | while (td_dma) { |
890 | int cc; | |
1da177e4 LT |
891 | |
892 | td = dma_to_td (ohci, td_dma); | |
893 | if (!td) { | |
894 | ohci_err (ohci, "bad entry %8x\n", td_dma); | |
895 | break; | |
896 | } | |
897 | ||
898 | td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE); | |
899 | cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO)); | |
900 | ||
901 | /* Non-iso endpoints can halt on error; un-halt, | |
902 | * and dequeue any other TDs from this urb. | |
903 | * No other TD could have caused the halt. | |
904 | */ | |
905 | if (cc != TD_CC_NOERROR | |
906 | && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H))) | |
6e8fe43b | 907 | ed_halted(ohci, td, cc); |
1da177e4 | 908 | |
dd9048af | 909 | td->next_dl_td = td_rev; |
1da177e4 LT |
910 | td_rev = td; |
911 | td_dma = hc32_to_cpup (ohci, &td->hwNextTD); | |
dd9048af | 912 | } |
1da177e4 LT |
913 | return td_rev; |
914 | } | |
915 | ||
916 | /*-------------------------------------------------------------------------*/ | |
917 | ||
918 | /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */ | |
919 | static void | |
7d12e780 | 920 | finish_unlinks (struct ohci_hcd *ohci, u16 tick) |
1da177e4 LT |
921 | { |
922 | struct ed *ed, **last; | |
923 | ||
924 | rescan_all: | |
925 | for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) { | |
926 | struct list_head *entry, *tmp; | |
927 | int completed, modified; | |
928 | __hc32 *prev; | |
929 | ||
930 | /* only take off EDs that the HC isn't using, accounting for | |
931 | * frame counter wraps and EDs with partially retired TDs | |
932 | */ | |
b7463c71 | 933 | if (likely(ohci->rh_state == OHCI_RH_RUNNING)) { |
1da177e4 LT |
934 | if (tick_before (tick, ed->tick)) { |
935 | skip_ed: | |
936 | last = &ed->ed_next; | |
937 | continue; | |
938 | } | |
939 | ||
940 | if (!list_empty (&ed->td_list)) { | |
941 | struct td *td; | |
942 | u32 head; | |
943 | ||
944 | td = list_entry (ed->td_list.next, struct td, | |
945 | td_list); | |
946 | head = hc32_to_cpu (ohci, ed->hwHeadP) & | |
947 | TD_MASK; | |
948 | ||
949 | /* INTR_WDH may need to clean up first */ | |
89a0fd18 MN |
950 | if (td->td_dma != head) { |
951 | if (ed == ohci->ed_to_check) | |
952 | ohci->ed_to_check = NULL; | |
953 | else | |
954 | goto skip_ed; | |
955 | } | |
1da177e4 LT |
956 | } |
957 | } | |
958 | ||
e7b094f8 | 959 | /* ED's now officially unlinked, hc doesn't see */ |
e7b094f8 AS |
960 | if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT) |
961 | ohci->eds_scheduled--; | |
962 | ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H); | |
963 | ed->hwNextED = 0; | |
964 | wmb(); | |
965 | ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE); | |
e7b094f8 | 966 | |
1da177e4 LT |
967 | /* reentrancy: if we drop the schedule lock, someone might |
968 | * have modified this list. normally it's just prepending | |
969 | * entries (which we'd ignore), but paranoia won't hurt. | |
970 | */ | |
1da177e4 LT |
971 | modified = 0; |
972 | ||
973 | /* unlink urbs as requested, but rescan the list after | |
974 | * we call a completion since it might have unlinked | |
975 | * another (earlier) urb | |
976 | * | |
977 | * When we get here, the HC doesn't see this ed. But it | |
978 | * must not be rescheduled until all completed URBs have | |
979 | * been given back to the driver. | |
980 | */ | |
981 | rescan_this: | |
982 | completed = 0; | |
983 | prev = &ed->hwHeadP; | |
984 | list_for_each_safe (entry, tmp, &ed->td_list) { | |
985 | struct td *td; | |
986 | struct urb *urb; | |
987 | urb_priv_t *urb_priv; | |
988 | __hc32 savebits; | |
29c8f6a7 | 989 | u32 tdINFO; |
1da177e4 LT |
990 | |
991 | td = list_entry (entry, struct td, td_list); | |
992 | urb = td->urb; | |
993 | urb_priv = td->urb->hcpriv; | |
994 | ||
eb231054 | 995 | if (!urb->unlinked) { |
1da177e4 LT |
996 | prev = &td->hwNextTD; |
997 | continue; | |
998 | } | |
999 | ||
1000 | /* patch pointer hc uses */ | |
1001 | savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK); | |
1002 | *prev = td->hwNextTD | savebits; | |
1003 | ||
29c8f6a7 DB |
1004 | /* If this was unlinked, the TD may not have been |
1005 | * retired ... so manually save the data toggle. | |
1006 | * The controller ignores the value we save for | |
1007 | * control and ISO endpoints. | |
1008 | */ | |
1009 | tdINFO = hc32_to_cpup(ohci, &td->hwINFO); | |
1010 | if ((tdINFO & TD_T) == TD_T_DATA0) | |
1011 | ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C); | |
1012 | else if ((tdINFO & TD_T) == TD_T_DATA1) | |
1013 | ed->hwHeadP |= cpu_to_hc32(ohci, ED_C); | |
1014 | ||
1da177e4 LT |
1015 | /* HC may have partly processed this TD */ |
1016 | td_done (ohci, urb, td); | |
1017 | urb_priv->td_cnt++; | |
1018 | ||
1019 | /* if URB is done, clean up */ | |
7ca9229c | 1020 | if (urb_priv->td_cnt >= urb_priv->length) { |
1da177e4 | 1021 | modified = completed = 1; |
55d84968 | 1022 | finish_urb(ohci, urb, 0); |
1da177e4 LT |
1023 | } |
1024 | } | |
1025 | if (completed && !list_empty (&ed->td_list)) | |
1026 | goto rescan_this; | |
1027 | ||
e7b094f8 AS |
1028 | /* |
1029 | * If no TDs are queued, take ED off the ed_rm_list. | |
1030 | * Otherwise, if the HC is running, reschedule. | |
1031 | * If not, leave it on the list for further dequeues. | |
1032 | */ | |
1033 | if (list_empty(&ed->td_list)) { | |
1034 | *last = ed->ed_next; | |
1035 | ed->ed_next = NULL; | |
d106ce33 | 1036 | ed->state = ED_IDLE; |
e7b094f8 AS |
1037 | } else if (ohci->rh_state == OHCI_RH_RUNNING) { |
1038 | *last = ed->ed_next; | |
1039 | ed->ed_next = NULL; | |
1040 | ed_schedule(ohci, ed); | |
1041 | } else { | |
1042 | last = &ed->ed_next; | |
1da177e4 LT |
1043 | } |
1044 | ||
1045 | if (modified) | |
1046 | goto rescan_all; | |
dd9048af | 1047 | } |
1da177e4 | 1048 | |
dd9048af | 1049 | /* maybe reenable control and bulk lists */ |
b7463c71 | 1050 | if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) { |
1da177e4 LT |
1051 | u32 command = 0, control = 0; |
1052 | ||
1053 | if (ohci->ed_controltail) { | |
1054 | command |= OHCI_CLF; | |
89a0fd18 | 1055 | if (quirk_zfmicro(ohci)) |
0e498763 | 1056 | mdelay(1); |
1da177e4 LT |
1057 | if (!(ohci->hc_control & OHCI_CTRL_CLE)) { |
1058 | control |= OHCI_CTRL_CLE; | |
1059 | ohci_writel (ohci, 0, | |
1060 | &ohci->regs->ed_controlcurrent); | |
1061 | } | |
1062 | } | |
1063 | if (ohci->ed_bulktail) { | |
1064 | command |= OHCI_BLF; | |
89a0fd18 | 1065 | if (quirk_zfmicro(ohci)) |
0e498763 | 1066 | mdelay(1); |
1da177e4 LT |
1067 | if (!(ohci->hc_control & OHCI_CTRL_BLE)) { |
1068 | control |= OHCI_CTRL_BLE; | |
1069 | ohci_writel (ohci, 0, | |
1070 | &ohci->regs->ed_bulkcurrent); | |
1071 | } | |
1072 | } | |
dd9048af | 1073 | |
1da177e4 LT |
1074 | /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */ |
1075 | if (control) { | |
1076 | ohci->hc_control |= control; | |
89a0fd18 | 1077 | if (quirk_zfmicro(ohci)) |
0e498763 | 1078 | mdelay(1); |
dd9048af DB |
1079 | ohci_writel (ohci, ohci->hc_control, |
1080 | &ohci->regs->control); | |
1081 | } | |
0e498763 | 1082 | if (command) { |
89a0fd18 | 1083 | if (quirk_zfmicro(ohci)) |
0e498763 | 1084 | mdelay(1); |
dd9048af DB |
1085 | ohci_writel (ohci, command, &ohci->regs->cmdstatus); |
1086 | } | |
0e498763 | 1087 | } |
1da177e4 LT |
1088 | } |
1089 | ||
1090 | ||
1091 | ||
1092 | /*-------------------------------------------------------------------------*/ | |
1093 | ||
89a0fd18 MN |
1094 | /* |
1095 | * Used to take back a TD from the host controller. This would normally be | |
1096 | * called from within dl_done_list, however it may be called directly if the | |
1097 | * HC no longer sees the TD and it has not appeared on the donelist (after | |
1098 | * two frames). This bug has been observed on ZF Micro systems. | |
1099 | */ | |
1100 | static void takeback_td(struct ohci_hcd *ohci, struct td *td) | |
1101 | { | |
1102 | struct urb *urb = td->urb; | |
1103 | urb_priv_t *urb_priv = urb->hcpriv; | |
1104 | struct ed *ed = td->ed; | |
55d84968 | 1105 | int status; |
89a0fd18 MN |
1106 | |
1107 | /* update URB's length and status from TD */ | |
55d84968 | 1108 | status = td_done(ohci, urb, td); |
89a0fd18 MN |
1109 | urb_priv->td_cnt++; |
1110 | ||
1111 | /* If all this urb's TDs are done, call complete() */ | |
7ca9229c | 1112 | if (urb_priv->td_cnt >= urb_priv->length) |
55d84968 | 1113 | finish_urb(ohci, urb, status); |
89a0fd18 MN |
1114 | |
1115 | /* clean schedule: unlink EDs that are no longer busy */ | |
1116 | if (list_empty(&ed->td_list)) { | |
1117 | if (ed->state == ED_OPER) | |
1118 | start_ed_unlink(ohci, ed); | |
1119 | ||
1120 | /* ... reenabling halted EDs only after fault cleanup */ | |
1121 | } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE)) | |
1122 | == cpu_to_hc32(ohci, ED_SKIP)) { | |
1123 | td = list_entry(ed->td_list.next, struct td, td_list); | |
1124 | if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) { | |
1125 | ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP); | |
1126 | /* ... hc may need waking-up */ | |
1127 | switch (ed->type) { | |
1128 | case PIPE_CONTROL: | |
1129 | ohci_writel(ohci, OHCI_CLF, | |
1130 | &ohci->regs->cmdstatus); | |
1131 | break; | |
1132 | case PIPE_BULK: | |
1133 | ohci_writel(ohci, OHCI_BLF, | |
1134 | &ohci->regs->cmdstatus); | |
1135 | break; | |
1136 | } | |
1137 | } | |
1138 | } | |
1139 | } | |
1140 | ||
1da177e4 LT |
1141 | /* |
1142 | * Process normal completions (error or success) and clean the schedules. | |
1143 | * | |
1144 | * This is the main path for handing urbs back to drivers. The only other | |
89a0fd18 MN |
1145 | * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list, |
1146 | * instead of scanning the (re-reversed) donelist as this does. There's | |
1147 | * an abnormal path too, handling a quirk in some Compaq silicon: URBs | |
1148 | * with TDs that appear to be orphaned are directly reclaimed. | |
1da177e4 LT |
1149 | */ |
1150 | static void | |
7d12e780 | 1151 | dl_done_list (struct ohci_hcd *ohci) |
1da177e4 LT |
1152 | { |
1153 | struct td *td = dl_reverse_done_list (ohci); | |
1154 | ||
dd9048af | 1155 | while (td) { |
1da177e4 | 1156 | struct td *td_next = td->next_dl_td; |
50ce5c06 AS |
1157 | struct ed *ed = td->ed; |
1158 | ||
1159 | /* | |
1160 | * Some OHCI controllers (NVIDIA for sure, maybe others) | |
1161 | * occasionally forget to add TDs to the done queue. Since | |
1162 | * TDs for a given endpoint are always processed in order, | |
1163 | * if we find a TD on the donelist then all of its | |
1164 | * predecessors must be finished as well. | |
1165 | */ | |
1166 | for (;;) { | |
1167 | struct td *td2; | |
1168 | ||
1169 | td2 = list_first_entry(&ed->td_list, struct td, | |
1170 | td_list); | |
1171 | if (td2 == td) | |
1172 | break; | |
1173 | takeback_td(ohci, td2); | |
1174 | } | |
1175 | ||
89a0fd18 | 1176 | takeback_td(ohci, td); |
dd9048af DB |
1177 | td = td_next; |
1178 | } | |
1da177e4 | 1179 | } |