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60bbfc84 VW |
1 | /* |
2 | * drivers/usb/host/ohci-pnx4008.c | |
3 | * | |
4 | * driver for Philips PNX4008 USB Host | |
5 | * | |
6 | * Authors: Dmitry Chigirev <source@mvista.com> | |
dd9048af | 7 | * Vitaly Wool <vitalywool@gmail.com> |
60bbfc84 VW |
8 | * |
9 | * register initialization is based on code examples provided by Philips | |
10 | * Copyright (c) 2005 Koninklijke Philips Electronics N.V. | |
11 | * | |
12 | * NOTE: This driver does not have suspend/resume functionality | |
13 | * This driver is intended for engineering development purposes only | |
14 | * | |
15 | * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under | |
16 | * the terms of the GNU General Public License version 2. This program | |
17 | * is licensed "as is" without any warranty of any kind, whether express | |
18 | * or implied. | |
19 | */ | |
20 | #include <linux/clk.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/i2c.h> | |
23 | ||
a09e64fb | 24 | #include <mach/hardware.h> |
60bbfc84 | 25 | #include <asm/io.h> |
60bbfc84 | 26 | |
a09e64fb RK |
27 | #include <mach/platform.h> |
28 | #include <mach/irqs.h> | |
29 | #include <mach/gpio.h> | |
60bbfc84 | 30 | |
dd9048af | 31 | #define USB_CTRL IO_ADDRESS(PNX4008_PWRMAN_BASE + 0x64) |
60bbfc84 VW |
32 | |
33 | /* USB_CTRL bit defines */ | |
34 | #define USB_SLAVE_HCLK_EN (1 << 24) | |
35 | #define USB_HOST_NEED_CLK_EN (1 << 21) | |
36 | ||
37 | #define USB_OTG_CLK_CTRL IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF4) | |
38 | #define USB_OTG_CLK_STAT IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xFF8) | |
39 | ||
40 | /* USB_OTG_CLK_CTRL bit defines */ | |
41 | #define AHB_M_CLOCK_ON (1 << 4) | |
42 | #define OTG_CLOCK_ON (1 << 3) | |
43 | #define I2C_CLOCK_ON (1 << 2) | |
44 | #define DEV_CLOCK_ON (1 << 1) | |
45 | #define HOST_CLOCK_ON (1 << 0) | |
46 | ||
47 | #define USB_OTG_STAT_CONTROL IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x110) | |
48 | ||
49 | /* USB_OTG_STAT_CONTROL bit defines */ | |
50 | #define TRANSPARENT_I2C_EN (1 << 7) | |
51 | #define HOST_EN (1 << 0) | |
52 | ||
53 | /* ISP1301 USB transceiver I2C registers */ | |
54 | #define ISP1301_MODE_CONTROL_1 0x04 /* u8 read, set, +1 clear */ | |
55 | ||
56 | #define MC1_SPEED_REG (1 << 0) | |
57 | #define MC1_SUSPEND_REG (1 << 1) | |
58 | #define MC1_DAT_SE0 (1 << 2) | |
59 | #define MC1_TRANSPARENT (1 << 3) | |
60 | #define MC1_BDIS_ACON_EN (1 << 4) | |
61 | #define MC1_OE_INT_EN (1 << 5) | |
62 | #define MC1_UART_EN (1 << 6) | |
63 | #define MC1_MASK 0x7f | |
64 | ||
65 | #define ISP1301_MODE_CONTROL_2 0x12 /* u8 read, set, +1 clear */ | |
66 | ||
67 | #define MC2_GLOBAL_PWR_DN (1 << 0) | |
68 | #define MC2_SPD_SUSP_CTRL (1 << 1) | |
69 | #define MC2_BI_DI (1 << 2) | |
70 | #define MC2_TRANSP_BDIR0 (1 << 3) | |
71 | #define MC2_TRANSP_BDIR1 (1 << 4) | |
72 | #define MC2_AUDIO_EN (1 << 5) | |
73 | #define MC2_PSW_EN (1 << 6) | |
74 | #define MC2_EN2V7 (1 << 7) | |
75 | ||
76 | #define ISP1301_OTG_CONTROL_1 0x06 /* u8 read, set, +1 clear */ | |
77 | # define OTG1_DP_PULLUP (1 << 0) | |
78 | # define OTG1_DM_PULLUP (1 << 1) | |
79 | # define OTG1_DP_PULLDOWN (1 << 2) | |
80 | # define OTG1_DM_PULLDOWN (1 << 3) | |
81 | # define OTG1_ID_PULLDOWN (1 << 4) | |
82 | # define OTG1_VBUS_DRV (1 << 5) | |
83 | # define OTG1_VBUS_DISCHRG (1 << 6) | |
84 | # define OTG1_VBUS_CHRG (1 << 7) | |
85 | #define ISP1301_OTG_STATUS 0x10 /* u8 readonly */ | |
86 | # define OTG_B_SESS_END (1 << 6) | |
87 | # define OTG_B_SESS_VLD (1 << 7) | |
88 | ||
89 | #define ISP1301_I2C_ADDR 0x2C | |
90 | ||
91 | #define ISP1301_I2C_MODE_CONTROL_1 0x4 | |
92 | #define ISP1301_I2C_MODE_CONTROL_2 0x12 | |
93 | #define ISP1301_I2C_OTG_CONTROL_1 0x6 | |
94 | #define ISP1301_I2C_OTG_CONTROL_2 0x10 | |
95 | #define ISP1301_I2C_INTERRUPT_SOURCE 0x8 | |
96 | #define ISP1301_I2C_INTERRUPT_LATCH 0xA | |
97 | #define ISP1301_I2C_INTERRUPT_FALLING 0xC | |
98 | #define ISP1301_I2C_INTERRUPT_RISING 0xE | |
99 | #define ISP1301_I2C_REG_CLEAR_ADDR 1 | |
100 | ||
101 | struct i2c_driver isp1301_driver; | |
102 | struct i2c_client *isp1301_i2c_client; | |
103 | ||
104 | extern int usb_disabled(void); | |
105 | extern int ocpi_enable(void); | |
106 | ||
107 | static struct clk *usb_clk; | |
108 | ||
2cdddeb8 | 109 | static const unsigned short normal_i2c[] = |
60bbfc84 | 110 | { ISP1301_I2C_ADDR, ISP1301_I2C_ADDR + 1, I2C_CLIENT_END }; |
60bbfc84 | 111 | |
3a407e73 JD |
112 | static int isp1301_probe(struct i2c_client *client, |
113 | const struct i2c_device_id *id) | |
60bbfc84 | 114 | { |
64b3d6d1 | 115 | return 0; |
60bbfc84 VW |
116 | } |
117 | ||
3a407e73 | 118 | static int isp1301_remove(struct i2c_client *client) |
60bbfc84 | 119 | { |
60bbfc84 VW |
120 | return 0; |
121 | } | |
122 | ||
3a407e73 JD |
123 | const struct i2c_device_id isp1301_id[] = { |
124 | { "isp1301_pnx", 0 }, | |
125 | { } | |
126 | }; | |
127 | ||
128 | struct i2c_driver isp1301_driver = { | |
129 | .driver = { | |
130 | .name = "isp1301_pnx", | |
131 | }, | |
132 | .probe = isp1301_probe, | |
133 | .remove = isp1301_remove, | |
134 | .id_table = isp1301_id, | |
135 | }; | |
136 | ||
60bbfc84 VW |
137 | static void i2c_write(u8 buf, u8 subaddr) |
138 | { | |
139 | char tmpbuf[2]; | |
140 | ||
141 | tmpbuf[0] = subaddr; /*register number */ | |
142 | tmpbuf[1] = buf; /*register data */ | |
143 | i2c_master_send(isp1301_i2c_client, &tmpbuf[0], 2); | |
144 | } | |
145 | ||
146 | static void isp1301_configure(void) | |
147 | { | |
148 | /* PNX4008 only supports DAT_SE0 USB mode */ | |
149 | /* PNX4008 R2A requires setting the MAX603 to output 3.6V */ | |
150 | /* Power up externel charge-pump */ | |
151 | ||
152 | i2c_write(MC1_DAT_SE0 | MC1_SPEED_REG, ISP1301_I2C_MODE_CONTROL_1); | |
153 | i2c_write(~(MC1_DAT_SE0 | MC1_SPEED_REG), | |
154 | ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR); | |
155 | i2c_write(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL, | |
156 | ISP1301_I2C_MODE_CONTROL_2); | |
157 | i2c_write(~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL), | |
158 | ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR); | |
159 | i2c_write(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN, | |
160 | ISP1301_I2C_OTG_CONTROL_1); | |
161 | i2c_write(~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN), | |
162 | ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR); | |
163 | i2c_write(0xFF, | |
164 | ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR); | |
165 | i2c_write(0xFF, | |
166 | ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR); | |
167 | i2c_write(0xFF, | |
168 | ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR); | |
169 | ||
170 | } | |
171 | ||
172 | static inline void isp1301_vbus_on(void) | |
173 | { | |
174 | i2c_write(OTG1_VBUS_DRV, ISP1301_I2C_OTG_CONTROL_1); | |
175 | } | |
176 | ||
177 | static inline void isp1301_vbus_off(void) | |
178 | { | |
179 | i2c_write(OTG1_VBUS_DRV, | |
180 | ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR); | |
181 | } | |
182 | ||
183 | static void pnx4008_start_hc(void) | |
184 | { | |
185 | unsigned long tmp = __raw_readl(USB_OTG_STAT_CONTROL) | HOST_EN; | |
186 | __raw_writel(tmp, USB_OTG_STAT_CONTROL); | |
187 | isp1301_vbus_on(); | |
188 | } | |
189 | ||
190 | static void pnx4008_stop_hc(void) | |
191 | { | |
192 | unsigned long tmp; | |
193 | isp1301_vbus_off(); | |
194 | tmp = __raw_readl(USB_OTG_STAT_CONTROL) & ~HOST_EN; | |
195 | __raw_writel(tmp, USB_OTG_STAT_CONTROL); | |
196 | } | |
197 | ||
198 | static int __devinit ohci_pnx4008_start(struct usb_hcd *hcd) | |
199 | { | |
200 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | |
201 | int ret; | |
202 | ||
203 | if ((ret = ohci_init(ohci)) < 0) | |
204 | return ret; | |
205 | ||
206 | if ((ret = ohci_run(ohci)) < 0) { | |
207 | dev_err(hcd->self.controller, "can't start\n"); | |
208 | ohci_stop(hcd); | |
209 | return ret; | |
210 | } | |
211 | return 0; | |
212 | } | |
213 | ||
214 | static const struct hc_driver ohci_pnx4008_hc_driver = { | |
215 | .description = hcd_name, | |
216 | .product_desc = "pnx4008 OHCI", | |
217 | ||
218 | /* | |
219 | * generic hardware linkage | |
220 | */ | |
221 | .irq = ohci_irq, | |
222 | .flags = HCD_USB11 | HCD_MEMORY, | |
223 | ||
224 | .hcd_priv_size = sizeof(struct ohci_hcd), | |
225 | /* | |
226 | * basic lifecycle operations | |
227 | */ | |
228 | .start = ohci_pnx4008_start, | |
229 | .stop = ohci_stop, | |
8442ae00 | 230 | .shutdown = ohci_shutdown, |
60bbfc84 VW |
231 | |
232 | /* | |
233 | * managing i/o requests and associated device resources | |
234 | */ | |
235 | .urb_enqueue = ohci_urb_enqueue, | |
236 | .urb_dequeue = ohci_urb_dequeue, | |
237 | .endpoint_disable = ohci_endpoint_disable, | |
238 | ||
239 | /* | |
240 | * scheduling support | |
241 | */ | |
242 | .get_frame_number = ohci_get_frame, | |
243 | ||
244 | /* | |
245 | * root hub support | |
246 | */ | |
247 | .hub_status_data = ohci_hub_status_data, | |
248 | .hub_control = ohci_hub_control, | |
8442ae00 DB |
249 | #ifdef CONFIG_PM |
250 | .bus_suspend = ohci_bus_suspend, | |
251 | .bus_resume = ohci_bus_resume, | |
252 | #endif | |
60bbfc84 VW |
253 | .start_port_reset = ohci_start_port_reset, |
254 | }; | |
255 | ||
256 | #define USB_CLOCK_MASK (AHB_M_CLOCK_ON| OTG_CLOCK_ON | HOST_CLOCK_ON | I2C_CLOCK_ON) | |
257 | ||
258 | static void pnx4008_set_usb_bits(void) | |
259 | { | |
260 | start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N); | |
261 | start_int_ack(SE_USB_OTG_ATX_INT_N); | |
262 | start_int_umask(SE_USB_OTG_ATX_INT_N); | |
263 | ||
264 | start_int_set_rising_edge(SE_USB_OTG_TIMER_INT); | |
265 | start_int_ack(SE_USB_OTG_TIMER_INT); | |
266 | start_int_umask(SE_USB_OTG_TIMER_INT); | |
267 | ||
268 | start_int_set_rising_edge(SE_USB_I2C_INT); | |
269 | start_int_ack(SE_USB_I2C_INT); | |
270 | start_int_umask(SE_USB_I2C_INT); | |
271 | ||
272 | start_int_set_rising_edge(SE_USB_INT); | |
273 | start_int_ack(SE_USB_INT); | |
274 | start_int_umask(SE_USB_INT); | |
275 | ||
276 | start_int_set_rising_edge(SE_USB_NEED_CLK_INT); | |
277 | start_int_ack(SE_USB_NEED_CLK_INT); | |
278 | start_int_umask(SE_USB_NEED_CLK_INT); | |
279 | ||
280 | start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT); | |
281 | start_int_ack(SE_USB_AHB_NEED_CLK_INT); | |
282 | start_int_umask(SE_USB_AHB_NEED_CLK_INT); | |
283 | } | |
284 | ||
285 | static void pnx4008_unset_usb_bits(void) | |
286 | { | |
287 | start_int_mask(SE_USB_OTG_ATX_INT_N); | |
288 | start_int_mask(SE_USB_OTG_TIMER_INT); | |
289 | start_int_mask(SE_USB_I2C_INT); | |
290 | start_int_mask(SE_USB_INT); | |
291 | start_int_mask(SE_USB_NEED_CLK_INT); | |
292 | start_int_mask(SE_USB_AHB_NEED_CLK_INT); | |
293 | } | |
294 | ||
295 | static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev) | |
296 | { | |
297 | struct usb_hcd *hcd = 0; | |
298 | struct ohci_hcd *ohci; | |
299 | const struct hc_driver *driver = &ohci_pnx4008_hc_driver; | |
3a407e73 JD |
300 | struct i2c_adapter *i2c_adap; |
301 | struct i2c_board_info i2c_info; | |
60bbfc84 VW |
302 | |
303 | int ret = 0, irq; | |
304 | ||
2b70f073 | 305 | dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (pnx4008)\n", hcd_name); |
60bbfc84 VW |
306 | if (usb_disabled()) { |
307 | err("USB is disabled"); | |
308 | ret = -ENODEV; | |
309 | goto out; | |
310 | } | |
311 | ||
312 | if (pdev->num_resources != 2 | |
313 | || pdev->resource[0].flags != IORESOURCE_MEM | |
314 | || pdev->resource[1].flags != IORESOURCE_IRQ) { | |
315 | err("Invalid resource configuration"); | |
316 | ret = -ENODEV; | |
317 | goto out; | |
318 | } | |
319 | ||
320 | /* Enable AHB slave USB clock, needed for further USB clock control */ | |
321 | __raw_writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL); | |
322 | ||
323 | ret = i2c_add_driver(&isp1301_driver); | |
324 | if (ret < 0) { | |
3a407e73 | 325 | err("failed to add ISP1301 driver"); |
60bbfc84 VW |
326 | goto out; |
327 | } | |
3a407e73 JD |
328 | i2c_adap = i2c_get_adapter(2); |
329 | memset(&i2c_info, 0, sizeof(struct i2c_board_info)); | |
330 | strlcpy(i2c_info.name, "isp1301_pnx", I2C_NAME_SIZE); | |
331 | isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info, | |
332 | normal_i2c); | |
333 | i2c_put_adapter(i2c_adap); | |
334 | if (!isp1301_i2c_client) { | |
335 | err("failed to connect I2C to ISP1301 USB Transceiver"); | |
336 | ret = -ENODEV; | |
337 | goto out_i2c_driver; | |
338 | } | |
60bbfc84 VW |
339 | |
340 | isp1301_configure(); | |
341 | ||
342 | /* Enable USB PLL */ | |
343 | usb_clk = clk_get(&pdev->dev, "ck_pll5"); | |
344 | if (IS_ERR(usb_clk)) { | |
345 | err("failed to acquire USB PLL"); | |
346 | ret = PTR_ERR(usb_clk); | |
347 | goto out1; | |
348 | } | |
349 | ||
350 | ret = clk_enable(usb_clk); | |
351 | if (ret < 0) { | |
352 | err("failed to start USB PLL"); | |
353 | goto out2; | |
354 | } | |
355 | ||
356 | ret = clk_set_rate(usb_clk, 48000); | |
357 | if (ret < 0) { | |
358 | err("failed to set USB clock rate"); | |
359 | goto out3; | |
360 | } | |
361 | ||
362 | __raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL); | |
363 | ||
364 | /* Set to enable all needed USB clocks */ | |
365 | __raw_writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL); | |
366 | ||
367 | while ((__raw_readl(USB_OTG_CLK_STAT) & USB_CLOCK_MASK) != | |
368 | USB_CLOCK_MASK) ; | |
369 | ||
7071a3ce | 370 | hcd = usb_create_hcd (driver, &pdev->dev, dev_name(&pdev->dev)); |
60bbfc84 VW |
371 | if (!hcd) { |
372 | err("Failed to allocate HC buffer"); | |
373 | ret = -ENOMEM; | |
374 | goto out3; | |
375 | } | |
376 | ||
377 | /* Set all USB bits in the Start Enable register */ | |
378 | pnx4008_set_usb_bits(); | |
379 | ||
380 | hcd->rsrc_start = pdev->resource[0].start; | |
381 | hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1; | |
382 | if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { | |
383 | dev_dbg(&pdev->dev, "request_mem_region failed\n"); | |
384 | ret = -ENOMEM; | |
385 | goto out4; | |
386 | } | |
387 | hcd->regs = (void __iomem *)pdev->resource[0].start; | |
388 | ||
389 | irq = platform_get_irq(pdev, 0); | |
390 | if (irq < 0) { | |
391 | ret = -ENXIO; | |
392 | goto out4; | |
393 | } | |
394 | ||
60bbfc84 VW |
395 | pnx4008_start_hc(); |
396 | platform_set_drvdata(pdev, hcd); | |
397 | ohci = hcd_to_ohci(hcd); | |
398 | ohci_hcd_init(ohci); | |
399 | ||
400 | dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq); | |
38515e90 | 401 | ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); |
60bbfc84 VW |
402 | if (ret == 0) |
403 | return ret; | |
404 | ||
405 | pnx4008_stop_hc(); | |
406 | out4: | |
407 | pnx4008_unset_usb_bits(); | |
408 | usb_put_hcd(hcd); | |
409 | out3: | |
410 | clk_disable(usb_clk); | |
411 | out2: | |
412 | clk_put(usb_clk); | |
413 | out1: | |
3a407e73 JD |
414 | i2c_unregister_client(isp1301_i2c_client); |
415 | isp1301_i2c_client = NULL; | |
416 | out_i2c_driver: | |
60bbfc84 VW |
417 | i2c_del_driver(&isp1301_driver); |
418 | out: | |
419 | return ret; | |
420 | } | |
421 | ||
422 | static int usb_hcd_pnx4008_remove(struct platform_device *pdev) | |
423 | { | |
424 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | |
425 | ||
426 | usb_remove_hcd(hcd); | |
427 | pnx4008_stop_hc(); | |
428 | release_mem_region(hcd->rsrc_start, hcd->rsrc_len); | |
429 | usb_put_hcd(hcd); | |
430 | pnx4008_unset_usb_bits(); | |
431 | clk_disable(usb_clk); | |
432 | clk_put(usb_clk); | |
3a407e73 JD |
433 | i2c_unregister_client(isp1301_i2c_client); |
434 | isp1301_i2c_client = NULL; | |
60bbfc84 VW |
435 | i2c_del_driver(&isp1301_driver); |
436 | ||
437 | platform_set_drvdata(pdev, NULL); | |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
f4fce61d KS |
442 | /* work with hotplug and coldplug */ |
443 | MODULE_ALIAS("platform:usb-ohci"); | |
444 | ||
60bbfc84 VW |
445 | static struct platform_driver usb_hcd_pnx4008_driver = { |
446 | .driver = { | |
447 | .name = "usb-ohci", | |
f4fce61d | 448 | .owner = THIS_MODULE, |
60bbfc84 VW |
449 | }, |
450 | .probe = usb_hcd_pnx4008_probe, | |
451 | .remove = usb_hcd_pnx4008_remove, | |
452 | }; | |
453 |