Commit | Line | Data |
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db11e47d SS |
1 | /* |
2 | * Driver for the NXP ISP1760 chip | |
3 | * | |
4 | * However, the code might contain some bugs. What doesn't work for sure is: | |
5 | * - ISO | |
6 | * - OTG | |
7 | e The interrupt line is configured as active low, level. | |
8 | * | |
9 | * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> | |
10 | * | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/list.h> | |
16 | #include <linux/usb.h> | |
17 | #include <linux/debugfs.h> | |
18 | #include <linux/uaccess.h> | |
19 | #include <linux/io.h> | |
db8516f6 | 20 | #include <linux/mm.h> |
db11e47d | 21 | #include <asm/unaligned.h> |
db8516f6 | 22 | #include <asm/cacheflush.h> |
db11e47d SS |
23 | |
24 | #include "../core/hcd.h" | |
25 | #include "isp1760-hcd.h" | |
26 | ||
27 | static struct kmem_cache *qtd_cachep; | |
28 | static struct kmem_cache *qh_cachep; | |
29 | ||
30 | struct isp1760_hcd { | |
31 | u32 hcs_params; | |
32 | spinlock_t lock; | |
33 | struct inter_packet_info atl_ints[32]; | |
34 | struct inter_packet_info int_ints[32]; | |
35 | struct memory_chunk memory_pool[BLOCKS]; | |
36 | ||
37 | /* periodic schedule support */ | |
38 | #define DEFAULT_I_TDPS 1024 | |
39 | unsigned periodic_size; | |
40 | unsigned i_thresh; | |
41 | unsigned long reset_done; | |
42 | unsigned long next_statechange; | |
3faefc88 | 43 | unsigned int devflags; |
db11e47d SS |
44 | }; |
45 | ||
46 | static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) | |
47 | { | |
48 | return (struct isp1760_hcd *) (hcd->hcd_priv); | |
49 | } | |
50 | static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv) | |
51 | { | |
52 | return container_of((void *) priv, struct usb_hcd, hcd_priv); | |
53 | } | |
54 | ||
55 | /* Section 2.2 Host Controller Capability Registers */ | |
56 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ | |
57 | #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ | |
58 | #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ | |
59 | #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ | |
60 | #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ | |
61 | #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ | |
62 | #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ | |
63 | ||
64 | /* Section 2.3 Host Controller Operational Registers */ | |
65 | #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ | |
66 | #define CMD_RESET (1<<1) /* reset HC not bus */ | |
67 | #define CMD_RUN (1<<0) /* start/stop HC */ | |
68 | #define STS_PCD (1<<2) /* port change detect */ | |
69 | #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ | |
70 | ||
71 | #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ | |
72 | #define PORT_POWER (1<<12) /* true: has power (see PPC) */ | |
73 | #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */ | |
74 | #define PORT_RESET (1<<8) /* reset port */ | |
75 | #define PORT_SUSPEND (1<<7) /* suspend port */ | |
76 | #define PORT_RESUME (1<<6) /* resume it */ | |
77 | #define PORT_PE (1<<2) /* port enable */ | |
78 | #define PORT_CSC (1<<1) /* connect status change */ | |
79 | #define PORT_CONNECT (1<<0) /* device connected */ | |
80 | #define PORT_RWC_BITS (PORT_CSC) | |
81 | ||
82 | struct isp1760_qtd { | |
83 | struct isp1760_qtd *hw_next; | |
84 | u8 packet_type; | |
85 | u8 toggle; | |
86 | ||
87 | void *data_buffer; | |
88 | /* the rest is HCD-private */ | |
89 | struct list_head qtd_list; | |
90 | struct urb *urb; | |
91 | size_t length; | |
92 | ||
93 | /* isp special*/ | |
94 | u32 status; | |
95 | #define URB_COMPLETE_NOTIFY (1 << 0) | |
96 | #define URB_ENQUEUED (1 << 1) | |
97 | #define URB_TYPE_ATL (1 << 2) | |
98 | #define URB_TYPE_INT (1 << 3) | |
99 | }; | |
100 | ||
101 | struct isp1760_qh { | |
102 | /* first part defined by EHCI spec */ | |
103 | struct list_head qtd_list; | |
104 | struct isp1760_hcd *priv; | |
105 | ||
106 | /* periodic schedule info */ | |
107 | unsigned short period; /* polling interval */ | |
108 | struct usb_device *dev; | |
109 | ||
110 | u32 toggle; | |
111 | u32 ping; | |
112 | }; | |
113 | ||
114 | #define ehci_port_speed(priv, portsc) (1 << USB_PORT_FEAT_HIGHSPEED) | |
115 | ||
116 | static unsigned int isp1760_readl(__u32 __iomem *regs) | |
117 | { | |
118 | return readl(regs); | |
119 | } | |
120 | ||
121 | static void isp1760_writel(const unsigned int val, __u32 __iomem *regs) | |
122 | { | |
123 | writel(val, regs); | |
124 | } | |
125 | ||
126 | /* | |
127 | * The next two copy via MMIO data to/from the device. memcpy_{to|from}io() | |
128 | * doesn't quite work because some people have to enforce 32-bit access | |
129 | */ | |
130 | static void priv_read_copy(struct isp1760_hcd *priv, u32 *src, | |
3f02a957 | 131 | __u32 __iomem *dst, u32 len) |
db11e47d | 132 | { |
db11e47d SS |
133 | u32 val; |
134 | u8 *buff8; | |
135 | ||
136 | if (!src) { | |
137 | printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len); | |
138 | return; | |
139 | } | |
db11e47d SS |
140 | |
141 | while (len >= 4) { | |
142 | *src = __raw_readl(dst); | |
143 | len -= 4; | |
144 | src++; | |
145 | dst++; | |
146 | } | |
147 | ||
148 | if (!len) | |
149 | return; | |
150 | ||
151 | /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully | |
152 | * allocated. | |
153 | */ | |
154 | val = isp1760_readl(dst); | |
155 | ||
156 | buff8 = (u8 *)src; | |
157 | while (len) { | |
158 | ||
159 | *buff8 = val; | |
160 | val >>= 8; | |
161 | len--; | |
162 | buff8++; | |
163 | } | |
164 | } | |
165 | ||
166 | static void priv_write_copy(const struct isp1760_hcd *priv, const u32 *src, | |
167 | __u32 __iomem *dst, u32 len) | |
168 | { | |
169 | while (len >= 4) { | |
170 | __raw_writel(*src, dst); | |
171 | len -= 4; | |
172 | src++; | |
173 | dst++; | |
174 | } | |
175 | ||
176 | if (!len) | |
177 | return; | |
178 | /* in case we have 3, 2 or 1 by left. The buffer is allocated and the | |
179 | * extra bytes should not be read by the HW | |
180 | */ | |
181 | ||
182 | __raw_writel(*src, dst); | |
183 | } | |
184 | ||
185 | /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ | |
186 | static void init_memory(struct isp1760_hcd *priv) | |
187 | { | |
188 | int i; | |
189 | u32 payload; | |
190 | ||
191 | payload = 0x1000; | |
192 | for (i = 0; i < BLOCK_1_NUM; i++) { | |
193 | priv->memory_pool[i].start = payload; | |
194 | priv->memory_pool[i].size = BLOCK_1_SIZE; | |
195 | priv->memory_pool[i].free = 1; | |
196 | payload += priv->memory_pool[i].size; | |
197 | } | |
198 | ||
199 | ||
200 | for (i = BLOCK_1_NUM; i < BLOCK_1_NUM + BLOCK_2_NUM; i++) { | |
201 | priv->memory_pool[i].start = payload; | |
202 | priv->memory_pool[i].size = BLOCK_2_SIZE; | |
203 | priv->memory_pool[i].free = 1; | |
204 | payload += priv->memory_pool[i].size; | |
205 | } | |
206 | ||
207 | ||
208 | for (i = BLOCK_1_NUM + BLOCK_2_NUM; i < BLOCKS; i++) { | |
209 | priv->memory_pool[i].start = payload; | |
210 | priv->memory_pool[i].size = BLOCK_3_SIZE; | |
211 | priv->memory_pool[i].free = 1; | |
212 | payload += priv->memory_pool[i].size; | |
213 | } | |
214 | ||
215 | BUG_ON(payload - priv->memory_pool[i - 1].size > PAYLOAD_SIZE); | |
216 | } | |
217 | ||
218 | static u32 alloc_mem(struct isp1760_hcd *priv, u32 size) | |
219 | { | |
220 | int i; | |
221 | ||
222 | if (!size) | |
223 | return ISP1760_NULL_POINTER; | |
224 | ||
225 | for (i = 0; i < BLOCKS; i++) { | |
226 | if (priv->memory_pool[i].size >= size && | |
227 | priv->memory_pool[i].free) { | |
228 | ||
229 | priv->memory_pool[i].free = 0; | |
230 | return priv->memory_pool[i].start; | |
231 | } | |
232 | } | |
233 | ||
234 | printk(KERN_ERR "ISP1760 MEM: can not allocate %d bytes of memory\n", | |
235 | size); | |
236 | printk(KERN_ERR "Current memory map:\n"); | |
237 | for (i = 0; i < BLOCKS; i++) { | |
238 | printk(KERN_ERR "Pool %2d size %4d status: %d\n", | |
239 | i, priv->memory_pool[i].size, | |
240 | priv->memory_pool[i].free); | |
241 | } | |
242 | /* XXX maybe -ENOMEM could be possible */ | |
243 | BUG(); | |
244 | return 0; | |
245 | } | |
246 | ||
247 | static void free_mem(struct isp1760_hcd *priv, u32 mem) | |
248 | { | |
249 | int i; | |
250 | ||
251 | if (mem == ISP1760_NULL_POINTER) | |
252 | return; | |
253 | ||
254 | for (i = 0; i < BLOCKS; i++) { | |
255 | if (priv->memory_pool[i].start == mem) { | |
256 | ||
257 | BUG_ON(priv->memory_pool[i].free); | |
258 | ||
259 | priv->memory_pool[i].free = 1; | |
260 | return ; | |
261 | } | |
262 | } | |
263 | ||
264 | printk(KERN_ERR "Trying to free not-here-allocated memory :%08x\n", | |
265 | mem); | |
266 | BUG(); | |
267 | } | |
268 | ||
269 | static void isp1760_init_regs(struct usb_hcd *hcd) | |
270 | { | |
271 | isp1760_writel(0, hcd->regs + HC_BUFFER_STATUS_REG); | |
272 | isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + | |
273 | HC_ATL_PTD_SKIPMAP_REG); | |
274 | isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + | |
275 | HC_INT_PTD_SKIPMAP_REG); | |
276 | isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs + | |
277 | HC_ISO_PTD_SKIPMAP_REG); | |
278 | ||
279 | isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs + | |
280 | HC_ATL_PTD_DONEMAP_REG); | |
281 | isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs + | |
282 | HC_INT_PTD_DONEMAP_REG); | |
283 | isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs + | |
284 | HC_ISO_PTD_DONEMAP_REG); | |
285 | } | |
286 | ||
287 | static int handshake(struct isp1760_hcd *priv, void __iomem *ptr, | |
288 | u32 mask, u32 done, int usec) | |
289 | { | |
290 | u32 result; | |
291 | ||
292 | do { | |
293 | result = isp1760_readl(ptr); | |
294 | if (result == ~0) | |
295 | return -ENODEV; | |
296 | result &= mask; | |
297 | if (result == done) | |
298 | return 0; | |
299 | udelay(1); | |
300 | usec--; | |
301 | } while (usec > 0); | |
302 | return -ETIMEDOUT; | |
303 | } | |
304 | ||
305 | /* reset a non-running (STS_HALT == 1) controller */ | |
306 | static int ehci_reset(struct isp1760_hcd *priv) | |
307 | { | |
308 | int retval; | |
309 | struct usb_hcd *hcd = priv_to_hcd(priv); | |
310 | u32 command = isp1760_readl(hcd->regs + HC_USBCMD); | |
311 | ||
312 | command |= CMD_RESET; | |
313 | isp1760_writel(command, hcd->regs + HC_USBCMD); | |
314 | hcd->state = HC_STATE_HALT; | |
315 | priv->next_statechange = jiffies; | |
316 | retval = handshake(priv, hcd->regs + HC_USBCMD, | |
317 | CMD_RESET, 0, 250 * 1000); | |
318 | return retval; | |
319 | } | |
320 | ||
321 | static void qh_destroy(struct isp1760_qh *qh) | |
322 | { | |
323 | BUG_ON(!list_empty(&qh->qtd_list)); | |
324 | kmem_cache_free(qh_cachep, qh); | |
325 | } | |
326 | ||
327 | static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv, | |
328 | gfp_t flags) | |
329 | { | |
330 | struct isp1760_qh *qh; | |
331 | ||
332 | qh = kmem_cache_zalloc(qh_cachep, flags); | |
333 | if (!qh) | |
334 | return qh; | |
335 | ||
336 | INIT_LIST_HEAD(&qh->qtd_list); | |
337 | qh->priv = priv; | |
338 | return qh; | |
339 | } | |
340 | ||
341 | /* magic numbers that can affect system performance */ | |
342 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
343 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
344 | #define EHCI_TUNE_RL_TT 0 | |
345 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
346 | #define EHCI_TUNE_MULT_TT 1 | |
347 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | |
348 | ||
349 | /* one-time init, only for memory state */ | |
350 | static int priv_init(struct usb_hcd *hcd) | |
351 | { | |
352 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
353 | u32 hcc_params; | |
354 | ||
355 | spin_lock_init(&priv->lock); | |
356 | ||
357 | /* | |
358 | * hw default: 1K periodic list heads, one per frame. | |
359 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
360 | */ | |
361 | priv->periodic_size = DEFAULT_I_TDPS; | |
362 | ||
363 | /* controllers may cache some of the periodic schedule ... */ | |
364 | hcc_params = isp1760_readl(hcd->regs + HC_HCCPARAMS); | |
365 | /* full frame cache */ | |
366 | if (HCC_ISOC_CACHE(hcc_params)) | |
367 | priv->i_thresh = 8; | |
368 | else /* N microframes cached */ | |
369 | priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | static int isp1760_hc_setup(struct usb_hcd *hcd) | |
375 | { | |
376 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
377 | int result; | |
3faefc88 NC |
378 | u32 scratch, hwmode; |
379 | ||
380 | /* Setup HW Mode Control: This assumes a level active-low interrupt */ | |
381 | hwmode = HW_DATA_BUS_32BIT; | |
382 | ||
383 | if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) | |
384 | hwmode &= ~HW_DATA_BUS_32BIT; | |
385 | if (priv->devflags & ISP1760_FLAG_ANALOG_OC) | |
386 | hwmode |= HW_ANA_DIGI_OC; | |
387 | if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH) | |
388 | hwmode |= HW_DACK_POL_HIGH; | |
389 | if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH) | |
390 | hwmode |= HW_DREQ_POL_HIGH; | |
9da69c60 MH |
391 | if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH) |
392 | hwmode |= HW_INTR_HIGH_ACT; | |
393 | if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG) | |
394 | hwmode |= HW_INTR_EDGE_TRIG; | |
3faefc88 NC |
395 | |
396 | /* | |
397 | * We have to set this first in case we're in 16-bit mode. | |
398 | * Write it twice to ensure correct upper bits if switching | |
399 | * to 16-bit mode. | |
400 | */ | |
401 | isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); | |
402 | isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); | |
db11e47d SS |
403 | |
404 | isp1760_writel(0xdeadbabe, hcd->regs + HC_SCRATCH_REG); | |
3faefc88 NC |
405 | /* Change bus pattern */ |
406 | scratch = isp1760_readl(hcd->regs + HC_CHIP_ID_REG); | |
db11e47d SS |
407 | scratch = isp1760_readl(hcd->regs + HC_SCRATCH_REG); |
408 | if (scratch != 0xdeadbabe) { | |
409 | printk(KERN_ERR "ISP1760: Scratch test failed.\n"); | |
410 | return -ENODEV; | |
411 | } | |
412 | ||
413 | /* pre reset */ | |
414 | isp1760_init_regs(hcd); | |
415 | ||
416 | /* reset */ | |
417 | isp1760_writel(SW_RESET_RESET_ALL, hcd->regs + HC_RESET_REG); | |
418 | mdelay(100); | |
419 | ||
420 | isp1760_writel(SW_RESET_RESET_HC, hcd->regs + HC_RESET_REG); | |
421 | mdelay(100); | |
422 | ||
423 | result = ehci_reset(priv); | |
424 | if (result) | |
425 | return result; | |
426 | ||
427 | /* Step 11 passed */ | |
428 | ||
3faefc88 NC |
429 | isp1760_info(priv, "bus width: %d, oc: %s\n", |
430 | (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ? | |
431 | 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ? | |
432 | "analog" : "digital"); | |
db11e47d SS |
433 | |
434 | /* ATL reset */ | |
3faefc88 | 435 | isp1760_writel(hwmode | ALL_ATX_RESET, hcd->regs + HC_HW_MODE_CTRL); |
db11e47d | 436 | mdelay(10); |
3faefc88 | 437 | isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL); |
db11e47d | 438 | |
3faefc88 NC |
439 | isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_REG); |
440 | isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_ENABLE); | |
441 | ||
442 | /* | |
443 | * PORT 1 Control register of the ISP1760 is the OTG control | |
42c65396 TH |
444 | * register on ISP1761. Since there is no OTG or device controller |
445 | * support in this driver, we use port 1 as a "normal" USB host port on | |
446 | * both chips. | |
3faefc88 | 447 | */ |
42c65396 TH |
448 | isp1760_writel(PORT1_POWER | PORT1_INIT2, |
449 | hcd->regs + HC_PORT1_CTRL); | |
450 | mdelay(10); | |
db11e47d SS |
451 | |
452 | priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS); | |
453 | ||
454 | return priv_init(hcd); | |
455 | } | |
456 | ||
457 | static void isp1760_init_maps(struct usb_hcd *hcd) | |
458 | { | |
459 | /*set last maps, for iso its only 1, else 32 tds bitmap*/ | |
460 | isp1760_writel(0x80000000, hcd->regs + HC_ATL_PTD_LASTPTD_REG); | |
461 | isp1760_writel(0x80000000, hcd->regs + HC_INT_PTD_LASTPTD_REG); | |
462 | isp1760_writel(0x00000001, hcd->regs + HC_ISO_PTD_LASTPTD_REG); | |
463 | } | |
464 | ||
465 | static void isp1760_enable_interrupts(struct usb_hcd *hcd) | |
466 | { | |
467 | isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_AND_REG); | |
468 | isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | |
469 | isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_AND_REG); | |
470 | isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_OR_REG); | |
471 | isp1760_writel(0, hcd->regs + HC_ISO_IRQ_MASK_AND_REG); | |
472 | isp1760_writel(0xffffffff, hcd->regs + HC_ISO_IRQ_MASK_OR_REG); | |
473 | /* step 23 passed */ | |
474 | } | |
475 | ||
476 | static int isp1760_run(struct usb_hcd *hcd) | |
477 | { | |
478 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
479 | int retval; | |
480 | u32 temp; | |
481 | u32 command; | |
482 | u32 chipid; | |
483 | ||
484 | hcd->uses_new_polling = 1; | |
485 | hcd->poll_rh = 0; | |
486 | ||
487 | hcd->state = HC_STATE_RUNNING; | |
488 | isp1760_enable_interrupts(hcd); | |
489 | temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); | |
3faefc88 | 490 | isp1760_writel(temp | HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); |
db11e47d SS |
491 | |
492 | command = isp1760_readl(hcd->regs + HC_USBCMD); | |
493 | command &= ~(CMD_LRESET|CMD_RESET); | |
494 | command |= CMD_RUN; | |
495 | isp1760_writel(command, hcd->regs + HC_USBCMD); | |
496 | ||
497 | retval = handshake(priv, hcd->regs + HC_USBCMD, CMD_RUN, CMD_RUN, | |
498 | 250 * 1000); | |
499 | if (retval) | |
500 | return retval; | |
501 | ||
502 | /* | |
503 | * XXX | |
504 | * Spec says to write FLAG_CF as last config action, priv code grabs | |
505 | * the semaphore while doing so. | |
506 | */ | |
507 | down_write(&ehci_cf_port_reset_rwsem); | |
508 | isp1760_writel(FLAG_CF, hcd->regs + HC_CONFIGFLAG); | |
509 | ||
510 | retval = handshake(priv, hcd->regs + HC_CONFIGFLAG, FLAG_CF, FLAG_CF, | |
511 | 250 * 1000); | |
512 | up_write(&ehci_cf_port_reset_rwsem); | |
513 | if (retval) | |
514 | return retval; | |
515 | ||
516 | chipid = isp1760_readl(hcd->regs + HC_CHIP_ID_REG); | |
517 | isp1760_info(priv, "USB ISP %04x HW rev. %d started\n", chipid & 0xffff, | |
518 | chipid >> 16); | |
519 | ||
520 | /* PTD Register Init Part 2, Step 28 */ | |
521 | /* enable INTs */ | |
522 | isp1760_init_maps(hcd); | |
523 | ||
524 | /* GRR this is run-once init(), being done every time the HC starts. | |
525 | * So long as they're part of class devices, we can't do it init() | |
526 | * since the class device isn't created that early. | |
527 | */ | |
528 | return 0; | |
529 | } | |
530 | ||
531 | static u32 base_to_chip(u32 base) | |
532 | { | |
533 | return ((base - 0x400) >> 3); | |
534 | } | |
535 | ||
536 | static void transform_into_atl(struct isp1760_hcd *priv, struct isp1760_qh *qh, | |
537 | struct isp1760_qtd *qtd, struct urb *urb, | |
538 | u32 payload, struct ptd *ptd) | |
539 | { | |
540 | u32 dw0; | |
541 | u32 dw1; | |
542 | u32 dw2; | |
543 | u32 dw3; | |
544 | u32 maxpacket; | |
545 | u32 multi; | |
546 | u32 pid_code; | |
547 | u32 rl = RL_COUNTER; | |
548 | u32 nak = NAK_COUNTER; | |
549 | ||
550 | /* according to 3.6.2, max packet len can not be > 0x400 */ | |
551 | maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); | |
552 | multi = 1 + ((maxpacket >> 11) & 0x3); | |
553 | maxpacket &= 0x7ff; | |
554 | ||
555 | /* DW0 */ | |
556 | dw0 = PTD_VALID; | |
557 | dw0 |= PTD_LENGTH(qtd->length); | |
558 | dw0 |= PTD_MAXPACKET(maxpacket); | |
559 | dw0 |= PTD_ENDPOINT(usb_pipeendpoint(urb->pipe)); | |
560 | dw1 = usb_pipeendpoint(urb->pipe) >> 1; | |
561 | ||
562 | /* DW1 */ | |
563 | dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(urb->pipe)); | |
564 | ||
565 | pid_code = qtd->packet_type; | |
566 | dw1 |= PTD_PID_TOKEN(pid_code); | |
567 | ||
568 | if (usb_pipebulk(urb->pipe)) | |
569 | dw1 |= PTD_TRANS_BULK; | |
570 | else if (usb_pipeint(urb->pipe)) | |
571 | dw1 |= PTD_TRANS_INT; | |
572 | ||
573 | if (urb->dev->speed != USB_SPEED_HIGH) { | |
574 | /* split transaction */ | |
575 | ||
576 | dw1 |= PTD_TRANS_SPLIT; | |
577 | if (urb->dev->speed == USB_SPEED_LOW) | |
578 | dw1 |= PTD_SE_USB_LOSPEED; | |
579 | ||
580 | dw1 |= PTD_PORT_NUM(urb->dev->ttport); | |
581 | dw1 |= PTD_HUB_NUM(urb->dev->tt->hub->devnum); | |
582 | ||
583 | /* SE bit for Split INT transfers */ | |
584 | if (usb_pipeint(urb->pipe) && | |
585 | (urb->dev->speed == USB_SPEED_LOW)) | |
586 | dw1 |= 2 << 16; | |
587 | ||
588 | dw3 = 0; | |
589 | rl = 0; | |
590 | nak = 0; | |
591 | } else { | |
592 | dw0 |= PTD_MULTI(multi); | |
593 | if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) | |
594 | dw3 = qh->ping; | |
595 | else | |
596 | dw3 = 0; | |
597 | } | |
598 | /* DW2 */ | |
599 | dw2 = 0; | |
600 | dw2 |= PTD_DATA_START_ADDR(base_to_chip(payload)); | |
601 | dw2 |= PTD_RL_CNT(rl); | |
602 | dw3 |= PTD_NAC_CNT(nak); | |
603 | ||
604 | /* DW3 */ | |
605 | if (usb_pipecontrol(urb->pipe)) | |
606 | dw3 |= PTD_DATA_TOGGLE(qtd->toggle); | |
607 | else | |
608 | dw3 |= qh->toggle; | |
609 | ||
610 | ||
611 | dw3 |= PTD_ACTIVE; | |
612 | /* Cerr */ | |
613 | dw3 |= PTD_CERR(ERR_COUNTER); | |
614 | ||
615 | memset(ptd, 0, sizeof(*ptd)); | |
616 | ||
617 | ptd->dw0 = cpu_to_le32(dw0); | |
618 | ptd->dw1 = cpu_to_le32(dw1); | |
619 | ptd->dw2 = cpu_to_le32(dw2); | |
620 | ptd->dw3 = cpu_to_le32(dw3); | |
621 | } | |
622 | ||
623 | static void transform_add_int(struct isp1760_hcd *priv, struct isp1760_qh *qh, | |
624 | struct isp1760_qtd *qtd, struct urb *urb, | |
625 | u32 payload, struct ptd *ptd) | |
626 | { | |
627 | u32 maxpacket; | |
628 | u32 multi; | |
629 | u32 numberofusofs; | |
630 | u32 i; | |
631 | u32 usofmask, usof; | |
632 | u32 period; | |
633 | ||
634 | maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); | |
635 | multi = 1 + ((maxpacket >> 11) & 0x3); | |
636 | maxpacket &= 0x7ff; | |
637 | /* length of the data per uframe */ | |
638 | maxpacket = multi * maxpacket; | |
639 | ||
640 | numberofusofs = urb->transfer_buffer_length / maxpacket; | |
641 | if (urb->transfer_buffer_length % maxpacket) | |
642 | numberofusofs += 1; | |
643 | ||
644 | usofmask = 1; | |
645 | usof = 0; | |
646 | for (i = 0; i < numberofusofs; i++) { | |
647 | usof |= usofmask; | |
648 | usofmask <<= 1; | |
649 | } | |
650 | ||
651 | if (urb->dev->speed != USB_SPEED_HIGH) { | |
652 | /* split */ | |
551509d2 | 653 | ptd->dw5 = cpu_to_le32(0x1c); |
db11e47d SS |
654 | |
655 | if (qh->period >= 32) | |
656 | period = qh->period / 2; | |
657 | else | |
658 | period = qh->period; | |
659 | ||
660 | } else { | |
661 | ||
662 | if (qh->period >= 8) | |
663 | period = qh->period/8; | |
664 | else | |
665 | period = qh->period; | |
666 | ||
667 | if (period >= 32) | |
668 | period = 16; | |
669 | ||
670 | if (qh->period >= 8) { | |
671 | /* millisecond period */ | |
672 | period = (period << 3); | |
673 | } else { | |
674 | /* usof based tranmsfers */ | |
675 | /* minimum 4 usofs */ | |
676 | usof = 0x11; | |
677 | } | |
678 | } | |
679 | ||
680 | ptd->dw2 |= cpu_to_le32(period); | |
681 | ptd->dw4 = cpu_to_le32(usof); | |
682 | } | |
683 | ||
684 | static void transform_into_int(struct isp1760_hcd *priv, struct isp1760_qh *qh, | |
685 | struct isp1760_qtd *qtd, struct urb *urb, | |
686 | u32 payload, struct ptd *ptd) | |
687 | { | |
688 | transform_into_atl(priv, qh, qtd, urb, payload, ptd); | |
689 | transform_add_int(priv, qh, qtd, urb, payload, ptd); | |
690 | } | |
691 | ||
692 | static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len, | |
693 | u32 token) | |
694 | { | |
695 | int count; | |
696 | ||
697 | qtd->data_buffer = databuffer; | |
698 | qtd->packet_type = GET_QTD_TOKEN_TYPE(token); | |
699 | qtd->toggle = GET_DATA_TOGGLE(token); | |
700 | ||
701 | if (len > HC_ATL_PL_SIZE) | |
702 | count = HC_ATL_PL_SIZE; | |
703 | else | |
704 | count = len; | |
705 | ||
706 | qtd->length = count; | |
707 | return count; | |
708 | } | |
709 | ||
710 | static int check_error(struct ptd *ptd) | |
711 | { | |
712 | int error = 0; | |
713 | u32 dw3; | |
714 | ||
715 | dw3 = le32_to_cpu(ptd->dw3); | |
716 | if (dw3 & DW3_HALT_BIT) | |
717 | error = -EPIPE; | |
718 | ||
719 | if (dw3 & DW3_ERROR_BIT) { | |
720 | printk(KERN_ERR "error bit is set in DW3\n"); | |
721 | error = -EPIPE; | |
722 | } | |
723 | ||
724 | if (dw3 & DW3_QTD_ACTIVE) { | |
725 | printk(KERN_ERR "transfer active bit is set DW3\n"); | |
726 | printk(KERN_ERR "nak counter: %d, rl: %d\n", (dw3 >> 19) & 0xf, | |
727 | (le32_to_cpu(ptd->dw2) >> 25) & 0xf); | |
728 | } | |
729 | ||
730 | return error; | |
731 | } | |
732 | ||
733 | static void check_int_err_status(u32 dw4) | |
734 | { | |
735 | u32 i; | |
736 | ||
737 | dw4 >>= 8; | |
738 | ||
739 | for (i = 0; i < 8; i++) { | |
740 | switch (dw4 & 0x7) { | |
741 | case INT_UNDERRUN: | |
742 | printk(KERN_ERR "ERROR: under run , %d\n", i); | |
743 | break; | |
744 | ||
745 | case INT_EXACT: | |
746 | printk(KERN_ERR "ERROR: transaction error, %d\n", i); | |
747 | break; | |
748 | ||
749 | case INT_BABBLE: | |
750 | printk(KERN_ERR "ERROR: babble error, %d\n", i); | |
751 | break; | |
752 | } | |
753 | dw4 >>= 3; | |
754 | } | |
755 | } | |
756 | ||
757 | static void enqueue_one_qtd(struct isp1760_qtd *qtd, struct isp1760_hcd *priv, | |
758 | u32 payload) | |
759 | { | |
760 | u32 token; | |
761 | struct usb_hcd *hcd = priv_to_hcd(priv); | |
762 | ||
763 | token = qtd->packet_type; | |
764 | ||
765 | if (qtd->length && (qtd->length <= HC_ATL_PL_SIZE)) { | |
766 | switch (token) { | |
767 | case IN_PID: | |
768 | break; | |
769 | case OUT_PID: | |
770 | case SETUP_PID: | |
771 | priv_write_copy(priv, qtd->data_buffer, | |
772 | hcd->regs + payload, | |
773 | qtd->length); | |
774 | } | |
775 | } | |
776 | } | |
777 | ||
778 | static void enqueue_one_atl_qtd(u32 atl_regs, u32 payload, | |
779 | struct isp1760_hcd *priv, struct isp1760_qh *qh, | |
780 | struct urb *urb, u32 slot, struct isp1760_qtd *qtd) | |
781 | { | |
782 | struct ptd ptd; | |
783 | struct usb_hcd *hcd = priv_to_hcd(priv); | |
784 | ||
785 | transform_into_atl(priv, qh, qtd, urb, payload, &ptd); | |
786 | priv_write_copy(priv, (u32 *)&ptd, hcd->regs + atl_regs, sizeof(ptd)); | |
787 | enqueue_one_qtd(qtd, priv, payload); | |
788 | ||
789 | priv->atl_ints[slot].urb = urb; | |
790 | priv->atl_ints[slot].qh = qh; | |
791 | priv->atl_ints[slot].qtd = qtd; | |
792 | priv->atl_ints[slot].data_buffer = qtd->data_buffer; | |
793 | priv->atl_ints[slot].payload = payload; | |
794 | qtd->status |= URB_ENQUEUED | URB_TYPE_ATL; | |
795 | qtd->status |= slot << 16; | |
796 | } | |
797 | ||
798 | static void enqueue_one_int_qtd(u32 int_regs, u32 payload, | |
799 | struct isp1760_hcd *priv, struct isp1760_qh *qh, | |
800 | struct urb *urb, u32 slot, struct isp1760_qtd *qtd) | |
801 | { | |
802 | struct ptd ptd; | |
803 | struct usb_hcd *hcd = priv_to_hcd(priv); | |
804 | ||
805 | transform_into_int(priv, qh, qtd, urb, payload, &ptd); | |
806 | priv_write_copy(priv, (u32 *)&ptd, hcd->regs + int_regs, sizeof(ptd)); | |
807 | enqueue_one_qtd(qtd, priv, payload); | |
808 | ||
809 | priv->int_ints[slot].urb = urb; | |
810 | priv->int_ints[slot].qh = qh; | |
811 | priv->int_ints[slot].qtd = qtd; | |
812 | priv->int_ints[slot].data_buffer = qtd->data_buffer; | |
813 | priv->int_ints[slot].payload = payload; | |
814 | qtd->status |= URB_ENQUEUED | URB_TYPE_INT; | |
815 | qtd->status |= slot << 16; | |
816 | } | |
817 | ||
473bca94 AB |
818 | static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh, |
819 | struct isp1760_qtd *qtd) | |
db11e47d SS |
820 | { |
821 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
822 | u32 skip_map, or_map; | |
823 | u32 queue_entry; | |
824 | u32 slot; | |
825 | u32 atl_regs, payload; | |
826 | u32 buffstatus; | |
827 | ||
e6bdfe36 CM |
828 | /* |
829 | * When this function is called from the interrupt handler to enqueue | |
830 | * a follow-up packet, the SKIP register gets written and read back | |
831 | * almost immediately. With ISP1761, this register requires a delay of | |
832 | * 195ns between a write and subsequent read (see section 15.1.1.3). | |
833 | */ | |
834 | ndelay(195); | |
db11e47d SS |
835 | skip_map = isp1760_readl(hcd->regs + HC_ATL_PTD_SKIPMAP_REG); |
836 | ||
837 | BUG_ON(!skip_map); | |
838 | slot = __ffs(skip_map); | |
839 | queue_entry = 1 << slot; | |
840 | ||
841 | atl_regs = ATL_REGS_OFFSET + slot * sizeof(struct ptd); | |
842 | ||
843 | payload = alloc_mem(priv, qtd->length); | |
844 | ||
845 | enqueue_one_atl_qtd(atl_regs, payload, priv, qh, qtd->urb, slot, qtd); | |
846 | ||
847 | or_map = isp1760_readl(hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | |
848 | or_map |= queue_entry; | |
849 | isp1760_writel(or_map, hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | |
850 | ||
851 | skip_map &= ~queue_entry; | |
852 | isp1760_writel(skip_map, hcd->regs + HC_ATL_PTD_SKIPMAP_REG); | |
853 | ||
854 | buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG); | |
855 | buffstatus |= ATL_BUFFER; | |
856 | isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG); | |
857 | } | |
858 | ||
473bca94 AB |
859 | static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh, |
860 | struct isp1760_qtd *qtd) | |
db11e47d SS |
861 | { |
862 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
863 | u32 skip_map, or_map; | |
864 | u32 queue_entry; | |
865 | u32 slot; | |
866 | u32 int_regs, payload; | |
867 | u32 buffstatus; | |
868 | ||
e6bdfe36 CM |
869 | /* |
870 | * When this function is called from the interrupt handler to enqueue | |
871 | * a follow-up packet, the SKIP register gets written and read back | |
872 | * almost immediately. With ISP1761, this register requires a delay of | |
873 | * 195ns between a write and subsequent read (see section 15.1.1.3). | |
874 | */ | |
875 | ndelay(195); | |
db11e47d SS |
876 | skip_map = isp1760_readl(hcd->regs + HC_INT_PTD_SKIPMAP_REG); |
877 | ||
878 | BUG_ON(!skip_map); | |
879 | slot = __ffs(skip_map); | |
880 | queue_entry = 1 << slot; | |
881 | ||
882 | int_regs = INT_REGS_OFFSET + slot * sizeof(struct ptd); | |
883 | ||
884 | payload = alloc_mem(priv, qtd->length); | |
885 | ||
886 | enqueue_one_int_qtd(int_regs, payload, priv, qh, qtd->urb, slot, qtd); | |
887 | ||
888 | or_map = isp1760_readl(hcd->regs + HC_INT_IRQ_MASK_OR_REG); | |
889 | or_map |= queue_entry; | |
890 | isp1760_writel(or_map, hcd->regs + HC_INT_IRQ_MASK_OR_REG); | |
891 | ||
892 | skip_map &= ~queue_entry; | |
893 | isp1760_writel(skip_map, hcd->regs + HC_INT_PTD_SKIPMAP_REG); | |
894 | ||
895 | buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG); | |
896 | buffstatus |= INT_BUFFER; | |
897 | isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG); | |
898 | } | |
899 | ||
900 | static void isp1760_urb_done(struct isp1760_hcd *priv, struct urb *urb, int status) | |
901 | __releases(priv->lock) | |
902 | __acquires(priv->lock) | |
903 | { | |
904 | if (!urb->unlinked) { | |
905 | if (status == -EINPROGRESS) | |
906 | status = 0; | |
907 | } | |
908 | ||
db8516f6 CM |
909 | if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { |
910 | void *ptr; | |
911 | for (ptr = urb->transfer_buffer; | |
912 | ptr < urb->transfer_buffer + urb->transfer_buffer_length; | |
913 | ptr += PAGE_SIZE) | |
914 | flush_dcache_page(virt_to_page(ptr)); | |
915 | } | |
916 | ||
db11e47d SS |
917 | /* complete() can reenter this HCD */ |
918 | usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb); | |
919 | spin_unlock(&priv->lock); | |
920 | usb_hcd_giveback_urb(priv_to_hcd(priv), urb, status); | |
921 | spin_lock(&priv->lock); | |
922 | } | |
923 | ||
924 | static void isp1760_qtd_free(struct isp1760_qtd *qtd) | |
925 | { | |
926 | kmem_cache_free(qtd_cachep, qtd); | |
927 | } | |
928 | ||
929 | static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd) | |
930 | { | |
931 | struct isp1760_qtd *tmp_qtd; | |
932 | ||
933 | tmp_qtd = qtd->hw_next; | |
934 | list_del(&qtd->qtd_list); | |
935 | isp1760_qtd_free(qtd); | |
936 | return tmp_qtd; | |
937 | } | |
938 | ||
939 | /* | |
940 | * Remove this QTD from the QH list and free its memory. If this QTD | |
941 | * isn't the last one than remove also his successor(s). | |
942 | * Returns the QTD which is part of an new URB and should be enqueued. | |
943 | */ | |
944 | static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd) | |
945 | { | |
946 | struct isp1760_qtd *tmp_qtd; | |
947 | int last_one; | |
948 | ||
949 | do { | |
950 | tmp_qtd = qtd->hw_next; | |
951 | last_one = qtd->status & URB_COMPLETE_NOTIFY; | |
952 | list_del(&qtd->qtd_list); | |
953 | isp1760_qtd_free(qtd); | |
954 | qtd = tmp_qtd; | |
955 | } while (!last_one && qtd); | |
956 | ||
957 | return qtd; | |
958 | } | |
959 | ||
960 | static void do_atl_int(struct usb_hcd *usb_hcd) | |
961 | { | |
962 | struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); | |
963 | u32 done_map, skip_map; | |
964 | struct ptd ptd; | |
965 | struct urb *urb = NULL; | |
966 | u32 atl_regs_base; | |
967 | u32 atl_regs; | |
968 | u32 queue_entry; | |
969 | u32 payload; | |
970 | u32 length; | |
971 | u32 or_map; | |
972 | u32 status = -EINVAL; | |
973 | int error; | |
974 | struct isp1760_qtd *qtd; | |
975 | struct isp1760_qh *qh; | |
976 | u32 rl; | |
977 | u32 nakcount; | |
978 | ||
979 | done_map = isp1760_readl(usb_hcd->regs + | |
980 | HC_ATL_PTD_DONEMAP_REG); | |
981 | skip_map = isp1760_readl(usb_hcd->regs + | |
982 | HC_ATL_PTD_SKIPMAP_REG); | |
983 | ||
984 | or_map = isp1760_readl(usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | |
985 | or_map &= ~done_map; | |
986 | isp1760_writel(or_map, usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG); | |
987 | ||
988 | atl_regs_base = ATL_REGS_OFFSET; | |
989 | while (done_map) { | |
990 | u32 dw1; | |
991 | u32 dw2; | |
992 | u32 dw3; | |
993 | ||
994 | status = 0; | |
995 | ||
996 | queue_entry = __ffs(done_map); | |
997 | done_map &= ~(1 << queue_entry); | |
998 | skip_map |= 1 << queue_entry; | |
999 | ||
1000 | atl_regs = atl_regs_base + queue_entry * sizeof(struct ptd); | |
1001 | ||
1002 | urb = priv->atl_ints[queue_entry].urb; | |
1003 | qtd = priv->atl_ints[queue_entry].qtd; | |
1004 | qh = priv->atl_ints[queue_entry].qh; | |
1005 | payload = priv->atl_ints[queue_entry].payload; | |
1006 | ||
1007 | if (!qh) { | |
1008 | printk(KERN_ERR "qh is 0\n"); | |
1009 | continue; | |
1010 | } | |
3f02a957 ES |
1011 | isp1760_writel(atl_regs + ISP_BANK(0), usb_hcd->regs + |
1012 | HC_MEMORY_REG); | |
1013 | isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + | |
1014 | HC_MEMORY_REG); | |
1015 | /* | |
1016 | * write bank1 address twice to ensure the 90ns delay (time | |
1017 | * between BANK0 write and the priv_read_copy() call is at | |
380ec678 | 1018 | * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 109ns) |
3f02a957 ES |
1019 | */ |
1020 | isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + | |
1021 | HC_MEMORY_REG); | |
1022 | ||
1023 | priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs + | |
1024 | ISP_BANK(0), sizeof(ptd)); | |
db11e47d SS |
1025 | |
1026 | dw1 = le32_to_cpu(ptd.dw1); | |
1027 | dw2 = le32_to_cpu(ptd.dw2); | |
1028 | dw3 = le32_to_cpu(ptd.dw3); | |
1029 | rl = (dw2 >> 25) & 0x0f; | |
1030 | nakcount = (dw3 >> 19) & 0xf; | |
1031 | ||
1032 | /* Transfer Error, *but* active and no HALT -> reload */ | |
1033 | if ((dw3 & DW3_ERROR_BIT) && (dw3 & DW3_QTD_ACTIVE) && | |
1034 | !(dw3 & DW3_HALT_BIT)) { | |
1035 | ||
1036 | /* according to ppriv code, we have to | |
1037 | * reload this one if trasfered bytes != requested bytes | |
1038 | * else act like everything went smooth.. | |
1039 | * XXX This just doesn't feel right and hasn't | |
1040 | * triggered so far. | |
1041 | */ | |
1042 | ||
1043 | length = PTD_XFERRED_LENGTH(dw3); | |
1044 | printk(KERN_ERR "Should reload now.... transfered %d " | |
1045 | "of %zu\n", length, qtd->length); | |
1046 | BUG(); | |
1047 | } | |
1048 | ||
1049 | if (!nakcount && (dw3 & DW3_QTD_ACTIVE)) { | |
1050 | u32 buffstatus; | |
1051 | ||
c0d74142 | 1052 | /* |
db11e47d SS |
1053 | * NAKs are handled in HW by the chip. Usually if the |
1054 | * device is not able to send data fast enough. | |
c0d74142 | 1055 | * This happens mostly on slower hardware. |
db11e47d | 1056 | */ |
c0d74142 | 1057 | printk(KERN_NOTICE "Reloading ptd %p/%p... qh %p read: " |
22026473 | 1058 | "%d of %zu done: %08x cur: %08x\n", qtd, |
db11e47d SS |
1059 | urb, qh, PTD_XFERRED_LENGTH(dw3), |
1060 | qtd->length, done_map, | |
1061 | (1 << queue_entry)); | |
1062 | ||
1063 | /* RL counter = ERR counter */ | |
1064 | dw3 &= ~(0xf << 19); | |
1065 | dw3 |= rl << 19; | |
1066 | dw3 &= ~(3 << (55 - 32)); | |
1067 | dw3 |= ERR_COUNTER << (55 - 32); | |
1068 | ||
1069 | /* | |
1070 | * It is not needed to write skip map back because it | |
1071 | * is unchanged. Just make sure that this entry is | |
1072 | * unskipped once it gets written to the HW. | |
1073 | */ | |
1074 | skip_map &= ~(1 << queue_entry); | |
1075 | or_map = isp1760_readl(usb_hcd->regs + | |
1076 | HC_ATL_IRQ_MASK_OR_REG); | |
1077 | or_map |= 1 << queue_entry; | |
1078 | isp1760_writel(or_map, usb_hcd->regs + | |
1079 | HC_ATL_IRQ_MASK_OR_REG); | |
1080 | ||
1081 | ptd.dw3 = cpu_to_le32(dw3); | |
1082 | priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs + | |
1083 | atl_regs, sizeof(ptd)); | |
1084 | ||
551509d2 | 1085 | ptd.dw0 |= cpu_to_le32(PTD_VALID); |
db11e47d SS |
1086 | priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs + |
1087 | atl_regs, sizeof(ptd)); | |
1088 | ||
1089 | buffstatus = isp1760_readl(usb_hcd->regs + | |
1090 | HC_BUFFER_STATUS_REG); | |
1091 | buffstatus |= ATL_BUFFER; | |
1092 | isp1760_writel(buffstatus, usb_hcd->regs + | |
1093 | HC_BUFFER_STATUS_REG); | |
1094 | continue; | |
1095 | } | |
1096 | ||
1097 | error = check_error(&ptd); | |
1098 | if (error) { | |
1099 | status = error; | |
1100 | priv->atl_ints[queue_entry].qh->toggle = 0; | |
1101 | priv->atl_ints[queue_entry].qh->ping = 0; | |
1102 | urb->status = -EPIPE; | |
1103 | ||
1104 | #if 0 | |
1105 | printk(KERN_ERR "Error in %s().\n", __func__); | |
1106 | printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x " | |
1107 | "dw3: %08x dw4: %08x dw5: %08x dw6: " | |
1108 | "%08x dw7: %08x\n", | |
1109 | ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3, | |
1110 | ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7); | |
1111 | #endif | |
1112 | } else { | |
1113 | if (usb_pipetype(urb->pipe) == PIPE_BULK) { | |
1114 | priv->atl_ints[queue_entry].qh->toggle = dw3 & | |
1115 | (1 << 25); | |
1116 | priv->atl_ints[queue_entry].qh->ping = dw3 & | |
1117 | (1 << 26); | |
1118 | } | |
1119 | } | |
1120 | ||
1121 | length = PTD_XFERRED_LENGTH(dw3); | |
1122 | if (length) { | |
1123 | switch (DW1_GET_PID(dw1)) { | |
1124 | case IN_PID: | |
1125 | priv_read_copy(priv, | |
1126 | priv->atl_ints[queue_entry].data_buffer, | |
3f02a957 | 1127 | usb_hcd->regs + payload + ISP_BANK(1), |
db11e47d SS |
1128 | length); |
1129 | ||
1130 | case OUT_PID: | |
1131 | ||
1132 | urb->actual_length += length; | |
1133 | ||
1134 | case SETUP_PID: | |
1135 | break; | |
1136 | } | |
1137 | } | |
1138 | ||
1139 | priv->atl_ints[queue_entry].data_buffer = NULL; | |
1140 | priv->atl_ints[queue_entry].urb = NULL; | |
1141 | priv->atl_ints[queue_entry].qtd = NULL; | |
1142 | priv->atl_ints[queue_entry].qh = NULL; | |
1143 | ||
1144 | free_mem(priv, payload); | |
1145 | ||
1146 | isp1760_writel(skip_map, usb_hcd->regs + | |
1147 | HC_ATL_PTD_SKIPMAP_REG); | |
1148 | ||
1149 | if (urb->status == -EPIPE) { | |
1150 | /* HALT was received */ | |
1151 | ||
1152 | qtd = clean_up_qtdlist(qtd); | |
1153 | isp1760_urb_done(priv, urb, urb->status); | |
1154 | ||
1155 | } else if (usb_pipebulk(urb->pipe) && (length < qtd->length)) { | |
1156 | /* short BULK received */ | |
1157 | ||
db11e47d SS |
1158 | if (urb->transfer_flags & URB_SHORT_NOT_OK) { |
1159 | urb->status = -EREMOTEIO; | |
7839b516 SS |
1160 | isp1760_dbg(priv, "short bulk, %d instead %zu " |
1161 | "with URB_SHORT_NOT_OK flag.\n", | |
1162 | length, qtd->length); | |
db11e47d SS |
1163 | } |
1164 | ||
1165 | if (urb->status == -EINPROGRESS) | |
1166 | urb->status = 0; | |
1167 | ||
1168 | qtd = clean_up_qtdlist(qtd); | |
1169 | ||
1170 | isp1760_urb_done(priv, urb, urb->status); | |
1171 | ||
1172 | } else if (qtd->status & URB_COMPLETE_NOTIFY) { | |
1173 | /* that was the last qtd of that URB */ | |
1174 | ||
1175 | if (urb->status == -EINPROGRESS) | |
1176 | urb->status = 0; | |
1177 | ||
1178 | qtd = clean_this_qtd(qtd); | |
1179 | isp1760_urb_done(priv, urb, urb->status); | |
1180 | ||
1181 | } else { | |
1182 | /* next QTD of this URB */ | |
1183 | ||
1184 | qtd = clean_this_qtd(qtd); | |
1185 | BUG_ON(!qtd); | |
1186 | } | |
1187 | ||
1188 | if (qtd) | |
1189 | enqueue_an_ATL_packet(usb_hcd, qh, qtd); | |
1190 | ||
1191 | skip_map = isp1760_readl(usb_hcd->regs + | |
1192 | HC_ATL_PTD_SKIPMAP_REG); | |
1193 | } | |
1194 | } | |
1195 | ||
1196 | static void do_intl_int(struct usb_hcd *usb_hcd) | |
1197 | { | |
1198 | struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); | |
1199 | u32 done_map, skip_map; | |
1200 | struct ptd ptd; | |
1201 | struct urb *urb = NULL; | |
1202 | u32 int_regs; | |
1203 | u32 int_regs_base; | |
1204 | u32 payload; | |
1205 | u32 length; | |
1206 | u32 or_map; | |
1207 | int error; | |
1208 | u32 queue_entry; | |
1209 | struct isp1760_qtd *qtd; | |
1210 | struct isp1760_qh *qh; | |
1211 | ||
1212 | done_map = isp1760_readl(usb_hcd->regs + | |
1213 | HC_INT_PTD_DONEMAP_REG); | |
1214 | skip_map = isp1760_readl(usb_hcd->regs + | |
1215 | HC_INT_PTD_SKIPMAP_REG); | |
1216 | ||
1217 | or_map = isp1760_readl(usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG); | |
1218 | or_map &= ~done_map; | |
1219 | isp1760_writel(or_map, usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG); | |
1220 | ||
1221 | int_regs_base = INT_REGS_OFFSET; | |
1222 | ||
1223 | while (done_map) { | |
1224 | u32 dw1; | |
1225 | u32 dw3; | |
1226 | ||
1227 | queue_entry = __ffs(done_map); | |
1228 | done_map &= ~(1 << queue_entry); | |
1229 | skip_map |= 1 << queue_entry; | |
1230 | ||
1231 | int_regs = int_regs_base + queue_entry * sizeof(struct ptd); | |
1232 | urb = priv->int_ints[queue_entry].urb; | |
1233 | qtd = priv->int_ints[queue_entry].qtd; | |
1234 | qh = priv->int_ints[queue_entry].qh; | |
1235 | payload = priv->int_ints[queue_entry].payload; | |
1236 | ||
1237 | if (!qh) { | |
1238 | printk(KERN_ERR "(INT) qh is 0\n"); | |
1239 | continue; | |
1240 | } | |
1241 | ||
3f02a957 ES |
1242 | isp1760_writel(int_regs + ISP_BANK(0), usb_hcd->regs + |
1243 | HC_MEMORY_REG); | |
1244 | isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + | |
1245 | HC_MEMORY_REG); | |
1246 | /* | |
1247 | * write bank1 address twice to ensure the 90ns delay (time | |
1248 | * between BANK0 write and the priv_read_copy() call is at | |
1249 | * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns) | |
1250 | */ | |
1251 | isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs + | |
1252 | HC_MEMORY_REG); | |
1253 | ||
1254 | priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs + | |
1255 | ISP_BANK(0), sizeof(ptd)); | |
db11e47d SS |
1256 | dw1 = le32_to_cpu(ptd.dw1); |
1257 | dw3 = le32_to_cpu(ptd.dw3); | |
1258 | check_int_err_status(le32_to_cpu(ptd.dw4)); | |
1259 | ||
1260 | error = check_error(&ptd); | |
1261 | if (error) { | |
1262 | #if 0 | |
1263 | printk(KERN_ERR "Error in %s().\n", __func__); | |
1264 | printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x " | |
1265 | "dw3: %08x dw4: %08x dw5: %08x dw6: " | |
1266 | "%08x dw7: %08x\n", | |
1267 | ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3, | |
1268 | ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7); | |
1269 | #endif | |
1270 | urb->status = -EPIPE; | |
1271 | priv->int_ints[queue_entry].qh->toggle = 0; | |
1272 | priv->int_ints[queue_entry].qh->ping = 0; | |
1273 | ||
1274 | } else { | |
1275 | priv->int_ints[queue_entry].qh->toggle = | |
1276 | dw3 & (1 << 25); | |
1277 | priv->int_ints[queue_entry].qh->ping = dw3 & (1 << 26); | |
1278 | } | |
1279 | ||
1280 | if (urb->dev->speed != USB_SPEED_HIGH) | |
1281 | length = PTD_XFERRED_LENGTH_LO(dw3); | |
1282 | else | |
1283 | length = PTD_XFERRED_LENGTH(dw3); | |
1284 | ||
1285 | if (length) { | |
1286 | switch (DW1_GET_PID(dw1)) { | |
1287 | case IN_PID: | |
1288 | priv_read_copy(priv, | |
1289 | priv->int_ints[queue_entry].data_buffer, | |
3f02a957 | 1290 | usb_hcd->regs + payload + ISP_BANK(1), |
db11e47d SS |
1291 | length); |
1292 | case OUT_PID: | |
1293 | ||
1294 | urb->actual_length += length; | |
1295 | ||
1296 | case SETUP_PID: | |
1297 | break; | |
1298 | } | |
1299 | } | |
1300 | ||
1301 | priv->int_ints[queue_entry].data_buffer = NULL; | |
1302 | priv->int_ints[queue_entry].urb = NULL; | |
1303 | priv->int_ints[queue_entry].qtd = NULL; | |
1304 | priv->int_ints[queue_entry].qh = NULL; | |
1305 | ||
1306 | isp1760_writel(skip_map, usb_hcd->regs + | |
1307 | HC_INT_PTD_SKIPMAP_REG); | |
1308 | free_mem(priv, payload); | |
1309 | ||
1310 | if (urb->status == -EPIPE) { | |
1311 | /* HALT received */ | |
1312 | ||
1313 | qtd = clean_up_qtdlist(qtd); | |
1314 | isp1760_urb_done(priv, urb, urb->status); | |
1315 | ||
1316 | } else if (qtd->status & URB_COMPLETE_NOTIFY) { | |
1317 | ||
1318 | if (urb->status == -EINPROGRESS) | |
1319 | urb->status = 0; | |
1320 | ||
1321 | qtd = clean_this_qtd(qtd); | |
1322 | isp1760_urb_done(priv, urb, urb->status); | |
1323 | ||
1324 | } else { | |
1325 | /* next QTD of this URB */ | |
1326 | ||
1327 | qtd = clean_this_qtd(qtd); | |
1328 | BUG_ON(!qtd); | |
1329 | } | |
1330 | ||
1331 | if (qtd) | |
1332 | enqueue_an_INT_packet(usb_hcd, qh, qtd); | |
1333 | ||
1334 | skip_map = isp1760_readl(usb_hcd->regs + | |
1335 | HC_INT_PTD_SKIPMAP_REG); | |
1336 | } | |
1337 | } | |
1338 | ||
1339 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) | |
1340 | static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb, | |
1341 | gfp_t flags) | |
1342 | { | |
1343 | struct isp1760_qh *qh; | |
1344 | int is_input, type; | |
1345 | ||
1346 | qh = isp1760_qh_alloc(priv, flags); | |
1347 | if (!qh) | |
1348 | return qh; | |
1349 | ||
1350 | /* | |
1351 | * init endpoint/device data for this QH | |
1352 | */ | |
1353 | is_input = usb_pipein(urb->pipe); | |
1354 | type = usb_pipetype(urb->pipe); | |
1355 | ||
1356 | if (type == PIPE_INTERRUPT) { | |
1357 | ||
1358 | if (urb->dev->speed == USB_SPEED_HIGH) { | |
1359 | ||
1360 | qh->period = urb->interval >> 3; | |
1361 | if (qh->period == 0 && urb->interval != 1) { | |
1362 | /* NOTE interval 2 or 4 uframes could work. | |
1363 | * But interval 1 scheduling is simpler, and | |
1364 | * includes high bandwidth. | |
1365 | */ | |
1366 | printk(KERN_ERR "intr period %d uframes, NYET!", | |
1367 | urb->interval); | |
1368 | qh_destroy(qh); | |
1369 | return NULL; | |
1370 | } | |
1371 | } else { | |
1372 | qh->period = urb->interval; | |
1373 | } | |
1374 | } | |
1375 | ||
1376 | /* support for tt scheduling, and access to toggles */ | |
1377 | qh->dev = urb->dev; | |
1378 | ||
1379 | if (!usb_pipecontrol(urb->pipe)) | |
1380 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, | |
1381 | 1); | |
1382 | return qh; | |
1383 | } | |
1384 | ||
1385 | /* | |
1386 | * For control/bulk/interrupt, return QH with these TDs appended. | |
1387 | * Allocates and initializes the QH if necessary. | |
1388 | * Returns null if it can't allocate a QH it needs to. | |
1389 | * If the QH has TDs (urbs) already, that's great. | |
1390 | */ | |
1391 | static struct isp1760_qh *qh_append_tds(struct isp1760_hcd *priv, | |
1392 | struct urb *urb, struct list_head *qtd_list, int epnum, | |
1393 | void **ptr) | |
1394 | { | |
1395 | struct isp1760_qh *qh; | |
1396 | struct isp1760_qtd *qtd; | |
1397 | struct isp1760_qtd *prev_qtd; | |
1398 | ||
1399 | qh = (struct isp1760_qh *)*ptr; | |
1400 | if (!qh) { | |
1401 | /* can't sleep here, we have priv->lock... */ | |
1402 | qh = qh_make(priv, urb, GFP_ATOMIC); | |
1403 | if (!qh) | |
1404 | return qh; | |
1405 | *ptr = qh; | |
1406 | } | |
1407 | ||
1408 | qtd = list_entry(qtd_list->next, struct isp1760_qtd, | |
1409 | qtd_list); | |
1410 | if (!list_empty(&qh->qtd_list)) | |
1411 | prev_qtd = list_entry(qh->qtd_list.prev, | |
1412 | struct isp1760_qtd, qtd_list); | |
1413 | else | |
1414 | prev_qtd = NULL; | |
1415 | ||
1416 | list_splice(qtd_list, qh->qtd_list.prev); | |
1417 | if (prev_qtd) { | |
1418 | BUG_ON(prev_qtd->hw_next); | |
1419 | prev_qtd->hw_next = qtd; | |
1420 | } | |
1421 | ||
1422 | urb->hcpriv = qh; | |
1423 | return qh; | |
1424 | } | |
1425 | ||
1426 | static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb, | |
1427 | struct list_head *qtd_list) | |
1428 | { | |
1429 | struct list_head *entry, *temp; | |
1430 | ||
1431 | list_for_each_safe(entry, temp, qtd_list) { | |
1432 | struct isp1760_qtd *qtd; | |
1433 | ||
1434 | qtd = list_entry(entry, struct isp1760_qtd, qtd_list); | |
1435 | list_del(&qtd->qtd_list); | |
1436 | isp1760_qtd_free(qtd); | |
1437 | } | |
1438 | } | |
1439 | ||
1440 | static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb, | |
1441 | struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p) | |
1442 | { | |
1443 | struct isp1760_qtd *qtd; | |
1444 | int epnum; | |
1445 | unsigned long flags; | |
1446 | struct isp1760_qh *qh = NULL; | |
1447 | int rc; | |
1448 | int qh_busy; | |
1449 | ||
1450 | qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list); | |
1451 | epnum = urb->ep->desc.bEndpointAddress; | |
1452 | ||
1453 | spin_lock_irqsave(&priv->lock, flags); | |
1454 | if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &priv_to_hcd(priv)->flags)) { | |
1455 | rc = -ESHUTDOWN; | |
1456 | goto done; | |
1457 | } | |
1458 | rc = usb_hcd_link_urb_to_ep(priv_to_hcd(priv), urb); | |
1459 | if (rc) | |
1460 | goto done; | |
1461 | ||
1462 | qh = urb->ep->hcpriv; | |
1463 | if (qh) | |
1464 | qh_busy = !list_empty(&qh->qtd_list); | |
1465 | else | |
1466 | qh_busy = 0; | |
1467 | ||
1468 | qh = qh_append_tds(priv, urb, qtd_list, epnum, &urb->ep->hcpriv); | |
1469 | if (!qh) { | |
1470 | usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb); | |
1471 | rc = -ENOMEM; | |
1472 | goto done; | |
1473 | } | |
1474 | ||
1475 | if (!qh_busy) | |
1476 | p(priv_to_hcd(priv), qh, qtd); | |
1477 | ||
1478 | done: | |
1479 | spin_unlock_irqrestore(&priv->lock, flags); | |
1480 | if (!qh) | |
1481 | qtd_list_free(priv, urb, qtd_list); | |
1482 | return rc; | |
1483 | } | |
1484 | ||
1485 | static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv, | |
1486 | gfp_t flags) | |
1487 | { | |
1488 | struct isp1760_qtd *qtd; | |
1489 | ||
1490 | qtd = kmem_cache_zalloc(qtd_cachep, flags); | |
1491 | if (qtd) | |
1492 | INIT_LIST_HEAD(&qtd->qtd_list); | |
1493 | ||
1494 | return qtd; | |
1495 | } | |
1496 | ||
1497 | /* | |
1498 | * create a list of filled qtds for this URB; won't link into qh. | |
1499 | */ | |
1500 | static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv, | |
1501 | struct urb *urb, struct list_head *head, gfp_t flags) | |
1502 | { | |
1503 | struct isp1760_qtd *qtd, *qtd_prev; | |
1504 | void *buf; | |
1505 | int len, maxpacket; | |
1506 | int is_input; | |
1507 | u32 token; | |
1508 | ||
1509 | /* | |
1510 | * URBs map to sequences of QTDs: one logical transaction | |
1511 | */ | |
1512 | qtd = isp1760_qtd_alloc(priv, flags); | |
1513 | if (!qtd) | |
1514 | return NULL; | |
1515 | ||
1516 | list_add_tail(&qtd->qtd_list, head); | |
1517 | qtd->urb = urb; | |
1518 | urb->status = -EINPROGRESS; | |
1519 | ||
1520 | token = 0; | |
1521 | /* for split transactions, SplitXState initialized to zero */ | |
1522 | ||
1523 | len = urb->transfer_buffer_length; | |
1524 | is_input = usb_pipein(urb->pipe); | |
1525 | if (usb_pipecontrol(urb->pipe)) { | |
1526 | /* SETUP pid */ | |
1527 | qtd_fill(qtd, urb->setup_packet, | |
1528 | sizeof(struct usb_ctrlrequest), | |
1529 | token | SETUP_PID); | |
1530 | ||
1531 | /* ... and always at least one more pid */ | |
1532 | token ^= DATA_TOGGLE; | |
1533 | qtd_prev = qtd; | |
1534 | qtd = isp1760_qtd_alloc(priv, flags); | |
1535 | if (!qtd) | |
1536 | goto cleanup; | |
1537 | qtd->urb = urb; | |
1538 | qtd_prev->hw_next = qtd; | |
1539 | list_add_tail(&qtd->qtd_list, head); | |
1540 | ||
1541 | /* for zero length DATA stages, STATUS is always IN */ | |
1542 | if (len == 0) | |
1543 | token |= IN_PID; | |
1544 | } | |
1545 | ||
1546 | /* | |
1547 | * data transfer stage: buffer setup | |
1548 | */ | |
1549 | buf = urb->transfer_buffer; | |
1550 | ||
1551 | if (is_input) | |
1552 | token |= IN_PID; | |
1553 | else | |
1554 | token |= OUT_PID; | |
1555 | ||
1556 | maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input)); | |
1557 | ||
1558 | /* | |
1559 | * buffer gets wrapped in one or more qtds; | |
1560 | * last one may be "short" (including zero len) | |
1561 | * and may serve as a control status ack | |
1562 | */ | |
1563 | for (;;) { | |
1564 | int this_qtd_len; | |
1565 | ||
1566 | if (!buf && len) { | |
1567 | /* XXX This looks like usb storage / SCSI bug */ | |
1568 | printk(KERN_ERR "buf is null, dma is %08lx len is %d\n", | |
1569 | (long unsigned)urb->transfer_dma, len); | |
1570 | WARN_ON(1); | |
1571 | } | |
1572 | ||
1573 | this_qtd_len = qtd_fill(qtd, buf, len, token); | |
1574 | len -= this_qtd_len; | |
1575 | buf += this_qtd_len; | |
1576 | ||
1577 | /* qh makes control packets use qtd toggle; maybe switch it */ | |
1578 | if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0) | |
1579 | token ^= DATA_TOGGLE; | |
1580 | ||
1581 | if (len <= 0) | |
1582 | break; | |
1583 | ||
1584 | qtd_prev = qtd; | |
1585 | qtd = isp1760_qtd_alloc(priv, flags); | |
1586 | if (!qtd) | |
1587 | goto cleanup; | |
1588 | qtd->urb = urb; | |
1589 | qtd_prev->hw_next = qtd; | |
1590 | list_add_tail(&qtd->qtd_list, head); | |
1591 | } | |
1592 | ||
1593 | /* | |
1594 | * control requests may need a terminating data "status" ack; | |
1595 | * bulk ones may need a terminating short packet (zero length). | |
1596 | */ | |
1597 | if (urb->transfer_buffer_length != 0) { | |
1598 | int one_more = 0; | |
1599 | ||
1600 | if (usb_pipecontrol(urb->pipe)) { | |
1601 | one_more = 1; | |
1602 | /* "in" <--> "out" */ | |
1603 | token ^= IN_PID; | |
1604 | /* force DATA1 */ | |
1605 | token |= DATA_TOGGLE; | |
1606 | } else if (usb_pipebulk(urb->pipe) | |
1607 | && (urb->transfer_flags & URB_ZERO_PACKET) | |
1608 | && !(urb->transfer_buffer_length % maxpacket)) { | |
1609 | one_more = 1; | |
1610 | } | |
1611 | if (one_more) { | |
1612 | qtd_prev = qtd; | |
1613 | qtd = isp1760_qtd_alloc(priv, flags); | |
1614 | if (!qtd) | |
1615 | goto cleanup; | |
1616 | qtd->urb = urb; | |
1617 | qtd_prev->hw_next = qtd; | |
1618 | list_add_tail(&qtd->qtd_list, head); | |
1619 | ||
1620 | /* never any data in such packets */ | |
1621 | qtd_fill(qtd, NULL, 0, token); | |
1622 | } | |
1623 | } | |
1624 | ||
1625 | qtd->status = URB_COMPLETE_NOTIFY; | |
1626 | return head; | |
1627 | ||
1628 | cleanup: | |
1629 | qtd_list_free(priv, urb, head); | |
1630 | return NULL; | |
1631 | } | |
1632 | ||
1633 | static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, | |
1634 | gfp_t mem_flags) | |
1635 | { | |
1636 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1637 | struct list_head qtd_list; | |
1638 | packet_enqueue *pe; | |
1639 | ||
1640 | INIT_LIST_HEAD(&qtd_list); | |
1641 | ||
1642 | switch (usb_pipetype(urb->pipe)) { | |
1643 | case PIPE_CONTROL: | |
1644 | case PIPE_BULK: | |
1645 | ||
1646 | if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags)) | |
1647 | return -ENOMEM; | |
1648 | pe = enqueue_an_ATL_packet; | |
1649 | break; | |
1650 | ||
1651 | case PIPE_INTERRUPT: | |
1652 | if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags)) | |
1653 | return -ENOMEM; | |
1654 | pe = enqueue_an_INT_packet; | |
1655 | break; | |
1656 | ||
1657 | case PIPE_ISOCHRONOUS: | |
1658 | printk(KERN_ERR "PIPE_ISOCHRONOUS ain't supported\n"); | |
1659 | default: | |
1660 | return -EPIPE; | |
1661 | } | |
1662 | ||
a36c27df | 1663 | return isp1760_prepare_enqueue(priv, urb, &qtd_list, mem_flags, pe); |
db11e47d SS |
1664 | } |
1665 | ||
1666 | static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, | |
1667 | int status) | |
1668 | { | |
1669 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1670 | struct inter_packet_info *ints; | |
1671 | u32 i; | |
1672 | u32 reg_base, or_reg, skip_reg; | |
d249afdd | 1673 | unsigned long flags; |
db11e47d | 1674 | struct ptd ptd; |
0afb20e0 | 1675 | packet_enqueue *pe; |
db11e47d SS |
1676 | |
1677 | switch (usb_pipetype(urb->pipe)) { | |
1678 | case PIPE_ISOCHRONOUS: | |
1679 | return -EPIPE; | |
1680 | break; | |
1681 | ||
1682 | case PIPE_INTERRUPT: | |
1683 | ints = priv->int_ints; | |
1684 | reg_base = INT_REGS_OFFSET; | |
1685 | or_reg = HC_INT_IRQ_MASK_OR_REG; | |
1686 | skip_reg = HC_INT_PTD_SKIPMAP_REG; | |
0afb20e0 | 1687 | pe = enqueue_an_INT_packet; |
db11e47d SS |
1688 | break; |
1689 | ||
1690 | default: | |
1691 | ints = priv->atl_ints; | |
1692 | reg_base = ATL_REGS_OFFSET; | |
1693 | or_reg = HC_ATL_IRQ_MASK_OR_REG; | |
1694 | skip_reg = HC_ATL_PTD_SKIPMAP_REG; | |
0afb20e0 | 1695 | pe = enqueue_an_ATL_packet; |
db11e47d SS |
1696 | break; |
1697 | } | |
1698 | ||
1699 | memset(&ptd, 0, sizeof(ptd)); | |
1700 | spin_lock_irqsave(&priv->lock, flags); | |
1701 | ||
1702 | for (i = 0; i < 32; i++) { | |
1703 | if (ints->urb == urb) { | |
1704 | u32 skip_map; | |
1705 | u32 or_map; | |
1706 | struct isp1760_qtd *qtd; | |
0afb20e0 | 1707 | struct isp1760_qh *qh = ints->qh; |
db11e47d SS |
1708 | |
1709 | skip_map = isp1760_readl(hcd->regs + skip_reg); | |
1710 | skip_map |= 1 << i; | |
1711 | isp1760_writel(skip_map, hcd->regs + skip_reg); | |
1712 | ||
1713 | or_map = isp1760_readl(hcd->regs + or_reg); | |
1714 | or_map &= ~(1 << i); | |
1715 | isp1760_writel(or_map, hcd->regs + or_reg); | |
1716 | ||
1717 | priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base | |
1718 | + i * sizeof(ptd), sizeof(ptd)); | |
1719 | qtd = ints->qtd; | |
0afb20e0 | 1720 | qtd = clean_up_qtdlist(qtd); |
db11e47d SS |
1721 | |
1722 | free_mem(priv, ints->payload); | |
1723 | ||
1724 | ints->urb = NULL; | |
1725 | ints->qh = NULL; | |
1726 | ints->qtd = NULL; | |
1727 | ints->data_buffer = NULL; | |
1728 | ints->payload = 0; | |
1729 | ||
1730 | isp1760_urb_done(priv, urb, status); | |
0afb20e0 WF |
1731 | if (qtd) |
1732 | pe(hcd, qh, qtd); | |
db11e47d | 1733 | break; |
0afb20e0 WF |
1734 | |
1735 | } else if (ints->qtd) { | |
1736 | struct isp1760_qtd *qtd, *prev_qtd = ints->qtd; | |
1737 | ||
1738 | for (qtd = ints->qtd->hw_next; qtd; qtd = qtd->hw_next) { | |
1739 | if (qtd->urb == urb) { | |
1740 | prev_qtd->hw_next = clean_up_qtdlist(qtd); | |
1741 | isp1760_urb_done(priv, urb, status); | |
1742 | break; | |
1743 | } | |
1744 | prev_qtd = qtd; | |
1745 | } | |
1746 | /* we found the urb before the end of the list */ | |
1747 | if (qtd) | |
1748 | break; | |
db11e47d SS |
1749 | } |
1750 | ints++; | |
1751 | } | |
1752 | ||
1753 | spin_unlock_irqrestore(&priv->lock, flags); | |
1754 | return 0; | |
1755 | } | |
1756 | ||
1757 | static irqreturn_t isp1760_irq(struct usb_hcd *usb_hcd) | |
1758 | { | |
1759 | struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); | |
1760 | u32 imask; | |
1761 | irqreturn_t irqret = IRQ_NONE; | |
1762 | ||
1763 | spin_lock(&priv->lock); | |
1764 | ||
1765 | if (!(usb_hcd->state & HC_STATE_RUNNING)) | |
1766 | goto leave; | |
1767 | ||
1768 | imask = isp1760_readl(usb_hcd->regs + HC_INTERRUPT_REG); | |
1769 | if (unlikely(!imask)) | |
1770 | goto leave; | |
1771 | ||
1772 | isp1760_writel(imask, usb_hcd->regs + HC_INTERRUPT_REG); | |
1773 | if (imask & HC_ATL_INT) | |
1774 | do_atl_int(usb_hcd); | |
1775 | ||
1776 | if (imask & HC_INTL_INT) | |
1777 | do_intl_int(usb_hcd); | |
1778 | ||
1779 | irqret = IRQ_HANDLED; | |
1780 | leave: | |
1781 | spin_unlock(&priv->lock); | |
1782 | return irqret; | |
1783 | } | |
1784 | ||
1785 | static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) | |
1786 | { | |
1787 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1788 | u32 temp, status = 0; | |
1789 | u32 mask; | |
1790 | int retval = 1; | |
1791 | unsigned long flags; | |
1792 | ||
1793 | /* if !USB_SUSPEND, root hub timers won't get shut down ... */ | |
1794 | if (!HC_IS_RUNNING(hcd->state)) | |
1795 | return 0; | |
1796 | ||
1797 | /* init status to no-changes */ | |
1798 | buf[0] = 0; | |
1799 | mask = PORT_CSC; | |
1800 | ||
1801 | spin_lock_irqsave(&priv->lock, flags); | |
1802 | temp = isp1760_readl(hcd->regs + HC_PORTSC1); | |
1803 | ||
1804 | if (temp & PORT_OWNER) { | |
1805 | if (temp & PORT_CSC) { | |
1806 | temp &= ~PORT_CSC; | |
1807 | isp1760_writel(temp, hcd->regs + HC_PORTSC1); | |
1808 | goto done; | |
1809 | } | |
1810 | } | |
1811 | ||
1812 | /* | |
1813 | * Return status information even for ports with OWNER set. | |
1814 | * Otherwise khubd wouldn't see the disconnect event when a | |
1815 | * high-speed device is switched over to the companion | |
1816 | * controller by the user. | |
1817 | */ | |
1818 | ||
1819 | if ((temp & mask) != 0 | |
1820 | || ((temp & PORT_RESUME) != 0 | |
1821 | && time_after_eq(jiffies, | |
1822 | priv->reset_done))) { | |
1823 | buf [0] |= 1 << (0 + 1); | |
1824 | status = STS_PCD; | |
1825 | } | |
1826 | /* FIXME autosuspend idle root hubs */ | |
1827 | done: | |
1828 | spin_unlock_irqrestore(&priv->lock, flags); | |
1829 | return status ? retval : 0; | |
1830 | } | |
1831 | ||
1832 | static void isp1760_hub_descriptor(struct isp1760_hcd *priv, | |
1833 | struct usb_hub_descriptor *desc) | |
1834 | { | |
1835 | int ports = HCS_N_PORTS(priv->hcs_params); | |
1836 | u16 temp; | |
1837 | ||
1838 | desc->bDescriptorType = 0x29; | |
1839 | /* priv 1.0, 2.3.9 says 20ms max */ | |
1840 | desc->bPwrOn2PwrGood = 10; | |
1841 | desc->bHubContrCurrent = 0; | |
1842 | ||
1843 | desc->bNbrPorts = ports; | |
1844 | temp = 1 + (ports / 8); | |
1845 | desc->bDescLength = 7 + 2 * temp; | |
1846 | ||
1847 | /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */ | |
1848 | memset(&desc->bitmap[0], 0, temp); | |
1849 | memset(&desc->bitmap[temp], 0xff, temp); | |
1850 | ||
1851 | /* per-port overcurrent reporting */ | |
1852 | temp = 0x0008; | |
1853 | if (HCS_PPC(priv->hcs_params)) | |
1854 | /* per-port power control */ | |
1855 | temp |= 0x0001; | |
1856 | else | |
1857 | /* no power switching */ | |
1858 | temp |= 0x0002; | |
1859 | desc->wHubCharacteristics = cpu_to_le16(temp); | |
1860 | } | |
1861 | ||
1862 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) | |
1863 | ||
1864 | static int check_reset_complete(struct isp1760_hcd *priv, int index, | |
1865 | u32 __iomem *status_reg, int port_status) | |
1866 | { | |
1867 | if (!(port_status & PORT_CONNECT)) | |
1868 | return port_status; | |
1869 | ||
1870 | /* if reset finished and it's still not enabled -- handoff */ | |
1871 | if (!(port_status & PORT_PE)) { | |
1872 | ||
1873 | printk(KERN_ERR "port %d full speed --> companion\n", | |
1874 | index + 1); | |
1875 | ||
1876 | port_status |= PORT_OWNER; | |
1877 | port_status &= ~PORT_RWC_BITS; | |
1878 | isp1760_writel(port_status, status_reg); | |
1879 | ||
1880 | } else | |
1881 | printk(KERN_ERR "port %d high speed\n", index + 1); | |
1882 | ||
1883 | return port_status; | |
1884 | } | |
1885 | ||
1886 | static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |
1887 | u16 wValue, u16 wIndex, char *buf, u16 wLength) | |
1888 | { | |
1889 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1890 | int ports = HCS_N_PORTS(priv->hcs_params); | |
1891 | u32 __iomem *status_reg = hcd->regs + HC_PORTSC1; | |
1892 | u32 temp, status; | |
1893 | unsigned long flags; | |
1894 | int retval = 0; | |
1895 | unsigned selector; | |
1896 | ||
1897 | /* | |
1898 | * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. | |
1899 | * HCS_INDICATOR may say we can change LEDs to off/amber/green. | |
1900 | * (track current state ourselves) ... blink for diagnostics, | |
1901 | * power, "this is the one", etc. EHCI spec supports this. | |
1902 | */ | |
1903 | ||
1904 | spin_lock_irqsave(&priv->lock, flags); | |
1905 | switch (typeReq) { | |
1906 | case ClearHubFeature: | |
1907 | switch (wValue) { | |
1908 | case C_HUB_LOCAL_POWER: | |
1909 | case C_HUB_OVER_CURRENT: | |
1910 | /* no hub-wide feature/status flags */ | |
1911 | break; | |
1912 | default: | |
1913 | goto error; | |
1914 | } | |
1915 | break; | |
1916 | case ClearPortFeature: | |
1917 | if (!wIndex || wIndex > ports) | |
1918 | goto error; | |
1919 | wIndex--; | |
1920 | temp = isp1760_readl(status_reg); | |
1921 | ||
1922 | /* | |
1923 | * Even if OWNER is set, so the port is owned by the | |
1924 | * companion controller, khubd needs to be able to clear | |
1925 | * the port-change status bits (especially | |
1926 | * USB_PORT_FEAT_C_CONNECTION). | |
1927 | */ | |
1928 | ||
1929 | switch (wValue) { | |
1930 | case USB_PORT_FEAT_ENABLE: | |
1931 | isp1760_writel(temp & ~PORT_PE, status_reg); | |
1932 | break; | |
1933 | case USB_PORT_FEAT_C_ENABLE: | |
1934 | /* XXX error? */ | |
1935 | break; | |
1936 | case USB_PORT_FEAT_SUSPEND: | |
1937 | if (temp & PORT_RESET) | |
1938 | goto error; | |
1939 | ||
1940 | if (temp & PORT_SUSPEND) { | |
1941 | if ((temp & PORT_PE) == 0) | |
1942 | goto error; | |
1943 | /* resume signaling for 20 msec */ | |
1944 | temp &= ~(PORT_RWC_BITS); | |
1945 | isp1760_writel(temp | PORT_RESUME, | |
1946 | status_reg); | |
1947 | priv->reset_done = jiffies + | |
1948 | msecs_to_jiffies(20); | |
1949 | } | |
1950 | break; | |
1951 | case USB_PORT_FEAT_C_SUSPEND: | |
1952 | /* we auto-clear this feature */ | |
1953 | break; | |
1954 | case USB_PORT_FEAT_POWER: | |
1955 | if (HCS_PPC(priv->hcs_params)) | |
1956 | isp1760_writel(temp & ~PORT_POWER, status_reg); | |
1957 | break; | |
1958 | case USB_PORT_FEAT_C_CONNECTION: | |
1959 | isp1760_writel(temp | PORT_CSC, | |
1960 | status_reg); | |
1961 | break; | |
1962 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
1963 | /* XXX error ?*/ | |
1964 | break; | |
1965 | case USB_PORT_FEAT_C_RESET: | |
1966 | /* GetPortStatus clears reset */ | |
1967 | break; | |
1968 | default: | |
1969 | goto error; | |
1970 | } | |
1971 | isp1760_readl(hcd->regs + HC_USBCMD); | |
1972 | break; | |
1973 | case GetHubDescriptor: | |
1974 | isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) | |
1975 | buf); | |
1976 | break; | |
1977 | case GetHubStatus: | |
1978 | /* no hub-wide feature/status flags */ | |
1979 | memset(buf, 0, 4); | |
1980 | break; | |
1981 | case GetPortStatus: | |
1982 | if (!wIndex || wIndex > ports) | |
1983 | goto error; | |
1984 | wIndex--; | |
1985 | status = 0; | |
1986 | temp = isp1760_readl(status_reg); | |
1987 | ||
1988 | /* wPortChange bits */ | |
1989 | if (temp & PORT_CSC) | |
1990 | status |= 1 << USB_PORT_FEAT_C_CONNECTION; | |
1991 | ||
1992 | ||
1993 | /* whoever resumes must GetPortStatus to complete it!! */ | |
1994 | if (temp & PORT_RESUME) { | |
1995 | printk(KERN_ERR "Port resume should be skipped.\n"); | |
1996 | ||
1997 | /* Remote Wakeup received? */ | |
1998 | if (!priv->reset_done) { | |
1999 | /* resume signaling for 20 msec */ | |
2000 | priv->reset_done = jiffies | |
2001 | + msecs_to_jiffies(20); | |
2002 | /* check the port again */ | |
2003 | mod_timer(&priv_to_hcd(priv)->rh_timer, | |
2004 | priv->reset_done); | |
2005 | } | |
2006 | ||
2007 | /* resume completed? */ | |
2008 | else if (time_after_eq(jiffies, | |
2009 | priv->reset_done)) { | |
2010 | status |= 1 << USB_PORT_FEAT_C_SUSPEND; | |
2011 | priv->reset_done = 0; | |
2012 | ||
2013 | /* stop resume signaling */ | |
2014 | temp = isp1760_readl(status_reg); | |
2015 | isp1760_writel( | |
2016 | temp & ~(PORT_RWC_BITS | PORT_RESUME), | |
2017 | status_reg); | |
2018 | retval = handshake(priv, status_reg, | |
2019 | PORT_RESUME, 0, 2000 /* 2msec */); | |
2020 | if (retval != 0) { | |
2021 | isp1760_err(priv, | |
2022 | "port %d resume error %d\n", | |
2023 | wIndex + 1, retval); | |
2024 | goto error; | |
2025 | } | |
2026 | temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); | |
2027 | } | |
2028 | } | |
2029 | ||
2030 | /* whoever resets must GetPortStatus to complete it!! */ | |
2031 | if ((temp & PORT_RESET) | |
2032 | && time_after_eq(jiffies, | |
2033 | priv->reset_done)) { | |
2034 | status |= 1 << USB_PORT_FEAT_C_RESET; | |
2035 | priv->reset_done = 0; | |
2036 | ||
2037 | /* force reset to complete */ | |
2038 | isp1760_writel(temp & ~PORT_RESET, | |
2039 | status_reg); | |
2040 | /* REVISIT: some hardware needs 550+ usec to clear | |
2041 | * this bit; seems too long to spin routinely... | |
2042 | */ | |
2043 | retval = handshake(priv, status_reg, | |
2044 | PORT_RESET, 0, 750); | |
2045 | if (retval != 0) { | |
2046 | isp1760_err(priv, "port %d reset error %d\n", | |
2047 | wIndex + 1, retval); | |
2048 | goto error; | |
2049 | } | |
2050 | ||
2051 | /* see what we found out */ | |
2052 | temp = check_reset_complete(priv, wIndex, status_reg, | |
2053 | isp1760_readl(status_reg)); | |
2054 | } | |
2055 | /* | |
2056 | * Even if OWNER is set, there's no harm letting khubd | |
2057 | * see the wPortStatus values (they should all be 0 except | |
2058 | * for PORT_POWER anyway). | |
2059 | */ | |
2060 | ||
2061 | if (temp & PORT_OWNER) | |
2062 | printk(KERN_ERR "Warning: PORT_OWNER is set\n"); | |
2063 | ||
2064 | if (temp & PORT_CONNECT) { | |
2065 | status |= 1 << USB_PORT_FEAT_CONNECTION; | |
2066 | /* status may be from integrated TT */ | |
2067 | status |= ehci_port_speed(priv, temp); | |
2068 | } | |
2069 | if (temp & PORT_PE) | |
2070 | status |= 1 << USB_PORT_FEAT_ENABLE; | |
2071 | if (temp & (PORT_SUSPEND|PORT_RESUME)) | |
2072 | status |= 1 << USB_PORT_FEAT_SUSPEND; | |
2073 | if (temp & PORT_RESET) | |
2074 | status |= 1 << USB_PORT_FEAT_RESET; | |
2075 | if (temp & PORT_POWER) | |
2076 | status |= 1 << USB_PORT_FEAT_POWER; | |
2077 | ||
2078 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); | |
2079 | break; | |
2080 | case SetHubFeature: | |
2081 | switch (wValue) { | |
2082 | case C_HUB_LOCAL_POWER: | |
2083 | case C_HUB_OVER_CURRENT: | |
2084 | /* no hub-wide feature/status flags */ | |
2085 | break; | |
2086 | default: | |
2087 | goto error; | |
2088 | } | |
2089 | break; | |
2090 | case SetPortFeature: | |
2091 | selector = wIndex >> 8; | |
2092 | wIndex &= 0xff; | |
2093 | if (!wIndex || wIndex > ports) | |
2094 | goto error; | |
2095 | wIndex--; | |
2096 | temp = isp1760_readl(status_reg); | |
2097 | if (temp & PORT_OWNER) | |
2098 | break; | |
2099 | ||
2100 | /* temp &= ~PORT_RWC_BITS; */ | |
2101 | switch (wValue) { | |
2102 | case USB_PORT_FEAT_ENABLE: | |
2103 | isp1760_writel(temp | PORT_PE, status_reg); | |
2104 | break; | |
2105 | ||
2106 | case USB_PORT_FEAT_SUSPEND: | |
2107 | if ((temp & PORT_PE) == 0 | |
2108 | || (temp & PORT_RESET) != 0) | |
2109 | goto error; | |
2110 | ||
2111 | isp1760_writel(temp | PORT_SUSPEND, status_reg); | |
2112 | break; | |
2113 | case USB_PORT_FEAT_POWER: | |
2114 | if (HCS_PPC(priv->hcs_params)) | |
2115 | isp1760_writel(temp | PORT_POWER, | |
2116 | status_reg); | |
2117 | break; | |
2118 | case USB_PORT_FEAT_RESET: | |
2119 | if (temp & PORT_RESUME) | |
2120 | goto error; | |
2121 | /* line status bits may report this as low speed, | |
2122 | * which can be fine if this root hub has a | |
2123 | * transaction translator built in. | |
2124 | */ | |
2125 | if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT | |
2126 | && PORT_USB11(temp)) { | |
2127 | temp |= PORT_OWNER; | |
2128 | } else { | |
2129 | temp |= PORT_RESET; | |
2130 | temp &= ~PORT_PE; | |
2131 | ||
2132 | /* | |
2133 | * caller must wait, then call GetPortStatus | |
2134 | * usb 2.0 spec says 50 ms resets on root | |
2135 | */ | |
2136 | priv->reset_done = jiffies + | |
2137 | msecs_to_jiffies(50); | |
2138 | } | |
2139 | isp1760_writel(temp, status_reg); | |
2140 | break; | |
2141 | default: | |
2142 | goto error; | |
2143 | } | |
2144 | isp1760_readl(hcd->regs + HC_USBCMD); | |
2145 | break; | |
2146 | ||
2147 | default: | |
2148 | error: | |
2149 | /* "stall" on error */ | |
2150 | retval = -EPIPE; | |
2151 | } | |
2152 | spin_unlock_irqrestore(&priv->lock, flags); | |
2153 | return retval; | |
2154 | } | |
2155 | ||
2156 | static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd, | |
2157 | struct usb_host_endpoint *ep) | |
2158 | { | |
2159 | struct isp1760_hcd *priv = hcd_to_priv(usb_hcd); | |
2160 | struct isp1760_qh *qh; | |
2161 | struct isp1760_qtd *qtd; | |
d249afdd | 2162 | unsigned long flags; |
db11e47d SS |
2163 | |
2164 | spin_lock_irqsave(&priv->lock, flags); | |
2165 | qh = ep->hcpriv; | |
2166 | if (!qh) | |
2167 | goto out; | |
2168 | ||
2169 | ep->hcpriv = NULL; | |
2170 | do { | |
2171 | /* more than entry might get removed */ | |
2172 | if (list_empty(&qh->qtd_list)) | |
2173 | break; | |
2174 | ||
2175 | qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd, | |
2176 | qtd_list); | |
2177 | ||
2178 | if (qtd->status & URB_ENQUEUED) { | |
2179 | ||
2180 | spin_unlock_irqrestore(&priv->lock, flags); | |
2181 | isp1760_urb_dequeue(usb_hcd, qtd->urb, -ECONNRESET); | |
2182 | spin_lock_irqsave(&priv->lock, flags); | |
2183 | } else { | |
2184 | struct urb *urb; | |
2185 | ||
2186 | urb = qtd->urb; | |
2187 | clean_up_qtdlist(qtd); | |
2188 | isp1760_urb_done(priv, urb, -ECONNRESET); | |
2189 | } | |
2190 | } while (1); | |
2191 | ||
2192 | qh_destroy(qh); | |
2193 | /* remove requests and leak them. | |
2194 | * ATL are pretty fast done, INT could take a while... | |
2195 | * The latter shoule be removed | |
2196 | */ | |
2197 | out: | |
2198 | spin_unlock_irqrestore(&priv->lock, flags); | |
2199 | } | |
2200 | ||
2201 | static int isp1760_get_frame(struct usb_hcd *hcd) | |
2202 | { | |
2203 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
2204 | u32 fr; | |
2205 | ||
2206 | fr = isp1760_readl(hcd->regs + HC_FRINDEX); | |
2207 | return (fr >> 3) % priv->periodic_size; | |
2208 | } | |
2209 | ||
2210 | static void isp1760_stop(struct usb_hcd *hcd) | |
2211 | { | |
2212 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
3faefc88 | 2213 | u32 temp; |
db11e47d SS |
2214 | |
2215 | isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1, | |
2216 | NULL, 0); | |
2217 | mdelay(20); | |
2218 | ||
2219 | spin_lock_irq(&priv->lock); | |
2220 | ehci_reset(priv); | |
2221 | /* Disable IRQ */ | |
3faefc88 NC |
2222 | temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); |
2223 | isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); | |
db11e47d SS |
2224 | spin_unlock_irq(&priv->lock); |
2225 | ||
2226 | isp1760_writel(0, hcd->regs + HC_CONFIGFLAG); | |
2227 | } | |
2228 | ||
2229 | static void isp1760_shutdown(struct usb_hcd *hcd) | |
2230 | { | |
3faefc88 | 2231 | u32 command, temp; |
db11e47d SS |
2232 | |
2233 | isp1760_stop(hcd); | |
3faefc88 NC |
2234 | temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL); |
2235 | isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL); | |
db11e47d SS |
2236 | |
2237 | command = isp1760_readl(hcd->regs + HC_USBCMD); | |
2238 | command &= ~CMD_RUN; | |
2239 | isp1760_writel(command, hcd->regs + HC_USBCMD); | |
2240 | } | |
2241 | ||
2242 | static const struct hc_driver isp1760_hc_driver = { | |
2243 | .description = "isp1760-hcd", | |
2244 | .product_desc = "NXP ISP1760 USB Host Controller", | |
2245 | .hcd_priv_size = sizeof(struct isp1760_hcd), | |
2246 | .irq = isp1760_irq, | |
2247 | .flags = HCD_MEMORY | HCD_USB2, | |
2248 | .reset = isp1760_hc_setup, | |
2249 | .start = isp1760_run, | |
2250 | .stop = isp1760_stop, | |
2251 | .shutdown = isp1760_shutdown, | |
2252 | .urb_enqueue = isp1760_urb_enqueue, | |
2253 | .urb_dequeue = isp1760_urb_dequeue, | |
2254 | .endpoint_disable = isp1760_endpoint_disable, | |
2255 | .get_frame_number = isp1760_get_frame, | |
2256 | .hub_status_data = isp1760_hub_status_data, | |
2257 | .hub_control = isp1760_hub_control, | |
2258 | }; | |
2259 | ||
2260 | int __init init_kmem_once(void) | |
2261 | { | |
2262 | qtd_cachep = kmem_cache_create("isp1760_qtd", | |
2263 | sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | | |
2264 | SLAB_MEM_SPREAD, NULL); | |
2265 | ||
2266 | if (!qtd_cachep) | |
2267 | return -ENOMEM; | |
2268 | ||
2269 | qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), | |
2270 | 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); | |
2271 | ||
2272 | if (!qh_cachep) { | |
2273 | kmem_cache_destroy(qtd_cachep); | |
2274 | return -ENOMEM; | |
2275 | } | |
2276 | ||
2277 | return 0; | |
2278 | } | |
2279 | ||
2280 | void deinit_kmem_cache(void) | |
2281 | { | |
2282 | kmem_cache_destroy(qtd_cachep); | |
2283 | kmem_cache_destroy(qh_cachep); | |
2284 | } | |
2285 | ||
f9031f2c CM |
2286 | struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, |
2287 | int irq, unsigned long irqflags, | |
2288 | struct device *dev, const char *busname, | |
2289 | unsigned int devflags) | |
db11e47d SS |
2290 | { |
2291 | struct usb_hcd *hcd; | |
2292 | struct isp1760_hcd *priv; | |
2293 | int ret; | |
2294 | ||
2295 | if (usb_disabled()) | |
2296 | return ERR_PTR(-ENODEV); | |
2297 | ||
2298 | /* prevent usb-core allocating DMA pages */ | |
2299 | dev->dma_mask = NULL; | |
2300 | ||
0031a06e | 2301 | hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev)); |
db11e47d SS |
2302 | if (!hcd) |
2303 | return ERR_PTR(-ENOMEM); | |
2304 | ||
2305 | priv = hcd_to_priv(hcd); | |
3faefc88 | 2306 | priv->devflags = devflags; |
db11e47d SS |
2307 | init_memory(priv); |
2308 | hcd->regs = ioremap(res_start, res_len); | |
2309 | if (!hcd->regs) { | |
2310 | ret = -EIO; | |
2311 | goto err_put; | |
2312 | } | |
2313 | ||
db11e47d SS |
2314 | hcd->irq = irq; |
2315 | hcd->rsrc_start = res_start; | |
2316 | hcd->rsrc_len = res_len; | |
2317 | ||
e6942d63 NC |
2318 | ret = usb_add_hcd(hcd, irq, irqflags); |
2319 | if (ret) | |
2320 | goto err_unmap; | |
2321 | ||
db11e47d SS |
2322 | return hcd; |
2323 | ||
2324 | err_unmap: | |
2325 | iounmap(hcd->regs); | |
2326 | ||
2327 | err_put: | |
2328 | usb_put_hcd(hcd); | |
2329 | ||
2330 | return ERR_PTR(ret); | |
2331 | } | |
2332 | ||
2333 | MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP"); | |
2334 | MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>"); | |
2335 | MODULE_LICENSE("GPL v2"); |