Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
d49d4317 | 2 | * Copyright (C) 2001-2004 by David Brownell |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | /* this file is part of ehci-hcd.c */ | |
20 | ||
21 | /*-------------------------------------------------------------------------*/ | |
22 | ||
23 | /* | |
24 | * EHCI hardware queue manipulation ... the core. QH/QTD manipulation. | |
25 | * | |
26 | * Control, bulk, and interrupt traffic all use "qh" lists. They list "qtd" | |
27 | * entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned | |
28 | * buffers needed for the larger number). We use one QH per endpoint, queue | |
29 | * multiple urbs (all three types) per endpoint. URBs may need several qtds. | |
30 | * | |
31 | * ISO traffic uses "ISO TD" (itd, and sitd) records, and (along with | |
32 | * interrupts) needs careful scheduling. Performance improvements can be | |
33 | * an ongoing challenge. That's in "ehci-sched.c". | |
53bd6a60 | 34 | * |
1da177e4 LT |
35 | * USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs, |
36 | * or otherwise through transaction translators (TTs) in USB 2.0 hubs using | |
37 | * (b) special fields in qh entries or (c) split iso entries. TTs will | |
38 | * buffer low/full speed data so the host collects it at high speed. | |
39 | */ | |
40 | ||
41 | /*-------------------------------------------------------------------------*/ | |
42 | ||
43 | /* fill a qtd, returning how much of the buffer we were able to queue up */ | |
44 | ||
45 | static int | |
6dbd682b SR |
46 | qtd_fill(struct ehci_hcd *ehci, struct ehci_qtd *qtd, dma_addr_t buf, |
47 | size_t len, int token, int maxpacket) | |
1da177e4 LT |
48 | { |
49 | int i, count; | |
50 | u64 addr = buf; | |
51 | ||
52 | /* one buffer entry per 4K ... first might be short or unaligned */ | |
6dbd682b SR |
53 | qtd->hw_buf[0] = cpu_to_hc32(ehci, (u32)addr); |
54 | qtd->hw_buf_hi[0] = cpu_to_hc32(ehci, (u32)(addr >> 32)); | |
1da177e4 LT |
55 | count = 0x1000 - (buf & 0x0fff); /* rest of that page */ |
56 | if (likely (len < count)) /* ... iff needed */ | |
57 | count = len; | |
58 | else { | |
59 | buf += 0x1000; | |
60 | buf &= ~0x0fff; | |
61 | ||
62 | /* per-qtd limit: from 16K to 20K (best alignment) */ | |
63 | for (i = 1; count < len && i < 5; i++) { | |
64 | addr = buf; | |
6dbd682b SR |
65 | qtd->hw_buf[i] = cpu_to_hc32(ehci, (u32)addr); |
66 | qtd->hw_buf_hi[i] = cpu_to_hc32(ehci, | |
67 | (u32)(addr >> 32)); | |
1da177e4 LT |
68 | buf += 0x1000; |
69 | if ((count + 0x1000) < len) | |
70 | count += 0x1000; | |
71 | else | |
72 | count = len; | |
73 | } | |
74 | ||
75 | /* short packets may only terminate transfers */ | |
76 | if (count != len) | |
77 | count -= (count % maxpacket); | |
78 | } | |
6dbd682b | 79 | qtd->hw_token = cpu_to_hc32(ehci, (count << 16) | token); |
1da177e4 LT |
80 | qtd->length = count; |
81 | ||
82 | return count; | |
83 | } | |
84 | ||
85 | /*-------------------------------------------------------------------------*/ | |
86 | ||
87 | static inline void | |
88 | qh_update (struct ehci_hcd *ehci, struct ehci_qh *qh, struct ehci_qtd *qtd) | |
89 | { | |
90 | /* writes to an active overlay are unsafe */ | |
91 | BUG_ON(qh->qh_state != QH_STATE_IDLE); | |
92 | ||
6dbd682b SR |
93 | qh->hw_qtd_next = QTD_NEXT(ehci, qtd->qtd_dma); |
94 | qh->hw_alt_next = EHCI_LIST_END(ehci); | |
1da177e4 | 95 | |
a455212d AS |
96 | /* Except for control endpoints, we make hardware maintain data |
97 | * toggle (like OHCI) ... here (re)initialize the toggle in the QH, | |
98 | * and set the pseudo-toggle in udev. Only usb_clear_halt() will | |
99 | * ever clear it. | |
100 | */ | |
101 | if (!(qh->hw_info1 & cpu_to_hc32(ehci, 1 << 14))) { | |
102 | unsigned is_out, epnum; | |
103 | ||
104 | is_out = !(qtd->hw_token & cpu_to_hc32(ehci, 1 << 8)); | |
105 | epnum = (hc32_to_cpup(ehci, &qh->hw_info1) >> 8) & 0x0f; | |
106 | if (unlikely (!usb_gettoggle (qh->dev, epnum, is_out))) { | |
107 | qh->hw_token &= ~cpu_to_hc32(ehci, QTD_TOGGLE); | |
108 | usb_settoggle (qh->dev, epnum, is_out, 1); | |
109 | } | |
110 | } | |
111 | ||
1da177e4 LT |
112 | /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */ |
113 | wmb (); | |
6dbd682b | 114 | qh->hw_token &= cpu_to_hc32(ehci, QTD_TOGGLE | QTD_STS_PING); |
1da177e4 LT |
115 | } |
116 | ||
117 | /* if it weren't for a common silicon quirk (writing the dummy into the qh | |
118 | * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault | |
119 | * recovery (including urb dequeue) would need software changes to a QH... | |
120 | */ | |
121 | static void | |
122 | qh_refresh (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
123 | { | |
124 | struct ehci_qtd *qtd; | |
125 | ||
126 | if (list_empty (&qh->qtd_list)) | |
127 | qtd = qh->dummy; | |
128 | else { | |
129 | qtd = list_entry (qh->qtd_list.next, | |
130 | struct ehci_qtd, qtd_list); | |
131 | /* first qtd may already be partially processed */ | |
6dbd682b | 132 | if (cpu_to_hc32(ehci, qtd->qtd_dma) == qh->hw_current) |
1da177e4 LT |
133 | qtd = NULL; |
134 | } | |
135 | ||
136 | if (qtd) | |
137 | qh_update (ehci, qh, qtd); | |
138 | } | |
139 | ||
140 | /*-------------------------------------------------------------------------*/ | |
141 | ||
914b7012 AS |
142 | static void qh_link_async(struct ehci_hcd *ehci, struct ehci_qh *qh); |
143 | ||
144 | static void ehci_clear_tt_buffer_complete(struct usb_hcd *hcd, | |
145 | struct usb_host_endpoint *ep) | |
146 | { | |
147 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
148 | struct ehci_qh *qh = ep->hcpriv; | |
149 | unsigned long flags; | |
150 | ||
151 | spin_lock_irqsave(&ehci->lock, flags); | |
152 | qh->clearing_tt = 0; | |
153 | if (qh->qh_state == QH_STATE_IDLE && !list_empty(&qh->qtd_list) | |
154 | && HC_IS_RUNNING(hcd->state)) | |
155 | qh_link_async(ehci, qh); | |
156 | spin_unlock_irqrestore(&ehci->lock, flags); | |
157 | } | |
158 | ||
159 | static void ehci_clear_tt_buffer(struct ehci_hcd *ehci, struct ehci_qh *qh, | |
160 | struct urb *urb, u32 token) | |
161 | { | |
162 | ||
163 | /* If an async split transaction gets an error or is unlinked, | |
164 | * the TT buffer may be left in an indeterminate state. We | |
165 | * have to clear the TT buffer. | |
166 | * | |
167 | * Note: this routine is never called for Isochronous transfers. | |
168 | */ | |
169 | if (urb->dev->tt && !usb_pipeint(urb->pipe) && !qh->clearing_tt) { | |
170 | #ifdef DEBUG | |
171 | struct usb_device *tt = urb->dev->tt->hub; | |
172 | dev_dbg(&tt->dev, | |
173 | "clear tt buffer port %d, a%d ep%d t%08x\n", | |
174 | urb->dev->ttport, urb->dev->devnum, | |
175 | usb_pipeendpoint(urb->pipe), token); | |
176 | #endif /* DEBUG */ | |
177 | if (!ehci_is_TDI(ehci) | |
178 | || urb->dev->tt->hub != | |
179 | ehci_to_hcd(ehci)->self.root_hub) { | |
180 | if (usb_hub_clear_tt_buffer(urb) == 0) | |
181 | qh->clearing_tt = 1; | |
182 | } else { | |
183 | ||
184 | /* REVISIT ARC-derived cores don't clear the root | |
185 | * hub TT buffer in this way... | |
186 | */ | |
187 | } | |
188 | } | |
189 | } | |
190 | ||
14c04c0f | 191 | static int qtd_copy_status ( |
1da177e4 LT |
192 | struct ehci_hcd *ehci, |
193 | struct urb *urb, | |
194 | size_t length, | |
195 | u32 token | |
196 | ) | |
197 | { | |
14c04c0f AS |
198 | int status = -EINPROGRESS; |
199 | ||
1da177e4 LT |
200 | /* count IN/OUT bytes, not SETUP (even short packets) */ |
201 | if (likely (QTD_PID (token) != 2)) | |
202 | urb->actual_length += length - QTD_LENGTH (token); | |
203 | ||
204 | /* don't modify error codes */ | |
eb231054 | 205 | if (unlikely(urb->unlinked)) |
14c04c0f | 206 | return status; |
1da177e4 LT |
207 | |
208 | /* force cleanup after short read; not always an error */ | |
209 | if (unlikely (IS_SHORT_READ (token))) | |
14c04c0f | 210 | status = -EREMOTEIO; |
1da177e4 LT |
211 | |
212 | /* serious "can't proceed" faults reported by the hardware */ | |
213 | if (token & QTD_STS_HALT) { | |
214 | if (token & QTD_STS_BABBLE) { | |
215 | /* FIXME "must" disable babbling device's port too */ | |
14c04c0f | 216 | status = -EOVERFLOW; |
ba516de3 AS |
217 | /* CERR nonzero + halt --> stall */ |
218 | } else if (QTD_CERR(token)) { | |
219 | status = -EPIPE; | |
220 | ||
221 | /* In theory, more than one of the following bits can be set | |
222 | * since they are sticky and the transaction is retried. | |
223 | * Which to test first is rather arbitrary. | |
224 | */ | |
1da177e4 LT |
225 | } else if (token & QTD_STS_MMF) { |
226 | /* fs/ls interrupt xfer missed the complete-split */ | |
14c04c0f | 227 | status = -EPROTO; |
1da177e4 | 228 | } else if (token & QTD_STS_DBE) { |
14c04c0f | 229 | status = (QTD_PID (token) == 1) /* IN ? */ |
1da177e4 LT |
230 | ? -ENOSR /* hc couldn't read data */ |
231 | : -ECOMM; /* hc couldn't write data */ | |
232 | } else if (token & QTD_STS_XACT) { | |
ba516de3 AS |
233 | /* timeout, bad CRC, wrong PID, etc */ |
234 | ehci_dbg(ehci, "devpath %s ep%d%s 3strikes\n", | |
235 | urb->dev->devpath, | |
236 | usb_pipeendpoint(urb->pipe), | |
237 | usb_pipein(urb->pipe) ? "in" : "out"); | |
14c04c0f | 238 | status = -EPROTO; |
ba516de3 AS |
239 | } else { /* unknown */ |
240 | status = -EPROTO; | |
241 | } | |
1da177e4 LT |
242 | |
243 | ehci_vdbg (ehci, | |
244 | "dev%d ep%d%s qtd token %08x --> status %d\n", | |
245 | usb_pipedevice (urb->pipe), | |
246 | usb_pipeendpoint (urb->pipe), | |
247 | usb_pipein (urb->pipe) ? "in" : "out", | |
14c04c0f | 248 | token, status); |
1da177e4 | 249 | } |
14c04c0f AS |
250 | |
251 | return status; | |
1da177e4 LT |
252 | } |
253 | ||
254 | static void | |
14c04c0f | 255 | ehci_urb_done(struct ehci_hcd *ehci, struct urb *urb, int status) |
1da177e4 LT |
256 | __releases(ehci->lock) |
257 | __acquires(ehci->lock) | |
258 | { | |
259 | if (likely (urb->hcpriv != NULL)) { | |
260 | struct ehci_qh *qh = (struct ehci_qh *) urb->hcpriv; | |
261 | ||
262 | /* S-mask in a QH means it's an interrupt urb */ | |
6dbd682b | 263 | if ((qh->hw_info2 & cpu_to_hc32(ehci, QH_SMASK)) != 0) { |
1da177e4 LT |
264 | |
265 | /* ... update hc-wide periodic stats (for usbfs) */ | |
266 | ehci_to_hcd(ehci)->self.bandwidth_int_reqs--; | |
267 | } | |
268 | qh_put (qh); | |
269 | } | |
270 | ||
eb231054 AS |
271 | if (unlikely(urb->unlinked)) { |
272 | COUNT(ehci->stats.unlink); | |
273 | } else { | |
4f667627 DB |
274 | /* report non-error and short read status as zero */ |
275 | if (status == -EINPROGRESS || status == -EREMOTEIO) | |
14c04c0f | 276 | status = 0; |
eb231054 | 277 | COUNT(ehci->stats.complete); |
1da177e4 | 278 | } |
1da177e4 LT |
279 | |
280 | #ifdef EHCI_URB_TRACE | |
281 | ehci_dbg (ehci, | |
282 | "%s %s urb %p ep%d%s status %d len %d/%d\n", | |
441b62c1 | 283 | __func__, urb->dev->devpath, urb, |
1da177e4 LT |
284 | usb_pipeendpoint (urb->pipe), |
285 | usb_pipein (urb->pipe) ? "in" : "out", | |
14c04c0f | 286 | status, |
1da177e4 LT |
287 | urb->actual_length, urb->transfer_buffer_length); |
288 | #endif | |
289 | ||
290 | /* complete() can reenter this HCD */ | |
e9df41c5 | 291 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); |
1da177e4 | 292 | spin_unlock (&ehci->lock); |
4a00027d | 293 | usb_hcd_giveback_urb(ehci_to_hcd(ehci), urb, status); |
1da177e4 LT |
294 | spin_lock (&ehci->lock); |
295 | } | |
296 | ||
297 | static void start_unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh); | |
298 | static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh); | |
299 | ||
300 | static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh); | |
301 | static int qh_schedule (struct ehci_hcd *ehci, struct ehci_qh *qh); | |
302 | ||
303 | /* | |
304 | * Process and free completed qtds for a qh, returning URBs to drivers. | |
305 | * Chases up to qh->hw_current. Returns number of completions called, | |
306 | * indicating how much "real" work we did. | |
307 | */ | |
1da177e4 | 308 | static unsigned |
7d12e780 | 309 | qh_completions (struct ehci_hcd *ehci, struct ehci_qh *qh) |
1da177e4 LT |
310 | { |
311 | struct ehci_qtd *last = NULL, *end = qh->dummy; | |
312 | struct list_head *entry, *tmp; | |
14c04c0f | 313 | int last_status = -EINPROGRESS; |
1da177e4 LT |
314 | int stopped; |
315 | unsigned count = 0; | |
1da177e4 | 316 | u8 state; |
fd05e720 | 317 | __le32 halt = HALT_BIT(ehci); |
1da177e4 LT |
318 | |
319 | if (unlikely (list_empty (&qh->qtd_list))) | |
320 | return count; | |
321 | ||
322 | /* completions (or tasks on other cpus) must never clobber HALT | |
323 | * till we've gone through and cleaned everything up, even when | |
324 | * they add urbs to this qh's queue or mark them for unlinking. | |
325 | * | |
326 | * NOTE: unlinking expects to be done in queue order. | |
327 | */ | |
328 | state = qh->qh_state; | |
329 | qh->qh_state = QH_STATE_COMPLETING; | |
330 | stopped = (state == QH_STATE_IDLE); | |
331 | ||
332 | /* remove de-activated QTDs from front of queue. | |
333 | * after faults (including short reads), cleanup this urb | |
334 | * then let the queue advance. | |
335 | * if queue is stopped, handles unlinks. | |
336 | */ | |
337 | list_for_each_safe (entry, tmp, &qh->qtd_list) { | |
338 | struct ehci_qtd *qtd; | |
339 | struct urb *urb; | |
340 | u32 token = 0; | |
341 | ||
342 | qtd = list_entry (entry, struct ehci_qtd, qtd_list); | |
343 | urb = qtd->urb; | |
344 | ||
345 | /* clean up any state from previous QTD ...*/ | |
346 | if (last) { | |
347 | if (likely (last->urb != urb)) { | |
14c04c0f | 348 | ehci_urb_done(ehci, last->urb, last_status); |
1da177e4 | 349 | count++; |
b5f7a0ec | 350 | last_status = -EINPROGRESS; |
1da177e4 LT |
351 | } |
352 | ehci_qtd_free (ehci, last); | |
353 | last = NULL; | |
354 | } | |
355 | ||
356 | /* ignore urbs submitted during completions we reported */ | |
357 | if (qtd == end) | |
358 | break; | |
359 | ||
360 | /* hardware copies qtd out of qh overlay */ | |
361 | rmb (); | |
6dbd682b | 362 | token = hc32_to_cpu(ehci, qtd->hw_token); |
1da177e4 LT |
363 | |
364 | /* always clean up qtds the hc de-activated */ | |
a2c2706e | 365 | retry_xacterr: |
1da177e4 LT |
366 | if ((token & QTD_STS_ACTIVE) == 0) { |
367 | ||
a082b5c7 DB |
368 | /* on STALL, error, and short reads this urb must |
369 | * complete and all its qtds must be recycled. | |
370 | */ | |
1da177e4 | 371 | if ((token & QTD_STS_HALT) != 0) { |
a2c2706e AS |
372 | |
373 | /* retry transaction errors until we | |
374 | * reach the software xacterr limit | |
375 | */ | |
376 | if ((token & QTD_STS_XACT) && | |
377 | QTD_CERR(token) == 0 && | |
378 | --qh->xacterrs > 0 && | |
379 | !urb->unlinked) { | |
380 | ehci_dbg(ehci, | |
d0626808 | 381 | "detected XactErr len %zu/%zu retry %d\n", |
a2c2706e AS |
382 | qtd->length - QTD_LENGTH(token), qtd->length, |
383 | QH_XACTERR_MAX - qh->xacterrs); | |
384 | ||
385 | /* reset the token in the qtd and the | |
386 | * qh overlay (which still contains | |
387 | * the qtd) so that we pick up from | |
388 | * where we left off | |
389 | */ | |
390 | token &= ~QTD_STS_HALT; | |
391 | token |= QTD_STS_ACTIVE | | |
392 | (EHCI_TUNE_CERR << 10); | |
393 | qtd->hw_token = cpu_to_hc32(ehci, | |
394 | token); | |
395 | wmb(); | |
396 | qh->hw_token = cpu_to_hc32(ehci, token); | |
397 | goto retry_xacterr; | |
398 | } | |
1da177e4 LT |
399 | stopped = 1; |
400 | ||
401 | /* magic dummy for some short reads; qh won't advance. | |
402 | * that silicon quirk can kick in with this dummy too. | |
a082b5c7 DB |
403 | * |
404 | * other short reads won't stop the queue, including | |
405 | * control transfers (status stage handles that) or | |
406 | * most other single-qtd reads ... the queue stops if | |
407 | * URB_SHORT_NOT_OK was set so the driver submitting | |
408 | * the urbs could clean it up. | |
1da177e4 LT |
409 | */ |
410 | } else if (IS_SHORT_READ (token) | |
6dbd682b SR |
411 | && !(qtd->hw_alt_next |
412 | & EHCI_LIST_END(ehci))) { | |
1da177e4 LT |
413 | stopped = 1; |
414 | goto halt; | |
415 | } | |
416 | ||
417 | /* stop scanning when we reach qtds the hc is using */ | |
418 | } else if (likely (!stopped | |
419 | && HC_IS_RUNNING (ehci_to_hcd(ehci)->state))) { | |
420 | break; | |
421 | ||
a082b5c7 | 422 | /* scan the whole queue for unlinks whenever it stops */ |
1da177e4 LT |
423 | } else { |
424 | stopped = 1; | |
425 | ||
a082b5c7 DB |
426 | /* cancel everything if we halt, suspend, etc */ |
427 | if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) | |
14c04c0f | 428 | last_status = -ESHUTDOWN; |
1da177e4 | 429 | |
a082b5c7 DB |
430 | /* this qtd is active; skip it unless a previous qtd |
431 | * for its urb faulted, or its urb was canceled. | |
1da177e4 | 432 | */ |
a082b5c7 | 433 | else if (last_status == -EINPROGRESS && !urb->unlinked) |
1da177e4 | 434 | continue; |
53bd6a60 | 435 | |
a082b5c7 | 436 | /* qh unlinked; token in overlay may be most current */ |
1da177e4 | 437 | if (state == QH_STATE_IDLE |
6dbd682b | 438 | && cpu_to_hc32(ehci, qtd->qtd_dma) |
914b7012 | 439 | == qh->hw_current) { |
6dbd682b | 440 | token = hc32_to_cpu(ehci, qh->hw_token); |
1da177e4 | 441 | |
914b7012 AS |
442 | /* An unlink may leave an incomplete |
443 | * async transaction in the TT buffer. | |
444 | * We have to clear it. | |
445 | */ | |
446 | ehci_clear_tt_buffer(ehci, qh, urb, token); | |
447 | } | |
448 | ||
1da177e4 LT |
449 | /* force halt for unlinked or blocked qh, so we'll |
450 | * patch the qh later and so that completions can't | |
451 | * activate it while we "know" it's stopped. | |
452 | */ | |
6dbd682b | 453 | if ((halt & qh->hw_token) == 0) { |
1da177e4 | 454 | halt: |
6dbd682b | 455 | qh->hw_token |= halt; |
1da177e4 LT |
456 | wmb (); |
457 | } | |
458 | } | |
53bd6a60 | 459 | |
4f667627 DB |
460 | /* unless we already know the urb's status, collect qtd status |
461 | * and update count of bytes transferred. in common short read | |
462 | * cases with only one data qtd (including control transfers), | |
463 | * queue processing won't halt. but with two or more qtds (for | |
464 | * example, with a 32 KB transfer), when the first qtd gets a | |
465 | * short read the second must be removed by hand. | |
466 | */ | |
467 | if (last_status == -EINPROGRESS) { | |
468 | last_status = qtd_copy_status(ehci, urb, | |
469 | qtd->length, token); | |
470 | if (last_status == -EREMOTEIO | |
471 | && (qtd->hw_alt_next | |
472 | & EHCI_LIST_END(ehci))) | |
473 | last_status = -EINPROGRESS; | |
914b7012 AS |
474 | |
475 | /* As part of low/full-speed endpoint-halt processing | |
476 | * we must clear the TT buffer (11.17.5). | |
477 | */ | |
478 | if (unlikely(last_status != -EINPROGRESS && | |
479 | last_status != -EREMOTEIO)) | |
480 | ehci_clear_tt_buffer(ehci, qh, urb, token); | |
b0d9efba | 481 | } |
1da177e4 | 482 | |
a082b5c7 DB |
483 | /* if we're removing something not at the queue head, |
484 | * patch the hardware queue pointer. | |
485 | */ | |
1da177e4 LT |
486 | if (stopped && qtd->qtd_list.prev != &qh->qtd_list) { |
487 | last = list_entry (qtd->qtd_list.prev, | |
488 | struct ehci_qtd, qtd_list); | |
489 | last->hw_next = qtd->hw_next; | |
490 | } | |
a082b5c7 DB |
491 | |
492 | /* remove qtd; it's recycled after possible urb completion */ | |
1da177e4 LT |
493 | list_del (&qtd->qtd_list); |
494 | last = qtd; | |
a2c2706e AS |
495 | |
496 | /* reinit the xacterr counter for the next qtd */ | |
497 | qh->xacterrs = QH_XACTERR_MAX; | |
1da177e4 LT |
498 | } |
499 | ||
500 | /* last urb's completion might still need calling */ | |
501 | if (likely (last != NULL)) { | |
14c04c0f | 502 | ehci_urb_done(ehci, last->urb, last_status); |
1da177e4 LT |
503 | count++; |
504 | ehci_qtd_free (ehci, last); | |
505 | } | |
506 | ||
507 | /* restore original state; caller must unlink or relink */ | |
508 | qh->qh_state = state; | |
509 | ||
510 | /* be sure the hardware's done with the qh before refreshing | |
511 | * it after fault cleanup, or recovering from silicon wrongly | |
512 | * overlaying the dummy qtd (which reduces DMA chatter). | |
513 | */ | |
6dbd682b | 514 | if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END(ehci)) { |
1da177e4 LT |
515 | switch (state) { |
516 | case QH_STATE_IDLE: | |
517 | qh_refresh(ehci, qh); | |
518 | break; | |
519 | case QH_STATE_LINKED: | |
a082b5c7 DB |
520 | /* We won't refresh a QH that's linked (after the HC |
521 | * stopped the queue). That avoids a race: | |
522 | * - HC reads first part of QH; | |
523 | * - CPU updates that first part and the token; | |
524 | * - HC reads rest of that QH, including token | |
525 | * Result: HC gets an inconsistent image, and then | |
526 | * DMAs to/from the wrong memory (corrupting it). | |
527 | * | |
528 | * That should be rare for interrupt transfers, | |
1da177e4 LT |
529 | * except maybe high bandwidth ... |
530 | */ | |
6dbd682b | 531 | if ((cpu_to_hc32(ehci, QH_SMASK) |
7dedacf4 | 532 | & qh->hw_info2) != 0) { |
1da177e4 LT |
533 | intr_deschedule (ehci, qh); |
534 | (void) qh_schedule (ehci, qh); | |
535 | } else | |
536 | unlink_async (ehci, qh); | |
537 | break; | |
538 | /* otherwise, unlink already started */ | |
539 | } | |
540 | } | |
541 | ||
542 | return count; | |
543 | } | |
544 | ||
545 | /*-------------------------------------------------------------------------*/ | |
546 | ||
547 | // high bandwidth multiplier, as encoded in highspeed endpoint descriptors | |
548 | #define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) | |
549 | // ... and packet size, for any kind of endpoint descriptor | |
550 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) | |
551 | ||
552 | /* | |
553 | * reverse of qh_urb_transaction: free a list of TDs. | |
554 | * used for cleanup after errors, before HC sees an URB's TDs. | |
555 | */ | |
556 | static void qtd_list_free ( | |
557 | struct ehci_hcd *ehci, | |
558 | struct urb *urb, | |
559 | struct list_head *qtd_list | |
560 | ) { | |
561 | struct list_head *entry, *temp; | |
562 | ||
563 | list_for_each_safe (entry, temp, qtd_list) { | |
564 | struct ehci_qtd *qtd; | |
565 | ||
566 | qtd = list_entry (entry, struct ehci_qtd, qtd_list); | |
567 | list_del (&qtd->qtd_list); | |
568 | ehci_qtd_free (ehci, qtd); | |
569 | } | |
570 | } | |
571 | ||
572 | /* | |
573 | * create a list of filled qtds for this URB; won't link into qh. | |
574 | */ | |
575 | static struct list_head * | |
576 | qh_urb_transaction ( | |
577 | struct ehci_hcd *ehci, | |
578 | struct urb *urb, | |
579 | struct list_head *head, | |
55016f10 | 580 | gfp_t flags |
1da177e4 LT |
581 | ) { |
582 | struct ehci_qtd *qtd, *qtd_prev; | |
583 | dma_addr_t buf; | |
584 | int len, maxpacket; | |
585 | int is_input; | |
586 | u32 token; | |
587 | ||
588 | /* | |
589 | * URBs map to sequences of QTDs: one logical transaction | |
590 | */ | |
591 | qtd = ehci_qtd_alloc (ehci, flags); | |
592 | if (unlikely (!qtd)) | |
593 | return NULL; | |
594 | list_add_tail (&qtd->qtd_list, head); | |
595 | qtd->urb = urb; | |
596 | ||
597 | token = QTD_STS_ACTIVE; | |
598 | token |= (EHCI_TUNE_CERR << 10); | |
599 | /* for split transactions, SplitXState initialized to zero */ | |
600 | ||
601 | len = urb->transfer_buffer_length; | |
602 | is_input = usb_pipein (urb->pipe); | |
603 | if (usb_pipecontrol (urb->pipe)) { | |
604 | /* SETUP pid */ | |
6dbd682b SR |
605 | qtd_fill(ehci, qtd, urb->setup_dma, |
606 | sizeof (struct usb_ctrlrequest), | |
607 | token | (2 /* "setup" */ << 8), 8); | |
1da177e4 LT |
608 | |
609 | /* ... and always at least one more pid */ | |
610 | token ^= QTD_TOGGLE; | |
611 | qtd_prev = qtd; | |
612 | qtd = ehci_qtd_alloc (ehci, flags); | |
613 | if (unlikely (!qtd)) | |
614 | goto cleanup; | |
615 | qtd->urb = urb; | |
6dbd682b | 616 | qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma); |
1da177e4 | 617 | list_add_tail (&qtd->qtd_list, head); |
6912354a AS |
618 | |
619 | /* for zero length DATA stages, STATUS is always IN */ | |
620 | if (len == 0) | |
621 | token |= (1 /* "in" */ << 8); | |
53bd6a60 | 622 | } |
1da177e4 LT |
623 | |
624 | /* | |
625 | * data transfer stage: buffer setup | |
626 | */ | |
6912354a | 627 | buf = urb->transfer_dma; |
1da177e4 | 628 | |
6912354a | 629 | if (is_input) |
1da177e4 LT |
630 | token |= (1 /* "in" */ << 8); |
631 | /* else it's already initted to "out" pid (0 << 8) */ | |
632 | ||
633 | maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input)); | |
634 | ||
635 | /* | |
636 | * buffer gets wrapped in one or more qtds; | |
637 | * last one may be "short" (including zero len) | |
638 | * and may serve as a control status ack | |
639 | */ | |
640 | for (;;) { | |
641 | int this_qtd_len; | |
642 | ||
6dbd682b | 643 | this_qtd_len = qtd_fill(ehci, qtd, buf, len, token, maxpacket); |
1da177e4 LT |
644 | len -= this_qtd_len; |
645 | buf += this_qtd_len; | |
a082b5c7 DB |
646 | |
647 | /* | |
648 | * short reads advance to a "magic" dummy instead of the next | |
649 | * qtd ... that forces the queue to stop, for manual cleanup. | |
650 | * (this will usually be overridden later.) | |
651 | */ | |
1da177e4 LT |
652 | if (is_input) |
653 | qtd->hw_alt_next = ehci->async->hw_alt_next; | |
654 | ||
655 | /* qh makes control packets use qtd toggle; maybe switch it */ | |
656 | if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0) | |
657 | token ^= QTD_TOGGLE; | |
658 | ||
659 | if (likely (len <= 0)) | |
660 | break; | |
661 | ||
662 | qtd_prev = qtd; | |
663 | qtd = ehci_qtd_alloc (ehci, flags); | |
664 | if (unlikely (!qtd)) | |
665 | goto cleanup; | |
666 | qtd->urb = urb; | |
6dbd682b | 667 | qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma); |
1da177e4 LT |
668 | list_add_tail (&qtd->qtd_list, head); |
669 | } | |
670 | ||
a082b5c7 DB |
671 | /* |
672 | * unless the caller requires manual cleanup after short reads, | |
673 | * have the alt_next mechanism keep the queue running after the | |
674 | * last data qtd (the only one, for control and most other cases). | |
1da177e4 LT |
675 | */ |
676 | if (likely ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0 | |
677 | || usb_pipecontrol (urb->pipe))) | |
6dbd682b | 678 | qtd->hw_alt_next = EHCI_LIST_END(ehci); |
1da177e4 LT |
679 | |
680 | /* | |
681 | * control requests may need a terminating data "status" ack; | |
682 | * bulk ones may need a terminating short packet (zero length). | |
683 | */ | |
6912354a | 684 | if (likely (urb->transfer_buffer_length != 0)) { |
1da177e4 LT |
685 | int one_more = 0; |
686 | ||
687 | if (usb_pipecontrol (urb->pipe)) { | |
688 | one_more = 1; | |
689 | token ^= 0x0100; /* "in" <--> "out" */ | |
690 | token |= QTD_TOGGLE; /* force DATA1 */ | |
691 | } else if (usb_pipebulk (urb->pipe) | |
692 | && (urb->transfer_flags & URB_ZERO_PACKET) | |
693 | && !(urb->transfer_buffer_length % maxpacket)) { | |
694 | one_more = 1; | |
695 | } | |
696 | if (one_more) { | |
697 | qtd_prev = qtd; | |
698 | qtd = ehci_qtd_alloc (ehci, flags); | |
699 | if (unlikely (!qtd)) | |
700 | goto cleanup; | |
701 | qtd->urb = urb; | |
6dbd682b | 702 | qtd_prev->hw_next = QTD_NEXT(ehci, qtd->qtd_dma); |
1da177e4 LT |
703 | list_add_tail (&qtd->qtd_list, head); |
704 | ||
705 | /* never any data in such packets */ | |
6dbd682b | 706 | qtd_fill(ehci, qtd, 0, 0, token, 0); |
1da177e4 LT |
707 | } |
708 | } | |
709 | ||
710 | /* by default, enable interrupt on urb completion */ | |
711 | if (likely (!(urb->transfer_flags & URB_NO_INTERRUPT))) | |
6dbd682b | 712 | qtd->hw_token |= cpu_to_hc32(ehci, QTD_IOC); |
1da177e4 LT |
713 | return head; |
714 | ||
715 | cleanup: | |
716 | qtd_list_free (ehci, urb, head); | |
717 | return NULL; | |
718 | } | |
719 | ||
720 | /*-------------------------------------------------------------------------*/ | |
721 | ||
722 | // Would be best to create all qh's from config descriptors, | |
723 | // when each interface/altsetting is established. Unlink | |
724 | // any previous qh and cancel its urbs first; endpoints are | |
725 | // implicitly reset then (data toggle too). | |
726 | // That'd mean updating how usbcore talks to HCDs. (2.7?) | |
727 | ||
728 | ||
729 | /* | |
730 | * Each QH holds a qtd list; a QH is used for everything except iso. | |
731 | * | |
732 | * For interrupt urbs, the scheduler must set the microframe scheduling | |
733 | * mask(s) each time the QH gets scheduled. For highspeed, that's | |
734 | * just one microframe in the s-mask. For split interrupt transactions | |
735 | * there are additional complications: c-mask, maybe FSTNs. | |
736 | */ | |
737 | static struct ehci_qh * | |
738 | qh_make ( | |
739 | struct ehci_hcd *ehci, | |
740 | struct urb *urb, | |
55016f10 | 741 | gfp_t flags |
1da177e4 LT |
742 | ) { |
743 | struct ehci_qh *qh = ehci_qh_alloc (ehci, flags); | |
744 | u32 info1 = 0, info2 = 0; | |
745 | int is_input, type; | |
746 | int maxp = 0; | |
340ba5f9 | 747 | struct usb_tt *tt = urb->dev->tt; |
1da177e4 LT |
748 | |
749 | if (!qh) | |
750 | return qh; | |
751 | ||
752 | /* | |
753 | * init endpoint/device data for this QH | |
754 | */ | |
755 | info1 |= usb_pipeendpoint (urb->pipe) << 8; | |
756 | info1 |= usb_pipedevice (urb->pipe) << 0; | |
757 | ||
758 | is_input = usb_pipein (urb->pipe); | |
759 | type = usb_pipetype (urb->pipe); | |
760 | maxp = usb_maxpacket (urb->dev, urb->pipe, !is_input); | |
761 | ||
caa9ef67 DB |
762 | /* 1024 byte maxpacket is a hardware ceiling. High bandwidth |
763 | * acts like up to 3KB, but is built from smaller packets. | |
764 | */ | |
765 | if (max_packet(maxp) > 1024) { | |
766 | ehci_dbg(ehci, "bogus qh maxpacket %d\n", max_packet(maxp)); | |
767 | goto done; | |
768 | } | |
769 | ||
1da177e4 LT |
770 | /* Compute interrupt scheduling parameters just once, and save. |
771 | * - allowing for high bandwidth, how many nsec/uframe are used? | |
772 | * - split transactions need a second CSPLIT uframe; same question | |
773 | * - splits also need a schedule gap (for full/low speed I/O) | |
774 | * - qh has a polling interval | |
775 | * | |
776 | * For control/bulk requests, the HC or TT handles these. | |
777 | */ | |
778 | if (type == PIPE_INTERRUPT) { | |
340ba5f9 DB |
779 | qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH, |
780 | is_input, 0, | |
781 | hb_mult(maxp) * max_packet(maxp))); | |
1da177e4 LT |
782 | qh->start = NO_FRAME; |
783 | ||
784 | if (urb->dev->speed == USB_SPEED_HIGH) { | |
785 | qh->c_usecs = 0; | |
786 | qh->gap_uf = 0; | |
787 | ||
788 | qh->period = urb->interval >> 3; | |
789 | if (qh->period == 0 && urb->interval != 1) { | |
790 | /* NOTE interval 2 or 4 uframes could work. | |
791 | * But interval 1 scheduling is simpler, and | |
792 | * includes high bandwidth. | |
793 | */ | |
794 | dbg ("intr period %d uframes, NYET!", | |
795 | urb->interval); | |
796 | goto done; | |
797 | } | |
798 | } else { | |
d0384200 DB |
799 | int think_time; |
800 | ||
1da177e4 LT |
801 | /* gap is f(FS/LS transfer times) */ |
802 | qh->gap_uf = 1 + usb_calc_bus_time (urb->dev->speed, | |
803 | is_input, 0, maxp) / (125 * 1000); | |
804 | ||
805 | /* FIXME this just approximates SPLIT/CSPLIT times */ | |
806 | if (is_input) { // SPLIT, gap, CSPLIT+DATA | |
807 | qh->c_usecs = qh->usecs + HS_USECS (0); | |
808 | qh->usecs = HS_USECS (1); | |
809 | } else { // SPLIT+DATA, gap, CSPLIT | |
810 | qh->usecs += HS_USECS (1); | |
811 | qh->c_usecs = HS_USECS (0); | |
812 | } | |
813 | ||
d0384200 DB |
814 | think_time = tt ? tt->think_time : 0; |
815 | qh->tt_usecs = NS_TO_US (think_time + | |
816 | usb_calc_bus_time (urb->dev->speed, | |
817 | is_input, 0, max_packet (maxp))); | |
1da177e4 LT |
818 | qh->period = urb->interval; |
819 | } | |
820 | } | |
821 | ||
822 | /* support for tt scheduling, and access to toggles */ | |
6a8e87b2 | 823 | qh->dev = urb->dev; |
1da177e4 LT |
824 | |
825 | /* using TT? */ | |
826 | switch (urb->dev->speed) { | |
827 | case USB_SPEED_LOW: | |
828 | info1 |= (1 << 12); /* EPS "low" */ | |
829 | /* FALL THROUGH */ | |
830 | ||
831 | case USB_SPEED_FULL: | |
832 | /* EPS 0 means "full" */ | |
833 | if (type != PIPE_INTERRUPT) | |
834 | info1 |= (EHCI_TUNE_RL_TT << 28); | |
835 | if (type == PIPE_CONTROL) { | |
836 | info1 |= (1 << 27); /* for TT */ | |
837 | info1 |= 1 << 14; /* toggle from qtd */ | |
838 | } | |
839 | info1 |= maxp << 16; | |
840 | ||
841 | info2 |= (EHCI_TUNE_MULT_TT << 30); | |
8cd42e97 KG |
842 | |
843 | /* Some Freescale processors have an erratum in which the | |
844 | * port number in the queue head was 0..N-1 instead of 1..N. | |
845 | */ | |
846 | if (ehci_has_fsl_portno_bug(ehci)) | |
847 | info2 |= (urb->dev->ttport-1) << 23; | |
848 | else | |
849 | info2 |= urb->dev->ttport << 23; | |
1da177e4 LT |
850 | |
851 | /* set the address of the TT; for TDI's integrated | |
852 | * root hub tt, leave it zeroed. | |
853 | */ | |
340ba5f9 DB |
854 | if (tt && tt->hub != ehci_to_hcd(ehci)->self.root_hub) |
855 | info2 |= tt->hub->devnum << 16; | |
1da177e4 LT |
856 | |
857 | /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */ | |
858 | ||
859 | break; | |
860 | ||
861 | case USB_SPEED_HIGH: /* no TT involved */ | |
862 | info1 |= (2 << 12); /* EPS "high" */ | |
863 | if (type == PIPE_CONTROL) { | |
864 | info1 |= (EHCI_TUNE_RL_HS << 28); | |
865 | info1 |= 64 << 16; /* usb2 fixed maxpacket */ | |
866 | info1 |= 1 << 14; /* toggle from qtd */ | |
867 | info2 |= (EHCI_TUNE_MULT_HS << 30); | |
868 | } else if (type == PIPE_BULK) { | |
869 | info1 |= (EHCI_TUNE_RL_HS << 28); | |
caa9ef67 DB |
870 | /* The USB spec says that high speed bulk endpoints |
871 | * always use 512 byte maxpacket. But some device | |
872 | * vendors decided to ignore that, and MSFT is happy | |
873 | * to help them do so. So now people expect to use | |
874 | * such nonconformant devices with Linux too; sigh. | |
875 | */ | |
876 | info1 |= max_packet(maxp) << 16; | |
1da177e4 LT |
877 | info2 |= (EHCI_TUNE_MULT_HS << 30); |
878 | } else { /* PIPE_INTERRUPT */ | |
879 | info1 |= max_packet (maxp) << 16; | |
880 | info2 |= hb_mult (maxp) << 30; | |
881 | } | |
882 | break; | |
883 | default: | |
53bd6a60 | 884 | dbg ("bogus dev %p speed %d", urb->dev, urb->dev->speed); |
1da177e4 LT |
885 | done: |
886 | qh_put (qh); | |
887 | return NULL; | |
888 | } | |
889 | ||
890 | /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */ | |
891 | ||
892 | /* init as live, toggle clear, advance to dummy */ | |
893 | qh->qh_state = QH_STATE_IDLE; | |
6dbd682b SR |
894 | qh->hw_info1 = cpu_to_hc32(ehci, info1); |
895 | qh->hw_info2 = cpu_to_hc32(ehci, info2); | |
a455212d | 896 | usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), !is_input, 1); |
1da177e4 LT |
897 | qh_refresh (ehci, qh); |
898 | return qh; | |
899 | } | |
900 | ||
901 | /*-------------------------------------------------------------------------*/ | |
902 | ||
903 | /* move qh (and its qtds) onto async queue; maybe enable queue. */ | |
904 | ||
905 | static void qh_link_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
906 | { | |
6dbd682b | 907 | __hc32 dma = QH_NEXT(ehci, qh->qh_dma); |
1da177e4 LT |
908 | struct ehci_qh *head; |
909 | ||
914b7012 AS |
910 | /* Don't link a QH if there's a Clear-TT-Buffer pending */ |
911 | if (unlikely(qh->clearing_tt)) | |
912 | return; | |
913 | ||
1da177e4 LT |
914 | /* (re)start the async schedule? */ |
915 | head = ehci->async; | |
916 | timer_action_done (ehci, TIMER_ASYNC_OFF); | |
917 | if (!head->qh_next.qh) { | |
083522d7 | 918 | u32 cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
919 | |
920 | if (!(cmd & CMD_ASE)) { | |
921 | /* in case a clear of CMD_ASE didn't take yet */ | |
083522d7 BH |
922 | (void)handshake(ehci, &ehci->regs->status, |
923 | STS_ASS, 0, 150); | |
1da177e4 | 924 | cmd |= CMD_ASE | CMD_RUN; |
083522d7 | 925 | ehci_writel(ehci, cmd, &ehci->regs->command); |
1da177e4 LT |
926 | ehci_to_hcd(ehci)->state = HC_STATE_RUNNING; |
927 | /* posted write need not be known to HC yet ... */ | |
928 | } | |
929 | } | |
930 | ||
a455212d | 931 | /* clear halt and/or toggle; and maybe recover from silicon quirk */ |
1da177e4 LT |
932 | if (qh->qh_state == QH_STATE_IDLE) |
933 | qh_refresh (ehci, qh); | |
934 | ||
935 | /* splice right after start */ | |
936 | qh->qh_next = head->qh_next; | |
937 | qh->hw_next = head->hw_next; | |
938 | wmb (); | |
939 | ||
940 | head->qh_next.qh = qh; | |
941 | head->hw_next = dma; | |
942 | ||
a2c2706e | 943 | qh->xacterrs = QH_XACTERR_MAX; |
1da177e4 LT |
944 | qh->qh_state = QH_STATE_LINKED; |
945 | /* qtd completions reported later by interrupt */ | |
946 | } | |
947 | ||
948 | /*-------------------------------------------------------------------------*/ | |
949 | ||
1da177e4 LT |
950 | /* |
951 | * For control/bulk/interrupt, return QH with these TDs appended. | |
952 | * Allocates and initializes the QH if necessary. | |
953 | * Returns null if it can't allocate a QH it needs to. | |
954 | * If the QH has TDs (urbs) already, that's great. | |
955 | */ | |
956 | static struct ehci_qh *qh_append_tds ( | |
957 | struct ehci_hcd *ehci, | |
958 | struct urb *urb, | |
959 | struct list_head *qtd_list, | |
960 | int epnum, | |
961 | void **ptr | |
962 | ) | |
963 | { | |
964 | struct ehci_qh *qh = NULL; | |
fd05e720 | 965 | __hc32 qh_addr_mask = cpu_to_hc32(ehci, 0x7f); |
1da177e4 LT |
966 | |
967 | qh = (struct ehci_qh *) *ptr; | |
968 | if (unlikely (qh == NULL)) { | |
969 | /* can't sleep here, we have ehci->lock... */ | |
970 | qh = qh_make (ehci, urb, GFP_ATOMIC); | |
971 | *ptr = qh; | |
972 | } | |
973 | if (likely (qh != NULL)) { | |
974 | struct ehci_qtd *qtd; | |
975 | ||
976 | if (unlikely (list_empty (qtd_list))) | |
977 | qtd = NULL; | |
978 | else | |
979 | qtd = list_entry (qtd_list->next, struct ehci_qtd, | |
980 | qtd_list); | |
981 | ||
982 | /* control qh may need patching ... */ | |
983 | if (unlikely (epnum == 0)) { | |
984 | ||
985 | /* usb_reset_device() briefly reverts to address 0 */ | |
986 | if (usb_pipedevice (urb->pipe) == 0) | |
6dbd682b | 987 | qh->hw_info1 &= ~qh_addr_mask; |
1da177e4 LT |
988 | } |
989 | ||
990 | /* just one way to queue requests: swap with the dummy qtd. | |
991 | * only hc or qh_refresh() ever modify the overlay. | |
992 | */ | |
993 | if (likely (qtd != NULL)) { | |
994 | struct ehci_qtd *dummy; | |
995 | dma_addr_t dma; | |
6dbd682b | 996 | __hc32 token; |
1da177e4 LT |
997 | |
998 | /* to avoid racing the HC, use the dummy td instead of | |
999 | * the first td of our list (becomes new dummy). both | |
1000 | * tds stay deactivated until we're done, when the | |
1001 | * HC is allowed to fetch the old dummy (4.10.2). | |
1002 | */ | |
1003 | token = qtd->hw_token; | |
6dbd682b | 1004 | qtd->hw_token = HALT_BIT(ehci); |
1da177e4 LT |
1005 | wmb (); |
1006 | dummy = qh->dummy; | |
1007 | ||
1008 | dma = dummy->qtd_dma; | |
1009 | *dummy = *qtd; | |
1010 | dummy->qtd_dma = dma; | |
1011 | ||
1012 | list_del (&qtd->qtd_list); | |
1013 | list_add (&dummy->qtd_list, qtd_list); | |
7d283aee | 1014 | list_splice_tail(qtd_list, &qh->qtd_list); |
1da177e4 | 1015 | |
6dbd682b | 1016 | ehci_qtd_init(ehci, qtd, qtd->qtd_dma); |
1da177e4 LT |
1017 | qh->dummy = qtd; |
1018 | ||
1019 | /* hc must see the new dummy at list end */ | |
1020 | dma = qtd->qtd_dma; | |
1021 | qtd = list_entry (qh->qtd_list.prev, | |
1022 | struct ehci_qtd, qtd_list); | |
6dbd682b | 1023 | qtd->hw_next = QTD_NEXT(ehci, dma); |
1da177e4 LT |
1024 | |
1025 | /* let the hc process these next qtds */ | |
1026 | wmb (); | |
1027 | dummy->hw_token = token; | |
1028 | ||
1029 | urb->hcpriv = qh_get (qh); | |
1030 | } | |
1031 | } | |
1032 | return qh; | |
1033 | } | |
1034 | ||
1035 | /*-------------------------------------------------------------------------*/ | |
1036 | ||
1037 | static int | |
1038 | submit_async ( | |
1039 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1040 | struct urb *urb, |
1041 | struct list_head *qtd_list, | |
55016f10 | 1042 | gfp_t mem_flags |
1da177e4 LT |
1043 | ) { |
1044 | struct ehci_qtd *qtd; | |
1045 | int epnum; | |
1046 | unsigned long flags; | |
1047 | struct ehci_qh *qh = NULL; | |
e9df41c5 | 1048 | int rc; |
1da177e4 LT |
1049 | |
1050 | qtd = list_entry (qtd_list->next, struct ehci_qtd, qtd_list); | |
e9df41c5 | 1051 | epnum = urb->ep->desc.bEndpointAddress; |
1da177e4 LT |
1052 | |
1053 | #ifdef EHCI_URB_TRACE | |
1054 | ehci_dbg (ehci, | |
1055 | "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n", | |
441b62c1 | 1056 | __func__, urb->dev->devpath, urb, |
1da177e4 LT |
1057 | epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out", |
1058 | urb->transfer_buffer_length, | |
e9df41c5 | 1059 | qtd, urb->ep->hcpriv); |
1da177e4 LT |
1060 | #endif |
1061 | ||
1062 | spin_lock_irqsave (&ehci->lock, flags); | |
8de98402 BH |
1063 | if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE, |
1064 | &ehci_to_hcd(ehci)->flags))) { | |
1065 | rc = -ESHUTDOWN; | |
1066 | goto done; | |
1067 | } | |
e9df41c5 AS |
1068 | rc = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); |
1069 | if (unlikely(rc)) | |
1070 | goto done; | |
8de98402 | 1071 | |
e9df41c5 | 1072 | qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv); |
8de98402 | 1073 | if (unlikely(qh == NULL)) { |
e9df41c5 | 1074 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); |
8de98402 BH |
1075 | rc = -ENOMEM; |
1076 | goto done; | |
1077 | } | |
1da177e4 LT |
1078 | |
1079 | /* Control/bulk operations through TTs don't need scheduling, | |
1080 | * the HC and TT handle it when the TT has a buffer ready. | |
1081 | */ | |
8de98402 BH |
1082 | if (likely (qh->qh_state == QH_STATE_IDLE)) |
1083 | qh_link_async (ehci, qh_get (qh)); | |
1084 | done: | |
1da177e4 | 1085 | spin_unlock_irqrestore (&ehci->lock, flags); |
8de98402 | 1086 | if (unlikely (qh == NULL)) |
1da177e4 | 1087 | qtd_list_free (ehci, urb, qtd_list); |
8de98402 | 1088 | return rc; |
1da177e4 LT |
1089 | } |
1090 | ||
1091 | /*-------------------------------------------------------------------------*/ | |
1092 | ||
1093 | /* the async qh for the qtds being reclaimed are now unlinked from the HC */ | |
1094 | ||
7d12e780 | 1095 | static void end_unlink_async (struct ehci_hcd *ehci) |
1da177e4 LT |
1096 | { |
1097 | struct ehci_qh *qh = ehci->reclaim; | |
1098 | struct ehci_qh *next; | |
1099 | ||
07d29b63 | 1100 | iaa_watchdog_done(ehci); |
1da177e4 | 1101 | |
6dbd682b | 1102 | // qh->hw_next = cpu_to_hc32(qh->qh_dma); |
1da177e4 LT |
1103 | qh->qh_state = QH_STATE_IDLE; |
1104 | qh->qh_next.qh = NULL; | |
53bd6a60 | 1105 | qh_put (qh); // refcount from reclaim |
1da177e4 LT |
1106 | |
1107 | /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */ | |
1108 | next = qh->reclaim; | |
1109 | ehci->reclaim = next; | |
1da177e4 LT |
1110 | qh->reclaim = NULL; |
1111 | ||
7d12e780 | 1112 | qh_completions (ehci, qh); |
1da177e4 LT |
1113 | |
1114 | if (!list_empty (&qh->qtd_list) | |
1115 | && HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) | |
1116 | qh_link_async (ehci, qh); | |
1117 | else { | |
1118 | qh_put (qh); // refcount from async list | |
1119 | ||
1120 | /* it's not free to turn the async schedule on/off; leave it | |
1121 | * active but idle for a while once it empties. | |
1122 | */ | |
1123 | if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) | |
1124 | && ehci->async->qh_next.qh == NULL) | |
1125 | timer_action (ehci, TIMER_ASYNC_OFF); | |
1126 | } | |
1127 | ||
1128 | if (next) { | |
1129 | ehci->reclaim = NULL; | |
1130 | start_unlink_async (ehci, next); | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | /* makes sure the async qh will become idle */ | |
1135 | /* caller must own ehci->lock */ | |
1136 | ||
1137 | static void start_unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
1138 | { | |
083522d7 | 1139 | int cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
1140 | struct ehci_qh *prev; |
1141 | ||
1142 | #ifdef DEBUG | |
1143 | assert_spin_locked(&ehci->lock); | |
1144 | if (ehci->reclaim | |
1145 | || (qh->qh_state != QH_STATE_LINKED | |
1146 | && qh->qh_state != QH_STATE_UNLINK_WAIT) | |
1147 | ) | |
1148 | BUG (); | |
1149 | #endif | |
1150 | ||
1151 | /* stop async schedule right now? */ | |
1152 | if (unlikely (qh == ehci->async)) { | |
1153 | /* can't get here without STS_ASS set */ | |
d0852299 DB |
1154 | if (ehci_to_hcd(ehci)->state != HC_STATE_HALT |
1155 | && !ehci->reclaim) { | |
1156 | /* ... and CMD_IAAD clear */ | |
083522d7 BH |
1157 | ehci_writel(ehci, cmd & ~CMD_ASE, |
1158 | &ehci->regs->command); | |
1da177e4 LT |
1159 | wmb (); |
1160 | // handshake later, if we need to | |
d0852299 | 1161 | timer_action_done (ehci, TIMER_ASYNC_OFF); |
1da177e4 | 1162 | } |
1da177e4 | 1163 | return; |
53bd6a60 | 1164 | } |
1da177e4 LT |
1165 | |
1166 | qh->qh_state = QH_STATE_UNLINK; | |
1167 | ehci->reclaim = qh = qh_get (qh); | |
1168 | ||
1169 | prev = ehci->async; | |
1170 | while (prev->qh_next.qh != qh) | |
1171 | prev = prev->qh_next.qh; | |
1172 | ||
1173 | prev->hw_next = qh->hw_next; | |
1174 | prev->qh_next = qh->qh_next; | |
1175 | wmb (); | |
1176 | ||
391016f6 AS |
1177 | /* If the controller isn't running, we don't have to wait for it */ |
1178 | if (unlikely(!HC_IS_RUNNING(ehci_to_hcd(ehci)->state))) { | |
1da177e4 | 1179 | /* if (unlikely (qh->reclaim != 0)) |
53bd6a60 | 1180 | * this will recurse, probably not much |
1da177e4 | 1181 | */ |
7d12e780 | 1182 | end_unlink_async (ehci); |
1da177e4 LT |
1183 | return; |
1184 | } | |
1185 | ||
1da177e4 | 1186 | cmd |= CMD_IAAD; |
083522d7 BH |
1187 | ehci_writel(ehci, cmd, &ehci->regs->command); |
1188 | (void)ehci_readl(ehci, &ehci->regs->command); | |
07d29b63 | 1189 | iaa_watchdog_start(ehci); |
1da177e4 LT |
1190 | } |
1191 | ||
1192 | /*-------------------------------------------------------------------------*/ | |
1193 | ||
7d12e780 | 1194 | static void scan_async (struct ehci_hcd *ehci) |
1da177e4 LT |
1195 | { |
1196 | struct ehci_qh *qh; | |
1197 | enum ehci_timer_action action = TIMER_IO_WATCHDOG; | |
1198 | ||
b9638011 | 1199 | ehci->stamp = ehci_readl(ehci, &ehci->regs->frame_index); |
1da177e4 LT |
1200 | timer_action_done (ehci, TIMER_ASYNC_SHRINK); |
1201 | rescan: | |
1202 | qh = ehci->async->qh_next.qh; | |
1203 | if (likely (qh != NULL)) { | |
1204 | do { | |
1205 | /* clean any finished work for this qh */ | |
1206 | if (!list_empty (&qh->qtd_list) | |
1207 | && qh->stamp != ehci->stamp) { | |
1208 | int temp; | |
1209 | ||
1210 | /* unlinks could happen here; completion | |
1211 | * reporting drops the lock. rescan using | |
1212 | * the latest schedule, but don't rescan | |
1213 | * qhs we already finished (no looping). | |
1214 | */ | |
1215 | qh = qh_get (qh); | |
1216 | qh->stamp = ehci->stamp; | |
7d12e780 | 1217 | temp = qh_completions (ehci, qh); |
1da177e4 LT |
1218 | qh_put (qh); |
1219 | if (temp != 0) { | |
1220 | goto rescan; | |
1221 | } | |
1222 | } | |
1223 | ||
b9638011 | 1224 | /* unlink idle entries, reducing DMA usage as well |
1da177e4 LT |
1225 | * as HCD schedule-scanning costs. delay for any qh |
1226 | * we just scanned, there's a not-unusual case that it | |
1227 | * doesn't stay idle for long. | |
1228 | * (plus, avoids some kind of re-activation race.) | |
1229 | */ | |
b9638011 DB |
1230 | if (list_empty(&qh->qtd_list) |
1231 | && qh->qh_state == QH_STATE_LINKED) { | |
1232 | if (!ehci->reclaim | |
1233 | && ((ehci->stamp - qh->stamp) & 0x1fff) | |
1234 | >= (EHCI_SHRINK_FRAMES * 8)) | |
1235 | start_unlink_async(ehci, qh); | |
1236 | else | |
1da177e4 | 1237 | action = TIMER_ASYNC_SHRINK; |
1da177e4 LT |
1238 | } |
1239 | ||
1240 | qh = qh->qh_next.qh; | |
1241 | } while (qh); | |
1242 | } | |
1243 | if (action == TIMER_ASYNC_SHRINK) | |
1244 | timer_action (ehci, TIMER_ASYNC_SHRINK); | |
1245 | } |