[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / host / ehci-pci.c

/*
 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
 *
 * Copyright (c) 2000-2004 by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>

#include "ehci.h"
#include "pci-quirks.h"

#define DRIVER_DESC "EHCI PCI platform driver"

static const char hcd_name[] = "ehci-pci";

/* defined here to avoid adding to pci_ids.h for single instance use */
#define PCI_DEVICE_ID_INTEL_CE4100_USB	0x2e70

/*-------------------------------------------------------------------------*/
#define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC		0x0939
static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
{
	return pdev->vendor == PCI_VENDOR_ID_INTEL &&
		pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
}

/*
 * 0x84 is the offset of in/out threshold register,
 * and it is the same offset as the register of 'hostpc'.
 */
#define	intel_quark_x1000_insnreg01	hostpc

/* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
#define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD	0x007f007f

/* called after powerup, by probe or system-pm "wakeup" */
static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
{
	int			retval;

	/* we expect static quirk code to handle the "extended capabilities"
	 * (currently just BIOS handoff) allowed starting with EHCI 0.96
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	retval = pci_set_mwi(pdev);
	if (!retval)
		ehci_dbg(ehci, "MWI active\n");

	/* Reset the threshold limit */
	if (is_intel_quark_x1000(pdev)) {
		/*
		 * For the Intel QUARK X1000, raise the I/O threshold to the
		 * maximum usable value in order to improve performance.
		 */
		ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
			ehci->regs->intel_quark_x1000_insnreg01);
	}

	return 0;
}

/* called during probe() after chip reset completes */
static int ehci_pci_setup(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	struct pci_dev		*p_smbus;
	u8			rev;
	u32			temp;
	int			retval;

	ehci->caps = hcd->regs;

	/*
	 * ehci_init() causes memory for DMA transfers to be
	 * allocated.  Thus, any vendor-specific workarounds based on
	 * limiting the type of memory used for DMA transfers must
	 * happen before ehci_setup() is called.
	 *
	 * Most other workarounds can be done either before or after
	 * init and reset; they are located here too.
	 */
	switch (pdev->vendor) {
	case PCI_VENDOR_ID_TOSHIBA_2:
		/* celleb's companion chip */
		if (pdev->device == 0x01b5) {
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
			ehci->big_endian_mmio = 1;
#else
			ehci_warn(ehci,
				  "unsupported big endian Toshiba quirk\n");
#endif
		}
		break;
	case PCI_VENDOR_ID_NVIDIA:
		/* NVidia reports that certain chips don't handle
		 * QH, ITD, or SITD addresses above 2GB.  (But TD,
		 * data buffer, and periodic schedule are normal.)
		 */
		switch (pdev->device) {
		case 0x003c:	/* MCP04 */
		case 0x005b:	/* CK804 */
		case 0x00d8:	/* CK8 */
		case 0x00e8:	/* CK8S */
			if (pci_set_consistent_dma_mask(pdev,
						DMA_BIT_MASK(31)) < 0)
				ehci_warn(ehci, "can't enable NVidia "
					"workaround for >2GB RAM\n");
			break;

		/* Some NForce2 chips have problems with selective suspend;
		 * fixed in newer silicon.
		 */
		case 0x0068:
			if (pdev->revision < 0xa4)
				ehci->no_selective_suspend = 1;
			break;
		}
		break;
	case PCI_VENDOR_ID_INTEL:
		if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
			hcd->has_tt = 1;
		break;
	case PCI_VENDOR_ID_TDI:
		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
			hcd->has_tt = 1;
		break;
	case PCI_VENDOR_ID_AMD:
		/* AMD PLL quirk */
		if (usb_amd_find_chipset_info())
			ehci->amd_pll_fix = 1;
		/* AMD8111 EHCI doesn't work, according to AMD errata */
		if (pdev->device == 0x7463) {
			ehci_info(ehci, "ignoring AMD8111 (errata)\n");
			retval = -EIO;
			goto done;
		}

		/*
		 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
		 * read/write memory space which does not belong to it when
		 * there is NULL pointer with T-bit set to 1 in the frame list
		 * table. To avoid the issue, the frame list link pointer
		 * should always contain a valid pointer to a inactive qh.
		 */
		if (pdev->device == 0x7808) {
			ehci->use_dummy_qh = 1;
			ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
		}
		break;
	case PCI_VENDOR_ID_VIA:
		if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
			u8 tmp;

			/* The VT6212 defaults to a 1 usec EHCI sleep time which
			 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
			 * that sleep time use the conventional 10 usec.
			 */
			pci_read_config_byte(pdev, 0x4b, &tmp);
			if (tmp & 0x20)
				break;
			pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
		}
		break;
	case PCI_VENDOR_ID_ATI:
		/* AMD PLL quirk */
		if (usb_amd_find_chipset_info())
			ehci->amd_pll_fix = 1;

		/*
		 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
		 * read/write memory space which does not belong to it when
		 * there is NULL pointer with T-bit set to 1 in the frame list
		 * table. To avoid the issue, the frame list link pointer
		 * should always contain a valid pointer to a inactive qh.
		 */
		if (pdev->device == 0x4396) {
			ehci->use_dummy_qh = 1;
			ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
		}
		/* SB600 and old version of SB700 have a bug in EHCI controller,
		 * which causes usb devices lose response in some cases.
		 */
		if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
			p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
						 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
						 NULL);
			if (!p_smbus)
				break;
			rev = p_smbus->revision;
			if ((pdev->device == 0x4386) || (rev == 0x3a)
			    || (rev == 0x3b)) {
				u8 tmp;
				ehci_info(ehci, "applying AMD SB600/SB700 USB "
					"freeze workaround\n");
				pci_read_config_byte(pdev, 0x53, &tmp);
				pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
			}
			pci_dev_put(p_smbus);
		}
		break;
	case PCI_VENDOR_ID_NETMOS:
		/* MosChip frame-index-register bug */
		ehci_info(ehci, "applying MosChip frame-index workaround\n");
		ehci->frame_index_bug = 1;
		break;
	}

	/* optional debug port, normally in the first BAR */
	temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
	if (temp) {
		pci_read_config_dword(pdev, temp, &temp);
		temp >>= 16;
		if (((temp >> 13) & 7) == 1) {
			u32 hcs_params = ehci_readl(ehci,
						    &ehci->caps->hcs_params);

			temp &= 0x1fff;
			ehci->debug = hcd->regs + temp;
			temp = ehci_readl(ehci, &ehci->debug->control);
			ehci_info(ehci, "debug port %d%s\n",
				  HCS_DEBUG_PORT(hcs_params),
				  (temp & DBGP_ENABLED) ? " IN USE" : "");
			if (!(temp & DBGP_ENABLED))
				ehci->debug = NULL;
		}
	}

	retval = ehci_setup(hcd);
	if (retval)
		return retval;

	/* These workarounds need to be applied after ehci_setup() */
	switch (pdev->vendor) {
	case PCI_VENDOR_ID_NEC:
		ehci->need_io_watchdog = 0;
		break;
	case PCI_VENDOR_ID_INTEL:
		ehci->need_io_watchdog = 0;
		break;
	case PCI_VENDOR_ID_NVIDIA:
		switch (pdev->device) {
		/* MCP89 chips on the MacBookAir3,1 give EPROTO when
		 * fetching device descriptors unless LPM is disabled.
		 * There are also intermittent problems enumerating
		 * devices with PPCD enabled.
		 */
		case 0x0d9d:
			ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
			ehci->has_ppcd = 0;
			ehci->command &= ~CMD_PPCEE;
			break;
		}
		break;
	}

	/* at least the Genesys GL880S needs fixup here */
	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	temp &= 0x0f;
	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
		ehci_dbg(ehci, "bogus port configuration: "
			"cc=%d x pcc=%d < ports=%d\n",
			HCS_N_CC(ehci->hcs_params),
			HCS_N_PCC(ehci->hcs_params),
			HCS_N_PORTS(ehci->hcs_params));

		switch (pdev->vendor) {
		case 0x17a0:		/* GENESYS */
			/* GL880S: should be PORTS=2 */
			temp |= (ehci->hcs_params & ~0xf);
			ehci->hcs_params = temp;
			break;
		case PCI_VENDOR_ID_NVIDIA:
			/* NF4: should be PCC=10 */
			break;
		}
	}

	/* Serial Bus Release Number is at PCI 0x60 offset */
	if (pdev->vendor == PCI_VENDOR_ID_STMICRO
	    && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
		;	/* ConneXT has no sbrn register */
	else
		pci_read_config_byte(pdev, 0x60, &ehci->sbrn);

	/* Keep this around for a while just in case some EHCI
	 * implementation uses legacy PCI PM support.  This test
	 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
	 * been triggered by then.
	 */
	if (!device_can_wakeup(&pdev->dev)) {
		u16	port_wake;

		pci_read_config_word(pdev, 0x62, &port_wake);
		if (port_wake & 0x0001) {
			dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
			device_set_wakeup_capable(&pdev->dev, 1);
		}
	}

#ifdef	CONFIG_PM_RUNTIME
	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
		ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
#endif

	retval = ehci_pci_reinit(ehci, pdev);
done:
	return retval;
}

/*-------------------------------------------------------------------------*/

#ifdef	CONFIG_PM

/* suspend/resume, section 4.3 */

/* These routines rely on the PCI bus glue
 * to handle powerdown and wakeup, and currently also on
 * transceivers that don't need any software attention to set up
 * the right sort of wakeup.
 * Also they depend on separate root hub suspend/resume.
 */

static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
{
	return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
		pdev->vendor == PCI_VENDOR_ID_INTEL &&
		(pdev->device == 0x1E26 ||
		 pdev->device == 0x8C2D ||
		 pdev->device == 0x8C26 ||
		 pdev->device == 0x9C26);
}

static void ehci_enable_xhci_companion(void)
{
	struct pci_dev		*companion = NULL;

	/* The xHCI and EHCI controllers are not on the same PCI slot */
	for_each_pci_dev(companion) {
		if (!usb_is_intel_switchable_xhci(companion))
			continue;
		usb_enable_xhci_ports(companion);
		return;
	}
}

static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	/* The BIOS on systems with the Intel Panther Point chipset may or may
	 * not support xHCI natively.  That means that during system resume, it
	 * may switch the ports back to EHCI so that users can use their
	 * keyboard to select a kernel from GRUB after resume from hibernate.
	 *
	 * The BIOS is supposed to remember whether the OS had xHCI ports
	 * enabled before resume, and switch the ports back to xHCI when the
	 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
	 * writers.
	 *
	 * Unconditionally switch the ports back to xHCI after a system resume.
	 * We can't tell whether the EHCI or xHCI controller will be resumed
	 * first, so we have to do the port switchover in both drivers.  Writing
	 * a '1' to the port switchover registers should have no effect if the
	 * port was already switched over.
	 */
	if (usb_is_intel_switchable_ehci(pdev))
		ehci_enable_xhci_companion();

	if (ehci_resume(hcd, hibernated) != 0)
		(void) ehci_pci_reinit(ehci, pdev);
	return 0;
}

#else

#define ehci_suspend		NULL
#define ehci_pci_resume		NULL
#endif	/* CONFIG_PM */

static struct hc_driver __read_mostly ehci_pci_hc_driver;

static const struct ehci_driver_overrides pci_overrides __initconst = {
	.reset =		ehci_pci_setup,
};

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids [] = { {
	/* handle any USB 2.0 EHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
	.driver_data =	(unsigned long) &ehci_pci_hc_driver,
	}, {
	PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
	.driver_data = (unsigned long) &ehci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver ehci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	usb_hcd_pci_probe,
	.remove =	usb_hcd_pci_remove,
	.shutdown = 	usb_hcd_pci_shutdown,

#ifdef CONFIG_PM
	.driver =	{
		.pm =	&usb_hcd_pci_pm_ops
	},
#endif
};

static int __init ehci_pci_init(void)
{
	if (usb_disabled())
		return -ENODEV;

	pr_info("%s: " DRIVER_DESC "\n", hcd_name);

	ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);

	/* Entries for the PCI suspend/resume callbacks are special */
	ehci_pci_hc_driver.pci_suspend = ehci_suspend;
	ehci_pci_hc_driver.pci_resume = ehci_pci_resume;

	return pci_register_driver(&ehci_pci_driver);
}
module_init(ehci_pci_init);

static void __exit ehci_pci_cleanup(void)
{
	pci_unregister_driver(&ehci_pci_driver);
}
module_exit(ehci_pci_cleanup);

MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_AUTHOR("David Brownell");
MODULE_AUTHOR("Alan Stern");
MODULE_LICENSE("GPL");
Commit	Line	Data
7ff71d6a MP	1	/*
	2	* EHCI HCD (Host Controller Driver) PCI Bus Glue.
	3	*
	4	* Copyright (c) 2000-2004 by David Brownell
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	* for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software Foundation,
	18	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
adfa79d1 AS	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/pci.h>
	24	#include <linux/usb.h>
	25	#include <linux/usb/hcd.h>
	26
	27	#include "ehci.h"
	28	#include "pci-quirks.h"
	29
	30	#define DRIVER_DESC "EHCI PCI platform driver"
	31
	32	static const char hcd_name[] = "ehci-pci";
7ff71d6a	33
4f683843 DB	34	/* defined here to avoid adding to pci_ids.h for single instance use */
	35	#define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
	36
7ff71d6a	37	/-------------------------------------------------------------------------/
f788fb41 BD	38	#define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC 0x0939
	39	static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
	40	{
	41	return pdev->vendor == PCI_VENDOR_ID_INTEL &&
	42	pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
	43	}
	44
	45	/*
	46	* 0x84 is the offset of in/out threshold register,
	47	* and it is the same offset as the register of 'hostpc'.
	48	*/
	49	#define intel_quark_x1000_insnreg01 hostpc
	50
	51	/* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
	52	#define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD 0x007f007f
7ff71d6a	53
18807521 DB	54	/* called after powerup, by probe or system-pm "wakeup" */
	55	static int ehci_pci_reinit(struct ehci_hcd ehci, struct pci_dev pdev)
	56	{
18807521	57	int retval;
18807521	58
401feafa DB	59	/* we expect static quirk code to handle the "extended capabilities"
	60	* (currently just BIOS handoff) allowed starting with EHCI 0.96
	61	*/
18807521 DB	62
	63	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	64	retval = pci_set_mwi(pdev);
	65	if (!retval)
	66	ehci_dbg(ehci, "MWI active\n");
	67
f788fb41 BD	68	/* Reset the threshold limit */
	69	if (is_intel_quark_x1000(pdev)) {
	70	/*
	71	* For the Intel QUARK X1000, raise the I/O threshold to the
	72	* maximum usable value in order to improve performance.
	73	*/
	74	ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
	75	ehci->regs->intel_quark_x1000_insnreg01);
	76	}
	77
18807521 DB	78	return 0;
	79	}
	80
8926bfa7 DB	81	/* called during probe() after chip reset completes */
8926bfa7 DB	82	static int ehci_pci_setup(struct usb_hcd *hcd)
7ff71d6a	83	{
abcc9448 DB	84	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
abcc9448 DB	85	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
b09bc6cb AX	86	struct pci_dev *p_smbus;
b09bc6cb AX	87	u8 rev;
7ff71d6a	88	u32 temp;
18807521	89	int retval;
7ff71d6a	90
1a49e2ac AS	91	ehci->caps = hcd->regs;
	92
	93	/*
	94	* ehci_init() causes memory for DMA transfers to be
	95	* allocated. Thus, any vendor-specific workarounds based on
	96	* limiting the type of memory used for DMA transfers must
	97	* happen before ehci_setup() is called.
	98	*
	99	* Most other workarounds can be done either before or after
	100	* init and reset; they are located here too.
	101	*/
083522d7 BH	102	switch (pdev->vendor) {
	103	case PCI_VENDOR_ID_TOSHIBA_2:
	104	/* celleb's companion chip */
	105	if (pdev->device == 0x01b5) {
	106	#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
	107	ehci->big_endian_mmio = 1;
	108	#else
	109	ehci_warn(ehci,
	110	"unsupported big endian Toshiba quirk\n");
	111	#endif
	112	}
	113	break;
c32ba30f PS	114	case PCI_VENDOR_ID_NVIDIA:
	115	/* NVidia reports that certain chips don't handle
	116	* QH, ITD, or SITD addresses above 2GB. (But TD,
	117	* data buffer, and periodic schedule are normal.)
	118	*/
	119	switch (pdev->device) {
	120	case 0x003c: /* MCP04 */
	121	case 0x005b: /* CK804 */
	122	case 0x00d8: /* CK8 */
	123	case 0x00e8: /* CK8S */
	124	if (pci_set_consistent_dma_mask(pdev,
929a22a5	125	DMA_BIT_MASK(31)) < 0)
c32ba30f PS	126	ehci_warn(ehci, "can't enable NVidia "
	127	"workaround for >2GB RAM\n");
	128	break;
7ff71d6a	129
1a49e2ac AS	130	/* Some NForce2 chips have problems with selective suspend;
1a49e2ac AS	131	* fixed in newer silicon.
3d091a6f	132	*/
1a49e2ac AS	133	case 0x0068:
	134	if (pdev->revision < 0xa4)
	135	ehci->no_selective_suspend = 1;
	136	break;
	137	}
3681d8f3	138	break;
403dbd36	139	case PCI_VENDOR_ID_INTEL:
1a49e2ac	140	if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
4f683843	141	hcd->has_tt = 1;
403dbd36	142	break;
abcc9448	143	case PCI_VENDOR_ID_TDI:
1a49e2ac	144	if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
7329e211	145	hcd->has_tt = 1;
abcc9448 DB	146	break;
abcc9448 DB	147	case PCI_VENDOR_ID_AMD:
ad93562b AX	148	/* AMD PLL quirk */
	149	if (usb_amd_find_chipset_info())
	150	ehci->amd_pll_fix = 1;
abcc9448 DB	151	/* AMD8111 EHCI doesn't work, according to AMD errata */
	152	if (pdev->device == 0x7463) {
	153	ehci_info(ehci, "ignoring AMD8111 (errata)\n");
8926bfa7 DB	154	retval = -EIO;
8926bfa7 DB	155	goto done;
abcc9448	156	}
a85b4e7f	157
1a49e2ac AS	158	/*
	159	* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
	160	* read/write memory space which does not belong to it when
	161	* there is NULL pointer with T-bit set to 1 in the frame list
	162	* table. To avoid the issue, the frame list link pointer
	163	* should always contain a valid pointer to a inactive qh.
a85b4e7f	164	*/
1a49e2ac AS	165	if (pdev->device == 0x7808) {
	166	ehci->use_dummy_qh = 1;
	167	ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
7ff71d6a	168	}
abcc9448	169	break;
055b93c9 RH	170	case PCI_VENDOR_ID_VIA:
	171	if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
	172	u8 tmp;
	173
	174	/* The VT6212 defaults to a 1 usec EHCI sleep time which
	175	* hogs the PCI bus badly. Setting bit 5 of 0x4B makes
	176	* that sleep time use the conventional 10 usec.
	177	*/
	178	pci_read_config_byte(pdev, 0x4b, &tmp);
	179	if (tmp & 0x20)
	180	break;
	181	pci_write_config_byte(pdev, 0x4b, tmp \| 0x20);
	182	}
	183	break;
b09bc6cb	184	case PCI_VENDOR_ID_ATI:
ad93562b AX	185	/* AMD PLL quirk */
	186	if (usb_amd_find_chipset_info())
	187	ehci->amd_pll_fix = 1;
1a49e2ac AS	188
	189	/*
	190	* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
	191	* read/write memory space which does not belong to it when
	192	* there is NULL pointer with T-bit set to 1 in the frame list
	193	* table. To avoid the issue, the frame list link pointer
	194	* should always contain a valid pointer to a inactive qh.
	195	*/
	196	if (pdev->device == 0x4396) {
	197	ehci->use_dummy_qh = 1;
	198	ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
	199	}
0a99e8ac	200	/* SB600 and old version of SB700 have a bug in EHCI controller,
b09bc6cb AX	201	* which causes usb devices lose response in some cases.
b09bc6cb AX	202	*/
0a99e8ac	203	if ((pdev->device == 0x4386) \|\| (pdev->device == 0x4396)) {
b09bc6cb AX	204	p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
	205	PCI_DEVICE_ID_ATI_SBX00_SMBUS,
	206	NULL);
	207	if (!p_smbus)
	208	break;
	209	rev = p_smbus->revision;
0a99e8ac SH	210	if ((pdev->device == 0x4386) \|\| (rev == 0x3a)
0a99e8ac SH	211	\|\| (rev == 0x3b)) {
b09bc6cb	212	u8 tmp;
0a99e8ac SH	213	ehci_info(ehci, "applying AMD SB600/SB700 USB "
0a99e8ac SH	214	"freeze workaround\n");
b09bc6cb AX	215	pci_read_config_byte(pdev, 0x53, &tmp);
	216	pci_write_config_byte(pdev, 0x53, tmp \| (1<<3));
	217	}
	218	pci_dev_put(p_smbus);
	219	}
	220	break;
68aa95d5 AS	221	case PCI_VENDOR_ID_NETMOS:
	222	/* MosChip frame-index-register bug */
	223	ehci_info(ehci, "applying MosChip frame-index workaround\n");
	224	ehci->frame_index_bug = 1;
	225	break;
abcc9448	226	}
7ff71d6a	227
75e1a2ae JB	228	/* optional debug port, normally in the first BAR */
	229	temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
	230	if (temp) {
	231	pci_read_config_dword(pdev, temp, &temp);
	232	temp >>= 16;
	233	if (((temp >> 13) & 7) == 1) {
	234	u32 hcs_params = ehci_readl(ehci,
	235	&ehci->caps->hcs_params);
	236
	237	temp &= 0x1fff;
	238	ehci->debug = hcd->regs + temp;
	239	temp = ehci_readl(ehci, &ehci->debug->control);
	240	ehci_info(ehci, "debug port %d%s\n",
	241	HCS_DEBUG_PORT(hcs_params),
	242	(temp & DBGP_ENABLED) ? " IN USE" : "");
	243	if (!(temp & DBGP_ENABLED))
	244	ehci->debug = NULL;
	245	}
	246	}
	247
1a49e2ac AS	248	retval = ehci_setup(hcd);
	249	if (retval)
	250	return retval;
	251
	252	/* These workarounds need to be applied after ehci_setup() */
	253	switch (pdev->vendor) {
	254	case PCI_VENDOR_ID_NEC:
	255	ehci->need_io_watchdog = 0;
	256	break;
	257	case PCI_VENDOR_ID_INTEL:
	258	ehci->need_io_watchdog = 0;
1a49e2ac AS	259	break;
	260	case PCI_VENDOR_ID_NVIDIA:
	261	switch (pdev->device) {
	262	/* MCP89 chips on the MacBookAir3,1 give EPROTO when
	263	* fetching device descriptors unless LPM is disabled.
	264	* There are also intermittent problems enumerating
	265	* devices with PPCD enabled.
	266	*/
	267	case 0x0d9d:
4968f951	268	ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
1a49e2ac AS	269	ehci->has_ppcd = 0;
	270	ehci->command &= ~CMD_PPCEE;
	271	break;
	272	}
	273	break;
	274	}
	275
7ff71d6a MP	276	/* at least the Genesys GL880S needs fixup here */
	277	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	278	temp &= 0x0f;
	279	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
abcc9448	280	ehci_dbg(ehci, "bogus port configuration: "
7ff71d6a MP	281	"cc=%d x pcc=%d < ports=%d\n",
	282	HCS_N_CC(ehci->hcs_params),
	283	HCS_N_PCC(ehci->hcs_params),
	284	HCS_N_PORTS(ehci->hcs_params));
	285
abcc9448 DB	286	switch (pdev->vendor) {
	287	case 0x17a0: /* GENESYS */
	288	/* GL880S: should be PORTS=2 */
	289	temp \|= (ehci->hcs_params & ~0xf);
	290	ehci->hcs_params = temp;
	291	break;
	292	case PCI_VENDOR_ID_NVIDIA:
	293	/* NF4: should be PCC=10 */
	294	break;
7ff71d6a MP	295	}
	296	}
	297
abcc9448	298	/* Serial Bus Release Number is at PCI 0x60 offset */
3a0bac06 AR	299	if (pdev->vendor == PCI_VENDOR_ID_STMICRO
3a0bac06 AR	300	&& pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
1a49e2ac AS	301	; /* ConneXT has no sbrn register */
	302	else
	303	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
7ff71d6a	304
6fd9086a AS	305	/* Keep this around for a while just in case some EHCI
	306	* implementation uses legacy PCI PM support. This test
	307	* can be removed on 17 Dec 2009 if the dev_warn() hasn't
	308	* been triggered by then.
2c1c3c4c DB	309	*/
	310	if (!device_can_wakeup(&pdev->dev)) {
	311	u16 port_wake;
	312
	313	pci_read_config_word(pdev, 0x62, &port_wake);
6fd9086a AS	314	if (port_wake & 0x0001) {
6fd9086a AS	315	dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
bcca06ef	316	device_set_wakeup_capable(&pdev->dev, 1);
6fd9086a	317	}
2c1c3c4c	318	}
7ff71d6a	319
84ebc102	320	#ifdef CONFIG_PM_RUNTIME
f8aeb3bb DB	321	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
	322	ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
	323	#endif
	324
18807521	325	retval = ehci_pci_reinit(ehci, pdev);
8926bfa7 DB	326	done:
8926bfa7 DB	327	return retval;
7ff71d6a MP	328	}
	329
	330	/-------------------------------------------------------------------------/
	331
	332	#ifdef CONFIG_PM
	333
	334	/* suspend/resume, section 4.3 */
	335
f03c17fc	336	/* These routines rely on the PCI bus glue
7ff71d6a MP	337	* to handle powerdown and wakeup, and currently also on
	338	* transceivers that don't need any software attention to set up
	339	* the right sort of wakeup.
f03c17fc	340	* Also they depend on separate root hub suspend/resume.
7ff71d6a MP	341	*/
7ff71d6a MP	342
69e848c2 SS	343	static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
	344	{
	345	return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
	346	pdev->vendor == PCI_VENDOR_ID_INTEL &&
1c12443a SS	347	(pdev->device == 0x1E26 \|\|
1c12443a SS	348	pdev->device == 0x8C2D \|\|
bb1e5dd7 RW	349	pdev->device == 0x8C26 \|\|
bb1e5dd7 RW	350	pdev->device == 0x9C26);
69e848c2 SS	351	}
	352
	353	static void ehci_enable_xhci_companion(void)
	354	{
	355	struct pci_dev *companion = NULL;
	356
	357	/* The xHCI and EHCI controllers are not on the same PCI slot */
	358	for_each_pci_dev(companion) {
	359	if (!usb_is_intel_switchable_xhci(companion))
	360	continue;
	361	usb_enable_xhci_ports(companion);
	362	return;
	363	}
	364	}
	365
6ec4beb5	366	static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
7ff71d6a	367	{
abcc9448	368	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
18807521	369	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	370
69e848c2 SS	371	/* The BIOS on systems with the Intel Panther Point chipset may or may
	372	* not support xHCI natively. That means that during system resume, it
	373	* may switch the ports back to EHCI so that users can use their
	374	* keyboard to select a kernel from GRUB after resume from hibernate.
	375	*
	376	* The BIOS is supposed to remember whether the OS had xHCI ports
	377	* enabled before resume, and switch the ports back to xHCI when the
	378	* BIOS/OS semaphore is written, but we all know we can't trust BIOS
	379	* writers.
	380	*
	381	* Unconditionally switch the ports back to xHCI after a system resume.
	382	* We can't tell whether the EHCI or xHCI controller will be resumed
	383	* first, so we have to do the port switchover in both drivers. Writing
	384	* a '1' to the port switchover registers should have no effect if the
	385	* port was already switched over.
	386	*/
	387	if (usb_is_intel_switchable_ehci(pdev))
	388	ehci_enable_xhci_companion();
	389
c5cf9212 AS	390	if (ehci_resume(hcd, hibernated) != 0)
c5cf9212 AS	391	(void) ehci_pci_reinit(ehci, pdev);
8c03356a	392	return 0;
7ff71d6a	393	}
7ff71d6a	394
adfa79d1	395	#else
7ff71d6a	396
adfa79d1 AS	397	#define ehci_suspend NULL
	398	#define ehci_pci_resume NULL
	399	#endif /* CONFIG_PM */
7ff71d6a	400
adfa79d1	401	static struct hc_driver __read_mostly ehci_pci_hc_driver;
7ff71d6a	402
62d08a11	403	static const struct ehci_driver_overrides pci_overrides __initconst = {
adfa79d1	404	.reset = ehci_pci_setup,
7ff71d6a MP	405	};
	406
	407	/-------------------------------------------------------------------------/
	408
	409	/* PCI driver selection metadata; PCI hotplugging uses this */
	410	static const struct pci_device_id pci_ids [] = { {
	411	/* handle any USB 2.0 EHCI controller */
c67808ee	412	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
7ff71d6a	413	.driver_data = (unsigned long) &ehci_pci_hc_driver,
3a0bac06 AR	414	}, {
	415	PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
	416	.driver_data = (unsigned long) &ehci_pci_hc_driver,
7ff71d6a MP	417	},
	418	{ /* end: all zeroes */ }
	419	};
abcc9448	420	MODULE_DEVICE_TABLE(pci, pci_ids);
7ff71d6a MP	421
	422	/* pci driver glue; this is a "new style" PCI driver module */
	423	static struct pci_driver ehci_pci_driver = {
	424	.name = (char *) hcd_name,
	425	.id_table = pci_ids,
	426
	427	.probe = usb_hcd_pci_probe,
	428	.remove = usb_hcd_pci_remove,
abb30641	429	.shutdown = usb_hcd_pci_shutdown,
7ff71d6a	430
c9dd3462	431	#ifdef CONFIG_PM
abb30641 AS	432	.driver = {
	433	.pm = &usb_hcd_pci_pm_ops
	434	},
7ff71d6a MP	435	#endif
7ff71d6a MP	436	};
adfa79d1 AS	437
	438	static int __init ehci_pci_init(void)
	439	{
	440	if (usb_disabled())
	441	return -ENODEV;
	442
	443	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
	444
1b36810e	445	ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
adfa79d1 AS	446
	447	/* Entries for the PCI suspend/resume callbacks are special */
	448	ehci_pci_hc_driver.pci_suspend = ehci_suspend;
	449	ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
	450
	451	return pci_register_driver(&ehci_pci_driver);
	452	}
	453	module_init(ehci_pci_init);
	454
	455	static void __exit ehci_pci_cleanup(void)
	456	{
	457	pci_unregister_driver(&ehci_pci_driver);
	458	}
	459	module_exit(ehci_pci_cleanup);
	460
	461	MODULE_DESCRIPTION(DRIVER_DESC);
	462	MODULE_AUTHOR("David Brownell");
	463	MODULE_AUTHOR("Alan Stern");
	464	MODULE_LICENSE("GPL");