[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / usb / host / ehci-pci.c

/*
 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
 *
 * Copyright (c) 2000-2004 by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>

#include "ehci.h"
#include "pci-quirks.h"

#define DRIVER_DESC "EHCI PCI platform driver"

static const char hcd_name[] = "ehci-pci";

/* defined here to avoid adding to pci_ids.h for single instance use */
#define PCI_DEVICE_ID_INTEL_CE4100_USB	0x2e70

/*-------------------------------------------------------------------------*/
#define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC		0x0939
static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
{
	return pdev->vendor == PCI_VENDOR_ID_INTEL &&
		pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
}

/*
 * This is the list of PCI IDs for the devices that have EHCI USB class and
 * specific drivers for that. One of the example is a ChipIdea device installed
 * on some Intel MID platforms.
 */
static const struct pci_device_id bypass_pci_id_table[] = {
	/* ChipIdea on Intel MID platform */
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), },
	{}
};

static inline bool is_bypassed_id(struct pci_dev *pdev)
{
	return !!pci_match_id(bypass_pci_id_table, pdev);
}

/*
 * 0x84 is the offset of in/out threshold register,
 * and it is the same offset as the register of 'hostpc'.
 */
#define	intel_quark_x1000_insnreg01	hostpc

/* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
#define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD	0x007f007f

/* called after powerup, by probe or system-pm "wakeup" */
static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
{
	int			retval;

	/* we expect static quirk code to handle the "extended capabilities"
	 * (currently just BIOS handoff) allowed starting with EHCI 0.96
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	retval = pci_set_mwi(pdev);
	if (!retval)
		ehci_dbg(ehci, "MWI active\n");

	/* Reset the threshold limit */
	if (is_intel_quark_x1000(pdev)) {
		/*
		 * For the Intel QUARK X1000, raise the I/O threshold to the
		 * maximum usable value in order to improve performance.
		 */
		ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
			ehci->regs->intel_quark_x1000_insnreg01);
	}

	return 0;
}

/* called during probe() after chip reset completes */
static int ehci_pci_setup(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	u32			temp;
	int			retval;

	ehci->caps = hcd->regs;

	/*
	 * ehci_init() causes memory for DMA transfers to be
	 * allocated.  Thus, any vendor-specific workarounds based on
	 * limiting the type of memory used for DMA transfers must
	 * happen before ehci_setup() is called.
	 *
	 * Most other workarounds can be done either before or after
	 * init and reset; they are located here too.
	 */
	switch (pdev->vendor) {
	case PCI_VENDOR_ID_TOSHIBA_2:
		/* celleb's companion chip */
		if (pdev->device == 0x01b5) {
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
			ehci->big_endian_mmio = 1;
#else
			ehci_warn(ehci,
				  "unsupported big endian Toshiba quirk\n");
#endif
		}
		break;
	case PCI_VENDOR_ID_NVIDIA:
		/* NVidia reports that certain chips don't handle
		 * QH, ITD, or SITD addresses above 2GB.  (But TD,
		 * data buffer, and periodic schedule are normal.)
		 */
		switch (pdev->device) {
		case 0x003c:	/* MCP04 */
		case 0x005b:	/* CK804 */
		case 0x00d8:	/* CK8 */
		case 0x00e8:	/* CK8S */
			if (pci_set_consistent_dma_mask(pdev,
						DMA_BIT_MASK(31)) < 0)
				ehci_warn(ehci, "can't enable NVidia "
					"workaround for >2GB RAM\n");
			break;

		/* Some NForce2 chips have problems with selective suspend;
		 * fixed in newer silicon.
		 */
		case 0x0068:
			if (pdev->revision < 0xa4)
				ehci->no_selective_suspend = 1;
			break;
		}
		break;
	case PCI_VENDOR_ID_INTEL:
		if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
			hcd->has_tt = 1;
		break;
	case PCI_VENDOR_ID_TDI:
		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
			hcd->has_tt = 1;
		break;
	case PCI_VENDOR_ID_AMD:
		/* AMD PLL quirk */
		if (usb_amd_find_chipset_info())
			ehci->amd_pll_fix = 1;
		/* AMD8111 EHCI doesn't work, according to AMD errata */
		if (pdev->device == 0x7463) {
			ehci_info(ehci, "ignoring AMD8111 (errata)\n");
			retval = -EIO;
			goto done;
		}

		/*
		 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
		 * read/write memory space which does not belong to it when
		 * there is NULL pointer with T-bit set to 1 in the frame list
		 * table. To avoid the issue, the frame list link pointer
		 * should always contain a valid pointer to a inactive qh.
		 */
		if (pdev->device == 0x7808) {
			ehci->use_dummy_qh = 1;
			ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
		}
		break;
	case PCI_VENDOR_ID_VIA:
		if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
			u8 tmp;

			/* The VT6212 defaults to a 1 usec EHCI sleep time which
			 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
			 * that sleep time use the conventional 10 usec.
			 */
			pci_read_config_byte(pdev, 0x4b, &tmp);
			if (tmp & 0x20)
				break;
			pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
		}
		break;
	case PCI_VENDOR_ID_ATI:
		/* AMD PLL quirk */
		if (usb_amd_find_chipset_info())
			ehci->amd_pll_fix = 1;

		/*
		 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
		 * read/write memory space which does not belong to it when
		 * there is NULL pointer with T-bit set to 1 in the frame list
		 * table. To avoid the issue, the frame list link pointer
		 * should always contain a valid pointer to a inactive qh.
		 */
		if (pdev->device == 0x4396) {
			ehci->use_dummy_qh = 1;
			ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
		}
		/* SB600 and old version of SB700 have a bug in EHCI controller,
		 * which causes usb devices lose response in some cases.
		 */
		if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&
				usb_amd_hang_symptom_quirk()) {
			u8 tmp;
			ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
			pci_read_config_byte(pdev, 0x53, &tmp);
			pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
		}
		break;
	case PCI_VENDOR_ID_NETMOS:
		/* MosChip frame-index-register bug */
		ehci_info(ehci, "applying MosChip frame-index workaround\n");
		ehci->frame_index_bug = 1;
		break;
	}

	/* optional debug port, normally in the first BAR */
	temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
	if (temp) {
		pci_read_config_dword(pdev, temp, &temp);
		temp >>= 16;
		if (((temp >> 13) & 7) == 1) {
			u32 hcs_params = ehci_readl(ehci,
						    &ehci->caps->hcs_params);

			temp &= 0x1fff;
			ehci->debug = hcd->regs + temp;
			temp = ehci_readl(ehci, &ehci->debug->control);
			ehci_info(ehci, "debug port %d%s\n",
				  HCS_DEBUG_PORT(hcs_params),
				  (temp & DBGP_ENABLED) ? " IN USE" : "");
			if (!(temp & DBGP_ENABLED))
				ehci->debug = NULL;
		}
	}

	retval = ehci_setup(hcd);
	if (retval)
		return retval;

	/* These workarounds need to be applied after ehci_setup() */
	switch (pdev->vendor) {
	case PCI_VENDOR_ID_NEC:
	case PCI_VENDOR_ID_INTEL:
	case PCI_VENDOR_ID_AMD:
		ehci->need_io_watchdog = 0;
		break;
	case PCI_VENDOR_ID_NVIDIA:
		switch (pdev->device) {
		/* MCP89 chips on the MacBookAir3,1 give EPROTO when
		 * fetching device descriptors unless LPM is disabled.
		 * There are also intermittent problems enumerating
		 * devices with PPCD enabled.
		 */
		case 0x0d9d:
			ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
			ehci->has_ppcd = 0;
			ehci->command &= ~CMD_PPCEE;
			break;
		}
		break;
	}

	/* at least the Genesys GL880S needs fixup here */
	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	temp &= 0x0f;
	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
		ehci_dbg(ehci, "bogus port configuration: "
			"cc=%d x pcc=%d < ports=%d\n",
			HCS_N_CC(ehci->hcs_params),
			HCS_N_PCC(ehci->hcs_params),
			HCS_N_PORTS(ehci->hcs_params));

		switch (pdev->vendor) {
		case 0x17a0:		/* GENESYS */
			/* GL880S: should be PORTS=2 */
			temp |= (ehci->hcs_params & ~0xf);
			ehci->hcs_params = temp;
			break;
		case PCI_VENDOR_ID_NVIDIA:
			/* NF4: should be PCC=10 */
			break;
		}
	}

	/* Serial Bus Release Number is at PCI 0x60 offset */
	if (pdev->vendor == PCI_VENDOR_ID_STMICRO
	    && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
		;	/* ConneXT has no sbrn register */
	else
		pci_read_config_byte(pdev, 0x60, &ehci->sbrn);

	/* Keep this around for a while just in case some EHCI
	 * implementation uses legacy PCI PM support.  This test
	 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
	 * been triggered by then.
	 */
	if (!device_can_wakeup(&pdev->dev)) {
		u16	port_wake;

		pci_read_config_word(pdev, 0x62, &port_wake);
		if (port_wake & 0x0001) {
			dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
			device_set_wakeup_capable(&pdev->dev, 1);
		}
	}

#ifdef	CONFIG_PM
	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
		ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
#endif

	retval = ehci_pci_reinit(ehci, pdev);
done:
	return retval;
}

/*-------------------------------------------------------------------------*/

#ifdef	CONFIG_PM

/* suspend/resume, section 4.3 */

/* These routines rely on the PCI bus glue
 * to handle powerdown and wakeup, and currently also on
 * transceivers that don't need any software attention to set up
 * the right sort of wakeup.
 * Also they depend on separate root hub suspend/resume.
 */

static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	if (ehci_resume(hcd, hibernated) != 0)
		(void) ehci_pci_reinit(ehci, pdev);
	return 0;
}

#else

#define ehci_suspend		NULL
#define ehci_pci_resume		NULL
#endif	/* CONFIG_PM */

static struct hc_driver __read_mostly ehci_pci_hc_driver;

static const struct ehci_driver_overrides pci_overrides __initconst = {
	.reset =		ehci_pci_setup,
};

/*-------------------------------------------------------------------------*/

static int ehci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	if (is_bypassed_id(pdev))
		return -ENODEV;
	return usb_hcd_pci_probe(pdev, id);
}

static void ehci_pci_remove(struct pci_dev *pdev)
{
	pci_clear_mwi(pdev);
	usb_hcd_pci_remove(pdev);	
}

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids [] = { {
	/* handle any USB 2.0 EHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
	.driver_data =	(unsigned long) &ehci_pci_hc_driver,
	}, {
	PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
	.driver_data = (unsigned long) &ehci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver ehci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	ehci_pci_probe,
	.remove =	ehci_pci_remove,
	.shutdown = 	usb_hcd_pci_shutdown,

#ifdef CONFIG_PM
	.driver =	{
		.pm =	&usb_hcd_pci_pm_ops
	},
#endif
};

static int __init ehci_pci_init(void)
{
	if (usb_disabled())
		return -ENODEV;

	pr_info("%s: " DRIVER_DESC "\n", hcd_name);

	ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);

	/* Entries for the PCI suspend/resume callbacks are special */
	ehci_pci_hc_driver.pci_suspend = ehci_suspend;
	ehci_pci_hc_driver.pci_resume = ehci_pci_resume;

	return pci_register_driver(&ehci_pci_driver);
}
module_init(ehci_pci_init);

static void __exit ehci_pci_cleanup(void)
{
	pci_unregister_driver(&ehci_pci_driver);
}
module_exit(ehci_pci_cleanup);

MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_AUTHOR("David Brownell");
MODULE_AUTHOR("Alan Stern");
MODULE_LICENSE("GPL");
Commit	Line	Data
7ff71d6a MP	1	/*
	2	* EHCI HCD (Host Controller Driver) PCI Bus Glue.
	3	*
	4	* Copyright (c) 2000-2004 by David Brownell
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	* for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software Foundation,
	18	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
adfa79d1 AS	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/pci.h>
	24	#include <linux/usb.h>
	25	#include <linux/usb/hcd.h>
	26
	27	#include "ehci.h"
	28	#include "pci-quirks.h"
	29
	30	#define DRIVER_DESC "EHCI PCI platform driver"
	31
	32	static const char hcd_name[] = "ehci-pci";
7ff71d6a	33
4f683843 DB	34	/* defined here to avoid adding to pci_ids.h for single instance use */
	35	#define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
	36
7ff71d6a	37	/-------------------------------------------------------------------------/
6e693739 BD	38	#define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC 0x0939
	39	static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
	40	{
	41	return pdev->vendor == PCI_VENDOR_ID_INTEL &&
	42	pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
	43	}
	44
518ca8d9 AS	45	/*
	46	* This is the list of PCI IDs for the devices that have EHCI USB class and
	47	* specific drivers for that. One of the example is a ChipIdea device installed
	48	* on some Intel MID platforms.
	49	*/
	50	static const struct pci_device_id bypass_pci_id_table[] = {
	51	/* ChipIdea on Intel MID platform */
cefa9a31 AS	52	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), },
	53	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), },
	54	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), },
	55	{}
	56	};
	57
518ca8d9	58	static inline bool is_bypassed_id(struct pci_dev *pdev)
cefa9a31	59	{
518ca8d9	60	return !!pci_match_id(bypass_pci_id_table, pdev);
cefa9a31 AS	61	}
cefa9a31 AS	62
6e693739 BD	63	/*
	64	* 0x84 is the offset of in/out threshold register,
	65	* and it is the same offset as the register of 'hostpc'.
	66	*/
	67	#define intel_quark_x1000_insnreg01 hostpc
	68
	69	/* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
	70	#define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD 0x007f007f
7ff71d6a	71
18807521 DB	72	/* called after powerup, by probe or system-pm "wakeup" */
	73	static int ehci_pci_reinit(struct ehci_hcd ehci, struct pci_dev pdev)
	74	{
18807521	75	int retval;
18807521	76
401feafa DB	77	/* we expect static quirk code to handle the "extended capabilities"
	78	* (currently just BIOS handoff) allowed starting with EHCI 0.96
	79	*/
18807521 DB	80
	81	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	82	retval = pci_set_mwi(pdev);
	83	if (!retval)
	84	ehci_dbg(ehci, "MWI active\n");
	85
6e693739 BD	86	/* Reset the threshold limit */
	87	if (is_intel_quark_x1000(pdev)) {
	88	/*
	89	* For the Intel QUARK X1000, raise the I/O threshold to the
	90	* maximum usable value in order to improve performance.
	91	*/
	92	ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
	93	ehci->regs->intel_quark_x1000_insnreg01);
	94	}
	95
18807521 DB	96	return 0;
	97	}
	98
8926bfa7 DB	99	/* called during probe() after chip reset completes */
8926bfa7 DB	100	static int ehci_pci_setup(struct usb_hcd *hcd)
7ff71d6a	101	{
abcc9448 DB	102	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
abcc9448 DB	103	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	104	u32 temp;
18807521	105	int retval;
7ff71d6a	106
1a49e2ac AS	107	ehci->caps = hcd->regs;
	108
	109	/*
	110	* ehci_init() causes memory for DMA transfers to be
	111	* allocated. Thus, any vendor-specific workarounds based on
	112	* limiting the type of memory used for DMA transfers must
	113	* happen before ehci_setup() is called.
	114	*
	115	* Most other workarounds can be done either before or after
	116	* init and reset; they are located here too.
	117	*/
083522d7 BH	118	switch (pdev->vendor) {
	119	case PCI_VENDOR_ID_TOSHIBA_2:
	120	/* celleb's companion chip */
	121	if (pdev->device == 0x01b5) {
	122	#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
	123	ehci->big_endian_mmio = 1;
	124	#else
	125	ehci_warn(ehci,
	126	"unsupported big endian Toshiba quirk\n");
	127	#endif
	128	}
	129	break;
c32ba30f PS	130	case PCI_VENDOR_ID_NVIDIA:
	131	/* NVidia reports that certain chips don't handle
	132	* QH, ITD, or SITD addresses above 2GB. (But TD,
	133	* data buffer, and periodic schedule are normal.)
	134	*/
	135	switch (pdev->device) {
	136	case 0x003c: /* MCP04 */
	137	case 0x005b: /* CK804 */
	138	case 0x00d8: /* CK8 */
	139	case 0x00e8: /* CK8S */
	140	if (pci_set_consistent_dma_mask(pdev,
929a22a5	141	DMA_BIT_MASK(31)) < 0)
c32ba30f PS	142	ehci_warn(ehci, "can't enable NVidia "
	143	"workaround for >2GB RAM\n");
	144	break;
7ff71d6a	145
1a49e2ac AS	146	/* Some NForce2 chips have problems with selective suspend;
1a49e2ac AS	147	* fixed in newer silicon.
3d091a6f	148	*/
1a49e2ac AS	149	case 0x0068:
	150	if (pdev->revision < 0xa4)
	151	ehci->no_selective_suspend = 1;
	152	break;
	153	}
3681d8f3	154	break;
403dbd36	155	case PCI_VENDOR_ID_INTEL:
1a49e2ac	156	if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
4f683843	157	hcd->has_tt = 1;
403dbd36	158	break;
abcc9448	159	case PCI_VENDOR_ID_TDI:
1a49e2ac	160	if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
7329e211	161	hcd->has_tt = 1;
abcc9448 DB	162	break;
abcc9448 DB	163	case PCI_VENDOR_ID_AMD:
ad93562b AX	164	/* AMD PLL quirk */
	165	if (usb_amd_find_chipset_info())
	166	ehci->amd_pll_fix = 1;
abcc9448 DB	167	/* AMD8111 EHCI doesn't work, according to AMD errata */
	168	if (pdev->device == 0x7463) {
	169	ehci_info(ehci, "ignoring AMD8111 (errata)\n");
8926bfa7 DB	170	retval = -EIO;
8926bfa7 DB	171	goto done;
abcc9448	172	}
a85b4e7f	173
1a49e2ac AS	174	/*
	175	* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
	176	* read/write memory space which does not belong to it when
	177	* there is NULL pointer with T-bit set to 1 in the frame list
	178	* table. To avoid the issue, the frame list link pointer
	179	* should always contain a valid pointer to a inactive qh.
a85b4e7f	180	*/
1a49e2ac AS	181	if (pdev->device == 0x7808) {
	182	ehci->use_dummy_qh = 1;
	183	ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
7ff71d6a	184	}
abcc9448	185	break;
055b93c9 RH	186	case PCI_VENDOR_ID_VIA:
	187	if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
	188	u8 tmp;
	189
	190	/* The VT6212 defaults to a 1 usec EHCI sleep time which
	191	* hogs the PCI bus badly. Setting bit 5 of 0x4B makes
	192	* that sleep time use the conventional 10 usec.
	193	*/
	194	pci_read_config_byte(pdev, 0x4b, &tmp);
	195	if (tmp & 0x20)
	196	break;
	197	pci_write_config_byte(pdev, 0x4b, tmp \| 0x20);
	198	}
	199	break;
b09bc6cb	200	case PCI_VENDOR_ID_ATI:
ad93562b AX	201	/* AMD PLL quirk */
	202	if (usb_amd_find_chipset_info())
	203	ehci->amd_pll_fix = 1;
1a49e2ac AS	204
	205	/*
	206	* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
	207	* read/write memory space which does not belong to it when
	208	* there is NULL pointer with T-bit set to 1 in the frame list
	209	* table. To avoid the issue, the frame list link pointer
	210	* should always contain a valid pointer to a inactive qh.
	211	*/
	212	if (pdev->device == 0x4396) {
	213	ehci->use_dummy_qh = 1;
	214	ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
	215	}
0a99e8ac	216	/* SB600 and old version of SB700 have a bug in EHCI controller,
b09bc6cb AX	217	* which causes usb devices lose response in some cases.
b09bc6cb AX	218	*/
3ad145b6 HR	219	if ((pdev->device == 0x4386 \|\| pdev->device == 0x4396) &&
	220	usb_amd_hang_symptom_quirk()) {
	221	u8 tmp;
	222	ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
	223	pci_read_config_byte(pdev, 0x53, &tmp);
	224	pci_write_config_byte(pdev, 0x53, tmp \| (1<<3));
b09bc6cb AX	225	}
b09bc6cb AX	226	break;
68aa95d5 AS	227	case PCI_VENDOR_ID_NETMOS:
	228	/* MosChip frame-index-register bug */
	229	ehci_info(ehci, "applying MosChip frame-index workaround\n");
	230	ehci->frame_index_bug = 1;
	231	break;
abcc9448	232	}
7ff71d6a	233
75e1a2ae JB	234	/* optional debug port, normally in the first BAR */
	235	temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
	236	if (temp) {
	237	pci_read_config_dword(pdev, temp, &temp);
	238	temp >>= 16;
	239	if (((temp >> 13) & 7) == 1) {
	240	u32 hcs_params = ehci_readl(ehci,
	241	&ehci->caps->hcs_params);
	242
	243	temp &= 0x1fff;
	244	ehci->debug = hcd->regs + temp;
	245	temp = ehci_readl(ehci, &ehci->debug->control);
	246	ehci_info(ehci, "debug port %d%s\n",
	247	HCS_DEBUG_PORT(hcs_params),
	248	(temp & DBGP_ENABLED) ? " IN USE" : "");
	249	if (!(temp & DBGP_ENABLED))
	250	ehci->debug = NULL;
	251	}
	252	}
	253
1a49e2ac AS	254	retval = ehci_setup(hcd);
	255	if (retval)
	256	return retval;
	257
	258	/* These workarounds need to be applied after ehci_setup() */
	259	switch (pdev->vendor) {
	260	case PCI_VENDOR_ID_NEC:
1a49e2ac	261	case PCI_VENDOR_ID_INTEL:
5c2ad982	262	case PCI_VENDOR_ID_AMD:
1a49e2ac	263	ehci->need_io_watchdog = 0;
1a49e2ac AS	264	break;
	265	case PCI_VENDOR_ID_NVIDIA:
	266	switch (pdev->device) {
	267	/* MCP89 chips on the MacBookAir3,1 give EPROTO when
	268	* fetching device descriptors unless LPM is disabled.
	269	* There are also intermittent problems enumerating
	270	* devices with PPCD enabled.
	271	*/
	272	case 0x0d9d:
4968f951	273	ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
1a49e2ac AS	274	ehci->has_ppcd = 0;
	275	ehci->command &= ~CMD_PPCEE;
	276	break;
	277	}
	278	break;
	279	}
	280
7ff71d6a MP	281	/* at least the Genesys GL880S needs fixup here */
	282	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	283	temp &= 0x0f;
	284	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
abcc9448	285	ehci_dbg(ehci, "bogus port configuration: "
7ff71d6a MP	286	"cc=%d x pcc=%d < ports=%d\n",
	287	HCS_N_CC(ehci->hcs_params),
	288	HCS_N_PCC(ehci->hcs_params),
	289	HCS_N_PORTS(ehci->hcs_params));
	290
abcc9448 DB	291	switch (pdev->vendor) {
	292	case 0x17a0: /* GENESYS */
	293	/* GL880S: should be PORTS=2 */
	294	temp \|= (ehci->hcs_params & ~0xf);
	295	ehci->hcs_params = temp;
	296	break;
	297	case PCI_VENDOR_ID_NVIDIA:
	298	/* NF4: should be PCC=10 */
	299	break;
7ff71d6a MP	300	}
	301	}
	302
abcc9448	303	/* Serial Bus Release Number is at PCI 0x60 offset */
3a0bac06 AR	304	if (pdev->vendor == PCI_VENDOR_ID_STMICRO
3a0bac06 AR	305	&& pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
1a49e2ac AS	306	; /* ConneXT has no sbrn register */
	307	else
	308	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
7ff71d6a	309
6fd9086a AS	310	/* Keep this around for a while just in case some EHCI
	311	* implementation uses legacy PCI PM support. This test
	312	* can be removed on 17 Dec 2009 if the dev_warn() hasn't
	313	* been triggered by then.
2c1c3c4c DB	314	*/
	315	if (!device_can_wakeup(&pdev->dev)) {
	316	u16 port_wake;
	317
	318	pci_read_config_word(pdev, 0x62, &port_wake);
6fd9086a AS	319	if (port_wake & 0x0001) {
6fd9086a AS	320	dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
bcca06ef	321	device_set_wakeup_capable(&pdev->dev, 1);
6fd9086a	322	}
2c1c3c4c	323	}
7ff71d6a	324
ceb6c9c8	325	#ifdef CONFIG_PM
f8aeb3bb DB	326	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
	327	ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
	328	#endif
	329
18807521	330	retval = ehci_pci_reinit(ehci, pdev);
8926bfa7 DB	331	done:
8926bfa7 DB	332	return retval;
7ff71d6a MP	333	}
	334
	335	/-------------------------------------------------------------------------/
	336
	337	#ifdef CONFIG_PM
	338
	339	/* suspend/resume, section 4.3 */
	340
f03c17fc	341	/* These routines rely on the PCI bus glue
7ff71d6a MP	342	* to handle powerdown and wakeup, and currently also on
	343	* transceivers that don't need any software attention to set up
	344	* the right sort of wakeup.
f03c17fc	345	* Also they depend on separate root hub suspend/resume.
7ff71d6a MP	346	*/
7ff71d6a MP	347
6ec4beb5	348	static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
7ff71d6a	349	{
abcc9448	350	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
18807521	351	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	352
c5cf9212 AS	353	if (ehci_resume(hcd, hibernated) != 0)
c5cf9212 AS	354	(void) ehci_pci_reinit(ehci, pdev);
8c03356a	355	return 0;
7ff71d6a	356	}
7ff71d6a	357
adfa79d1	358	#else
7ff71d6a	359
adfa79d1 AS	360	#define ehci_suspend NULL
	361	#define ehci_pci_resume NULL
	362	#endif /* CONFIG_PM */
7ff71d6a	363
adfa79d1	364	static struct hc_driver __read_mostly ehci_pci_hc_driver;
7ff71d6a	365
62d08a11	366	static const struct ehci_driver_overrides pci_overrides __initconst = {
adfa79d1	367	.reset = ehci_pci_setup,
7ff71d6a MP	368	};
	369
	370	/-------------------------------------------------------------------------/
	371
cefa9a31 AS	372	static int ehci_pci_probe(struct pci_dev pdev, const struct pci_device_id id)
cefa9a31 AS	373	{
518ca8d9	374	if (is_bypassed_id(pdev))
cefa9a31 AS	375	return -ENODEV;
	376	return usb_hcd_pci_probe(pdev, id);
	377	}
	378
e3e2e36c JJB	379	static void ehci_pci_remove(struct pci_dev *pdev)
	380	{
	381	pci_clear_mwi(pdev);
	382	usb_hcd_pci_remove(pdev);
	383	}
	384
7ff71d6a MP	385	/* PCI driver selection metadata; PCI hotplugging uses this */
	386	static const struct pci_device_id pci_ids [] = { {
	387	/* handle any USB 2.0 EHCI controller */
c67808ee	388	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
7ff71d6a	389	.driver_data = (unsigned long) &ehci_pci_hc_driver,
3a0bac06 AR	390	}, {
	391	PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
	392	.driver_data = (unsigned long) &ehci_pci_hc_driver,
7ff71d6a MP	393	},
	394	{ /* end: all zeroes */ }
	395	};
abcc9448	396	MODULE_DEVICE_TABLE(pci, pci_ids);
7ff71d6a MP	397
	398	/* pci driver glue; this is a "new style" PCI driver module */
	399	static struct pci_driver ehci_pci_driver = {
	400	.name = (char *) hcd_name,
	401	.id_table = pci_ids,
	402
cefa9a31	403	.probe = ehci_pci_probe,
e3e2e36c	404	.remove = ehci_pci_remove,
abb30641	405	.shutdown = usb_hcd_pci_shutdown,
7ff71d6a	406
f875fdbf	407	#ifdef CONFIG_PM
abb30641 AS	408	.driver = {
	409	.pm = &usb_hcd_pci_pm_ops
	410	},
7ff71d6a MP	411	#endif
7ff71d6a MP	412	};
adfa79d1 AS	413
	414	static int __init ehci_pci_init(void)
	415	{
	416	if (usb_disabled())
	417	return -ENODEV;
	418
	419	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
	420
1b36810e	421	ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
adfa79d1 AS	422
	423	/* Entries for the PCI suspend/resume callbacks are special */
	424	ehci_pci_hc_driver.pci_suspend = ehci_suspend;
	425	ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
	426
	427	return pci_register_driver(&ehci_pci_driver);
	428	}
	429	module_init(ehci_pci_init);
	430
	431	static void __exit ehci_pci_cleanup(void)
	432	{
	433	pci_unregister_driver(&ehci_pci_driver);
	434	}
	435	module_exit(ehci_pci_cleanup);
	436
	437	MODULE_DESCRIPTION(DRIVER_DESC);
	438	MODULE_AUTHOR("David Brownell");
	439	MODULE_AUTHOR("Alan Stern");
	440	MODULE_LICENSE("GPL");