projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 58c559e6 | 1 | /* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc. |
| 80cb9aee RV |
2 | * Copyright (c) 2005 MontaVista Software |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify it | |
| 5 | * under the terms of the GNU General Public License as published by the | |
| 6 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 7 | * option) any later version. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, but | |
| 10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 12 | * General Public License for more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License along | |
| 15 | * with this program; if not, write to the Free Software Foundation, Inc., | |
| 16 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 17 | */ | |
| 18 | #ifndef _EHCI_FSL_H | |
| 19 | #define _EHCI_FSL_H | |
| 20 | ||
| 21 | /* offsets for the non-ehci registers in the FSL SOC USB controller */ | |
| 761bbcb7 AG |
22 | #define FSL_SOC_USB_SBUSCFG 0x90 |
| 23 | #define SBUSCFG_INCR8 0x02 /* INCR8, specified */ | |
| 80cb9aee RV |
24 | #define FSL_SOC_USB_ULPIVP 0x170 |
| 25 | #define FSL_SOC_USB_PORTSC1 0x184 | |
| 26 | #define PORT_PTS_MSK (3<<30) | |
| 27 | #define PORT_PTS_UTMI (0<<30) | |
| 28 | #define PORT_PTS_ULPI (2<<30) | |
| 29 | #define PORT_PTS_SERIAL (3<<30) | |
| 30 | #define PORT_PTS_PTW (1<<28) | |
| 31 | #define FSL_SOC_USB_PORTSC2 0x188 | |
| 13b7ee2a AG |
32 | #define FSL_SOC_USB_USBMODE 0x1a8 |
| 33 | #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ | |
| 34 | #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */ | |
| 35 | #define USBMODE_ES (1 << 2) /* (Big) Endian Select */ | |
| 230f7ede AG |
36 | |
| 37 | #define FSL_SOC_USB_USBGENCTRL 0x200 | |
| 38 | #define USBGENCTRL_PPP (1 << 3) | |
| 39 | #define USBGENCTRL_PFP (1 << 2) | |
| 40 | #define FSL_SOC_USB_ISIPHYCTRL 0x204 | |
| 41 | #define ISIPHYCTRL_PXE (1) | |
| 42 | #define ISIPHYCTRL_PHYE (1 << 4) | |
| 43 | ||
| 80cb9aee RV |
44 | #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ |
| 45 | #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ | |
| 46 | #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ | |
| 7378c57a CE |
47 | #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ |
| 48 | #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ | |
| 80cb9aee | 49 | #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ |
| 28c56ea1 | 50 | #define CTRL_UTMI_PHY_EN (1<<9) |
| 529febee | 51 | #define CTRL_PHY_CLK_VALID (1 << 17) |
| 40acc095 | 52 | #define SNOOP_SIZE_2GB 0x1e |
| 58c559e6 RM |
53 | |
| 54 | /* control Register Bit Masks */ | |
| 55 | #define ULPI_INT_EN (1<<0) | |
| 56 | #define WU_INT_EN (1<<1) | |
| 57 | #define USB_CTRL_USB_EN (1<<2) | |
| 58 | #define LINE_STATE_FILTER__EN (1<<3) | |
| 59 | #define KEEP_OTG_ON (1<<4) | |
| 60 | #define OTG_PORT (1<<5) | |
| 61 | #define PLL_RESET (1<<8) | |
| 62 | #define UTMI_PHY_EN (1<<9) | |
| 63 | #define ULPI_PHY_CLK_SEL (1<<10) | |
| 3735ba8d | 64 | #define PHY_CLK_VALID (1<<17) |
| 80cb9aee | 65 | #endif /* _EHCI_FSL_H */ |