Commit | Line | Data |
---|---|---|
5b7d70c6 | 1 | /* linux/drivers/usb/gadget/s3c-hsotg.c |
dfbc6fa3 AT |
2 | * |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5b7d70c6 BD |
5 | * |
6 | * Copyright 2008 Openmoko, Inc. | |
7 | * Copyright 2008 Simtec Electronics | |
8 | * Ben Dooks <ben@simtec.co.uk> | |
9 | * http://armlinux.simtec.co.uk/ | |
10 | * | |
11 | * S3C USB2.0 High-speed / OtG driver | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/seq_file.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/io.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
e50bf385 | 29 | #include <linux/clk.h> |
5b7d70c6 BD |
30 | |
31 | #include <linux/usb/ch9.h> | |
32 | #include <linux/usb/gadget.h> | |
33 | ||
34 | #include <mach/map.h> | |
35 | ||
36 | #include <plat/regs-usb-hsotg-phy.h> | |
37 | #include <plat/regs-usb-hsotg.h> | |
f9fed7cd | 38 | #include <mach/regs-sys.h> |
5b7d70c6 | 39 | #include <plat/udc-hs.h> |
4d47166c | 40 | #include <plat/cpu.h> |
5b7d70c6 BD |
41 | |
42 | #define DMA_ADDR_INVALID (~((dma_addr_t)0)) | |
43 | ||
44 | /* EP0_MPS_LIMIT | |
45 | * | |
46 | * Unfortunately there seems to be a limit of the amount of data that can | |
25985edc LDM |
47 | * be transferred by IN transactions on EP0. This is either 127 bytes or 3 |
48 | * packets (which practically means 1 packet and 63 bytes of data) when the | |
5b7d70c6 BD |
49 | * MPS is set to 64. |
50 | * | |
51 | * This means if we are wanting to move >127 bytes of data, we need to | |
52 | * split the transactions up, but just doing one packet at a time does | |
53 | * not work (this may be an implicit DATA0 PID on first packet of the | |
54 | * transaction) and doing 2 packets is outside the controller's limits. | |
55 | * | |
56 | * If we try to lower the MPS size for EP0, then no transfers work properly | |
57 | * for EP0, and the system will fail basic enumeration. As no cause for this | |
58 | * has currently been found, we cannot support any large IN transfers for | |
59 | * EP0. | |
60 | */ | |
61 | #define EP0_MPS_LIMIT 64 | |
62 | ||
63 | struct s3c_hsotg; | |
64 | struct s3c_hsotg_req; | |
65 | ||
66 | /** | |
67 | * struct s3c_hsotg_ep - driver endpoint definition. | |
68 | * @ep: The gadget layer representation of the endpoint. | |
69 | * @name: The driver generated name for the endpoint. | |
70 | * @queue: Queue of requests for this endpoint. | |
71 | * @parent: Reference back to the parent device structure. | |
72 | * @req: The current request that the endpoint is processing. This is | |
73 | * used to indicate an request has been loaded onto the endpoint | |
74 | * and has yet to be completed (maybe due to data move, or simply | |
75 | * awaiting an ack from the core all the data has been completed). | |
76 | * @debugfs: File entry for debugfs file for this endpoint. | |
77 | * @lock: State lock to protect contents of endpoint. | |
78 | * @dir_in: Set to true if this endpoint is of the IN direction, which | |
79 | * means that it is sending data to the Host. | |
80 | * @index: The index for the endpoint registers. | |
81 | * @name: The name array passed to the USB core. | |
82 | * @halted: Set if the endpoint has been halted. | |
83 | * @periodic: Set if this is a periodic ep, such as Interrupt | |
84 | * @sent_zlp: Set if we've sent a zero-length packet. | |
85 | * @total_data: The total number of data bytes done. | |
86 | * @fifo_size: The size of the FIFO (for periodic IN endpoints) | |
87 | * @fifo_load: The amount of data loaded into the FIFO (periodic IN) | |
88 | * @last_load: The offset of data for the last start of request. | |
89 | * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN | |
90 | * | |
91 | * This is the driver's state for each registered enpoint, allowing it | |
92 | * to keep track of transactions that need doing. Each endpoint has a | |
93 | * lock to protect the state, to try and avoid using an overall lock | |
94 | * for the host controller as much as possible. | |
95 | * | |
96 | * For periodic IN endpoints, we have fifo_size and fifo_load to try | |
97 | * and keep track of the amount of data in the periodic FIFO for each | |
98 | * of these as we don't have a status register that tells us how much | |
e7a9ff54 BD |
99 | * is in each of them. (note, this may actually be useless information |
100 | * as in shared-fifo mode periodic in acts like a single-frame packet | |
101 | * buffer than a fifo) | |
5b7d70c6 BD |
102 | */ |
103 | struct s3c_hsotg_ep { | |
104 | struct usb_ep ep; | |
105 | struct list_head queue; | |
106 | struct s3c_hsotg *parent; | |
107 | struct s3c_hsotg_req *req; | |
108 | struct dentry *debugfs; | |
109 | ||
110 | spinlock_t lock; | |
111 | ||
112 | unsigned long total_data; | |
113 | unsigned int size_loaded; | |
114 | unsigned int last_load; | |
115 | unsigned int fifo_load; | |
116 | unsigned short fifo_size; | |
117 | ||
118 | unsigned char dir_in; | |
119 | unsigned char index; | |
120 | ||
121 | unsigned int halted:1; | |
122 | unsigned int periodic:1; | |
123 | unsigned int sent_zlp:1; | |
124 | ||
125 | char name[10]; | |
126 | }; | |
127 | ||
128 | #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */ | |
129 | ||
130 | /** | |
131 | * struct s3c_hsotg - driver state. | |
132 | * @dev: The parent device supplied to the probe function | |
133 | * @driver: USB gadget driver | |
134 | * @plat: The platform specific configuration data. | |
135 | * @regs: The memory area mapped for accessing registers. | |
136 | * @regs_res: The resource that was allocated when claiming register space. | |
137 | * @irq: The IRQ number we are using | |
10aebc77 | 138 | * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. |
5b7d70c6 BD |
139 | * @debug_root: root directrory for debugfs. |
140 | * @debug_file: main status file for debugfs. | |
141 | * @debug_fifo: FIFO status file for debugfs. | |
142 | * @ep0_reply: Request used for ep0 reply. | |
143 | * @ep0_buff: Buffer for EP0 reply data, if needed. | |
144 | * @ctrl_buff: Buffer for EP0 control requests. | |
145 | * @ctrl_req: Request for EP0 control packets. | |
146 | * @eps: The endpoints being supplied to the gadget framework | |
147 | */ | |
148 | struct s3c_hsotg { | |
149 | struct device *dev; | |
150 | struct usb_gadget_driver *driver; | |
151 | struct s3c_hsotg_plat *plat; | |
152 | ||
153 | void __iomem *regs; | |
154 | struct resource *regs_res; | |
155 | int irq; | |
31ee04de | 156 | struct clk *clk; |
5b7d70c6 | 157 | |
10aebc77 BD |
158 | unsigned int dedicated_fifos:1; |
159 | ||
5b7d70c6 BD |
160 | struct dentry *debug_root; |
161 | struct dentry *debug_file; | |
162 | struct dentry *debug_fifo; | |
163 | ||
164 | struct usb_request *ep0_reply; | |
165 | struct usb_request *ctrl_req; | |
166 | u8 ep0_buff[8]; | |
167 | u8 ctrl_buff[8]; | |
168 | ||
169 | struct usb_gadget gadget; | |
170 | struct s3c_hsotg_ep eps[]; | |
171 | }; | |
172 | ||
173 | /** | |
174 | * struct s3c_hsotg_req - data transfer request | |
175 | * @req: The USB gadget request | |
176 | * @queue: The list of requests for the endpoint this is queued for. | |
177 | * @in_progress: Has already had size/packets written to core | |
178 | * @mapped: DMA buffer for this request has been mapped via dma_map_single(). | |
179 | */ | |
180 | struct s3c_hsotg_req { | |
181 | struct usb_request req; | |
182 | struct list_head queue; | |
183 | unsigned char in_progress; | |
184 | unsigned char mapped; | |
185 | }; | |
186 | ||
187 | /* conversion functions */ | |
188 | static inline struct s3c_hsotg_req *our_req(struct usb_request *req) | |
189 | { | |
190 | return container_of(req, struct s3c_hsotg_req, req); | |
191 | } | |
192 | ||
193 | static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep) | |
194 | { | |
195 | return container_of(ep, struct s3c_hsotg_ep, ep); | |
196 | } | |
197 | ||
198 | static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget) | |
199 | { | |
200 | return container_of(gadget, struct s3c_hsotg, gadget); | |
201 | } | |
202 | ||
203 | static inline void __orr32(void __iomem *ptr, u32 val) | |
204 | { | |
205 | writel(readl(ptr) | val, ptr); | |
206 | } | |
207 | ||
208 | static inline void __bic32(void __iomem *ptr, u32 val) | |
209 | { | |
210 | writel(readl(ptr) & ~val, ptr); | |
211 | } | |
212 | ||
213 | /* forward decleration of functions */ | |
214 | static void s3c_hsotg_dump(struct s3c_hsotg *hsotg); | |
215 | ||
216 | /** | |
217 | * using_dma - return the DMA status of the driver. | |
218 | * @hsotg: The driver state. | |
219 | * | |
220 | * Return true if we're using DMA. | |
221 | * | |
222 | * Currently, we have the DMA support code worked into everywhere | |
223 | * that needs it, but the AMBA DMA implementation in the hardware can | |
224 | * only DMA from 32bit aligned addresses. This means that gadgets such | |
225 | * as the CDC Ethernet cannot work as they often pass packets which are | |
226 | * not 32bit aligned. | |
227 | * | |
228 | * Unfortunately the choice to use DMA or not is global to the controller | |
229 | * and seems to be only settable when the controller is being put through | |
230 | * a core reset. This means we either need to fix the gadgets to take | |
231 | * account of DMA alignment, or add bounce buffers (yuerk). | |
232 | * | |
233 | * Until this issue is sorted out, we always return 'false'. | |
234 | */ | |
235 | static inline bool using_dma(struct s3c_hsotg *hsotg) | |
236 | { | |
237 | return false; /* support is not complete */ | |
238 | } | |
239 | ||
240 | /** | |
241 | * s3c_hsotg_en_gsint - enable one or more of the general interrupt | |
242 | * @hsotg: The device state | |
243 | * @ints: A bitmask of the interrupts to enable | |
244 | */ | |
245 | static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints) | |
246 | { | |
247 | u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK); | |
248 | u32 new_gsintmsk; | |
249 | ||
250 | new_gsintmsk = gsintmsk | ints; | |
251 | ||
252 | if (new_gsintmsk != gsintmsk) { | |
253 | dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); | |
254 | writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK); | |
255 | } | |
256 | } | |
257 | ||
258 | /** | |
259 | * s3c_hsotg_disable_gsint - disable one or more of the general interrupt | |
260 | * @hsotg: The device state | |
261 | * @ints: A bitmask of the interrupts to enable | |
262 | */ | |
263 | static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints) | |
264 | { | |
265 | u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK); | |
266 | u32 new_gsintmsk; | |
267 | ||
268 | new_gsintmsk = gsintmsk & ~ints; | |
269 | ||
270 | if (new_gsintmsk != gsintmsk) | |
271 | writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK); | |
272 | } | |
273 | ||
274 | /** | |
275 | * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq | |
276 | * @hsotg: The device state | |
277 | * @ep: The endpoint index | |
278 | * @dir_in: True if direction is in. | |
279 | * @en: The enable value, true to enable | |
280 | * | |
281 | * Set or clear the mask for an individual endpoint's interrupt | |
282 | * request. | |
283 | */ | |
284 | static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg, | |
285 | unsigned int ep, unsigned int dir_in, | |
286 | unsigned int en) | |
287 | { | |
288 | unsigned long flags; | |
289 | u32 bit = 1 << ep; | |
290 | u32 daint; | |
291 | ||
292 | if (!dir_in) | |
293 | bit <<= 16; | |
294 | ||
295 | local_irq_save(flags); | |
296 | daint = readl(hsotg->regs + S3C_DAINTMSK); | |
297 | if (en) | |
298 | daint |= bit; | |
299 | else | |
300 | daint &= ~bit; | |
301 | writel(daint, hsotg->regs + S3C_DAINTMSK); | |
302 | local_irq_restore(flags); | |
303 | } | |
304 | ||
305 | /** | |
306 | * s3c_hsotg_init_fifo - initialise non-periodic FIFOs | |
307 | * @hsotg: The device instance. | |
308 | */ | |
309 | static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg) | |
310 | { | |
0f002d20 BD |
311 | unsigned int ep; |
312 | unsigned int addr; | |
313 | unsigned int size; | |
1703a6d3 | 314 | int timeout; |
0f002d20 BD |
315 | u32 val; |
316 | ||
5b7d70c6 BD |
317 | /* the ryu 2.6.24 release ahs |
318 | writel(0x1C0, hsotg->regs + S3C_GRXFSIZ); | |
319 | writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) | | |
320 | S3C_GNPTXFSIZ_NPTxFDep(0x1C0), | |
321 | hsotg->regs + S3C_GNPTXFSIZ); | |
322 | */ | |
323 | ||
6d091ee7 | 324 | /* set FIFO sizes to 2048/1024 */ |
5b7d70c6 BD |
325 | |
326 | writel(2048, hsotg->regs + S3C_GRXFSIZ); | |
327 | writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) | | |
6d091ee7 | 328 | S3C_GNPTXFSIZ_NPTxFDep(1024), |
5b7d70c6 | 329 | hsotg->regs + S3C_GNPTXFSIZ); |
0f002d20 BD |
330 | |
331 | /* arange all the rest of the TX FIFOs, as some versions of this | |
332 | * block have overlapping default addresses. This also ensures | |
333 | * that if the settings have been changed, then they are set to | |
334 | * known values. */ | |
335 | ||
336 | /* start at the end of the GNPTXFSIZ, rounded up */ | |
337 | addr = 2048 + 1024; | |
338 | size = 768; | |
339 | ||
340 | /* currently we allocate TX FIFOs for all possible endpoints, | |
341 | * and assume that they are all the same size. */ | |
342 | ||
343 | for (ep = 0; ep <= 15; ep++) { | |
344 | val = addr; | |
345 | val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT; | |
346 | addr += size; | |
347 | ||
348 | writel(val, hsotg->regs + S3C_DPTXFSIZn(ep)); | |
349 | } | |
1703a6d3 BD |
350 | |
351 | /* according to p428 of the design guide, we need to ensure that | |
352 | * all fifos are flushed before continuing */ | |
353 | ||
354 | writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh | | |
355 | S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL); | |
356 | ||
357 | /* wait until the fifos are both flushed */ | |
358 | timeout = 100; | |
359 | while (1) { | |
360 | val = readl(hsotg->regs + S3C_GRSTCTL); | |
361 | ||
362 | if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0) | |
363 | break; | |
364 | ||
365 | if (--timeout == 0) { | |
366 | dev_err(hsotg->dev, | |
367 | "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
368 | __func__, val); | |
369 | } | |
370 | ||
371 | udelay(1); | |
372 | } | |
373 | ||
374 | dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
5b7d70c6 BD |
375 | } |
376 | ||
377 | /** | |
378 | * @ep: USB endpoint to allocate request for. | |
379 | * @flags: Allocation flags | |
380 | * | |
381 | * Allocate a new USB request structure appropriate for the specified endpoint | |
382 | */ | |
0978f8c5 MB |
383 | static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep, |
384 | gfp_t flags) | |
5b7d70c6 BD |
385 | { |
386 | struct s3c_hsotg_req *req; | |
387 | ||
388 | req = kzalloc(sizeof(struct s3c_hsotg_req), flags); | |
389 | if (!req) | |
390 | return NULL; | |
391 | ||
392 | INIT_LIST_HEAD(&req->queue); | |
393 | ||
394 | req->req.dma = DMA_ADDR_INVALID; | |
395 | return &req->req; | |
396 | } | |
397 | ||
398 | /** | |
399 | * is_ep_periodic - return true if the endpoint is in periodic mode. | |
400 | * @hs_ep: The endpoint to query. | |
401 | * | |
402 | * Returns true if the endpoint is in periodic mode, meaning it is being | |
403 | * used for an Interrupt or ISO transfer. | |
404 | */ | |
405 | static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep) | |
406 | { | |
407 | return hs_ep->periodic; | |
408 | } | |
409 | ||
410 | /** | |
411 | * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request | |
412 | * @hsotg: The device state. | |
413 | * @hs_ep: The endpoint for the request | |
414 | * @hs_req: The request being processed. | |
415 | * | |
416 | * This is the reverse of s3c_hsotg_map_dma(), called for the completion | |
417 | * of a request to ensure the buffer is ready for access by the caller. | |
418 | */ | |
419 | static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg, | |
420 | struct s3c_hsotg_ep *hs_ep, | |
421 | struct s3c_hsotg_req *hs_req) | |
422 | { | |
423 | struct usb_request *req = &hs_req->req; | |
424 | enum dma_data_direction dir; | |
425 | ||
426 | dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
427 | ||
428 | /* ignore this if we're not moving any data */ | |
429 | if (hs_req->req.length == 0) | |
430 | return; | |
431 | ||
432 | if (hs_req->mapped) { | |
433 | /* we mapped this, so unmap and remove the dma */ | |
434 | ||
435 | dma_unmap_single(hsotg->dev, req->dma, req->length, dir); | |
436 | ||
437 | req->dma = DMA_ADDR_INVALID; | |
438 | hs_req->mapped = 0; | |
439 | } else { | |
5b520259 | 440 | dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir); |
5b7d70c6 BD |
441 | } |
442 | } | |
443 | ||
444 | /** | |
445 | * s3c_hsotg_write_fifo - write packet Data to the TxFIFO | |
446 | * @hsotg: The controller state. | |
447 | * @hs_ep: The endpoint we're going to write for. | |
448 | * @hs_req: The request to write data for. | |
449 | * | |
450 | * This is called when the TxFIFO has some space in it to hold a new | |
451 | * transmission and we have something to give it. The actual setup of | |
452 | * the data size is done elsewhere, so all we have to do is to actually | |
453 | * write the data. | |
454 | * | |
455 | * The return value is zero if there is more space (or nothing was done) | |
456 | * otherwise -ENOSPC is returned if the FIFO space was used up. | |
457 | * | |
458 | * This routine is only needed for PIO | |
459 | */ | |
460 | static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg, | |
461 | struct s3c_hsotg_ep *hs_ep, | |
462 | struct s3c_hsotg_req *hs_req) | |
463 | { | |
464 | bool periodic = is_ep_periodic(hs_ep); | |
465 | u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS); | |
466 | int buf_pos = hs_req->req.actual; | |
467 | int to_write = hs_ep->size_loaded; | |
468 | void *data; | |
469 | int can_write; | |
470 | int pkt_round; | |
471 | ||
472 | to_write -= (buf_pos - hs_ep->last_load); | |
473 | ||
474 | /* if there's nothing to write, get out early */ | |
475 | if (to_write == 0) | |
476 | return 0; | |
477 | ||
10aebc77 | 478 | if (periodic && !hsotg->dedicated_fifos) { |
5b7d70c6 BD |
479 | u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index)); |
480 | int size_left; | |
481 | int size_done; | |
482 | ||
483 | /* work out how much data was loaded so we can calculate | |
484 | * how much data is left in the fifo. */ | |
485 | ||
486 | size_left = S3C_DxEPTSIZ_XferSize_GET(epsize); | |
487 | ||
e7a9ff54 BD |
488 | /* if shared fifo, we cannot write anything until the |
489 | * previous data has been completely sent. | |
490 | */ | |
491 | if (hs_ep->fifo_load != 0) { | |
492 | s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp); | |
493 | return -ENOSPC; | |
494 | } | |
495 | ||
5b7d70c6 BD |
496 | dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n", |
497 | __func__, size_left, | |
498 | hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size); | |
499 | ||
500 | /* how much of the data has moved */ | |
501 | size_done = hs_ep->size_loaded - size_left; | |
502 | ||
503 | /* how much data is left in the fifo */ | |
504 | can_write = hs_ep->fifo_load - size_done; | |
505 | dev_dbg(hsotg->dev, "%s: => can_write1=%d\n", | |
506 | __func__, can_write); | |
507 | ||
508 | can_write = hs_ep->fifo_size - can_write; | |
509 | dev_dbg(hsotg->dev, "%s: => can_write2=%d\n", | |
510 | __func__, can_write); | |
511 | ||
512 | if (can_write <= 0) { | |
513 | s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp); | |
514 | return -ENOSPC; | |
515 | } | |
10aebc77 BD |
516 | } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { |
517 | can_write = readl(hsotg->regs + S3C_DTXFSTS(hs_ep->index)); | |
518 | ||
519 | can_write &= 0xffff; | |
520 | can_write *= 4; | |
5b7d70c6 BD |
521 | } else { |
522 | if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) { | |
523 | dev_dbg(hsotg->dev, | |
524 | "%s: no queue slots available (0x%08x)\n", | |
525 | __func__, gnptxsts); | |
526 | ||
527 | s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp); | |
528 | return -ENOSPC; | |
529 | } | |
530 | ||
531 | can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts); | |
679f9b7c | 532 | can_write *= 4; /* fifo size is in 32bit quantities. */ |
5b7d70c6 BD |
533 | } |
534 | ||
535 | dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n", | |
536 | __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket); | |
537 | ||
538 | /* limit to 512 bytes of data, it seems at least on the non-periodic | |
539 | * FIFO, requests of >512 cause the endpoint to get stuck with a | |
540 | * fragment of the end of the transfer in it. | |
541 | */ | |
542 | if (can_write > 512) | |
543 | can_write = 512; | |
544 | ||
03e10e5a BD |
545 | /* limit the write to one max-packet size worth of data, but allow |
546 | * the transfer to return that it did not run out of fifo space | |
547 | * doing it. */ | |
548 | if (to_write > hs_ep->ep.maxpacket) { | |
549 | to_write = hs_ep->ep.maxpacket; | |
550 | ||
551 | s3c_hsotg_en_gsint(hsotg, | |
552 | periodic ? S3C_GINTSTS_PTxFEmp : | |
553 | S3C_GINTSTS_NPTxFEmp); | |
554 | } | |
555 | ||
5b7d70c6 BD |
556 | /* see if we can write data */ |
557 | ||
558 | if (to_write > can_write) { | |
559 | to_write = can_write; | |
560 | pkt_round = to_write % hs_ep->ep.maxpacket; | |
561 | ||
562 | /* Not sure, but we probably shouldn't be writing partial | |
563 | * packets into the FIFO, so round the write down to an | |
564 | * exact number of packets. | |
565 | * | |
566 | * Note, we do not currently check to see if we can ever | |
567 | * write a full packet or not to the FIFO. | |
568 | */ | |
569 | ||
570 | if (pkt_round) | |
571 | to_write -= pkt_round; | |
572 | ||
573 | /* enable correct FIFO interrupt to alert us when there | |
574 | * is more room left. */ | |
575 | ||
576 | s3c_hsotg_en_gsint(hsotg, | |
577 | periodic ? S3C_GINTSTS_PTxFEmp : | |
578 | S3C_GINTSTS_NPTxFEmp); | |
579 | } | |
580 | ||
581 | dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", | |
582 | to_write, hs_req->req.length, can_write, buf_pos); | |
583 | ||
584 | if (to_write <= 0) | |
585 | return -ENOSPC; | |
586 | ||
587 | hs_req->req.actual = buf_pos + to_write; | |
588 | hs_ep->total_data += to_write; | |
589 | ||
590 | if (periodic) | |
591 | hs_ep->fifo_load += to_write; | |
592 | ||
593 | to_write = DIV_ROUND_UP(to_write, 4); | |
594 | data = hs_req->req.buf + buf_pos; | |
595 | ||
596 | writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write); | |
597 | ||
598 | return (to_write >= can_write) ? -ENOSPC : 0; | |
599 | } | |
600 | ||
601 | /** | |
602 | * get_ep_limit - get the maximum data legnth for this endpoint | |
603 | * @hs_ep: The endpoint | |
604 | * | |
605 | * Return the maximum data that can be queued in one go on a given endpoint | |
606 | * so that transfers that are too long can be split. | |
607 | */ | |
608 | static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep) | |
609 | { | |
610 | int index = hs_ep->index; | |
611 | unsigned maxsize; | |
612 | unsigned maxpkt; | |
613 | ||
614 | if (index != 0) { | |
615 | maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1; | |
616 | maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1; | |
617 | } else { | |
b05ca580 | 618 | maxsize = 64+64; |
66e5c643 | 619 | if (hs_ep->dir_in) |
5b7d70c6 | 620 | maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1; |
66e5c643 | 621 | else |
5b7d70c6 | 622 | maxpkt = 2; |
5b7d70c6 BD |
623 | } |
624 | ||
625 | /* we made the constant loading easier above by using +1 */ | |
626 | maxpkt--; | |
627 | maxsize--; | |
628 | ||
629 | /* constrain by packet count if maxpkts*pktsize is greater | |
630 | * than the length register size. */ | |
631 | ||
632 | if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) | |
633 | maxsize = maxpkt * hs_ep->ep.maxpacket; | |
634 | ||
635 | return maxsize; | |
636 | } | |
637 | ||
638 | /** | |
639 | * s3c_hsotg_start_req - start a USB request from an endpoint's queue | |
640 | * @hsotg: The controller state. | |
641 | * @hs_ep: The endpoint to process a request for | |
642 | * @hs_req: The request to start. | |
643 | * @continuing: True if we are doing more for the current request. | |
644 | * | |
645 | * Start the given request running by setting the endpoint registers | |
646 | * appropriately, and writing any data to the FIFOs. | |
647 | */ | |
648 | static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg, | |
649 | struct s3c_hsotg_ep *hs_ep, | |
650 | struct s3c_hsotg_req *hs_req, | |
651 | bool continuing) | |
652 | { | |
653 | struct usb_request *ureq = &hs_req->req; | |
654 | int index = hs_ep->index; | |
655 | int dir_in = hs_ep->dir_in; | |
656 | u32 epctrl_reg; | |
657 | u32 epsize_reg; | |
658 | u32 epsize; | |
659 | u32 ctrl; | |
660 | unsigned length; | |
661 | unsigned packets; | |
662 | unsigned maxreq; | |
663 | ||
664 | if (index != 0) { | |
665 | if (hs_ep->req && !continuing) { | |
666 | dev_err(hsotg->dev, "%s: active request\n", __func__); | |
667 | WARN_ON(1); | |
668 | return; | |
669 | } else if (hs_ep->req != hs_req && continuing) { | |
670 | dev_err(hsotg->dev, | |
671 | "%s: continue different req\n", __func__); | |
672 | WARN_ON(1); | |
673 | return; | |
674 | } | |
675 | } | |
676 | ||
677 | epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index); | |
678 | epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index); | |
679 | ||
680 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", | |
681 | __func__, readl(hsotg->regs + epctrl_reg), index, | |
682 | hs_ep->dir_in ? "in" : "out"); | |
683 | ||
9c39ddc6 AT |
684 | /* If endpoint is stalled, we will restart request later */ |
685 | ctrl = readl(hsotg->regs + epctrl_reg); | |
686 | ||
687 | if (ctrl & S3C_DxEPCTL_Stall) { | |
688 | dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); | |
689 | return; | |
690 | } | |
691 | ||
5b7d70c6 BD |
692 | length = ureq->length - ureq->actual; |
693 | ||
694 | if (0) | |
695 | dev_dbg(hsotg->dev, | |
696 | "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n", | |
697 | ureq->buf, length, ureq->dma, | |
698 | ureq->no_interrupt, ureq->zero, ureq->short_not_ok); | |
699 | ||
700 | maxreq = get_ep_limit(hs_ep); | |
701 | if (length > maxreq) { | |
702 | int round = maxreq % hs_ep->ep.maxpacket; | |
703 | ||
704 | dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n", | |
705 | __func__, length, maxreq, round); | |
706 | ||
707 | /* round down to multiple of packets */ | |
708 | if (round) | |
709 | maxreq -= round; | |
710 | ||
711 | length = maxreq; | |
712 | } | |
713 | ||
714 | if (length) | |
715 | packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket); | |
716 | else | |
717 | packets = 1; /* send one packet if length is zero. */ | |
718 | ||
719 | if (dir_in && index != 0) | |
720 | epsize = S3C_DxEPTSIZ_MC(1); | |
721 | else | |
722 | epsize = 0; | |
723 | ||
724 | if (index != 0 && ureq->zero) { | |
725 | /* test for the packets being exactly right for the | |
726 | * transfer */ | |
727 | ||
728 | if (length == (packets * hs_ep->ep.maxpacket)) | |
729 | packets++; | |
730 | } | |
731 | ||
732 | epsize |= S3C_DxEPTSIZ_PktCnt(packets); | |
733 | epsize |= S3C_DxEPTSIZ_XferSize(length); | |
734 | ||
735 | dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", | |
736 | __func__, packets, length, ureq->length, epsize, epsize_reg); | |
737 | ||
738 | /* store the request as the current one we're doing */ | |
739 | hs_ep->req = hs_req; | |
740 | ||
741 | /* write size / packets */ | |
742 | writel(epsize, hsotg->regs + epsize_reg); | |
743 | ||
5b7d70c6 BD |
744 | if (using_dma(hsotg)) { |
745 | unsigned int dma_reg; | |
746 | ||
747 | /* write DMA address to control register, buffer already | |
748 | * synced by s3c_hsotg_ep_queue(). */ | |
749 | ||
750 | dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index); | |
751 | writel(ureq->dma, hsotg->regs + dma_reg); | |
752 | ||
753 | dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n", | |
754 | __func__, ureq->dma, dma_reg); | |
755 | } | |
756 | ||
757 | ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */ | |
758 | ctrl |= S3C_DxEPCTL_USBActEp; | |
759 | ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */ | |
760 | ||
761 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
762 | writel(ctrl, hsotg->regs + epctrl_reg); | |
763 | ||
764 | /* set these, it seems that DMA support increments past the end | |
765 | * of the packet buffer so we need to calculate the length from | |
766 | * this information. */ | |
767 | hs_ep->size_loaded = length; | |
768 | hs_ep->last_load = ureq->actual; | |
769 | ||
770 | if (dir_in && !using_dma(hsotg)) { | |
771 | /* set these anyway, we may need them for non-periodic in */ | |
772 | hs_ep->fifo_load = 0; | |
773 | ||
774 | s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
775 | } | |
776 | ||
777 | /* clear the INTknTXFEmpMsk when we start request, more as a aide | |
778 | * to debugging to see what is going on. */ | |
779 | if (dir_in) | |
780 | writel(S3C_DIEPMSK_INTknTXFEmpMsk, | |
781 | hsotg->regs + S3C_DIEPINT(index)); | |
782 | ||
783 | /* Note, trying to clear the NAK here causes problems with transmit | |
25985edc | 784 | * on the S3C6400 ending up with the TXFIFO becoming full. */ |
5b7d70c6 BD |
785 | |
786 | /* check ep is enabled */ | |
787 | if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna)) | |
788 | dev_warn(hsotg->dev, | |
789 | "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n", | |
790 | index, readl(hsotg->regs + epctrl_reg)); | |
791 | ||
792 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", | |
793 | __func__, readl(hsotg->regs + epctrl_reg)); | |
794 | } | |
795 | ||
796 | /** | |
797 | * s3c_hsotg_map_dma - map the DMA memory being used for the request | |
798 | * @hsotg: The device state. | |
799 | * @hs_ep: The endpoint the request is on. | |
800 | * @req: The request being processed. | |
801 | * | |
802 | * We've been asked to queue a request, so ensure that the memory buffer | |
803 | * is correctly setup for DMA. If we've been passed an extant DMA address | |
804 | * then ensure the buffer has been synced to memory. If our buffer has no | |
805 | * DMA memory, then we map the memory and mark our request to allow us to | |
806 | * cleanup on completion. | |
807 | */ | |
808 | static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg, | |
809 | struct s3c_hsotg_ep *hs_ep, | |
810 | struct usb_request *req) | |
811 | { | |
812 | enum dma_data_direction dir; | |
813 | struct s3c_hsotg_req *hs_req = our_req(req); | |
814 | ||
815 | dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
816 | ||
817 | /* if the length is zero, ignore the DMA data */ | |
818 | if (hs_req->req.length == 0) | |
819 | return 0; | |
820 | ||
821 | if (req->dma == DMA_ADDR_INVALID) { | |
822 | dma_addr_t dma; | |
823 | ||
824 | dma = dma_map_single(hsotg->dev, req->buf, req->length, dir); | |
825 | ||
826 | if (unlikely(dma_mapping_error(hsotg->dev, dma))) | |
827 | goto dma_error; | |
828 | ||
829 | if (dma & 3) { | |
830 | dev_err(hsotg->dev, "%s: unaligned dma buffer\n", | |
831 | __func__); | |
832 | ||
833 | dma_unmap_single(hsotg->dev, dma, req->length, dir); | |
834 | return -EINVAL; | |
835 | } | |
836 | ||
837 | hs_req->mapped = 1; | |
838 | req->dma = dma; | |
839 | } else { | |
5b520259 | 840 | dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir); |
5b7d70c6 BD |
841 | hs_req->mapped = 0; |
842 | } | |
843 | ||
844 | return 0; | |
845 | ||
846 | dma_error: | |
847 | dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n", | |
848 | __func__, req->buf, req->length); | |
849 | ||
850 | return -EIO; | |
851 | } | |
852 | ||
853 | static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req, | |
854 | gfp_t gfp_flags) | |
855 | { | |
856 | struct s3c_hsotg_req *hs_req = our_req(req); | |
857 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
858 | struct s3c_hsotg *hs = hs_ep->parent; | |
859 | unsigned long irqflags; | |
860 | bool first; | |
861 | ||
862 | dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n", | |
863 | ep->name, req, req->length, req->buf, req->no_interrupt, | |
864 | req->zero, req->short_not_ok); | |
865 | ||
866 | /* initialise status of the request */ | |
867 | INIT_LIST_HEAD(&hs_req->queue); | |
868 | req->actual = 0; | |
869 | req->status = -EINPROGRESS; | |
870 | ||
871 | /* if we're using DMA, sync the buffers as necessary */ | |
872 | if (using_dma(hs)) { | |
873 | int ret = s3c_hsotg_map_dma(hs, hs_ep, req); | |
874 | if (ret) | |
875 | return ret; | |
876 | } | |
877 | ||
878 | spin_lock_irqsave(&hs_ep->lock, irqflags); | |
879 | ||
880 | first = list_empty(&hs_ep->queue); | |
881 | list_add_tail(&hs_req->queue, &hs_ep->queue); | |
882 | ||
883 | if (first) | |
884 | s3c_hsotg_start_req(hs, hs_ep, hs_req, false); | |
885 | ||
886 | spin_unlock_irqrestore(&hs_ep->lock, irqflags); | |
887 | ||
888 | return 0; | |
889 | } | |
890 | ||
891 | static void s3c_hsotg_ep_free_request(struct usb_ep *ep, | |
892 | struct usb_request *req) | |
893 | { | |
894 | struct s3c_hsotg_req *hs_req = our_req(req); | |
895 | ||
896 | kfree(hs_req); | |
897 | } | |
898 | ||
899 | /** | |
900 | * s3c_hsotg_complete_oursetup - setup completion callback | |
901 | * @ep: The endpoint the request was on. | |
902 | * @req: The request completed. | |
903 | * | |
904 | * Called on completion of any requests the driver itself | |
905 | * submitted that need cleaning up. | |
906 | */ | |
907 | static void s3c_hsotg_complete_oursetup(struct usb_ep *ep, | |
908 | struct usb_request *req) | |
909 | { | |
910 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
911 | struct s3c_hsotg *hsotg = hs_ep->parent; | |
912 | ||
913 | dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req); | |
914 | ||
915 | s3c_hsotg_ep_free_request(ep, req); | |
916 | } | |
917 | ||
918 | /** | |
919 | * ep_from_windex - convert control wIndex value to endpoint | |
920 | * @hsotg: The driver state. | |
921 | * @windex: The control request wIndex field (in host order). | |
922 | * | |
923 | * Convert the given wIndex into a pointer to an driver endpoint | |
924 | * structure, or return NULL if it is not a valid endpoint. | |
925 | */ | |
926 | static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg, | |
927 | u32 windex) | |
928 | { | |
929 | struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F]; | |
930 | int dir = (windex & USB_DIR_IN) ? 1 : 0; | |
931 | int idx = windex & 0x7F; | |
932 | ||
933 | if (windex >= 0x100) | |
934 | return NULL; | |
935 | ||
936 | if (idx > S3C_HSOTG_EPS) | |
937 | return NULL; | |
938 | ||
939 | if (idx && ep->dir_in != dir) | |
940 | return NULL; | |
941 | ||
942 | return ep; | |
943 | } | |
944 | ||
945 | /** | |
946 | * s3c_hsotg_send_reply - send reply to control request | |
947 | * @hsotg: The device state | |
948 | * @ep: Endpoint 0 | |
949 | * @buff: Buffer for request | |
950 | * @length: Length of reply. | |
951 | * | |
952 | * Create a request and queue it on the given endpoint. This is useful as | |
953 | * an internal method of sending replies to certain control requests, etc. | |
954 | */ | |
955 | static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg, | |
956 | struct s3c_hsotg_ep *ep, | |
957 | void *buff, | |
958 | int length) | |
959 | { | |
960 | struct usb_request *req; | |
961 | int ret; | |
962 | ||
963 | dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length); | |
964 | ||
965 | req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC); | |
966 | hsotg->ep0_reply = req; | |
967 | if (!req) { | |
968 | dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__); | |
969 | return -ENOMEM; | |
970 | } | |
971 | ||
972 | req->buf = hsotg->ep0_buff; | |
973 | req->length = length; | |
974 | req->zero = 1; /* always do zero-length final transfer */ | |
975 | req->complete = s3c_hsotg_complete_oursetup; | |
976 | ||
977 | if (length) | |
978 | memcpy(req->buf, buff, length); | |
979 | else | |
980 | ep->sent_zlp = 1; | |
981 | ||
982 | ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC); | |
983 | if (ret) { | |
984 | dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__); | |
985 | return ret; | |
986 | } | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
991 | /** | |
992 | * s3c_hsotg_process_req_status - process request GET_STATUS | |
993 | * @hsotg: The device state | |
994 | * @ctrl: USB control request | |
995 | */ | |
996 | static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg, | |
997 | struct usb_ctrlrequest *ctrl) | |
998 | { | |
999 | struct s3c_hsotg_ep *ep0 = &hsotg->eps[0]; | |
1000 | struct s3c_hsotg_ep *ep; | |
1001 | __le16 reply; | |
1002 | int ret; | |
1003 | ||
1004 | dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__); | |
1005 | ||
1006 | if (!ep0->dir_in) { | |
1007 | dev_warn(hsotg->dev, "%s: direction out?\n", __func__); | |
1008 | return -EINVAL; | |
1009 | } | |
1010 | ||
1011 | switch (ctrl->bRequestType & USB_RECIP_MASK) { | |
1012 | case USB_RECIP_DEVICE: | |
1013 | reply = cpu_to_le16(0); /* bit 0 => self powered, | |
1014 | * bit 1 => remote wakeup */ | |
1015 | break; | |
1016 | ||
1017 | case USB_RECIP_INTERFACE: | |
1018 | /* currently, the data result should be zero */ | |
1019 | reply = cpu_to_le16(0); | |
1020 | break; | |
1021 | ||
1022 | case USB_RECIP_ENDPOINT: | |
1023 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1024 | if (!ep) | |
1025 | return -ENOENT; | |
1026 | ||
1027 | reply = cpu_to_le16(ep->halted ? 1 : 0); | |
1028 | break; | |
1029 | ||
1030 | default: | |
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | if (le16_to_cpu(ctrl->wLength) != 2) | |
1035 | return -EINVAL; | |
1036 | ||
1037 | ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2); | |
1038 | if (ret) { | |
1039 | dev_err(hsotg->dev, "%s: failed to send reply\n", __func__); | |
1040 | return ret; | |
1041 | } | |
1042 | ||
1043 | return 1; | |
1044 | } | |
1045 | ||
1046 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value); | |
1047 | ||
9c39ddc6 AT |
1048 | /** |
1049 | * get_ep_head - return the first request on the endpoint | |
1050 | * @hs_ep: The controller endpoint to get | |
1051 | * | |
1052 | * Get the first request on the endpoint. | |
1053 | */ | |
1054 | static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep) | |
1055 | { | |
1056 | if (list_empty(&hs_ep->queue)) | |
1057 | return NULL; | |
1058 | ||
1059 | return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue); | |
1060 | } | |
1061 | ||
5b7d70c6 BD |
1062 | /** |
1063 | * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE | |
1064 | * @hsotg: The device state | |
1065 | * @ctrl: USB control request | |
1066 | */ | |
1067 | static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg, | |
1068 | struct usb_ctrlrequest *ctrl) | |
1069 | { | |
26ab3d0c | 1070 | struct s3c_hsotg_ep *ep0 = &hsotg->eps[0]; |
9c39ddc6 AT |
1071 | struct s3c_hsotg_req *hs_req; |
1072 | bool restart; | |
5b7d70c6 BD |
1073 | bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE); |
1074 | struct s3c_hsotg_ep *ep; | |
26ab3d0c | 1075 | int ret; |
5b7d70c6 BD |
1076 | |
1077 | dev_dbg(hsotg->dev, "%s: %s_FEATURE\n", | |
1078 | __func__, set ? "SET" : "CLEAR"); | |
1079 | ||
1080 | if (ctrl->bRequestType == USB_RECIP_ENDPOINT) { | |
1081 | ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex)); | |
1082 | if (!ep) { | |
1083 | dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n", | |
1084 | __func__, le16_to_cpu(ctrl->wIndex)); | |
1085 | return -ENOENT; | |
1086 | } | |
1087 | ||
1088 | switch (le16_to_cpu(ctrl->wValue)) { | |
1089 | case USB_ENDPOINT_HALT: | |
1090 | s3c_hsotg_ep_sethalt(&ep->ep, set); | |
26ab3d0c AT |
1091 | |
1092 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1093 | if (ret) { | |
1094 | dev_err(hsotg->dev, | |
1095 | "%s: failed to send reply\n", __func__); | |
1096 | return ret; | |
1097 | } | |
9c39ddc6 AT |
1098 | |
1099 | if (!set) { | |
1100 | /* | |
1101 | * If we have request in progress, | |
1102 | * then complete it | |
1103 | */ | |
1104 | if (ep->req) { | |
1105 | hs_req = ep->req; | |
1106 | ep->req = NULL; | |
1107 | list_del_init(&hs_req->queue); | |
1108 | hs_req->req.complete(&ep->ep, | |
1109 | &hs_req->req); | |
1110 | } | |
1111 | ||
1112 | /* If we have pending request, then start it */ | |
1113 | restart = !list_empty(&ep->queue); | |
1114 | if (restart) { | |
1115 | hs_req = get_ep_head(ep); | |
1116 | s3c_hsotg_start_req(hsotg, ep, | |
1117 | hs_req, false); | |
1118 | } | |
1119 | } | |
1120 | ||
5b7d70c6 BD |
1121 | break; |
1122 | ||
1123 | default: | |
1124 | return -ENOENT; | |
1125 | } | |
1126 | } else | |
1127 | return -ENOENT; /* currently only deal with endpoint */ | |
1128 | ||
1129 | return 1; | |
1130 | } | |
1131 | ||
1132 | /** | |
1133 | * s3c_hsotg_process_control - process a control request | |
1134 | * @hsotg: The device state | |
1135 | * @ctrl: The control request received | |
1136 | * | |
1137 | * The controller has received the SETUP phase of a control request, and | |
1138 | * needs to work out what to do next (and whether to pass it on to the | |
1139 | * gadget driver). | |
1140 | */ | |
1141 | static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg, | |
1142 | struct usb_ctrlrequest *ctrl) | |
1143 | { | |
1144 | struct s3c_hsotg_ep *ep0 = &hsotg->eps[0]; | |
1145 | int ret = 0; | |
1146 | u32 dcfg; | |
1147 | ||
1148 | ep0->sent_zlp = 0; | |
1149 | ||
1150 | dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n", | |
1151 | ctrl->bRequest, ctrl->bRequestType, | |
1152 | ctrl->wValue, ctrl->wLength); | |
1153 | ||
1154 | /* record the direction of the request, for later use when enquing | |
1155 | * packets onto EP0. */ | |
1156 | ||
1157 | ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0; | |
1158 | dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in); | |
1159 | ||
1160 | /* if we've no data with this request, then the last part of the | |
1161 | * transaction is going to implicitly be IN. */ | |
1162 | if (ctrl->wLength == 0) | |
1163 | ep0->dir_in = 1; | |
1164 | ||
1165 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1166 | switch (ctrl->bRequest) { | |
1167 | case USB_REQ_SET_ADDRESS: | |
1168 | dcfg = readl(hsotg->regs + S3C_DCFG); | |
1169 | dcfg &= ~S3C_DCFG_DevAddr_MASK; | |
1170 | dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT; | |
1171 | writel(dcfg, hsotg->regs + S3C_DCFG); | |
1172 | ||
1173 | dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); | |
1174 | ||
1175 | ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0); | |
1176 | return; | |
1177 | ||
1178 | case USB_REQ_GET_STATUS: | |
1179 | ret = s3c_hsotg_process_req_status(hsotg, ctrl); | |
1180 | break; | |
1181 | ||
1182 | case USB_REQ_CLEAR_FEATURE: | |
1183 | case USB_REQ_SET_FEATURE: | |
1184 | ret = s3c_hsotg_process_req_feature(hsotg, ctrl); | |
1185 | break; | |
1186 | } | |
1187 | } | |
1188 | ||
1189 | /* as a fallback, try delivering it to the driver to deal with */ | |
1190 | ||
1191 | if (ret == 0 && hsotg->driver) { | |
1192 | ret = hsotg->driver->setup(&hsotg->gadget, ctrl); | |
1193 | if (ret < 0) | |
1194 | dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); | |
1195 | } | |
1196 | ||
5b7d70c6 BD |
1197 | /* the request is either unhandlable, or is not formatted correctly |
1198 | * so respond with a STALL for the status stage to indicate failure. | |
1199 | */ | |
1200 | ||
1201 | if (ret < 0) { | |
1202 | u32 reg; | |
1203 | u32 ctrl; | |
1204 | ||
1205 | dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); | |
1206 | reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0; | |
1207 | ||
1208 | /* S3C_DxEPCTL_Stall will be cleared by EP once it has | |
1209 | * taken effect, so no need to clear later. */ | |
1210 | ||
1211 | ctrl = readl(hsotg->regs + reg); | |
1212 | ctrl |= S3C_DxEPCTL_Stall; | |
1213 | ctrl |= S3C_DxEPCTL_CNAK; | |
1214 | writel(ctrl, hsotg->regs + reg); | |
1215 | ||
1216 | dev_dbg(hsotg->dev, | |
25985edc | 1217 | "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n", |
5b7d70c6 BD |
1218 | ctrl, reg, readl(hsotg->regs + reg)); |
1219 | ||
25985edc | 1220 | /* don't believe we need to anything more to get the EP |
5b7d70c6 BD |
1221 | * to reply with a STALL packet */ |
1222 | } | |
1223 | } | |
1224 | ||
1225 | static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg); | |
1226 | ||
1227 | /** | |
1228 | * s3c_hsotg_complete_setup - completion of a setup transfer | |
1229 | * @ep: The endpoint the request was on. | |
1230 | * @req: The request completed. | |
1231 | * | |
1232 | * Called on completion of any requests the driver itself submitted for | |
1233 | * EP0 setup packets | |
1234 | */ | |
1235 | static void s3c_hsotg_complete_setup(struct usb_ep *ep, | |
1236 | struct usb_request *req) | |
1237 | { | |
1238 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
1239 | struct s3c_hsotg *hsotg = hs_ep->parent; | |
1240 | ||
1241 | if (req->status < 0) { | |
1242 | dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status); | |
1243 | return; | |
1244 | } | |
1245 | ||
1246 | if (req->actual == 0) | |
1247 | s3c_hsotg_enqueue_setup(hsotg); | |
1248 | else | |
1249 | s3c_hsotg_process_control(hsotg, req->buf); | |
1250 | } | |
1251 | ||
1252 | /** | |
1253 | * s3c_hsotg_enqueue_setup - start a request for EP0 packets | |
1254 | * @hsotg: The device state. | |
1255 | * | |
1256 | * Enqueue a request on EP0 if necessary to received any SETUP packets | |
1257 | * received from the host. | |
1258 | */ | |
1259 | static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg) | |
1260 | { | |
1261 | struct usb_request *req = hsotg->ctrl_req; | |
1262 | struct s3c_hsotg_req *hs_req = our_req(req); | |
1263 | int ret; | |
1264 | ||
1265 | dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__); | |
1266 | ||
1267 | req->zero = 0; | |
1268 | req->length = 8; | |
1269 | req->buf = hsotg->ctrl_buff; | |
1270 | req->complete = s3c_hsotg_complete_setup; | |
1271 | ||
1272 | if (!list_empty(&hs_req->queue)) { | |
1273 | dev_dbg(hsotg->dev, "%s already queued???\n", __func__); | |
1274 | return; | |
1275 | } | |
1276 | ||
1277 | hsotg->eps[0].dir_in = 0; | |
1278 | ||
1279 | ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC); | |
1280 | if (ret < 0) { | |
1281 | dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); | |
1282 | /* Don't think there's much we can do other than watch the | |
1283 | * driver fail. */ | |
1284 | } | |
1285 | } | |
1286 | ||
5b7d70c6 BD |
1287 | /** |
1288 | * s3c_hsotg_complete_request - complete a request given to us | |
1289 | * @hsotg: The device state. | |
1290 | * @hs_ep: The endpoint the request was on. | |
1291 | * @hs_req: The request to complete. | |
1292 | * @result: The result code (0 => Ok, otherwise errno) | |
1293 | * | |
1294 | * The given request has finished, so call the necessary completion | |
1295 | * if it has one and then look to see if we can start a new request | |
1296 | * on the endpoint. | |
1297 | * | |
1298 | * Note, expects the ep to already be locked as appropriate. | |
1299 | */ | |
1300 | static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg, | |
1301 | struct s3c_hsotg_ep *hs_ep, | |
1302 | struct s3c_hsotg_req *hs_req, | |
1303 | int result) | |
1304 | { | |
1305 | bool restart; | |
1306 | ||
1307 | if (!hs_req) { | |
1308 | dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__); | |
1309 | return; | |
1310 | } | |
1311 | ||
1312 | dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", | |
1313 | hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); | |
1314 | ||
1315 | /* only replace the status if we've not already set an error | |
1316 | * from a previous transaction */ | |
1317 | ||
1318 | if (hs_req->req.status == -EINPROGRESS) | |
1319 | hs_req->req.status = result; | |
1320 | ||
1321 | hs_ep->req = NULL; | |
1322 | list_del_init(&hs_req->queue); | |
1323 | ||
1324 | if (using_dma(hsotg)) | |
1325 | s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req); | |
1326 | ||
1327 | /* call the complete request with the locks off, just in case the | |
1328 | * request tries to queue more work for this endpoint. */ | |
1329 | ||
1330 | if (hs_req->req.complete) { | |
1331 | spin_unlock(&hs_ep->lock); | |
1332 | hs_req->req.complete(&hs_ep->ep, &hs_req->req); | |
1333 | spin_lock(&hs_ep->lock); | |
1334 | } | |
1335 | ||
1336 | /* Look to see if there is anything else to do. Note, the completion | |
1337 | * of the previous request may have caused a new request to be started | |
1338 | * so be careful when doing this. */ | |
1339 | ||
1340 | if (!hs_ep->req && result >= 0) { | |
1341 | restart = !list_empty(&hs_ep->queue); | |
1342 | if (restart) { | |
1343 | hs_req = get_ep_head(hs_ep); | |
1344 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false); | |
1345 | } | |
1346 | } | |
1347 | } | |
1348 | ||
1349 | /** | |
1350 | * s3c_hsotg_complete_request_lock - complete a request given to us (locked) | |
1351 | * @hsotg: The device state. | |
1352 | * @hs_ep: The endpoint the request was on. | |
1353 | * @hs_req: The request to complete. | |
1354 | * @result: The result code (0 => Ok, otherwise errno) | |
1355 | * | |
1356 | * See s3c_hsotg_complete_request(), but called with the endpoint's | |
1357 | * lock held. | |
1358 | */ | |
1359 | static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg, | |
1360 | struct s3c_hsotg_ep *hs_ep, | |
1361 | struct s3c_hsotg_req *hs_req, | |
1362 | int result) | |
1363 | { | |
1364 | unsigned long flags; | |
1365 | ||
1366 | spin_lock_irqsave(&hs_ep->lock, flags); | |
1367 | s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result); | |
1368 | spin_unlock_irqrestore(&hs_ep->lock, flags); | |
1369 | } | |
1370 | ||
1371 | /** | |
1372 | * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint | |
1373 | * @hsotg: The device state. | |
1374 | * @ep_idx: The endpoint index for the data | |
1375 | * @size: The size of data in the fifo, in bytes | |
1376 | * | |
1377 | * The FIFO status shows there is data to read from the FIFO for a given | |
1378 | * endpoint, so sort out whether we need to read the data into a request | |
1379 | * that has been made for that endpoint. | |
1380 | */ | |
1381 | static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size) | |
1382 | { | |
1383 | struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx]; | |
1384 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
1385 | void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx); | |
1386 | int to_read; | |
1387 | int max_req; | |
1388 | int read_ptr; | |
1389 | ||
1390 | if (!hs_req) { | |
1391 | u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx)); | |
1392 | int ptr; | |
1393 | ||
1394 | dev_warn(hsotg->dev, | |
1395 | "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n", | |
1396 | __func__, size, ep_idx, epctl); | |
1397 | ||
1398 | /* dump the data from the FIFO, we've nothing we can do */ | |
1399 | for (ptr = 0; ptr < size; ptr += 4) | |
1400 | (void)readl(fifo); | |
1401 | ||
1402 | return; | |
1403 | } | |
1404 | ||
1405 | spin_lock(&hs_ep->lock); | |
1406 | ||
1407 | to_read = size; | |
1408 | read_ptr = hs_req->req.actual; | |
1409 | max_req = hs_req->req.length - read_ptr; | |
1410 | ||
a33e7136 BD |
1411 | dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n", |
1412 | __func__, to_read, max_req, read_ptr, hs_req->req.length); | |
1413 | ||
5b7d70c6 BD |
1414 | if (to_read > max_req) { |
1415 | /* more data appeared than we where willing | |
1416 | * to deal with in this request. | |
1417 | */ | |
1418 | ||
1419 | /* currently we don't deal this */ | |
1420 | WARN_ON_ONCE(1); | |
1421 | } | |
1422 | ||
5b7d70c6 BD |
1423 | hs_ep->total_data += to_read; |
1424 | hs_req->req.actual += to_read; | |
1425 | to_read = DIV_ROUND_UP(to_read, 4); | |
1426 | ||
1427 | /* note, we might over-write the buffer end by 3 bytes depending on | |
1428 | * alignment of the data. */ | |
1429 | readsl(fifo, hs_req->req.buf + read_ptr, to_read); | |
1430 | ||
1431 | spin_unlock(&hs_ep->lock); | |
1432 | } | |
1433 | ||
1434 | /** | |
1435 | * s3c_hsotg_send_zlp - send zero-length packet on control endpoint | |
1436 | * @hsotg: The device instance | |
1437 | * @req: The request currently on this endpoint | |
1438 | * | |
1439 | * Generate a zero-length IN packet request for terminating a SETUP | |
1440 | * transaction. | |
1441 | * | |
1442 | * Note, since we don't write any data to the TxFIFO, then it is | |
25985edc | 1443 | * currently believed that we do not need to wait for any space in |
5b7d70c6 BD |
1444 | * the TxFIFO. |
1445 | */ | |
1446 | static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg, | |
1447 | struct s3c_hsotg_req *req) | |
1448 | { | |
1449 | u32 ctrl; | |
1450 | ||
1451 | if (!req) { | |
1452 | dev_warn(hsotg->dev, "%s: no request?\n", __func__); | |
1453 | return; | |
1454 | } | |
1455 | ||
1456 | if (req->req.length == 0) { | |
1457 | hsotg->eps[0].sent_zlp = 1; | |
1458 | s3c_hsotg_enqueue_setup(hsotg); | |
1459 | return; | |
1460 | } | |
1461 | ||
1462 | hsotg->eps[0].dir_in = 1; | |
1463 | hsotg->eps[0].sent_zlp = 1; | |
1464 | ||
1465 | dev_dbg(hsotg->dev, "sending zero-length packet\n"); | |
1466 | ||
1467 | /* issue a zero-sized packet to terminate this */ | |
1468 | writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) | | |
1469 | S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0)); | |
1470 | ||
1471 | ctrl = readl(hsotg->regs + S3C_DIEPCTL0); | |
1472 | ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */ | |
1473 | ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */ | |
1474 | ctrl |= S3C_DxEPCTL_USBActEp; | |
1475 | writel(ctrl, hsotg->regs + S3C_DIEPCTL0); | |
1476 | } | |
1477 | ||
1478 | /** | |
1479 | * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO | |
1480 | * @hsotg: The device instance | |
1481 | * @epnum: The endpoint received from | |
1482 | * @was_setup: Set if processing a SetupDone event. | |
1483 | * | |
1484 | * The RXFIFO has delivered an OutDone event, which means that the data | |
1485 | * transfer for an OUT endpoint has been completed, either by a short | |
1486 | * packet or by the finish of a transfer. | |
1487 | */ | |
1488 | static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg, | |
1489 | int epnum, bool was_setup) | |
1490 | { | |
a33e7136 | 1491 | u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum)); |
5b7d70c6 BD |
1492 | struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum]; |
1493 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
1494 | struct usb_request *req = &hs_req->req; | |
a33e7136 | 1495 | unsigned size_left = S3C_DxEPTSIZ_XferSize_GET(epsize); |
5b7d70c6 BD |
1496 | int result = 0; |
1497 | ||
1498 | if (!hs_req) { | |
1499 | dev_dbg(hsotg->dev, "%s: no request active\n", __func__); | |
1500 | return; | |
1501 | } | |
1502 | ||
1503 | if (using_dma(hsotg)) { | |
5b7d70c6 | 1504 | unsigned size_done; |
5b7d70c6 BD |
1505 | |
1506 | /* Calculate the size of the transfer by checking how much | |
1507 | * is left in the endpoint size register and then working it | |
1508 | * out from the amount we loaded for the transfer. | |
1509 | * | |
1510 | * We need to do this as DMA pointers are always 32bit aligned | |
1511 | * so may overshoot/undershoot the transfer. | |
1512 | */ | |
1513 | ||
5b7d70c6 BD |
1514 | size_done = hs_ep->size_loaded - size_left; |
1515 | size_done += hs_ep->last_load; | |
1516 | ||
1517 | req->actual = size_done; | |
1518 | } | |
1519 | ||
a33e7136 BD |
1520 | /* if there is more request to do, schedule new transfer */ |
1521 | if (req->actual < req->length && size_left == 0) { | |
1522 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
1523 | return; | |
1524 | } | |
1525 | ||
5b7d70c6 BD |
1526 | if (req->actual < req->length && req->short_not_ok) { |
1527 | dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", | |
1528 | __func__, req->actual, req->length); | |
1529 | ||
1530 | /* todo - what should we return here? there's no one else | |
1531 | * even bothering to check the status. */ | |
1532 | } | |
1533 | ||
1534 | if (epnum == 0) { | |
1535 | if (!was_setup && req->complete != s3c_hsotg_complete_setup) | |
1536 | s3c_hsotg_send_zlp(hsotg, hs_req); | |
1537 | } | |
1538 | ||
1539 | s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result); | |
1540 | } | |
1541 | ||
1542 | /** | |
1543 | * s3c_hsotg_read_frameno - read current frame number | |
1544 | * @hsotg: The device instance | |
1545 | * | |
1546 | * Return the current frame number | |
1547 | */ | |
1548 | static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg) | |
1549 | { | |
1550 | u32 dsts; | |
1551 | ||
1552 | dsts = readl(hsotg->regs + S3C_DSTS); | |
1553 | dsts &= S3C_DSTS_SOFFN_MASK; | |
1554 | dsts >>= S3C_DSTS_SOFFN_SHIFT; | |
1555 | ||
1556 | return dsts; | |
1557 | } | |
1558 | ||
1559 | /** | |
1560 | * s3c_hsotg_handle_rx - RX FIFO has data | |
1561 | * @hsotg: The device instance | |
1562 | * | |
1563 | * The IRQ handler has detected that the RX FIFO has some data in it | |
1564 | * that requires processing, so find out what is in there and do the | |
1565 | * appropriate read. | |
1566 | * | |
25985edc | 1567 | * The RXFIFO is a true FIFO, the packets coming out are still in packet |
5b7d70c6 BD |
1568 | * chunks, so if you have x packets received on an endpoint you'll get x |
1569 | * FIFO events delivered, each with a packet's worth of data in it. | |
1570 | * | |
1571 | * When using DMA, we should not be processing events from the RXFIFO | |
1572 | * as the actual data should be sent to the memory directly and we turn | |
1573 | * on the completion interrupts to get notifications of transfer completion. | |
1574 | */ | |
0978f8c5 | 1575 | static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg) |
5b7d70c6 BD |
1576 | { |
1577 | u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP); | |
1578 | u32 epnum, status, size; | |
1579 | ||
1580 | WARN_ON(using_dma(hsotg)); | |
1581 | ||
1582 | epnum = grxstsr & S3C_GRXSTS_EPNum_MASK; | |
1583 | status = grxstsr & S3C_GRXSTS_PktSts_MASK; | |
1584 | ||
1585 | size = grxstsr & S3C_GRXSTS_ByteCnt_MASK; | |
1586 | size >>= S3C_GRXSTS_ByteCnt_SHIFT; | |
1587 | ||
1588 | if (1) | |
1589 | dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", | |
1590 | __func__, grxstsr, size, epnum); | |
1591 | ||
1592 | #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT) | |
1593 | ||
1594 | switch (status >> S3C_GRXSTS_PktSts_SHIFT) { | |
1595 | case __status(S3C_GRXSTS_PktSts_GlobalOutNAK): | |
1596 | dev_dbg(hsotg->dev, "GlobalOutNAK\n"); | |
1597 | break; | |
1598 | ||
1599 | case __status(S3C_GRXSTS_PktSts_OutDone): | |
1600 | dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", | |
1601 | s3c_hsotg_read_frameno(hsotg)); | |
1602 | ||
1603 | if (!using_dma(hsotg)) | |
1604 | s3c_hsotg_handle_outdone(hsotg, epnum, false); | |
1605 | break; | |
1606 | ||
1607 | case __status(S3C_GRXSTS_PktSts_SetupDone): | |
1608 | dev_dbg(hsotg->dev, | |
1609 | "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1610 | s3c_hsotg_read_frameno(hsotg), | |
1611 | readl(hsotg->regs + S3C_DOEPCTL(0))); | |
1612 | ||
1613 | s3c_hsotg_handle_outdone(hsotg, epnum, true); | |
1614 | break; | |
1615 | ||
1616 | case __status(S3C_GRXSTS_PktSts_OutRX): | |
1617 | s3c_hsotg_rx_data(hsotg, epnum, size); | |
1618 | break; | |
1619 | ||
1620 | case __status(S3C_GRXSTS_PktSts_SetupRX): | |
1621 | dev_dbg(hsotg->dev, | |
1622 | "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", | |
1623 | s3c_hsotg_read_frameno(hsotg), | |
1624 | readl(hsotg->regs + S3C_DOEPCTL(0))); | |
1625 | ||
1626 | s3c_hsotg_rx_data(hsotg, epnum, size); | |
1627 | break; | |
1628 | ||
1629 | default: | |
1630 | dev_warn(hsotg->dev, "%s: unknown status %08x\n", | |
1631 | __func__, grxstsr); | |
1632 | ||
1633 | s3c_hsotg_dump(hsotg); | |
1634 | break; | |
1635 | } | |
1636 | } | |
1637 | ||
1638 | /** | |
1639 | * s3c_hsotg_ep0_mps - turn max packet size into register setting | |
1640 | * @mps: The maximum packet size in bytes. | |
1641 | */ | |
1642 | static u32 s3c_hsotg_ep0_mps(unsigned int mps) | |
1643 | { | |
1644 | switch (mps) { | |
1645 | case 64: | |
1646 | return S3C_D0EPCTL_MPS_64; | |
1647 | case 32: | |
1648 | return S3C_D0EPCTL_MPS_32; | |
1649 | case 16: | |
1650 | return S3C_D0EPCTL_MPS_16; | |
1651 | case 8: | |
1652 | return S3C_D0EPCTL_MPS_8; | |
1653 | } | |
1654 | ||
1655 | /* bad max packet size, warn and return invalid result */ | |
1656 | WARN_ON(1); | |
1657 | return (u32)-1; | |
1658 | } | |
1659 | ||
1660 | /** | |
1661 | * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field | |
1662 | * @hsotg: The driver state. | |
1663 | * @ep: The index number of the endpoint | |
1664 | * @mps: The maximum packet size in bytes | |
1665 | * | |
1666 | * Configure the maximum packet size for the given endpoint, updating | |
1667 | * the hardware control registers to reflect this. | |
1668 | */ | |
1669 | static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg, | |
1670 | unsigned int ep, unsigned int mps) | |
1671 | { | |
1672 | struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep]; | |
1673 | void __iomem *regs = hsotg->regs; | |
1674 | u32 mpsval; | |
1675 | u32 reg; | |
1676 | ||
1677 | if (ep == 0) { | |
1678 | /* EP0 is a special case */ | |
1679 | mpsval = s3c_hsotg_ep0_mps(mps); | |
1680 | if (mpsval > 3) | |
1681 | goto bad_mps; | |
1682 | } else { | |
1683 | if (mps >= S3C_DxEPCTL_MPS_LIMIT+1) | |
1684 | goto bad_mps; | |
1685 | ||
1686 | mpsval = mps; | |
1687 | } | |
1688 | ||
1689 | hs_ep->ep.maxpacket = mps; | |
1690 | ||
1691 | /* update both the in and out endpoint controldir_ registers, even | |
1692 | * if one of the directions may not be in use. */ | |
1693 | ||
1694 | reg = readl(regs + S3C_DIEPCTL(ep)); | |
1695 | reg &= ~S3C_DxEPCTL_MPS_MASK; | |
1696 | reg |= mpsval; | |
1697 | writel(reg, regs + S3C_DIEPCTL(ep)); | |
1698 | ||
1699 | reg = readl(regs + S3C_DOEPCTL(ep)); | |
1700 | reg &= ~S3C_DxEPCTL_MPS_MASK; | |
1701 | reg |= mpsval; | |
1702 | writel(reg, regs + S3C_DOEPCTL(ep)); | |
1703 | ||
1704 | return; | |
1705 | ||
1706 | bad_mps: | |
1707 | dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps); | |
1708 | } | |
1709 | ||
9c39ddc6 AT |
1710 | /** |
1711 | * s3c_hsotg_txfifo_flush - flush Tx FIFO | |
1712 | * @hsotg: The driver state | |
1713 | * @idx: The index for the endpoint (0..15) | |
1714 | */ | |
1715 | static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx) | |
1716 | { | |
1717 | int timeout; | |
1718 | int val; | |
1719 | ||
1720 | writel(S3C_GRSTCTL_TxFNum(idx) | S3C_GRSTCTL_TxFFlsh, | |
1721 | hsotg->regs + S3C_GRSTCTL); | |
1722 | ||
1723 | /* wait until the fifo is flushed */ | |
1724 | timeout = 100; | |
1725 | ||
1726 | while (1) { | |
1727 | val = readl(hsotg->regs + S3C_GRSTCTL); | |
1728 | ||
1729 | if ((val & (S3C_GRSTCTL_TxFFlsh)) == 0) | |
1730 | break; | |
1731 | ||
1732 | if (--timeout == 0) { | |
1733 | dev_err(hsotg->dev, | |
1734 | "%s: timeout flushing fifo (GRSTCTL=%08x)\n", | |
1735 | __func__, val); | |
1736 | } | |
1737 | ||
1738 | udelay(1); | |
1739 | } | |
1740 | } | |
5b7d70c6 BD |
1741 | |
1742 | /** | |
1743 | * s3c_hsotg_trytx - check to see if anything needs transmitting | |
1744 | * @hsotg: The driver state | |
1745 | * @hs_ep: The driver endpoint to check. | |
1746 | * | |
1747 | * Check to see if there is a request that has data to send, and if so | |
1748 | * make an attempt to write data into the FIFO. | |
1749 | */ | |
1750 | static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg, | |
1751 | struct s3c_hsotg_ep *hs_ep) | |
1752 | { | |
1753 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
1754 | ||
1755 | if (!hs_ep->dir_in || !hs_req) | |
1756 | return 0; | |
1757 | ||
1758 | if (hs_req->req.actual < hs_req->req.length) { | |
1759 | dev_dbg(hsotg->dev, "trying to write more for ep%d\n", | |
1760 | hs_ep->index); | |
1761 | return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); | |
1762 | } | |
1763 | ||
1764 | return 0; | |
1765 | } | |
1766 | ||
1767 | /** | |
1768 | * s3c_hsotg_complete_in - complete IN transfer | |
1769 | * @hsotg: The device state. | |
1770 | * @hs_ep: The endpoint that has just completed. | |
1771 | * | |
1772 | * An IN transfer has been completed, update the transfer's state and then | |
1773 | * call the relevant completion routines. | |
1774 | */ | |
1775 | static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg, | |
1776 | struct s3c_hsotg_ep *hs_ep) | |
1777 | { | |
1778 | struct s3c_hsotg_req *hs_req = hs_ep->req; | |
1779 | u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index)); | |
1780 | int size_left, size_done; | |
1781 | ||
1782 | if (!hs_req) { | |
1783 | dev_dbg(hsotg->dev, "XferCompl but no req\n"); | |
1784 | return; | |
1785 | } | |
1786 | ||
1787 | /* Calculate the size of the transfer by checking how much is left | |
1788 | * in the endpoint size register and then working it out from | |
1789 | * the amount we loaded for the transfer. | |
1790 | * | |
1791 | * We do this even for DMA, as the transfer may have incremented | |
1792 | * past the end of the buffer (DMA transfers are always 32bit | |
1793 | * aligned). | |
1794 | */ | |
1795 | ||
1796 | size_left = S3C_DxEPTSIZ_XferSize_GET(epsize); | |
1797 | ||
1798 | size_done = hs_ep->size_loaded - size_left; | |
1799 | size_done += hs_ep->last_load; | |
1800 | ||
1801 | if (hs_req->req.actual != size_done) | |
1802 | dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n", | |
1803 | __func__, hs_req->req.actual, size_done); | |
1804 | ||
1805 | hs_req->req.actual = size_done; | |
1806 | ||
1807 | /* if we did all of the transfer, and there is more data left | |
1808 | * around, then try restarting the rest of the request */ | |
1809 | ||
1810 | if (!size_left && hs_req->req.actual < hs_req->req.length) { | |
1811 | dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); | |
1812 | s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); | |
1813 | } else | |
1814 | s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0); | |
1815 | } | |
1816 | ||
1817 | /** | |
1818 | * s3c_hsotg_epint - handle an in/out endpoint interrupt | |
1819 | * @hsotg: The driver state | |
1820 | * @idx: The index for the endpoint (0..15) | |
1821 | * @dir_in: Set if this is an IN endpoint | |
1822 | * | |
1823 | * Process and clear any interrupt pending for an individual endpoint | |
1824 | */ | |
1825 | static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx, | |
1826 | int dir_in) | |
1827 | { | |
1828 | struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx]; | |
1829 | u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx); | |
1830 | u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx); | |
1831 | u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx); | |
1832 | u32 ints; | |
5b7d70c6 BD |
1833 | |
1834 | ints = readl(hsotg->regs + epint_reg); | |
1835 | ||
a3395f0d AT |
1836 | /* Clear endpoint interrupts */ |
1837 | writel(ints, hsotg->regs + epint_reg); | |
1838 | ||
5b7d70c6 BD |
1839 | dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", |
1840 | __func__, idx, dir_in ? "in" : "out", ints); | |
1841 | ||
1842 | if (ints & S3C_DxEPINT_XferCompl) { | |
1843 | dev_dbg(hsotg->dev, | |
1844 | "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n", | |
1845 | __func__, readl(hsotg->regs + epctl_reg), | |
1846 | readl(hsotg->regs + epsiz_reg)); | |
1847 | ||
1848 | /* we get OutDone from the FIFO, so we only need to look | |
1849 | * at completing IN requests here */ | |
1850 | if (dir_in) { | |
1851 | s3c_hsotg_complete_in(hsotg, hs_ep); | |
1852 | ||
c9a64ea8 | 1853 | if (idx == 0 && !hs_ep->req) |
5b7d70c6 BD |
1854 | s3c_hsotg_enqueue_setup(hsotg); |
1855 | } else if (using_dma(hsotg)) { | |
1856 | /* We're using DMA, we need to fire an OutDone here | |
1857 | * as we ignore the RXFIFO. */ | |
1858 | ||
1859 | s3c_hsotg_handle_outdone(hsotg, idx, false); | |
1860 | } | |
5b7d70c6 BD |
1861 | } |
1862 | ||
9c39ddc6 | 1863 | if (ints & S3C_DxEPINT_EPDisbld) { |
5b7d70c6 | 1864 | dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); |
5b7d70c6 | 1865 | |
9c39ddc6 AT |
1866 | if (dir_in) { |
1867 | int epctl = readl(hsotg->regs + epctl_reg); | |
1868 | ||
1869 | s3c_hsotg_txfifo_flush(hsotg, idx); | |
1870 | ||
1871 | if ((epctl & S3C_DxEPCTL_Stall) && | |
1872 | (epctl & S3C_DxEPCTL_EPType_Bulk)) { | |
1873 | int dctl = readl(hsotg->regs + S3C_DCTL); | |
1874 | ||
1875 | dctl |= S3C_DCTL_CGNPInNAK; | |
1876 | writel(dctl, hsotg->regs + S3C_DCTL); | |
1877 | } | |
1878 | } | |
1879 | } | |
1880 | ||
a3395f0d | 1881 | if (ints & S3C_DxEPINT_AHBErr) |
5b7d70c6 | 1882 | dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); |
5b7d70c6 BD |
1883 | |
1884 | if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */ | |
1885 | dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); | |
1886 | ||
1887 | if (using_dma(hsotg) && idx == 0) { | |
1888 | /* this is the notification we've received a | |
1889 | * setup packet. In non-DMA mode we'd get this | |
1890 | * from the RXFIFO, instead we need to process | |
1891 | * the setup here. */ | |
1892 | ||
1893 | if (dir_in) | |
1894 | WARN_ON_ONCE(1); | |
1895 | else | |
1896 | s3c_hsotg_handle_outdone(hsotg, 0, true); | |
1897 | } | |
5b7d70c6 BD |
1898 | } |
1899 | ||
a3395f0d | 1900 | if (ints & S3C_DxEPINT_Back2BackSetup) |
5b7d70c6 | 1901 | dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); |
5b7d70c6 BD |
1902 | |
1903 | if (dir_in) { | |
1904 | /* not sure if this is important, but we'll clear it anyway | |
1905 | */ | |
1906 | if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) { | |
1907 | dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", | |
1908 | __func__, idx); | |
5b7d70c6 BD |
1909 | } |
1910 | ||
1911 | /* this probably means something bad is happening */ | |
1912 | if (ints & S3C_DIEPMSK_INTknEPMisMsk) { | |
1913 | dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", | |
1914 | __func__, idx); | |
5b7d70c6 | 1915 | } |
10aebc77 BD |
1916 | |
1917 | /* FIFO has space or is empty (see GAHBCFG) */ | |
1918 | if (hsotg->dedicated_fifos && | |
1919 | ints & S3C_DIEPMSK_TxFIFOEmpty) { | |
1920 | dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", | |
1921 | __func__, idx); | |
1922 | s3c_hsotg_trytx(hsotg, hs_ep); | |
10aebc77 | 1923 | } |
5b7d70c6 | 1924 | } |
5b7d70c6 BD |
1925 | } |
1926 | ||
1927 | /** | |
1928 | * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done) | |
1929 | * @hsotg: The device state. | |
1930 | * | |
1931 | * Handle updating the device settings after the enumeration phase has | |
1932 | * been completed. | |
1933 | */ | |
1934 | static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg) | |
1935 | { | |
1936 | u32 dsts = readl(hsotg->regs + S3C_DSTS); | |
1937 | int ep0_mps = 0, ep_mps; | |
1938 | ||
1939 | /* This should signal the finish of the enumeration phase | |
1940 | * of the USB handshaking, so we should now know what rate | |
1941 | * we connected at. */ | |
1942 | ||
1943 | dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); | |
1944 | ||
1945 | /* note, since we're limited by the size of transfer on EP0, and | |
1946 | * it seems IN transfers must be a even number of packets we do | |
1947 | * not advertise a 64byte MPS on EP0. */ | |
1948 | ||
1949 | /* catch both EnumSpd_FS and EnumSpd_FS48 */ | |
1950 | switch (dsts & S3C_DSTS_EnumSpd_MASK) { | |
1951 | case S3C_DSTS_EnumSpd_FS: | |
1952 | case S3C_DSTS_EnumSpd_FS48: | |
1953 | hsotg->gadget.speed = USB_SPEED_FULL; | |
5b7d70c6 BD |
1954 | ep0_mps = EP0_MPS_LIMIT; |
1955 | ep_mps = 64; | |
1956 | break; | |
1957 | ||
1958 | case S3C_DSTS_EnumSpd_HS: | |
5b7d70c6 | 1959 | hsotg->gadget.speed = USB_SPEED_HIGH; |
5b7d70c6 BD |
1960 | ep0_mps = EP0_MPS_LIMIT; |
1961 | ep_mps = 512; | |
1962 | break; | |
1963 | ||
1964 | case S3C_DSTS_EnumSpd_LS: | |
1965 | hsotg->gadget.speed = USB_SPEED_LOW; | |
5b7d70c6 BD |
1966 | /* note, we don't actually support LS in this driver at the |
1967 | * moment, and the documentation seems to imply that it isn't | |
1968 | * supported by the PHYs on some of the devices. | |
1969 | */ | |
1970 | break; | |
1971 | } | |
e538dfda MN |
1972 | dev_info(hsotg->dev, "new device is %s\n", |
1973 | usb_speed_string(hsotg->gadget.speed)); | |
5b7d70c6 BD |
1974 | |
1975 | /* we should now know the maximum packet size for an | |
1976 | * endpoint, so set the endpoints to a default value. */ | |
1977 | ||
1978 | if (ep0_mps) { | |
1979 | int i; | |
1980 | s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps); | |
1981 | for (i = 1; i < S3C_HSOTG_EPS; i++) | |
1982 | s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps); | |
1983 | } | |
1984 | ||
1985 | /* ensure after enumeration our EP0 is active */ | |
1986 | ||
1987 | s3c_hsotg_enqueue_setup(hsotg); | |
1988 | ||
1989 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", | |
1990 | readl(hsotg->regs + S3C_DIEPCTL0), | |
1991 | readl(hsotg->regs + S3C_DOEPCTL0)); | |
1992 | } | |
1993 | ||
1994 | /** | |
1995 | * kill_all_requests - remove all requests from the endpoint's queue | |
1996 | * @hsotg: The device state. | |
1997 | * @ep: The endpoint the requests may be on. | |
1998 | * @result: The result code to use. | |
1999 | * @force: Force removal of any current requests | |
2000 | * | |
2001 | * Go through the requests on the given endpoint and mark them | |
2002 | * completed with the given result code. | |
2003 | */ | |
2004 | static void kill_all_requests(struct s3c_hsotg *hsotg, | |
2005 | struct s3c_hsotg_ep *ep, | |
2006 | int result, bool force) | |
2007 | { | |
2008 | struct s3c_hsotg_req *req, *treq; | |
2009 | unsigned long flags; | |
2010 | ||
2011 | spin_lock_irqsave(&ep->lock, flags); | |
2012 | ||
2013 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
2014 | /* currently, we can't do much about an already | |
2015 | * running request on an in endpoint */ | |
2016 | ||
2017 | if (ep->req == req && ep->dir_in && !force) | |
2018 | continue; | |
2019 | ||
2020 | s3c_hsotg_complete_request(hsotg, ep, req, | |
2021 | result); | |
2022 | } | |
2023 | ||
2024 | spin_unlock_irqrestore(&ep->lock, flags); | |
2025 | } | |
2026 | ||
2027 | #define call_gadget(_hs, _entry) \ | |
2028 | if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ | |
2029 | (_hs)->driver && (_hs)->driver->_entry) \ | |
2030 | (_hs)->driver->_entry(&(_hs)->gadget); | |
2031 | ||
2032 | /** | |
2033 | * s3c_hsotg_disconnect_irq - disconnect irq service | |
2034 | * @hsotg: The device state. | |
2035 | * | |
2036 | * A disconnect IRQ has been received, meaning that the host has | |
2037 | * lost contact with the bus. Remove all current transactions | |
2038 | * and signal the gadget driver that this has happened. | |
2039 | */ | |
2040 | static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg) | |
2041 | { | |
2042 | unsigned ep; | |
2043 | ||
2044 | for (ep = 0; ep < S3C_HSOTG_EPS; ep++) | |
2045 | kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true); | |
2046 | ||
2047 | call_gadget(hsotg, disconnect); | |
2048 | } | |
2049 | ||
2050 | /** | |
2051 | * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler | |
2052 | * @hsotg: The device state: | |
2053 | * @periodic: True if this is a periodic FIFO interrupt | |
2054 | */ | |
2055 | static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic) | |
2056 | { | |
2057 | struct s3c_hsotg_ep *ep; | |
2058 | int epno, ret; | |
2059 | ||
2060 | /* look through for any more data to transmit */ | |
2061 | ||
2062 | for (epno = 0; epno < S3C_HSOTG_EPS; epno++) { | |
2063 | ep = &hsotg->eps[epno]; | |
2064 | ||
2065 | if (!ep->dir_in) | |
2066 | continue; | |
2067 | ||
2068 | if ((periodic && !ep->periodic) || | |
2069 | (!periodic && ep->periodic)) | |
2070 | continue; | |
2071 | ||
2072 | ret = s3c_hsotg_trytx(hsotg, ep); | |
2073 | if (ret < 0) | |
2074 | break; | |
2075 | } | |
2076 | } | |
2077 | ||
2078 | static struct s3c_hsotg *our_hsotg; | |
2079 | ||
2080 | /* IRQ flags which will trigger a retry around the IRQ loop */ | |
2081 | #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \ | |
2082 | S3C_GINTSTS_PTxFEmp | \ | |
2083 | S3C_GINTSTS_RxFLvl) | |
2084 | ||
2085 | /** | |
2086 | * s3c_hsotg_irq - handle device interrupt | |
2087 | * @irq: The IRQ number triggered | |
2088 | * @pw: The pw value when registered the handler. | |
2089 | */ | |
2090 | static irqreturn_t s3c_hsotg_irq(int irq, void *pw) | |
2091 | { | |
2092 | struct s3c_hsotg *hsotg = pw; | |
2093 | int retry_count = 8; | |
2094 | u32 gintsts; | |
2095 | u32 gintmsk; | |
2096 | ||
2097 | irq_retry: | |
2098 | gintsts = readl(hsotg->regs + S3C_GINTSTS); | |
2099 | gintmsk = readl(hsotg->regs + S3C_GINTMSK); | |
2100 | ||
2101 | dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", | |
2102 | __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); | |
2103 | ||
2104 | gintsts &= gintmsk; | |
2105 | ||
2106 | if (gintsts & S3C_GINTSTS_OTGInt) { | |
2107 | u32 otgint = readl(hsotg->regs + S3C_GOTGINT); | |
2108 | ||
2109 | dev_info(hsotg->dev, "OTGInt: %08x\n", otgint); | |
2110 | ||
2111 | writel(otgint, hsotg->regs + S3C_GOTGINT); | |
5b7d70c6 BD |
2112 | } |
2113 | ||
2114 | if (gintsts & S3C_GINTSTS_DisconnInt) { | |
2115 | dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__); | |
2116 | writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS); | |
2117 | ||
2118 | s3c_hsotg_disconnect_irq(hsotg); | |
2119 | } | |
2120 | ||
2121 | if (gintsts & S3C_GINTSTS_SessReqInt) { | |
2122 | dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__); | |
2123 | writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS); | |
2124 | } | |
2125 | ||
2126 | if (gintsts & S3C_GINTSTS_EnumDone) { | |
5b7d70c6 | 2127 | writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS); |
a3395f0d AT |
2128 | |
2129 | s3c_hsotg_irq_enumdone(hsotg); | |
5b7d70c6 BD |
2130 | } |
2131 | ||
2132 | if (gintsts & S3C_GINTSTS_ConIDStsChng) { | |
2133 | dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n", | |
2134 | readl(hsotg->regs + S3C_DSTS), | |
2135 | readl(hsotg->regs + S3C_GOTGCTL)); | |
2136 | ||
2137 | writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS); | |
2138 | } | |
2139 | ||
2140 | if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) { | |
2141 | u32 daint = readl(hsotg->regs + S3C_DAINT); | |
2142 | u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT; | |
2143 | u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT); | |
2144 | int ep; | |
2145 | ||
2146 | dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); | |
2147 | ||
2148 | for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) { | |
2149 | if (daint_out & 1) | |
2150 | s3c_hsotg_epint(hsotg, ep, 0); | |
2151 | } | |
2152 | ||
2153 | for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) { | |
2154 | if (daint_in & 1) | |
2155 | s3c_hsotg_epint(hsotg, ep, 1); | |
2156 | } | |
5b7d70c6 BD |
2157 | } |
2158 | ||
2159 | if (gintsts & S3C_GINTSTS_USBRst) { | |
2160 | dev_info(hsotg->dev, "%s: USBRst\n", __func__); | |
2161 | dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", | |
2162 | readl(hsotg->regs + S3C_GNPTXSTS)); | |
2163 | ||
a3395f0d AT |
2164 | writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS); |
2165 | ||
5b7d70c6 BD |
2166 | kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true); |
2167 | ||
2168 | /* it seems after a reset we can end up with a situation | |
b3864ced BD |
2169 | * where the TXFIFO still has data in it... the docs |
2170 | * suggest resetting all the fifos, so use the init_fifo | |
2171 | * code to relayout and flush the fifos. | |
5b7d70c6 BD |
2172 | */ |
2173 | ||
b3864ced | 2174 | s3c_hsotg_init_fifo(hsotg); |
5b7d70c6 BD |
2175 | |
2176 | s3c_hsotg_enqueue_setup(hsotg); | |
5b7d70c6 BD |
2177 | } |
2178 | ||
2179 | /* check both FIFOs */ | |
2180 | ||
2181 | if (gintsts & S3C_GINTSTS_NPTxFEmp) { | |
2182 | dev_dbg(hsotg->dev, "NPTxFEmp\n"); | |
2183 | ||
2184 | /* Disable the interrupt to stop it happening again | |
2185 | * unless one of these endpoint routines decides that | |
2186 | * it needs re-enabling */ | |
2187 | ||
2188 | s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp); | |
2189 | s3c_hsotg_irq_fifoempty(hsotg, false); | |
5b7d70c6 BD |
2190 | } |
2191 | ||
2192 | if (gintsts & S3C_GINTSTS_PTxFEmp) { | |
2193 | dev_dbg(hsotg->dev, "PTxFEmp\n"); | |
2194 | ||
2195 | /* See note in S3C_GINTSTS_NPTxFEmp */ | |
2196 | ||
2197 | s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp); | |
2198 | s3c_hsotg_irq_fifoempty(hsotg, true); | |
5b7d70c6 BD |
2199 | } |
2200 | ||
2201 | if (gintsts & S3C_GINTSTS_RxFLvl) { | |
2202 | /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, | |
2203 | * we need to retry s3c_hsotg_handle_rx if this is still | |
2204 | * set. */ | |
2205 | ||
2206 | s3c_hsotg_handle_rx(hsotg); | |
5b7d70c6 BD |
2207 | } |
2208 | ||
2209 | if (gintsts & S3C_GINTSTS_ModeMis) { | |
2210 | dev_warn(hsotg->dev, "warning, mode mismatch triggered\n"); | |
2211 | writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS); | |
2212 | } | |
2213 | ||
2214 | if (gintsts & S3C_GINTSTS_USBSusp) { | |
2215 | dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n"); | |
2216 | writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS); | |
2217 | ||
2218 | call_gadget(hsotg, suspend); | |
2219 | } | |
2220 | ||
2221 | if (gintsts & S3C_GINTSTS_WkUpInt) { | |
2222 | dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n"); | |
2223 | writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS); | |
2224 | ||
2225 | call_gadget(hsotg, resume); | |
2226 | } | |
2227 | ||
2228 | if (gintsts & S3C_GINTSTS_ErlySusp) { | |
2229 | dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n"); | |
2230 | writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS); | |
2231 | } | |
2232 | ||
2233 | /* these next two seem to crop-up occasionally causing the core | |
2234 | * to shutdown the USB transfer, so try clearing them and logging | |
25985edc | 2235 | * the occurrence. */ |
5b7d70c6 BD |
2236 | |
2237 | if (gintsts & S3C_GINTSTS_GOUTNakEff) { | |
2238 | dev_info(hsotg->dev, "GOUTNakEff triggered\n"); | |
2239 | ||
5b7d70c6 | 2240 | writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL); |
a3395f0d AT |
2241 | |
2242 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2243 | } |
2244 | ||
2245 | if (gintsts & S3C_GINTSTS_GINNakEff) { | |
2246 | dev_info(hsotg->dev, "GINNakEff triggered\n"); | |
2247 | ||
5b7d70c6 | 2248 | writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL); |
a3395f0d AT |
2249 | |
2250 | s3c_hsotg_dump(hsotg); | |
5b7d70c6 BD |
2251 | } |
2252 | ||
2253 | /* if we've had fifo events, we should try and go around the | |
2254 | * loop again to see if there's any point in returning yet. */ | |
2255 | ||
2256 | if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) | |
2257 | goto irq_retry; | |
2258 | ||
2259 | return IRQ_HANDLED; | |
2260 | } | |
2261 | ||
2262 | /** | |
2263 | * s3c_hsotg_ep_enable - enable the given endpoint | |
2264 | * @ep: The USB endpint to configure | |
2265 | * @desc: The USB endpoint descriptor to configure with. | |
2266 | * | |
2267 | * This is called from the USB gadget code's usb_ep_enable(). | |
2268 | */ | |
2269 | static int s3c_hsotg_ep_enable(struct usb_ep *ep, | |
2270 | const struct usb_endpoint_descriptor *desc) | |
2271 | { | |
2272 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2273 | struct s3c_hsotg *hsotg = hs_ep->parent; | |
2274 | unsigned long flags; | |
2275 | int index = hs_ep->index; | |
2276 | u32 epctrl_reg; | |
2277 | u32 epctrl; | |
2278 | u32 mps; | |
2279 | int dir_in; | |
19c190f9 | 2280 | int ret = 0; |
5b7d70c6 BD |
2281 | |
2282 | dev_dbg(hsotg->dev, | |
2283 | "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n", | |
2284 | __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes, | |
2285 | desc->wMaxPacketSize, desc->bInterval); | |
2286 | ||
2287 | /* not to be called for EP0 */ | |
2288 | WARN_ON(index == 0); | |
2289 | ||
2290 | dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0; | |
2291 | if (dir_in != hs_ep->dir_in) { | |
2292 | dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__); | |
2293 | return -EINVAL; | |
2294 | } | |
2295 | ||
29cc8897 | 2296 | mps = usb_endpoint_maxp(desc); |
5b7d70c6 BD |
2297 | |
2298 | /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */ | |
2299 | ||
2300 | epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index); | |
2301 | epctrl = readl(hsotg->regs + epctrl_reg); | |
2302 | ||
2303 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", | |
2304 | __func__, epctrl, epctrl_reg); | |
2305 | ||
2306 | spin_lock_irqsave(&hs_ep->lock, flags); | |
2307 | ||
2308 | epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK); | |
2309 | epctrl |= S3C_DxEPCTL_MPS(mps); | |
2310 | ||
2311 | /* mark the endpoint as active, otherwise the core may ignore | |
2312 | * transactions entirely for this endpoint */ | |
2313 | epctrl |= S3C_DxEPCTL_USBActEp; | |
2314 | ||
2315 | /* set the NAK status on the endpoint, otherwise we might try and | |
2316 | * do something with data that we've yet got a request to process | |
2317 | * since the RXFIFO will take data for an endpoint even if the | |
2318 | * size register hasn't been set. | |
2319 | */ | |
2320 | ||
2321 | epctrl |= S3C_DxEPCTL_SNAK; | |
2322 | ||
2323 | /* update the endpoint state */ | |
2324 | hs_ep->ep.maxpacket = mps; | |
2325 | ||
2326 | /* default, set to non-periodic */ | |
2327 | hs_ep->periodic = 0; | |
2328 | ||
2329 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { | |
2330 | case USB_ENDPOINT_XFER_ISOC: | |
2331 | dev_err(hsotg->dev, "no current ISOC support\n"); | |
19c190f9 JL |
2332 | ret = -EINVAL; |
2333 | goto out; | |
5b7d70c6 BD |
2334 | |
2335 | case USB_ENDPOINT_XFER_BULK: | |
2336 | epctrl |= S3C_DxEPCTL_EPType_Bulk; | |
2337 | break; | |
2338 | ||
2339 | case USB_ENDPOINT_XFER_INT: | |
2340 | if (dir_in) { | |
2341 | /* Allocate our TxFNum by simply using the index | |
2342 | * of the endpoint for the moment. We could do | |
2343 | * something better if the host indicates how | |
2344 | * many FIFOs we are expecting to use. */ | |
2345 | ||
2346 | hs_ep->periodic = 1; | |
2347 | epctrl |= S3C_DxEPCTL_TxFNum(index); | |
2348 | } | |
2349 | ||
2350 | epctrl |= S3C_DxEPCTL_EPType_Intterupt; | |
2351 | break; | |
2352 | ||
2353 | case USB_ENDPOINT_XFER_CONTROL: | |
2354 | epctrl |= S3C_DxEPCTL_EPType_Control; | |
2355 | break; | |
2356 | } | |
2357 | ||
10aebc77 BD |
2358 | /* if the hardware has dedicated fifos, we must give each IN EP |
2359 | * a unique tx-fifo even if it is non-periodic. | |
2360 | */ | |
2361 | if (dir_in && hsotg->dedicated_fifos) | |
2362 | epctrl |= S3C_DxEPCTL_TxFNum(index); | |
2363 | ||
5b7d70c6 BD |
2364 | /* for non control endpoints, set PID to D0 */ |
2365 | if (index) | |
2366 | epctrl |= S3C_DxEPCTL_SetD0PID; | |
2367 | ||
2368 | dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", | |
2369 | __func__, epctrl); | |
2370 | ||
2371 | writel(epctrl, hsotg->regs + epctrl_reg); | |
2372 | dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", | |
2373 | __func__, readl(hsotg->regs + epctrl_reg)); | |
2374 | ||
2375 | /* enable the endpoint interrupt */ | |
2376 | s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1); | |
2377 | ||
19c190f9 | 2378 | out: |
5b7d70c6 | 2379 | spin_unlock_irqrestore(&hs_ep->lock, flags); |
19c190f9 | 2380 | return ret; |
5b7d70c6 BD |
2381 | } |
2382 | ||
2383 | static int s3c_hsotg_ep_disable(struct usb_ep *ep) | |
2384 | { | |
2385 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2386 | struct s3c_hsotg *hsotg = hs_ep->parent; | |
2387 | int dir_in = hs_ep->dir_in; | |
2388 | int index = hs_ep->index; | |
2389 | unsigned long flags; | |
2390 | u32 epctrl_reg; | |
2391 | u32 ctrl; | |
2392 | ||
2393 | dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep); | |
2394 | ||
2395 | if (ep == &hsotg->eps[0].ep) { | |
2396 | dev_err(hsotg->dev, "%s: called for ep0\n", __func__); | |
2397 | return -EINVAL; | |
2398 | } | |
2399 | ||
2400 | epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index); | |
2401 | ||
2402 | /* terminate all requests with shutdown */ | |
2403 | kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false); | |
2404 | ||
2405 | spin_lock_irqsave(&hs_ep->lock, flags); | |
2406 | ||
2407 | ctrl = readl(hsotg->regs + epctrl_reg); | |
2408 | ctrl &= ~S3C_DxEPCTL_EPEna; | |
2409 | ctrl &= ~S3C_DxEPCTL_USBActEp; | |
2410 | ctrl |= S3C_DxEPCTL_SNAK; | |
2411 | ||
2412 | dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); | |
2413 | writel(ctrl, hsotg->regs + epctrl_reg); | |
2414 | ||
2415 | /* disable endpoint interrupts */ | |
2416 | s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); | |
2417 | ||
2418 | spin_unlock_irqrestore(&hs_ep->lock, flags); | |
2419 | return 0; | |
2420 | } | |
2421 | ||
2422 | /** | |
2423 | * on_list - check request is on the given endpoint | |
2424 | * @ep: The endpoint to check. | |
2425 | * @test: The request to test if it is on the endpoint. | |
2426 | */ | |
2427 | static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test) | |
2428 | { | |
2429 | struct s3c_hsotg_req *req, *treq; | |
2430 | ||
2431 | list_for_each_entry_safe(req, treq, &ep->queue, queue) { | |
2432 | if (req == test) | |
2433 | return true; | |
2434 | } | |
2435 | ||
2436 | return false; | |
2437 | } | |
2438 | ||
2439 | static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) | |
2440 | { | |
2441 | struct s3c_hsotg_req *hs_req = our_req(req); | |
2442 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2443 | struct s3c_hsotg *hs = hs_ep->parent; | |
2444 | unsigned long flags; | |
2445 | ||
2446 | dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req); | |
2447 | ||
5b7d70c6 BD |
2448 | spin_lock_irqsave(&hs_ep->lock, flags); |
2449 | ||
2450 | if (!on_list(hs_ep, hs_req)) { | |
2451 | spin_unlock_irqrestore(&hs_ep->lock, flags); | |
2452 | return -EINVAL; | |
2453 | } | |
2454 | ||
2455 | s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET); | |
2456 | spin_unlock_irqrestore(&hs_ep->lock, flags); | |
2457 | ||
2458 | return 0; | |
2459 | } | |
2460 | ||
2461 | static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value) | |
2462 | { | |
2463 | struct s3c_hsotg_ep *hs_ep = our_ep(ep); | |
2464 | struct s3c_hsotg *hs = hs_ep->parent; | |
2465 | int index = hs_ep->index; | |
2466 | unsigned long irqflags; | |
2467 | u32 epreg; | |
2468 | u32 epctl; | |
9c39ddc6 | 2469 | u32 xfertype; |
5b7d70c6 BD |
2470 | |
2471 | dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value); | |
2472 | ||
2473 | spin_lock_irqsave(&hs_ep->lock, irqflags); | |
2474 | ||
2475 | /* write both IN and OUT control registers */ | |
2476 | ||
2477 | epreg = S3C_DIEPCTL(index); | |
2478 | epctl = readl(hs->regs + epreg); | |
2479 | ||
9c39ddc6 AT |
2480 | if (value) { |
2481 | epctl |= S3C_DxEPCTL_Stall + S3C_DxEPCTL_SNAK; | |
2482 | if (epctl & S3C_DxEPCTL_EPEna) | |
2483 | epctl |= S3C_DxEPCTL_EPDis; | |
2484 | } else { | |
5b7d70c6 | 2485 | epctl &= ~S3C_DxEPCTL_Stall; |
9c39ddc6 AT |
2486 | xfertype = epctl & S3C_DxEPCTL_EPType_MASK; |
2487 | if (xfertype == S3C_DxEPCTL_EPType_Bulk || | |
2488 | xfertype == S3C_DxEPCTL_EPType_Intterupt) | |
2489 | epctl |= S3C_DxEPCTL_SetD0PID; | |
2490 | } | |
5b7d70c6 BD |
2491 | |
2492 | writel(epctl, hs->regs + epreg); | |
2493 | ||
2494 | epreg = S3C_DOEPCTL(index); | |
2495 | epctl = readl(hs->regs + epreg); | |
2496 | ||
2497 | if (value) | |
2498 | epctl |= S3C_DxEPCTL_Stall; | |
9c39ddc6 | 2499 | else { |
5b7d70c6 | 2500 | epctl &= ~S3C_DxEPCTL_Stall; |
9c39ddc6 AT |
2501 | xfertype = epctl & S3C_DxEPCTL_EPType_MASK; |
2502 | if (xfertype == S3C_DxEPCTL_EPType_Bulk || | |
2503 | xfertype == S3C_DxEPCTL_EPType_Intterupt) | |
2504 | epctl |= S3C_DxEPCTL_SetD0PID; | |
2505 | } | |
5b7d70c6 BD |
2506 | |
2507 | writel(epctl, hs->regs + epreg); | |
2508 | ||
2509 | spin_unlock_irqrestore(&hs_ep->lock, irqflags); | |
2510 | ||
2511 | return 0; | |
2512 | } | |
2513 | ||
2514 | static struct usb_ep_ops s3c_hsotg_ep_ops = { | |
2515 | .enable = s3c_hsotg_ep_enable, | |
2516 | .disable = s3c_hsotg_ep_disable, | |
2517 | .alloc_request = s3c_hsotg_ep_alloc_request, | |
2518 | .free_request = s3c_hsotg_ep_free_request, | |
2519 | .queue = s3c_hsotg_ep_queue, | |
2520 | .dequeue = s3c_hsotg_ep_dequeue, | |
2521 | .set_halt = s3c_hsotg_ep_sethalt, | |
25985edc | 2522 | /* note, don't believe we have any call for the fifo routines */ |
5b7d70c6 BD |
2523 | }; |
2524 | ||
2525 | /** | |
2526 | * s3c_hsotg_corereset - issue softreset to the core | |
2527 | * @hsotg: The device state | |
2528 | * | |
2529 | * Issue a soft reset to the core, and await the core finishing it. | |
2530 | */ | |
2531 | static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg) | |
2532 | { | |
2533 | int timeout; | |
2534 | u32 grstctl; | |
2535 | ||
2536 | dev_dbg(hsotg->dev, "resetting core\n"); | |
2537 | ||
2538 | /* issue soft reset */ | |
2539 | writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL); | |
2540 | ||
2541 | timeout = 1000; | |
2542 | do { | |
2543 | grstctl = readl(hsotg->regs + S3C_GRSTCTL); | |
d00f5004 | 2544 | } while ((grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0); |
5b7d70c6 | 2545 | |
d00f5004 | 2546 | if (grstctl & S3C_GRSTCTL_CSftRst) { |
5b7d70c6 BD |
2547 | dev_err(hsotg->dev, "Failed to get CSftRst asserted\n"); |
2548 | return -EINVAL; | |
2549 | } | |
2550 | ||
2551 | timeout = 1000; | |
2552 | ||
2553 | while (1) { | |
2554 | u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL); | |
2555 | ||
2556 | if (timeout-- < 0) { | |
2557 | dev_info(hsotg->dev, | |
2558 | "%s: reset failed, GRSTCTL=%08x\n", | |
2559 | __func__, grstctl); | |
2560 | return -ETIMEDOUT; | |
2561 | } | |
2562 | ||
5b7d70c6 BD |
2563 | if (!(grstctl & S3C_GRSTCTL_AHBIdle)) |
2564 | continue; | |
2565 | ||
66e5c643 | 2566 | break; /* reset done */ |
5b7d70c6 BD |
2567 | } |
2568 | ||
2569 | dev_dbg(hsotg->dev, "reset successful\n"); | |
2570 | return 0; | |
2571 | } | |
2572 | ||
0f91349b | 2573 | static int s3c_hsotg_start(struct usb_gadget_driver *driver, |
b0fca50f | 2574 | int (*bind)(struct usb_gadget *)) |
5b7d70c6 BD |
2575 | { |
2576 | struct s3c_hsotg *hsotg = our_hsotg; | |
2577 | int ret; | |
2578 | ||
2579 | if (!hsotg) { | |
2580 | printk(KERN_ERR "%s: called with no device\n", __func__); | |
2581 | return -ENODEV; | |
2582 | } | |
2583 | ||
2584 | if (!driver) { | |
2585 | dev_err(hsotg->dev, "%s: no driver\n", __func__); | |
2586 | return -EINVAL; | |
2587 | } | |
2588 | ||
7177aed4 | 2589 | if (driver->max_speed < USB_SPEED_FULL) |
5b7d70c6 | 2590 | dev_err(hsotg->dev, "%s: bad speed\n", __func__); |
5b7d70c6 | 2591 | |
b0fca50f | 2592 | if (!bind || !driver->setup) { |
5b7d70c6 BD |
2593 | dev_err(hsotg->dev, "%s: missing entry points\n", __func__); |
2594 | return -EINVAL; | |
2595 | } | |
2596 | ||
2597 | WARN_ON(hsotg->driver); | |
2598 | ||
2599 | driver->driver.bus = NULL; | |
2600 | hsotg->driver = driver; | |
2601 | hsotg->gadget.dev.driver = &driver->driver; | |
2602 | hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask; | |
2603 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
2604 | ||
2605 | ret = device_add(&hsotg->gadget.dev); | |
2606 | if (ret) { | |
2607 | dev_err(hsotg->dev, "failed to register gadget device\n"); | |
2608 | goto err; | |
2609 | } | |
2610 | ||
b0fca50f | 2611 | ret = bind(&hsotg->gadget); |
5b7d70c6 BD |
2612 | if (ret) { |
2613 | dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name); | |
2614 | ||
2615 | hsotg->gadget.dev.driver = NULL; | |
2616 | hsotg->driver = NULL; | |
2617 | goto err; | |
2618 | } | |
2619 | ||
2620 | /* we must now enable ep0 ready for host detection and then | |
2621 | * set configuration. */ | |
2622 | ||
2623 | s3c_hsotg_corereset(hsotg); | |
2624 | ||
2625 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
2626 | writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | | |
2627 | (0x5 << 10), hsotg->regs + S3C_GUSBCFG); | |
2628 | ||
2629 | /* looks like soft-reset changes state of FIFOs */ | |
2630 | s3c_hsotg_init_fifo(hsotg); | |
2631 | ||
2632 | __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon); | |
2633 | ||
2634 | writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG); | |
2635 | ||
a3395f0d AT |
2636 | /* Clear any pending OTG interrupts */ |
2637 | writel(0xffffffff, hsotg->regs + S3C_GOTGINT); | |
2638 | ||
2639 | /* Clear any pending interrupts */ | |
2640 | writel(0xffffffff, hsotg->regs + S3C_GINTSTS); | |
2641 | ||
5b7d70c6 BD |
2642 | writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt | |
2643 | S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst | | |
2644 | S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt | | |
2645 | S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt | | |
2646 | S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff | | |
2647 | S3C_GINTSTS_ErlySusp, | |
2648 | hsotg->regs + S3C_GINTMSK); | |
2649 | ||
2650 | if (using_dma(hsotg)) | |
2651 | writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn | | |
2652 | S3C_GAHBCFG_HBstLen_Incr4, | |
2653 | hsotg->regs + S3C_GAHBCFG); | |
2654 | else | |
2655 | writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG); | |
2656 | ||
2657 | /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end | |
2658 | * up being flooded with interrupts if the host is polling the | |
2659 | * endpoint to try and read data. */ | |
2660 | ||
2661 | writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk | | |
2662 | S3C_DIEPMSK_INTknEPMisMsk | | |
10aebc77 BD |
2663 | S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk | |
2664 | ((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0), | |
5b7d70c6 BD |
2665 | hsotg->regs + S3C_DIEPMSK); |
2666 | ||
2667 | /* don't need XferCompl, we get that from RXFIFO in slave mode. In | |
2668 | * DMA mode we may need this. */ | |
2669 | writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk | | |
2670 | S3C_DOEPMSK_EPDisbldMsk | | |
b7800218 RK |
2671 | (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk | |
2672 | S3C_DIEPMSK_TimeOUTMsk) : 0), | |
5b7d70c6 BD |
2673 | hsotg->regs + S3C_DOEPMSK); |
2674 | ||
2675 | writel(0, hsotg->regs + S3C_DAINTMSK); | |
2676 | ||
83a01804 MB |
2677 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", |
2678 | readl(hsotg->regs + S3C_DIEPCTL0), | |
2679 | readl(hsotg->regs + S3C_DOEPCTL0)); | |
5b7d70c6 BD |
2680 | |
2681 | /* enable in and out endpoint interrupts */ | |
2682 | s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt); | |
2683 | ||
2684 | /* Enable the RXFIFO when in slave mode, as this is how we collect | |
2685 | * the data. In DMA mode, we get events from the FIFO but also | |
2686 | * things we cannot process, so do not use it. */ | |
2687 | if (!using_dma(hsotg)) | |
2688 | s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl); | |
2689 | ||
2690 | /* Enable interrupts for EP0 in and out */ | |
2691 | s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1); | |
2692 | s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1); | |
2693 | ||
2694 | __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone); | |
2695 | udelay(10); /* see openiboot */ | |
2696 | __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone); | |
2697 | ||
83a01804 | 2698 | dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL)); |
5b7d70c6 BD |
2699 | |
2700 | /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by | |
2701 | writing to the EPCTL register.. */ | |
2702 | ||
2703 | /* set to read 1 8byte packet */ | |
2704 | writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) | | |
2705 | S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0); | |
2706 | ||
2707 | writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | | |
2708 | S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna | | |
2709 | S3C_DxEPCTL_USBActEp, | |
2710 | hsotg->regs + S3C_DOEPCTL0); | |
2711 | ||
2712 | /* enable, but don't activate EP0in */ | |
2713 | writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | | |
2714 | S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0); | |
2715 | ||
2716 | s3c_hsotg_enqueue_setup(hsotg); | |
2717 | ||
83a01804 MB |
2718 | dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", |
2719 | readl(hsotg->regs + S3C_DIEPCTL0), | |
2720 | readl(hsotg->regs + S3C_DOEPCTL0)); | |
5b7d70c6 BD |
2721 | |
2722 | /* clear global NAKs */ | |
2723 | writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK, | |
2724 | hsotg->regs + S3C_DCTL); | |
2725 | ||
2e0e0777 BD |
2726 | /* must be at-least 3ms to allow bus to see disconnect */ |
2727 | msleep(3); | |
2728 | ||
5b7d70c6 BD |
2729 | /* remove the soft-disconnect and let's go */ |
2730 | __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon); | |
2731 | ||
2732 | /* report to the user, and return */ | |
2733 | ||
2734 | dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); | |
2735 | return 0; | |
2736 | ||
2737 | err: | |
2738 | hsotg->driver = NULL; | |
2739 | hsotg->gadget.dev.driver = NULL; | |
2740 | return ret; | |
2741 | } | |
2742 | ||
0f91349b | 2743 | static int s3c_hsotg_stop(struct usb_gadget_driver *driver) |
5b7d70c6 BD |
2744 | { |
2745 | struct s3c_hsotg *hsotg = our_hsotg; | |
2746 | int ep; | |
2747 | ||
2748 | if (!hsotg) | |
2749 | return -ENODEV; | |
2750 | ||
2751 | if (!driver || driver != hsotg->driver || !driver->unbind) | |
2752 | return -EINVAL; | |
2753 | ||
2754 | /* all endpoints should be shutdown */ | |
2755 | for (ep = 0; ep < S3C_HSOTG_EPS; ep++) | |
2756 | s3c_hsotg_ep_disable(&hsotg->eps[ep].ep); | |
2757 | ||
2758 | call_gadget(hsotg, disconnect); | |
2759 | ||
2760 | driver->unbind(&hsotg->gadget); | |
2761 | hsotg->driver = NULL; | |
2762 | hsotg->gadget.speed = USB_SPEED_UNKNOWN; | |
2763 | ||
2764 | device_del(&hsotg->gadget.dev); | |
2765 | ||
2766 | dev_info(hsotg->dev, "unregistered gadget driver '%s'\n", | |
2767 | driver->driver.name); | |
2768 | ||
2769 | return 0; | |
2770 | } | |
5b7d70c6 BD |
2771 | |
2772 | static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget) | |
2773 | { | |
2774 | return s3c_hsotg_read_frameno(to_hsotg(gadget)); | |
2775 | } | |
2776 | ||
2777 | static struct usb_gadget_ops s3c_hsotg_gadget_ops = { | |
2778 | .get_frame = s3c_hsotg_gadget_getframe, | |
0f91349b SAS |
2779 | .start = s3c_hsotg_start, |
2780 | .stop = s3c_hsotg_stop, | |
5b7d70c6 BD |
2781 | }; |
2782 | ||
2783 | /** | |
2784 | * s3c_hsotg_initep - initialise a single endpoint | |
2785 | * @hsotg: The device state. | |
2786 | * @hs_ep: The endpoint to be initialised. | |
2787 | * @epnum: The endpoint number | |
2788 | * | |
2789 | * Initialise the given endpoint (as part of the probe and device state | |
2790 | * creation) to give to the gadget driver. Setup the endpoint name, any | |
2791 | * direction information and other state that may be required. | |
2792 | */ | |
2793 | static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg, | |
2794 | struct s3c_hsotg_ep *hs_ep, | |
2795 | int epnum) | |
2796 | { | |
2797 | u32 ptxfifo; | |
2798 | char *dir; | |
2799 | ||
2800 | if (epnum == 0) | |
2801 | dir = ""; | |
2802 | else if ((epnum % 2) == 0) { | |
2803 | dir = "out"; | |
2804 | } else { | |
2805 | dir = "in"; | |
2806 | hs_ep->dir_in = 1; | |
2807 | } | |
2808 | ||
2809 | hs_ep->index = epnum; | |
2810 | ||
2811 | snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir); | |
2812 | ||
2813 | INIT_LIST_HEAD(&hs_ep->queue); | |
2814 | INIT_LIST_HEAD(&hs_ep->ep.ep_list); | |
2815 | ||
2816 | spin_lock_init(&hs_ep->lock); | |
2817 | ||
2818 | /* add to the list of endpoints known by the gadget driver */ | |
2819 | if (epnum) | |
2820 | list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list); | |
2821 | ||
2822 | hs_ep->parent = hsotg; | |
2823 | hs_ep->ep.name = hs_ep->name; | |
2824 | hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT; | |
2825 | hs_ep->ep.ops = &s3c_hsotg_ep_ops; | |
2826 | ||
2827 | /* Read the FIFO size for the Periodic TX FIFO, even if we're | |
2828 | * an OUT endpoint, we may as well do this if in future the | |
2829 | * code is changed to make each endpoint's direction changeable. | |
2830 | */ | |
2831 | ||
2832 | ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum)); | |
679f9b7c | 2833 | hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4; |
5b7d70c6 BD |
2834 | |
2835 | /* if we're using dma, we need to set the next-endpoint pointer | |
2836 | * to be something valid. | |
2837 | */ | |
2838 | ||
2839 | if (using_dma(hsotg)) { | |
2840 | u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15); | |
2841 | writel(next, hsotg->regs + S3C_DIEPCTL(epnum)); | |
2842 | writel(next, hsotg->regs + S3C_DOEPCTL(epnum)); | |
2843 | } | |
2844 | } | |
2845 | ||
2846 | /** | |
2847 | * s3c_hsotg_otgreset - reset the OtG phy block | |
2848 | * @hsotg: The host state. | |
2849 | * | |
2850 | * Power up the phy, set the basic configuration and start the PHY. | |
2851 | */ | |
2852 | static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg) | |
2853 | { | |
e50bf385 | 2854 | struct clk *xusbxti; |
1eb838d3 | 2855 | u32 pwr, osc; |
5b7d70c6 | 2856 | |
1eb838d3 MS |
2857 | pwr = readl(S3C_PHYPWR); |
2858 | pwr &= ~0x19; | |
2859 | writel(pwr, S3C_PHYPWR); | |
5b7d70c6 BD |
2860 | mdelay(1); |
2861 | ||
2862 | osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0; | |
2863 | ||
e50bf385 MC |
2864 | xusbxti = clk_get(hsotg->dev, "xusbxti"); |
2865 | if (xusbxti && !IS_ERR(xusbxti)) { | |
2866 | switch (clk_get_rate(xusbxti)) { | |
2867 | case 12*MHZ: | |
2868 | osc |= S3C_PHYCLK_CLKSEL_12M; | |
2869 | break; | |
2870 | case 24*MHZ: | |
2871 | osc |= S3C_PHYCLK_CLKSEL_24M; | |
2872 | break; | |
2873 | default: | |
2874 | case 48*MHZ: | |
2875 | /* default reference clock */ | |
2876 | break; | |
2877 | } | |
2878 | clk_put(xusbxti); | |
2879 | } | |
2880 | ||
5b7d70c6 BD |
2881 | writel(osc | 0x10, S3C_PHYCLK); |
2882 | ||
2883 | /* issue a full set of resets to the otg and core */ | |
2884 | ||
2885 | writel(S3C_RSTCON_PHY, S3C_RSTCON); | |
2886 | udelay(20); /* at-least 10uS */ | |
2887 | writel(0, S3C_RSTCON); | |
2888 | } | |
2889 | ||
2890 | ||
2891 | static void s3c_hsotg_init(struct s3c_hsotg *hsotg) | |
2892 | { | |
10aebc77 BD |
2893 | u32 cfg4; |
2894 | ||
5b7d70c6 BD |
2895 | /* unmask subset of endpoint interrupts */ |
2896 | ||
2897 | writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk | | |
2898 | S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk, | |
2899 | hsotg->regs + S3C_DIEPMSK); | |
2900 | ||
2901 | writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk | | |
2902 | S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk, | |
2903 | hsotg->regs + S3C_DOEPMSK); | |
2904 | ||
2905 | writel(0, hsotg->regs + S3C_DAINTMSK); | |
2906 | ||
390b1661 TA |
2907 | /* Be in disconnected state until gadget is registered */ |
2908 | __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon); | |
2909 | ||
5b7d70c6 BD |
2910 | if (0) { |
2911 | /* post global nak until we're ready */ | |
2912 | writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak, | |
2913 | hsotg->regs + S3C_DCTL); | |
2914 | } | |
2915 | ||
2916 | /* setup fifos */ | |
2917 | ||
83a01804 MB |
2918 | dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", |
2919 | readl(hsotg->regs + S3C_GRXFSIZ), | |
2920 | readl(hsotg->regs + S3C_GNPTXFSIZ)); | |
5b7d70c6 BD |
2921 | |
2922 | s3c_hsotg_init_fifo(hsotg); | |
2923 | ||
2924 | /* set the PLL on, remove the HNP/SRP and set the PHY */ | |
2925 | writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10), | |
2926 | hsotg->regs + S3C_GUSBCFG); | |
2927 | ||
2928 | writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0, | |
2929 | hsotg->regs + S3C_GAHBCFG); | |
10aebc77 BD |
2930 | |
2931 | /* check hardware configuration */ | |
2932 | ||
2933 | cfg4 = readl(hsotg->regs + 0x50); | |
2934 | hsotg->dedicated_fifos = (cfg4 >> 25) & 1; | |
2935 | ||
2936 | dev_info(hsotg->dev, "%s fifos\n", | |
2937 | hsotg->dedicated_fifos ? "dedicated" : "shared"); | |
5b7d70c6 BD |
2938 | } |
2939 | ||
2940 | static void s3c_hsotg_dump(struct s3c_hsotg *hsotg) | |
2941 | { | |
83a01804 | 2942 | #ifdef DEBUG |
5b7d70c6 BD |
2943 | struct device *dev = hsotg->dev; |
2944 | void __iomem *regs = hsotg->regs; | |
2945 | u32 val; | |
2946 | int idx; | |
2947 | ||
2948 | dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", | |
2949 | readl(regs + S3C_DCFG), readl(regs + S3C_DCTL), | |
2950 | readl(regs + S3C_DIEPMSK)); | |
2951 | ||
2952 | dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n", | |
2953 | readl(regs + S3C_GAHBCFG), readl(regs + 0x44)); | |
2954 | ||
2955 | dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", | |
2956 | readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ)); | |
2957 | ||
2958 | /* show periodic fifo settings */ | |
2959 | ||
2960 | for (idx = 1; idx <= 15; idx++) { | |
2961 | val = readl(regs + S3C_DPTXFSIZn(idx)); | |
2962 | dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, | |
2963 | val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT, | |
2964 | val & S3C_DPTXFSIZn_DPTxFStAddr_MASK); | |
2965 | } | |
2966 | ||
2967 | for (idx = 0; idx < 15; idx++) { | |
2968 | dev_info(dev, | |
2969 | "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, | |
2970 | readl(regs + S3C_DIEPCTL(idx)), | |
2971 | readl(regs + S3C_DIEPTSIZ(idx)), | |
2972 | readl(regs + S3C_DIEPDMA(idx))); | |
2973 | ||
2974 | val = readl(regs + S3C_DOEPCTL(idx)); | |
2975 | dev_info(dev, | |
2976 | "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", | |
2977 | idx, readl(regs + S3C_DOEPCTL(idx)), | |
2978 | readl(regs + S3C_DOEPTSIZ(idx)), | |
2979 | readl(regs + S3C_DOEPDMA(idx))); | |
2980 | ||
2981 | } | |
2982 | ||
2983 | dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", | |
2984 | readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE)); | |
83a01804 | 2985 | #endif |
5b7d70c6 BD |
2986 | } |
2987 | ||
2988 | ||
2989 | /** | |
2990 | * state_show - debugfs: show overall driver and device state. | |
2991 | * @seq: The seq file to write to. | |
2992 | * @v: Unused parameter. | |
2993 | * | |
2994 | * This debugfs entry shows the overall state of the hardware and | |
2995 | * some general information about each of the endpoints available | |
2996 | * to the system. | |
2997 | */ | |
2998 | static int state_show(struct seq_file *seq, void *v) | |
2999 | { | |
3000 | struct s3c_hsotg *hsotg = seq->private; | |
3001 | void __iomem *regs = hsotg->regs; | |
3002 | int idx; | |
3003 | ||
3004 | seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", | |
3005 | readl(regs + S3C_DCFG), | |
3006 | readl(regs + S3C_DCTL), | |
3007 | readl(regs + S3C_DSTS)); | |
3008 | ||
3009 | seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", | |
3010 | readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK)); | |
3011 | ||
3012 | seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", | |
3013 | readl(regs + S3C_GINTMSK), | |
3014 | readl(regs + S3C_GINTSTS)); | |
3015 | ||
3016 | seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", | |
3017 | readl(regs + S3C_DAINTMSK), | |
3018 | readl(regs + S3C_DAINT)); | |
3019 | ||
3020 | seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", | |
3021 | readl(regs + S3C_GNPTXSTS), | |
3022 | readl(regs + S3C_GRXSTSR)); | |
3023 | ||
3024 | seq_printf(seq, "\nEndpoint status:\n"); | |
3025 | ||
3026 | for (idx = 0; idx < 15; idx++) { | |
3027 | u32 in, out; | |
3028 | ||
3029 | in = readl(regs + S3C_DIEPCTL(idx)); | |
3030 | out = readl(regs + S3C_DOEPCTL(idx)); | |
3031 | ||
3032 | seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", | |
3033 | idx, in, out); | |
3034 | ||
3035 | in = readl(regs + S3C_DIEPTSIZ(idx)); | |
3036 | out = readl(regs + S3C_DOEPTSIZ(idx)); | |
3037 | ||
3038 | seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", | |
3039 | in, out); | |
3040 | ||
3041 | seq_printf(seq, "\n"); | |
3042 | } | |
3043 | ||
3044 | return 0; | |
3045 | } | |
3046 | ||
3047 | static int state_open(struct inode *inode, struct file *file) | |
3048 | { | |
3049 | return single_open(file, state_show, inode->i_private); | |
3050 | } | |
3051 | ||
3052 | static const struct file_operations state_fops = { | |
3053 | .owner = THIS_MODULE, | |
3054 | .open = state_open, | |
3055 | .read = seq_read, | |
3056 | .llseek = seq_lseek, | |
3057 | .release = single_release, | |
3058 | }; | |
3059 | ||
3060 | /** | |
3061 | * fifo_show - debugfs: show the fifo information | |
3062 | * @seq: The seq_file to write data to. | |
3063 | * @v: Unused parameter. | |
3064 | * | |
3065 | * Show the FIFO information for the overall fifo and all the | |
3066 | * periodic transmission FIFOs. | |
3067 | */ | |
3068 | static int fifo_show(struct seq_file *seq, void *v) | |
3069 | { | |
3070 | struct s3c_hsotg *hsotg = seq->private; | |
3071 | void __iomem *regs = hsotg->regs; | |
3072 | u32 val; | |
3073 | int idx; | |
3074 | ||
3075 | seq_printf(seq, "Non-periodic FIFOs:\n"); | |
3076 | seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ)); | |
3077 | ||
3078 | val = readl(regs + S3C_GNPTXFSIZ); | |
3079 | seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", | |
3080 | val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT, | |
3081 | val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK); | |
3082 | ||
3083 | seq_printf(seq, "\nPeriodic TXFIFOs:\n"); | |
3084 | ||
3085 | for (idx = 1; idx <= 15; idx++) { | |
3086 | val = readl(regs + S3C_DPTXFSIZn(idx)); | |
3087 | ||
3088 | seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, | |
3089 | val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT, | |
3090 | val & S3C_DPTXFSIZn_DPTxFStAddr_MASK); | |
3091 | } | |
3092 | ||
3093 | return 0; | |
3094 | } | |
3095 | ||
3096 | static int fifo_open(struct inode *inode, struct file *file) | |
3097 | { | |
3098 | return single_open(file, fifo_show, inode->i_private); | |
3099 | } | |
3100 | ||
3101 | static const struct file_operations fifo_fops = { | |
3102 | .owner = THIS_MODULE, | |
3103 | .open = fifo_open, | |
3104 | .read = seq_read, | |
3105 | .llseek = seq_lseek, | |
3106 | .release = single_release, | |
3107 | }; | |
3108 | ||
3109 | ||
3110 | static const char *decode_direction(int is_in) | |
3111 | { | |
3112 | return is_in ? "in" : "out"; | |
3113 | } | |
3114 | ||
3115 | /** | |
3116 | * ep_show - debugfs: show the state of an endpoint. | |
3117 | * @seq: The seq_file to write data to. | |
3118 | * @v: Unused parameter. | |
3119 | * | |
3120 | * This debugfs entry shows the state of the given endpoint (one is | |
3121 | * registered for each available). | |
3122 | */ | |
3123 | static int ep_show(struct seq_file *seq, void *v) | |
3124 | { | |
3125 | struct s3c_hsotg_ep *ep = seq->private; | |
3126 | struct s3c_hsotg *hsotg = ep->parent; | |
3127 | struct s3c_hsotg_req *req; | |
3128 | void __iomem *regs = hsotg->regs; | |
3129 | int index = ep->index; | |
3130 | int show_limit = 15; | |
3131 | unsigned long flags; | |
3132 | ||
3133 | seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n", | |
3134 | ep->index, ep->ep.name, decode_direction(ep->dir_in)); | |
3135 | ||
3136 | /* first show the register state */ | |
3137 | ||
3138 | seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", | |
3139 | readl(regs + S3C_DIEPCTL(index)), | |
3140 | readl(regs + S3C_DOEPCTL(index))); | |
3141 | ||
3142 | seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", | |
3143 | readl(regs + S3C_DIEPDMA(index)), | |
3144 | readl(regs + S3C_DOEPDMA(index))); | |
3145 | ||
3146 | seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", | |
3147 | readl(regs + S3C_DIEPINT(index)), | |
3148 | readl(regs + S3C_DOEPINT(index))); | |
3149 | ||
3150 | seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", | |
3151 | readl(regs + S3C_DIEPTSIZ(index)), | |
3152 | readl(regs + S3C_DOEPTSIZ(index))); | |
3153 | ||
3154 | seq_printf(seq, "\n"); | |
3155 | seq_printf(seq, "mps %d\n", ep->ep.maxpacket); | |
3156 | seq_printf(seq, "total_data=%ld\n", ep->total_data); | |
3157 | ||
3158 | seq_printf(seq, "request list (%p,%p):\n", | |
3159 | ep->queue.next, ep->queue.prev); | |
3160 | ||
3161 | spin_lock_irqsave(&ep->lock, flags); | |
3162 | ||
3163 | list_for_each_entry(req, &ep->queue, queue) { | |
3164 | if (--show_limit < 0) { | |
3165 | seq_printf(seq, "not showing more requests...\n"); | |
3166 | break; | |
3167 | } | |
3168 | ||
3169 | seq_printf(seq, "%c req %p: %d bytes @%p, ", | |
3170 | req == ep->req ? '*' : ' ', | |
3171 | req, req->req.length, req->req.buf); | |
3172 | seq_printf(seq, "%d done, res %d\n", | |
3173 | req->req.actual, req->req.status); | |
3174 | } | |
3175 | ||
3176 | spin_unlock_irqrestore(&ep->lock, flags); | |
3177 | ||
3178 | return 0; | |
3179 | } | |
3180 | ||
3181 | static int ep_open(struct inode *inode, struct file *file) | |
3182 | { | |
3183 | return single_open(file, ep_show, inode->i_private); | |
3184 | } | |
3185 | ||
3186 | static const struct file_operations ep_fops = { | |
3187 | .owner = THIS_MODULE, | |
3188 | .open = ep_open, | |
3189 | .read = seq_read, | |
3190 | .llseek = seq_lseek, | |
3191 | .release = single_release, | |
3192 | }; | |
3193 | ||
3194 | /** | |
3195 | * s3c_hsotg_create_debug - create debugfs directory and files | |
3196 | * @hsotg: The driver state | |
3197 | * | |
3198 | * Create the debugfs files to allow the user to get information | |
3199 | * about the state of the system. The directory name is created | |
3200 | * with the same name as the device itself, in case we end up | |
3201 | * with multiple blocks in future systems. | |
3202 | */ | |
3203 | static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg) | |
3204 | { | |
3205 | struct dentry *root; | |
3206 | unsigned epidx; | |
3207 | ||
3208 | root = debugfs_create_dir(dev_name(hsotg->dev), NULL); | |
3209 | hsotg->debug_root = root; | |
3210 | if (IS_ERR(root)) { | |
3211 | dev_err(hsotg->dev, "cannot create debug root\n"); | |
3212 | return; | |
3213 | } | |
3214 | ||
3215 | /* create general state file */ | |
3216 | ||
3217 | hsotg->debug_file = debugfs_create_file("state", 0444, root, | |
3218 | hsotg, &state_fops); | |
3219 | ||
3220 | if (IS_ERR(hsotg->debug_file)) | |
3221 | dev_err(hsotg->dev, "%s: failed to create state\n", __func__); | |
3222 | ||
3223 | hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root, | |
3224 | hsotg, &fifo_fops); | |
3225 | ||
3226 | if (IS_ERR(hsotg->debug_fifo)) | |
3227 | dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__); | |
3228 | ||
3229 | /* create one file for each endpoint */ | |
3230 | ||
3231 | for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) { | |
3232 | struct s3c_hsotg_ep *ep = &hsotg->eps[epidx]; | |
3233 | ||
3234 | ep->debugfs = debugfs_create_file(ep->name, 0444, | |
3235 | root, ep, &ep_fops); | |
3236 | ||
3237 | if (IS_ERR(ep->debugfs)) | |
3238 | dev_err(hsotg->dev, "failed to create %s debug file\n", | |
3239 | ep->name); | |
3240 | } | |
3241 | } | |
3242 | ||
3243 | /** | |
3244 | * s3c_hsotg_delete_debug - cleanup debugfs entries | |
3245 | * @hsotg: The driver state | |
3246 | * | |
3247 | * Cleanup (remove) the debugfs files for use on module exit. | |
3248 | */ | |
3249 | static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg) | |
3250 | { | |
3251 | unsigned epidx; | |
3252 | ||
3253 | for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) { | |
3254 | struct s3c_hsotg_ep *ep = &hsotg->eps[epidx]; | |
3255 | debugfs_remove(ep->debugfs); | |
3256 | } | |
3257 | ||
3258 | debugfs_remove(hsotg->debug_file); | |
3259 | debugfs_remove(hsotg->debug_fifo); | |
3260 | debugfs_remove(hsotg->debug_root); | |
3261 | } | |
3262 | ||
3263 | /** | |
3264 | * s3c_hsotg_gate - set the hardware gate for the block | |
3265 | * @pdev: The device we bound to | |
3266 | * @on: On or off. | |
3267 | * | |
3268 | * Set the hardware gate setting into the block. If we end up on | |
3269 | * something other than an S3C64XX, then we might need to change this | |
3270 | * to using a platform data callback, or some other mechanism. | |
3271 | */ | |
3272 | static void s3c_hsotg_gate(struct platform_device *pdev, bool on) | |
3273 | { | |
3274 | unsigned long flags; | |
3275 | u32 others; | |
3276 | ||
3277 | local_irq_save(flags); | |
3278 | ||
3279 | others = __raw_readl(S3C64XX_OTHERS); | |
3280 | if (on) | |
3281 | others |= S3C64XX_OTHERS_USBMASK; | |
3282 | else | |
3283 | others &= ~S3C64XX_OTHERS_USBMASK; | |
3284 | __raw_writel(others, S3C64XX_OTHERS); | |
3285 | ||
3286 | local_irq_restore(flags); | |
3287 | } | |
3288 | ||
0978f8c5 | 3289 | static struct s3c_hsotg_plat s3c_hsotg_default_pdata; |
5b7d70c6 BD |
3290 | |
3291 | static int __devinit s3c_hsotg_probe(struct platform_device *pdev) | |
3292 | { | |
3293 | struct s3c_hsotg_plat *plat = pdev->dev.platform_data; | |
3294 | struct device *dev = &pdev->dev; | |
3295 | struct s3c_hsotg *hsotg; | |
3296 | struct resource *res; | |
3297 | int epnum; | |
3298 | int ret; | |
3299 | ||
3300 | if (!plat) | |
3301 | plat = &s3c_hsotg_default_pdata; | |
3302 | ||
3303 | hsotg = kzalloc(sizeof(struct s3c_hsotg) + | |
3304 | sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS, | |
3305 | GFP_KERNEL); | |
3306 | if (!hsotg) { | |
3307 | dev_err(dev, "cannot get memory\n"); | |
3308 | return -ENOMEM; | |
3309 | } | |
3310 | ||
3311 | hsotg->dev = dev; | |
3312 | hsotg->plat = plat; | |
3313 | ||
31ee04de MS |
3314 | hsotg->clk = clk_get(&pdev->dev, "otg"); |
3315 | if (IS_ERR(hsotg->clk)) { | |
3316 | dev_err(dev, "cannot get otg clock\n"); | |
2328ceae | 3317 | ret = PTR_ERR(hsotg->clk); |
31ee04de MS |
3318 | goto err_mem; |
3319 | } | |
3320 | ||
5b7d70c6 BD |
3321 | platform_set_drvdata(pdev, hsotg); |
3322 | ||
3323 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
3324 | if (!res) { | |
3325 | dev_err(dev, "cannot find register resource 0\n"); | |
3326 | ret = -EINVAL; | |
31ee04de | 3327 | goto err_clk; |
5b7d70c6 BD |
3328 | } |
3329 | ||
3330 | hsotg->regs_res = request_mem_region(res->start, resource_size(res), | |
3331 | dev_name(dev)); | |
3332 | if (!hsotg->regs_res) { | |
3333 | dev_err(dev, "cannot reserve registers\n"); | |
3334 | ret = -ENOENT; | |
31ee04de | 3335 | goto err_clk; |
5b7d70c6 BD |
3336 | } |
3337 | ||
3338 | hsotg->regs = ioremap(res->start, resource_size(res)); | |
3339 | if (!hsotg->regs) { | |
3340 | dev_err(dev, "cannot map registers\n"); | |
3341 | ret = -ENXIO; | |
3342 | goto err_regs_res; | |
3343 | } | |
3344 | ||
3345 | ret = platform_get_irq(pdev, 0); | |
3346 | if (ret < 0) { | |
3347 | dev_err(dev, "cannot find IRQ\n"); | |
3348 | goto err_regs; | |
3349 | } | |
3350 | ||
3351 | hsotg->irq = ret; | |
3352 | ||
3353 | ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg); | |
3354 | if (ret < 0) { | |
3355 | dev_err(dev, "cannot claim IRQ\n"); | |
3356 | goto err_regs; | |
3357 | } | |
3358 | ||
3359 | dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq); | |
3360 | ||
3361 | device_initialize(&hsotg->gadget.dev); | |
3362 | ||
3363 | dev_set_name(&hsotg->gadget.dev, "gadget"); | |
3364 | ||
d327ab5b | 3365 | hsotg->gadget.max_speed = USB_SPEED_HIGH; |
5b7d70c6 BD |
3366 | hsotg->gadget.ops = &s3c_hsotg_gadget_ops; |
3367 | hsotg->gadget.name = dev_name(dev); | |
3368 | ||
3369 | hsotg->gadget.dev.parent = dev; | |
3370 | hsotg->gadget.dev.dma_mask = dev->dma_mask; | |
3371 | ||
3372 | /* setup endpoint information */ | |
3373 | ||
3374 | INIT_LIST_HEAD(&hsotg->gadget.ep_list); | |
3375 | hsotg->gadget.ep0 = &hsotg->eps[0].ep; | |
3376 | ||
3377 | /* allocate EP0 request */ | |
3378 | ||
3379 | hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep, | |
3380 | GFP_KERNEL); | |
3381 | if (!hsotg->ctrl_req) { | |
3382 | dev_err(dev, "failed to allocate ctrl req\n"); | |
3383 | goto err_regs; | |
3384 | } | |
3385 | ||
3386 | /* reset the system */ | |
3387 | ||
31ee04de MS |
3388 | clk_enable(hsotg->clk); |
3389 | ||
5b7d70c6 BD |
3390 | s3c_hsotg_gate(pdev, true); |
3391 | ||
3392 | s3c_hsotg_otgreset(hsotg); | |
3393 | s3c_hsotg_corereset(hsotg); | |
3394 | s3c_hsotg_init(hsotg); | |
3395 | ||
3396 | /* initialise the endpoints now the core has been initialised */ | |
3397 | for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++) | |
3398 | s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum); | |
3399 | ||
0f91349b SAS |
3400 | ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget); |
3401 | if (ret) | |
3402 | goto err_add_udc; | |
3403 | ||
5b7d70c6 BD |
3404 | s3c_hsotg_create_debug(hsotg); |
3405 | ||
3406 | s3c_hsotg_dump(hsotg); | |
3407 | ||
3408 | our_hsotg = hsotg; | |
3409 | return 0; | |
3410 | ||
0f91349b SAS |
3411 | err_add_udc: |
3412 | s3c_hsotg_gate(pdev, false); | |
3413 | clk_disable(hsotg->clk); | |
3414 | clk_put(hsotg->clk); | |
3415 | ||
5b7d70c6 BD |
3416 | err_regs: |
3417 | iounmap(hsotg->regs); | |
3418 | ||
3419 | err_regs_res: | |
3420 | release_resource(hsotg->regs_res); | |
3421 | kfree(hsotg->regs_res); | |
31ee04de MS |
3422 | err_clk: |
3423 | clk_put(hsotg->clk); | |
5b7d70c6 BD |
3424 | err_mem: |
3425 | kfree(hsotg); | |
3426 | return ret; | |
3427 | } | |
3428 | ||
3429 | static int __devexit s3c_hsotg_remove(struct platform_device *pdev) | |
3430 | { | |
3431 | struct s3c_hsotg *hsotg = platform_get_drvdata(pdev); | |
3432 | ||
0f91349b SAS |
3433 | usb_del_gadget_udc(&hsotg->gadget); |
3434 | ||
5b7d70c6 BD |
3435 | s3c_hsotg_delete_debug(hsotg); |
3436 | ||
3437 | usb_gadget_unregister_driver(hsotg->driver); | |
3438 | ||
3439 | free_irq(hsotg->irq, hsotg); | |
3440 | iounmap(hsotg->regs); | |
3441 | ||
3442 | release_resource(hsotg->regs_res); | |
3443 | kfree(hsotg->regs_res); | |
3444 | ||
3445 | s3c_hsotg_gate(pdev, false); | |
3446 | ||
31ee04de MS |
3447 | clk_disable(hsotg->clk); |
3448 | clk_put(hsotg->clk); | |
3449 | ||
5b7d70c6 BD |
3450 | kfree(hsotg); |
3451 | return 0; | |
3452 | } | |
3453 | ||
3454 | #if 1 | |
3455 | #define s3c_hsotg_suspend NULL | |
3456 | #define s3c_hsotg_resume NULL | |
3457 | #endif | |
3458 | ||
3459 | static struct platform_driver s3c_hsotg_driver = { | |
3460 | .driver = { | |
3461 | .name = "s3c-hsotg", | |
3462 | .owner = THIS_MODULE, | |
3463 | }, | |
3464 | .probe = s3c_hsotg_probe, | |
3465 | .remove = __devexit_p(s3c_hsotg_remove), | |
3466 | .suspend = s3c_hsotg_suspend, | |
3467 | .resume = s3c_hsotg_resume, | |
3468 | }; | |
3469 | ||
cc27c96c | 3470 | module_platform_driver(s3c_hsotg_driver); |
5b7d70c6 BD |
3471 | |
3472 | MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device"); | |
3473 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
3474 | MODULE_LICENSE("GPL"); | |
3475 | MODULE_ALIAS("platform:s3c-hsotg"); |