Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
91987693 | 2 | * Intel PXA25x and IXP4xx on-chip full speed USB device controllers |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker) | |
5 | * Copyright (C) 2003 Robert Schwebel, Pengutronix | |
6 | * Copyright (C) 2003 Benedikt Spranger, Pengutronix | |
7 | * Copyright (C) 2003 David Brownell | |
8 | * Copyright (C) 2003 Joshua Wise | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
25 | ||
040fa1b9 | 26 | /* #define VERBOSE_DEBUG */ |
1da177e4 | 27 | |
9068a4c6 | 28 | #include <linux/device.h> |
1da177e4 LT |
29 | #include <linux/module.h> |
30 | #include <linux/kernel.h> | |
31 | #include <linux/ioport.h> | |
32 | #include <linux/types.h> | |
1da177e4 LT |
33 | #include <linux/errno.h> |
34 | #include <linux/delay.h> | |
1da177e4 LT |
35 | #include <linux/slab.h> |
36 | #include <linux/init.h> | |
37 | #include <linux/timer.h> | |
38 | #include <linux/list.h> | |
39 | #include <linux/interrupt.h> | |
1da177e4 | 40 | #include <linux/mm.h> |
d052d1be | 41 | #include <linux/platform_device.h> |
1da177e4 | 42 | #include <linux/dma-mapping.h> |
c7a3bd17 | 43 | #include <linux/irq.h> |
6549e6c9 RK |
44 | #include <linux/clk.h> |
45 | #include <linux/err.h> | |
040fa1b9 DES |
46 | #include <linux/seq_file.h> |
47 | #include <linux/debugfs.h> | |
284d115e | 48 | #include <linux/io.h> |
1da177e4 LT |
49 | |
50 | #include <asm/byteorder.h> | |
51 | #include <asm/dma.h> | |
9068a4c6 | 52 | #include <asm/gpio.h> |
1da177e4 LT |
53 | #include <asm/system.h> |
54 | #include <asm/mach-types.h> | |
55 | #include <asm/unaligned.h> | |
1da177e4 | 56 | |
5f848137 | 57 | #include <linux/usb/ch9.h> |
9454a57a | 58 | #include <linux/usb/gadget.h> |
ab26d20f | 59 | #include <linux/usb/otg.h> |
1da177e4 | 60 | |
284d115e RK |
61 | /* |
62 | * This driver is PXA25x only. Grab the right register definitions. | |
63 | */ | |
64 | #ifdef CONFIG_ARCH_PXA | |
a09e64fb | 65 | #include <mach/pxa25x-udc.h> |
284d115e RK |
66 | #endif |
67 | ||
0dc726bb EM |
68 | #ifdef CONFIG_ARCH_LUBBOCK |
69 | #include <mach/lubbock.h> | |
70 | #endif | |
71 | ||
9068a4c6 | 72 | #include <asm/mach/udc_pxa2xx.h> |
1da177e4 LT |
73 | |
74 | ||
75 | /* | |
91987693 | 76 | * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x |
1da177e4 LT |
77 | * series processors. The UDC for the IXP 4xx series is very similar. |
78 | * There are fifteen endpoints, in addition to ep0. | |
79 | * | |
80 | * Such controller drivers work with a gadget driver. The gadget driver | |
81 | * returns descriptors, implements configuration and data protocols used | |
82 | * by the host to interact with this device, and allocates endpoints to | |
83 | * the different protocol interfaces. The controller driver virtualizes | |
84 | * usb hardware so that the gadget drivers will be more portable. | |
34ebcd28 | 85 | * |
1da177e4 LT |
86 | * This UDC hardware wants to implement a bit too much USB protocol, so |
87 | * it constrains the sorts of USB configuration change events that work. | |
88 | * The errata for these chips are misleading; some "fixed" bugs from | |
89 | * pxa250 a0/a1 b0/b1/b2 sure act like they're still there. | |
ad8c623f DB |
90 | * |
91 | * Note that the UDC hardware supports DMA (except on IXP) but that's | |
92 | * not used here. IN-DMA (to host) is simple enough, when the data is | |
93 | * suitably aligned (16 bytes) ... the network stack doesn't do that, | |
94 | * other software can. OUT-DMA is buggy in most chip versions, as well | |
95 | * as poorly designed (data toggle not automatic). So this driver won't | |
96 | * bother using DMA. (Mostly-working IN-DMA support was available in | |
97 | * kernels before 2.6.23, but was never enabled or well tested.) | |
1da177e4 LT |
98 | */ |
99 | ||
ad8c623f | 100 | #define DRIVER_VERSION "30-June-2007" |
91987693 | 101 | #define DRIVER_DESC "PXA 25x USB Device Controller driver" |
1da177e4 LT |
102 | |
103 | ||
7a857620 | 104 | static const char driver_name [] = "pxa25x_udc"; |
1da177e4 LT |
105 | |
106 | static const char ep0name [] = "ep0"; | |
107 | ||
108 | ||
1da177e4 | 109 | #ifdef CONFIG_ARCH_IXP4XX |
1da177e4 LT |
110 | |
111 | /* cpu-specific register addresses are compiled in to this code */ | |
112 | #ifdef CONFIG_ARCH_PXA | |
113 | #error "Can't configure both IXP and PXA" | |
114 | #endif | |
115 | ||
64cc2dd9 DES |
116 | /* IXP doesn't yet support <linux/clk.h> */ |
117 | #define clk_get(dev,name) NULL | |
118 | #define clk_enable(clk) do { } while (0) | |
119 | #define clk_disable(clk) do { } while (0) | |
120 | #define clk_put(clk) do { } while (0) | |
121 | ||
1da177e4 LT |
122 | #endif |
123 | ||
7a857620 | 124 | #include "pxa25x_udc.h" |
1da177e4 LT |
125 | |
126 | ||
7a857620 | 127 | #ifdef CONFIG_USB_PXA25X_SMALL |
1da177e4 LT |
128 | #define SIZE_STR " (small)" |
129 | #else | |
130 | #define SIZE_STR "" | |
131 | #endif | |
132 | ||
1da177e4 | 133 | /* --------------------------------------------------------------------------- |
34ebcd28 | 134 | * endpoint related parts of the api to the usb controller hardware, |
1da177e4 LT |
135 | * used by gadget driver; and the inner talker-to-hardware core. |
136 | * --------------------------------------------------------------------------- | |
137 | */ | |
138 | ||
7a857620 PZ |
139 | static void pxa25x_ep_fifo_flush (struct usb_ep *ep); |
140 | static void nuke (struct pxa25x_ep *, int status); | |
1da177e4 | 141 | |
b2bbb20b DB |
142 | /* one GPIO should control a D+ pullup, so host sees this device (or not) */ |
143 | static void pullup_off(void) | |
144 | { | |
145 | struct pxa2xx_udc_mach_info *mach = the_controller->mach; | |
8fb105f5 | 146 | int off_level = mach->gpio_pullup_inverted; |
b2bbb20b | 147 | |
56a075dc | 148 | if (gpio_is_valid(mach->gpio_pullup)) |
8fb105f5 | 149 | gpio_set_value(mach->gpio_pullup, off_level); |
b2bbb20b DB |
150 | else if (mach->udc_command) |
151 | mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT); | |
152 | } | |
153 | ||
154 | static void pullup_on(void) | |
155 | { | |
156 | struct pxa2xx_udc_mach_info *mach = the_controller->mach; | |
8fb105f5 | 157 | int on_level = !mach->gpio_pullup_inverted; |
b2bbb20b | 158 | |
56a075dc | 159 | if (gpio_is_valid(mach->gpio_pullup)) |
8fb105f5 | 160 | gpio_set_value(mach->gpio_pullup, on_level); |
b2bbb20b DB |
161 | else if (mach->udc_command) |
162 | mach->udc_command(PXA2XX_UDC_CMD_CONNECT); | |
163 | } | |
164 | ||
1da177e4 LT |
165 | static void pio_irq_enable(int bEndpointAddress) |
166 | { | |
167 | bEndpointAddress &= 0xf; | |
168 | if (bEndpointAddress < 8) | |
169 | UICR0 &= ~(1 << bEndpointAddress); | |
170 | else { | |
171 | bEndpointAddress -= 8; | |
172 | UICR1 &= ~(1 << bEndpointAddress); | |
173 | } | |
174 | } | |
175 | ||
176 | static void pio_irq_disable(int bEndpointAddress) | |
177 | { | |
178 | bEndpointAddress &= 0xf; | |
179 | if (bEndpointAddress < 8) | |
180 | UICR0 |= 1 << bEndpointAddress; | |
181 | else { | |
182 | bEndpointAddress -= 8; | |
183 | UICR1 |= 1 << bEndpointAddress; | |
184 | } | |
185 | } | |
186 | ||
187 | /* The UDCCR reg contains mask and interrupt status bits, | |
188 | * so using '|=' isn't safe as it may ack an interrupt. | |
189 | */ | |
190 | #define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE) | |
191 | ||
192 | static inline void udc_set_mask_UDCCR(int mask) | |
193 | { | |
194 | UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS); | |
195 | } | |
196 | ||
197 | static inline void udc_clear_mask_UDCCR(int mask) | |
198 | { | |
199 | UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS); | |
200 | } | |
201 | ||
202 | static inline void udc_ack_int_UDCCR(int mask) | |
203 | { | |
204 | /* udccr contains the bits we dont want to change */ | |
205 | __u32 udccr = UDCCR & UDCCR_MASK_BITS; | |
206 | ||
207 | UDCCR = udccr | (mask & ~UDCCR_MASK_BITS); | |
208 | } | |
209 | ||
210 | /* | |
211 | * endpoint enable/disable | |
212 | * | |
7a857620 | 213 | * we need to verify the descriptors used to enable endpoints. since pxa25x |
1da177e4 LT |
214 | * endpoint configurations are fixed, and are pretty much always enabled, |
215 | * there's not a lot to manage here. | |
216 | * | |
7a857620 | 217 | * because pxa25x can't selectively initialize bulk (or interrupt) endpoints, |
1da177e4 LT |
218 | * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except |
219 | * for a single interface (with only the default altsetting) and for gadget | |
220 | * drivers that don't halt endpoints (not reset by set_interface). that also | |
221 | * means that if you use ISO, you must violate the USB spec rule that all | |
222 | * iso endpoints must be in non-default altsettings. | |
223 | */ | |
7a857620 | 224 | static int pxa25x_ep_enable (struct usb_ep *_ep, |
1da177e4 LT |
225 | const struct usb_endpoint_descriptor *desc) |
226 | { | |
7a857620 PZ |
227 | struct pxa25x_ep *ep; |
228 | struct pxa25x_udc *dev; | |
1da177e4 | 229 | |
7a857620 | 230 | ep = container_of (_ep, struct pxa25x_ep, ep); |
1da177e4 LT |
231 | if (!_ep || !desc || ep->desc || _ep->name == ep0name |
232 | || desc->bDescriptorType != USB_DT_ENDPOINT | |
233 | || ep->bEndpointAddress != desc->bEndpointAddress | |
234 | || ep->fifo_size < le16_to_cpu | |
235 | (desc->wMaxPacketSize)) { | |
441b62c1 | 236 | DMSG("%s, bad ep or descriptor\n", __func__); |
1da177e4 LT |
237 | return -EINVAL; |
238 | } | |
239 | ||
240 | /* xfer types must match, except that interrupt ~= bulk */ | |
241 | if (ep->bmAttributes != desc->bmAttributes | |
242 | && ep->bmAttributes != USB_ENDPOINT_XFER_BULK | |
243 | && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { | |
441b62c1 | 244 | DMSG("%s, %s type mismatch\n", __func__, _ep->name); |
1da177e4 LT |
245 | return -EINVAL; |
246 | } | |
247 | ||
248 | /* hardware _could_ do smaller, but driver doesn't */ | |
249 | if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK | |
250 | && le16_to_cpu (desc->wMaxPacketSize) | |
251 | != BULK_FIFO_SIZE) | |
252 | || !desc->wMaxPacketSize) { | |
441b62c1 | 253 | DMSG("%s, bad %s maxpacket\n", __func__, _ep->name); |
1da177e4 LT |
254 | return -ERANGE; |
255 | } | |
256 | ||
257 | dev = ep->dev; | |
258 | if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { | |
441b62c1 | 259 | DMSG("%s, bogus device state\n", __func__); |
1da177e4 LT |
260 | return -ESHUTDOWN; |
261 | } | |
262 | ||
263 | ep->desc = desc; | |
1da177e4 | 264 | ep->stopped = 0; |
ad8c623f | 265 | ep->pio_irqs = 0; |
1da177e4 LT |
266 | ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize); |
267 | ||
268 | /* flush fifo (mostly for OUT buffers) */ | |
7a857620 | 269 | pxa25x_ep_fifo_flush (_ep); |
1da177e4 LT |
270 | |
271 | /* ... reset halt state too, if we could ... */ | |
272 | ||
1da177e4 LT |
273 | DBG(DBG_VERBOSE, "enabled %s\n", _ep->name); |
274 | return 0; | |
275 | } | |
276 | ||
7a857620 | 277 | static int pxa25x_ep_disable (struct usb_ep *_ep) |
1da177e4 | 278 | { |
7a857620 | 279 | struct pxa25x_ep *ep; |
91987693 | 280 | unsigned long flags; |
1da177e4 | 281 | |
7a857620 | 282 | ep = container_of (_ep, struct pxa25x_ep, ep); |
1da177e4 | 283 | if (!_ep || !ep->desc) { |
441b62c1 | 284 | DMSG("%s, %s not enabled\n", __func__, |
1da177e4 LT |
285 | _ep ? ep->ep.name : NULL); |
286 | return -EINVAL; | |
287 | } | |
91987693 DB |
288 | local_irq_save(flags); |
289 | ||
1da177e4 LT |
290 | nuke (ep, -ESHUTDOWN); |
291 | ||
1da177e4 | 292 | /* flush fifo (mostly for IN buffers) */ |
7a857620 | 293 | pxa25x_ep_fifo_flush (_ep); |
1da177e4 LT |
294 | |
295 | ep->desc = NULL; | |
296 | ep->stopped = 1; | |
297 | ||
91987693 | 298 | local_irq_restore(flags); |
1da177e4 LT |
299 | DBG(DBG_VERBOSE, "%s disabled\n", _ep->name); |
300 | return 0; | |
301 | } | |
302 | ||
303 | /*-------------------------------------------------------------------------*/ | |
304 | ||
7a857620 | 305 | /* for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers |
1da177e4 LT |
306 | * must still pass correctly initialized endpoints, since other controller |
307 | * drivers may care about how it's currently set up (dma issues etc). | |
308 | */ | |
309 | ||
310 | /* | |
7a857620 | 311 | * pxa25x_ep_alloc_request - allocate a request data structure |
1da177e4 LT |
312 | */ |
313 | static struct usb_request * | |
7a857620 | 314 | pxa25x_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags) |
1da177e4 | 315 | { |
7a857620 | 316 | struct pxa25x_request *req; |
1da177e4 | 317 | |
7039f422 | 318 | req = kzalloc(sizeof(*req), gfp_flags); |
1da177e4 LT |
319 | if (!req) |
320 | return NULL; | |
321 | ||
1da177e4 LT |
322 | INIT_LIST_HEAD (&req->queue); |
323 | return &req->req; | |
324 | } | |
325 | ||
326 | ||
327 | /* | |
7a857620 | 328 | * pxa25x_ep_free_request - deallocate a request data structure |
1da177e4 LT |
329 | */ |
330 | static void | |
7a857620 | 331 | pxa25x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req) |
1da177e4 | 332 | { |
7a857620 | 333 | struct pxa25x_request *req; |
1da177e4 | 334 | |
7a857620 | 335 | req = container_of (_req, struct pxa25x_request, req); |
b6c63937 | 336 | WARN_ON(!list_empty (&req->queue)); |
1da177e4 LT |
337 | kfree(req); |
338 | } | |
339 | ||
1da177e4 LT |
340 | /*-------------------------------------------------------------------------*/ |
341 | ||
342 | /* | |
343 | * done - retire a request; caller blocked irqs | |
344 | */ | |
7a857620 | 345 | static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status) |
1da177e4 LT |
346 | { |
347 | unsigned stopped = ep->stopped; | |
348 | ||
349 | list_del_init(&req->queue); | |
350 | ||
351 | if (likely (req->req.status == -EINPROGRESS)) | |
352 | req->req.status = status; | |
353 | else | |
354 | status = req->req.status; | |
355 | ||
356 | if (status && status != -ESHUTDOWN) | |
357 | DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n", | |
358 | ep->ep.name, &req->req, status, | |
359 | req->req.actual, req->req.length); | |
360 | ||
361 | /* don't modify queue heads during completion callback */ | |
362 | ep->stopped = 1; | |
363 | req->req.complete(&ep->ep, &req->req); | |
364 | ep->stopped = stopped; | |
365 | } | |
366 | ||
367 | ||
7a857620 | 368 | static inline void ep0_idle (struct pxa25x_udc *dev) |
1da177e4 LT |
369 | { |
370 | dev->ep0state = EP0_IDLE; | |
371 | } | |
372 | ||
373 | static int | |
7a857620 | 374 | write_packet(volatile u32 *uddr, struct pxa25x_request *req, unsigned max) |
1da177e4 LT |
375 | { |
376 | u8 *buf; | |
377 | unsigned length, count; | |
378 | ||
379 | buf = req->req.buf + req->req.actual; | |
380 | prefetch(buf); | |
381 | ||
382 | /* how big will this packet be? */ | |
383 | length = min(req->req.length - req->req.actual, max); | |
384 | req->req.actual += length; | |
385 | ||
386 | count = length; | |
387 | while (likely(count--)) | |
388 | *uddr = *buf++; | |
389 | ||
390 | return length; | |
391 | } | |
392 | ||
393 | /* | |
394 | * write to an IN endpoint fifo, as many packets as possible. | |
395 | * irqs will use this to write the rest later. | |
396 | * caller guarantees at least one packet buffer is ready (or a zlp). | |
397 | */ | |
398 | static int | |
7a857620 | 399 | write_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) |
1da177e4 LT |
400 | { |
401 | unsigned max; | |
402 | ||
403 | max = le16_to_cpu(ep->desc->wMaxPacketSize); | |
404 | do { | |
405 | unsigned count; | |
406 | int is_last, is_short; | |
407 | ||
408 | count = write_packet(ep->reg_uddr, req, max); | |
409 | ||
410 | /* last packet is usually short (or a zlp) */ | |
411 | if (unlikely (count != max)) | |
412 | is_last = is_short = 1; | |
413 | else { | |
414 | if (likely(req->req.length != req->req.actual) | |
415 | || req->req.zero) | |
416 | is_last = 0; | |
417 | else | |
418 | is_last = 1; | |
419 | /* interrupt/iso maxpacket may not fill the fifo */ | |
420 | is_short = unlikely (max < ep->fifo_size); | |
421 | } | |
422 | ||
423 | DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n", | |
424 | ep->ep.name, count, | |
425 | is_last ? "/L" : "", is_short ? "/S" : "", | |
426 | req->req.length - req->req.actual, req); | |
427 | ||
428 | /* let loose that packet. maybe try writing another one, | |
429 | * double buffering might work. TSP, TPC, and TFS | |
430 | * bit values are the same for all normal IN endpoints. | |
431 | */ | |
432 | *ep->reg_udccs = UDCCS_BI_TPC; | |
433 | if (is_short) | |
434 | *ep->reg_udccs = UDCCS_BI_TSP; | |
435 | ||
436 | /* requests complete when all IN data is in the FIFO */ | |
437 | if (is_last) { | |
438 | done (ep, req, 0); | |
ad8c623f | 439 | if (list_empty(&ep->queue)) |
1da177e4 | 440 | pio_irq_disable (ep->bEndpointAddress); |
1da177e4 LT |
441 | return 1; |
442 | } | |
443 | ||
444 | // TODO experiment: how robust can fifo mode tweaking be? | |
445 | // double buffering is off in the default fifo mode, which | |
446 | // prevents TFS from being set here. | |
447 | ||
448 | } while (*ep->reg_udccs & UDCCS_BI_TFS); | |
449 | return 0; | |
450 | } | |
451 | ||
452 | /* caller asserts req->pending (ep0 irq status nyet cleared); starts | |
453 | * ep0 data stage. these chips want very simple state transitions. | |
454 | */ | |
455 | static inline | |
7a857620 | 456 | void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag) |
1da177e4 LT |
457 | { |
458 | UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR; | |
459 | USIR0 = USIR0_IR0; | |
460 | dev->req_pending = 0; | |
461 | DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n", | |
441b62c1 | 462 | __func__, tag, UDCCS0, flags); |
1da177e4 LT |
463 | } |
464 | ||
465 | static int | |
7a857620 | 466 | write_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) |
1da177e4 LT |
467 | { |
468 | unsigned count; | |
469 | int is_short; | |
470 | ||
471 | count = write_packet(&UDDR0, req, EP0_FIFO_SIZE); | |
472 | ep->dev->stats.write.bytes += count; | |
473 | ||
474 | /* last packet "must be" short (or a zlp) */ | |
475 | is_short = (count != EP0_FIFO_SIZE); | |
476 | ||
477 | DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count, | |
478 | req->req.length - req->req.actual, req); | |
479 | ||
480 | if (unlikely (is_short)) { | |
481 | if (ep->dev->req_pending) | |
482 | ep0start(ep->dev, UDCCS0_IPR, "short IN"); | |
483 | else | |
484 | UDCCS0 = UDCCS0_IPR; | |
485 | ||
486 | count = req->req.length; | |
487 | done (ep, req, 0); | |
488 | ep0_idle(ep->dev); | |
043ea18b | 489 | #ifndef CONFIG_ARCH_IXP4XX |
1da177e4 LT |
490 | #if 1 |
491 | /* This seems to get rid of lost status irqs in some cases: | |
492 | * host responds quickly, or next request involves config | |
493 | * change automagic, or should have been hidden, or ... | |
494 | * | |
495 | * FIXME get rid of all udelays possible... | |
496 | */ | |
497 | if (count >= EP0_FIFO_SIZE) { | |
498 | count = 100; | |
499 | do { | |
500 | if ((UDCCS0 & UDCCS0_OPR) != 0) { | |
501 | /* clear OPR, generate ack */ | |
502 | UDCCS0 = UDCCS0_OPR; | |
503 | break; | |
504 | } | |
505 | count--; | |
506 | udelay(1); | |
507 | } while (count); | |
508 | } | |
043ea18b | 509 | #endif |
1da177e4 LT |
510 | #endif |
511 | } else if (ep->dev->req_pending) | |
512 | ep0start(ep->dev, 0, "IN"); | |
513 | return is_short; | |
514 | } | |
515 | ||
516 | ||
517 | /* | |
518 | * read_fifo - unload packet(s) from the fifo we use for usb OUT | |
519 | * transfers and put them into the request. caller should have made | |
520 | * sure there's at least one packet ready. | |
521 | * | |
522 | * returns true if the request completed because of short packet or the | |
523 | * request buffer having filled (and maybe overran till end-of-packet). | |
524 | */ | |
525 | static int | |
7a857620 | 526 | read_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) |
1da177e4 LT |
527 | { |
528 | for (;;) { | |
529 | u32 udccs; | |
530 | u8 *buf; | |
531 | unsigned bufferspace, count, is_short; | |
532 | ||
533 | /* make sure there's a packet in the FIFO. | |
534 | * UDCCS_{BO,IO}_RPC are all the same bit value. | |
535 | * UDCCS_{BO,IO}_RNE are all the same bit value. | |
536 | */ | |
537 | udccs = *ep->reg_udccs; | |
538 | if (unlikely ((udccs & UDCCS_BO_RPC) == 0)) | |
539 | break; | |
540 | buf = req->req.buf + req->req.actual; | |
541 | prefetchw(buf); | |
542 | bufferspace = req->req.length - req->req.actual; | |
543 | ||
544 | /* read all bytes from this packet */ | |
545 | if (likely (udccs & UDCCS_BO_RNE)) { | |
546 | count = 1 + (0x0ff & *ep->reg_ubcr); | |
547 | req->req.actual += min (count, bufferspace); | |
548 | } else /* zlp */ | |
549 | count = 0; | |
550 | is_short = (count < ep->ep.maxpacket); | |
551 | DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n", | |
552 | ep->ep.name, udccs, count, | |
553 | is_short ? "/S" : "", | |
554 | req, req->req.actual, req->req.length); | |
555 | while (likely (count-- != 0)) { | |
556 | u8 byte = (u8) *ep->reg_uddr; | |
557 | ||
558 | if (unlikely (bufferspace == 0)) { | |
559 | /* this happens when the driver's buffer | |
560 | * is smaller than what the host sent. | |
561 | * discard the extra data. | |
562 | */ | |
563 | if (req->req.status != -EOVERFLOW) | |
564 | DMSG("%s overflow %d\n", | |
565 | ep->ep.name, count); | |
566 | req->req.status = -EOVERFLOW; | |
567 | } else { | |
568 | *buf++ = byte; | |
569 | bufferspace--; | |
570 | } | |
571 | } | |
572 | *ep->reg_udccs = UDCCS_BO_RPC; | |
573 | /* RPC/RSP/RNE could now reflect the other packet buffer */ | |
574 | ||
575 | /* iso is one request per packet */ | |
576 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
577 | if (udccs & UDCCS_IO_ROF) | |
578 | req->req.status = -EHOSTUNREACH; | |
579 | /* more like "is_done" */ | |
580 | is_short = 1; | |
581 | } | |
582 | ||
583 | /* completion */ | |
584 | if (is_short || req->req.actual == req->req.length) { | |
585 | done (ep, req, 0); | |
586 | if (list_empty(&ep->queue)) | |
587 | pio_irq_disable (ep->bEndpointAddress); | |
588 | return 1; | |
589 | } | |
590 | ||
591 | /* finished that packet. the next one may be waiting... */ | |
592 | } | |
593 | return 0; | |
594 | } | |
595 | ||
596 | /* | |
597 | * special ep0 version of the above. no UBCR0 or double buffering; status | |
598 | * handshaking is magic. most device protocols don't need control-OUT. | |
599 | * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other | |
600 | * protocols do use them. | |
601 | */ | |
602 | static int | |
7a857620 | 603 | read_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) |
1da177e4 LT |
604 | { |
605 | u8 *buf, byte; | |
606 | unsigned bufferspace; | |
607 | ||
608 | buf = req->req.buf + req->req.actual; | |
609 | bufferspace = req->req.length - req->req.actual; | |
610 | ||
611 | while (UDCCS0 & UDCCS0_RNE) { | |
612 | byte = (u8) UDDR0; | |
613 | ||
614 | if (unlikely (bufferspace == 0)) { | |
615 | /* this happens when the driver's buffer | |
616 | * is smaller than what the host sent. | |
617 | * discard the extra data. | |
618 | */ | |
619 | if (req->req.status != -EOVERFLOW) | |
620 | DMSG("%s overflow\n", ep->ep.name); | |
621 | req->req.status = -EOVERFLOW; | |
622 | } else { | |
623 | *buf++ = byte; | |
624 | req->req.actual++; | |
625 | bufferspace--; | |
626 | } | |
627 | } | |
628 | ||
629 | UDCCS0 = UDCCS0_OPR | UDCCS0_IPR; | |
630 | ||
631 | /* completion */ | |
632 | if (req->req.actual >= req->req.length) | |
633 | return 1; | |
634 | ||
635 | /* finished that packet. the next one may be waiting... */ | |
636 | return 0; | |
637 | } | |
638 | ||
1da177e4 LT |
639 | /*-------------------------------------------------------------------------*/ |
640 | ||
641 | static int | |
7a857620 | 642 | pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) |
1da177e4 | 643 | { |
7a857620 PZ |
644 | struct pxa25x_request *req; |
645 | struct pxa25x_ep *ep; | |
646 | struct pxa25x_udc *dev; | |
1da177e4 LT |
647 | unsigned long flags; |
648 | ||
7a857620 | 649 | req = container_of(_req, struct pxa25x_request, req); |
1da177e4 LT |
650 | if (unlikely (!_req || !_req->complete || !_req->buf |
651 | || !list_empty(&req->queue))) { | |
441b62c1 | 652 | DMSG("%s, bad params\n", __func__); |
1da177e4 LT |
653 | return -EINVAL; |
654 | } | |
655 | ||
7a857620 | 656 | ep = container_of(_ep, struct pxa25x_ep, ep); |
1da177e4 | 657 | if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) { |
441b62c1 | 658 | DMSG("%s, bad ep\n", __func__); |
1da177e4 LT |
659 | return -EINVAL; |
660 | } | |
661 | ||
662 | dev = ep->dev; | |
663 | if (unlikely (!dev->driver | |
664 | || dev->gadget.speed == USB_SPEED_UNKNOWN)) { | |
441b62c1 | 665 | DMSG("%s, bogus device state\n", __func__); |
1da177e4 LT |
666 | return -ESHUTDOWN; |
667 | } | |
668 | ||
669 | /* iso is always one packet per request, that's the only way | |
670 | * we can report per-packet status. that also helps with dma. | |
671 | */ | |
672 | if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC | |
673 | && req->req.length > le16_to_cpu | |
674 | (ep->desc->wMaxPacketSize))) | |
675 | return -EMSGSIZE; | |
676 | ||
1da177e4 | 677 | DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n", |
ad8c623f | 678 | _ep->name, _req, _req->length, _req->buf); |
1da177e4 LT |
679 | |
680 | local_irq_save(flags); | |
681 | ||
682 | _req->status = -EINPROGRESS; | |
683 | _req->actual = 0; | |
684 | ||
685 | /* kickstart this i/o queue? */ | |
686 | if (list_empty(&ep->queue) && !ep->stopped) { | |
040fa1b9 | 687 | if (ep->desc == NULL/* ep0 */) { |
1da177e4 LT |
688 | unsigned length = _req->length; |
689 | ||
690 | switch (dev->ep0state) { | |
691 | case EP0_IN_DATA_PHASE: | |
692 | dev->stats.write.ops++; | |
693 | if (write_ep0_fifo(ep, req)) | |
694 | req = NULL; | |
695 | break; | |
696 | ||
697 | case EP0_OUT_DATA_PHASE: | |
698 | dev->stats.read.ops++; | |
699 | /* messy ... */ | |
700 | if (dev->req_config) { | |
701 | DBG(DBG_VERBOSE, "ep0 config ack%s\n", | |
702 | dev->has_cfr ? "" : " raced"); | |
703 | if (dev->has_cfr) | |
704 | UDCCFR = UDCCFR_AREN|UDCCFR_ACM | |
705 | |UDCCFR_MB1; | |
706 | done(ep, req, 0); | |
707 | dev->ep0state = EP0_END_XFER; | |
708 | local_irq_restore (flags); | |
709 | return 0; | |
710 | } | |
711 | if (dev->req_pending) | |
712 | ep0start(dev, UDCCS0_IPR, "OUT"); | |
713 | if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0 | |
714 | && read_ep0_fifo(ep, req))) { | |
715 | ep0_idle(dev); | |
716 | done(ep, req, 0); | |
717 | req = NULL; | |
718 | } | |
719 | break; | |
720 | ||
721 | default: | |
722 | DMSG("ep0 i/o, odd state %d\n", dev->ep0state); | |
723 | local_irq_restore (flags); | |
724 | return -EL2HLT; | |
725 | } | |
1da177e4 | 726 | /* can the FIFO can satisfy the request immediately? */ |
91987693 DB |
727 | } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) { |
728 | if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0 | |
729 | && write_fifo(ep, req)) | |
730 | req = NULL; | |
1da177e4 LT |
731 | } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0 |
732 | && read_fifo(ep, req)) { | |
733 | req = NULL; | |
734 | } | |
735 | ||
ad8c623f | 736 | if (likely (req && ep->desc)) |
1da177e4 LT |
737 | pio_irq_enable(ep->bEndpointAddress); |
738 | } | |
739 | ||
740 | /* pio or dma irq handler advances the queue. */ | |
040fa1b9 | 741 | if (likely(req != NULL)) |
1da177e4 LT |
742 | list_add_tail(&req->queue, &ep->queue); |
743 | local_irq_restore(flags); | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
748 | ||
749 | /* | |
34ebcd28 | 750 | * nuke - dequeue ALL requests |
1da177e4 | 751 | */ |
7a857620 | 752 | static void nuke(struct pxa25x_ep *ep, int status) |
1da177e4 | 753 | { |
7a857620 | 754 | struct pxa25x_request *req; |
1da177e4 LT |
755 | |
756 | /* called with irqs blocked */ | |
1da177e4 LT |
757 | while (!list_empty(&ep->queue)) { |
758 | req = list_entry(ep->queue.next, | |
7a857620 | 759 | struct pxa25x_request, |
1da177e4 LT |
760 | queue); |
761 | done(ep, req, status); | |
762 | } | |
763 | if (ep->desc) | |
764 | pio_irq_disable (ep->bEndpointAddress); | |
765 | } | |
766 | ||
767 | ||
768 | /* dequeue JUST ONE request */ | |
7a857620 | 769 | static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
1da177e4 | 770 | { |
7a857620 PZ |
771 | struct pxa25x_ep *ep; |
772 | struct pxa25x_request *req; | |
1da177e4 LT |
773 | unsigned long flags; |
774 | ||
7a857620 | 775 | ep = container_of(_ep, struct pxa25x_ep, ep); |
1da177e4 LT |
776 | if (!_ep || ep->ep.name == ep0name) |
777 | return -EINVAL; | |
778 | ||
779 | local_irq_save(flags); | |
780 | ||
781 | /* make sure it's actually queued on this endpoint */ | |
782 | list_for_each_entry (req, &ep->queue, queue) { | |
783 | if (&req->req == _req) | |
784 | break; | |
785 | } | |
786 | if (&req->req != _req) { | |
787 | local_irq_restore(flags); | |
788 | return -EINVAL; | |
789 | } | |
790 | ||
ad8c623f | 791 | done(ep, req, -ECONNRESET); |
1da177e4 LT |
792 | |
793 | local_irq_restore(flags); | |
794 | return 0; | |
795 | } | |
796 | ||
797 | /*-------------------------------------------------------------------------*/ | |
798 | ||
7a857620 | 799 | static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value) |
1da177e4 | 800 | { |
7a857620 | 801 | struct pxa25x_ep *ep; |
1da177e4 LT |
802 | unsigned long flags; |
803 | ||
7a857620 | 804 | ep = container_of(_ep, struct pxa25x_ep, ep); |
1da177e4 LT |
805 | if (unlikely (!_ep |
806 | || (!ep->desc && ep->ep.name != ep0name)) | |
807 | || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
441b62c1 | 808 | DMSG("%s, bad ep\n", __func__); |
1da177e4 LT |
809 | return -EINVAL; |
810 | } | |
811 | if (value == 0) { | |
812 | /* this path (reset toggle+halt) is needed to implement | |
813 | * SET_INTERFACE on normal hardware. but it can't be | |
814 | * done from software on the PXA UDC, and the hardware | |
815 | * forgets to do it as part of SET_INTERFACE automagic. | |
816 | */ | |
817 | DMSG("only host can clear %s halt\n", _ep->name); | |
818 | return -EROFS; | |
819 | } | |
820 | ||
821 | local_irq_save(flags); | |
822 | ||
823 | if ((ep->bEndpointAddress & USB_DIR_IN) != 0 | |
824 | && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0 | |
825 | || !list_empty(&ep->queue))) { | |
826 | local_irq_restore(flags); | |
827 | return -EAGAIN; | |
828 | } | |
829 | ||
830 | /* FST bit is the same for control, bulk in, bulk out, interrupt in */ | |
831 | *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF; | |
832 | ||
833 | /* ep0 needs special care */ | |
834 | if (!ep->desc) { | |
835 | start_watchdog(ep->dev); | |
836 | ep->dev->req_pending = 0; | |
837 | ep->dev->ep0state = EP0_STALL; | |
838 | ||
34ebcd28 DB |
839 | /* and bulk/intr endpoints like dropping stalls too */ |
840 | } else { | |
841 | unsigned i; | |
842 | for (i = 0; i < 1000; i += 20) { | |
843 | if (*ep->reg_udccs & UDCCS_BI_SST) | |
844 | break; | |
845 | udelay(20); | |
846 | } | |
847 | } | |
848 | local_irq_restore(flags); | |
1da177e4 LT |
849 | |
850 | DBG(DBG_VERBOSE, "%s halt\n", _ep->name); | |
851 | return 0; | |
852 | } | |
853 | ||
7a857620 | 854 | static int pxa25x_ep_fifo_status(struct usb_ep *_ep) |
1da177e4 | 855 | { |
7a857620 | 856 | struct pxa25x_ep *ep; |
1da177e4 | 857 | |
7a857620 | 858 | ep = container_of(_ep, struct pxa25x_ep, ep); |
1da177e4 | 859 | if (!_ep) { |
441b62c1 | 860 | DMSG("%s, bad ep\n", __func__); |
1da177e4 LT |
861 | return -ENODEV; |
862 | } | |
863 | /* pxa can't report unclaimed bytes from IN fifos */ | |
864 | if ((ep->bEndpointAddress & USB_DIR_IN) != 0) | |
865 | return -EOPNOTSUPP; | |
866 | if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN | |
867 | || (*ep->reg_udccs & UDCCS_BO_RFS) == 0) | |
868 | return 0; | |
869 | else | |
870 | return (*ep->reg_ubcr & 0xfff) + 1; | |
871 | } | |
872 | ||
7a857620 | 873 | static void pxa25x_ep_fifo_flush(struct usb_ep *_ep) |
1da177e4 | 874 | { |
7a857620 | 875 | struct pxa25x_ep *ep; |
1da177e4 | 876 | |
7a857620 | 877 | ep = container_of(_ep, struct pxa25x_ep, ep); |
1da177e4 | 878 | if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) { |
441b62c1 | 879 | DMSG("%s, bad ep\n", __func__); |
1da177e4 LT |
880 | return; |
881 | } | |
882 | ||
883 | /* toggle and halt bits stay unchanged */ | |
884 | ||
885 | /* for OUT, just read and discard the FIFO contents. */ | |
886 | if ((ep->bEndpointAddress & USB_DIR_IN) == 0) { | |
887 | while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0) | |
888 | (void) *ep->reg_uddr; | |
889 | return; | |
890 | } | |
891 | ||
892 | /* most IN status is the same, but ISO can't stall */ | |
893 | *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR | |
22eb36f4 RK |
894 | | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC |
895 | ? 0 : UDCCS_BI_SST); | |
1da177e4 LT |
896 | } |
897 | ||
898 | ||
7a857620 PZ |
899 | static struct usb_ep_ops pxa25x_ep_ops = { |
900 | .enable = pxa25x_ep_enable, | |
901 | .disable = pxa25x_ep_disable, | |
1da177e4 | 902 | |
7a857620 PZ |
903 | .alloc_request = pxa25x_ep_alloc_request, |
904 | .free_request = pxa25x_ep_free_request, | |
1da177e4 | 905 | |
7a857620 PZ |
906 | .queue = pxa25x_ep_queue, |
907 | .dequeue = pxa25x_ep_dequeue, | |
1da177e4 | 908 | |
7a857620 PZ |
909 | .set_halt = pxa25x_ep_set_halt, |
910 | .fifo_status = pxa25x_ep_fifo_status, | |
911 | .fifo_flush = pxa25x_ep_fifo_flush, | |
1da177e4 LT |
912 | }; |
913 | ||
914 | ||
915 | /* --------------------------------------------------------------------------- | |
34ebcd28 | 916 | * device-scoped parts of the api to the usb controller hardware |
1da177e4 LT |
917 | * --------------------------------------------------------------------------- |
918 | */ | |
919 | ||
7a857620 | 920 | static int pxa25x_udc_get_frame(struct usb_gadget *_gadget) |
1da177e4 LT |
921 | { |
922 | return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff); | |
923 | } | |
924 | ||
7a857620 | 925 | static int pxa25x_udc_wakeup(struct usb_gadget *_gadget) |
1da177e4 LT |
926 | { |
927 | /* host may not have enabled remote wakeup */ | |
928 | if ((UDCCS0 & UDCCS0_DRWF) == 0) | |
929 | return -EHOSTUNREACH; | |
930 | udc_set_mask_UDCCR(UDCCR_RSM); | |
931 | return 0; | |
932 | } | |
933 | ||
7a857620 PZ |
934 | static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *); |
935 | static void udc_enable (struct pxa25x_udc *); | |
936 | static void udc_disable(struct pxa25x_udc *); | |
1da177e4 LT |
937 | |
938 | /* We disable the UDC -- and its 48 MHz clock -- whenever it's not | |
34ebcd28 | 939 | * in active use. |
1da177e4 | 940 | */ |
7a857620 | 941 | static int pullup(struct pxa25x_udc *udc) |
1da177e4 | 942 | { |
64cc2dd9 | 943 | int is_active = udc->vbus && udc->pullup && !udc->suspended; |
1da177e4 | 944 | DMSG("%s\n", is_active ? "active" : "inactive"); |
64cc2dd9 DES |
945 | if (is_active) { |
946 | if (!udc->active) { | |
947 | udc->active = 1; | |
948 | /* Enable clock for USB device */ | |
949 | clk_enable(udc->clk); | |
950 | udc_enable(udc); | |
1da177e4 | 951 | } |
64cc2dd9 DES |
952 | } else { |
953 | if (udc->active) { | |
954 | if (udc->gadget.speed != USB_SPEED_UNKNOWN) { | |
955 | DMSG("disconnect %s\n", udc->driver | |
956 | ? udc->driver->driver.name | |
957 | : "(no driver)"); | |
958 | stop_activity(udc, udc->driver); | |
959 | } | |
960 | udc_disable(udc); | |
961 | /* Disable clock for USB device */ | |
962 | clk_disable(udc->clk); | |
963 | udc->active = 0; | |
964 | } | |
965 | ||
1da177e4 LT |
966 | } |
967 | return 0; | |
968 | } | |
969 | ||
970 | /* VBUS reporting logically comes from a transceiver */ | |
7a857620 | 971 | static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active) |
1da177e4 | 972 | { |
7a857620 | 973 | struct pxa25x_udc *udc; |
1da177e4 | 974 | |
7a857620 | 975 | udc = container_of(_gadget, struct pxa25x_udc, gadget); |
47fd6f7c | 976 | udc->vbus = is_active; |
1da177e4 | 977 | DMSG("vbus %s\n", is_active ? "supplied" : "inactive"); |
64cc2dd9 | 978 | pullup(udc); |
1da177e4 LT |
979 | return 0; |
980 | } | |
981 | ||
982 | /* drivers may have software control over D+ pullup */ | |
7a857620 | 983 | static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active) |
1da177e4 | 984 | { |
7a857620 | 985 | struct pxa25x_udc *udc; |
1da177e4 | 986 | |
7a857620 | 987 | udc = container_of(_gadget, struct pxa25x_udc, gadget); |
1da177e4 LT |
988 | |
989 | /* not all boards support pullup control */ | |
56a075dc | 990 | if (!gpio_is_valid(udc->mach->gpio_pullup) && !udc->mach->udc_command) |
1da177e4 LT |
991 | return -EOPNOTSUPP; |
992 | ||
64cc2dd9 DES |
993 | udc->pullup = (is_active != 0); |
994 | pullup(udc); | |
1da177e4 LT |
995 | return 0; |
996 | } | |
997 | ||
ab26d20f PZ |
998 | /* boards may consume current from VBUS, up to 100-500mA based on config. |
999 | * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs | |
1000 | * violate USB specs. | |
1001 | */ | |
1002 | static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA) | |
1003 | { | |
1004 | struct pxa25x_udc *udc; | |
1005 | ||
1006 | udc = container_of(_gadget, struct pxa25x_udc, gadget); | |
1007 | ||
1008 | if (udc->transceiver) | |
1009 | return otg_set_power(udc->transceiver, mA); | |
1010 | return -EOPNOTSUPP; | |
1011 | } | |
1012 | ||
7a857620 PZ |
1013 | static const struct usb_gadget_ops pxa25x_udc_ops = { |
1014 | .get_frame = pxa25x_udc_get_frame, | |
1015 | .wakeup = pxa25x_udc_wakeup, | |
1016 | .vbus_session = pxa25x_udc_vbus_session, | |
1017 | .pullup = pxa25x_udc_pullup, | |
ab26d20f | 1018 | .vbus_draw = pxa25x_udc_vbus_draw, |
1da177e4 LT |
1019 | }; |
1020 | ||
1021 | /*-------------------------------------------------------------------------*/ | |
1022 | ||
040fa1b9 | 1023 | #ifdef CONFIG_USB_GADGET_DEBUG_FS |
1da177e4 LT |
1024 | |
1025 | static int | |
64cc2dd9 | 1026 | udc_seq_show(struct seq_file *m, void *_d) |
1da177e4 | 1027 | { |
7a857620 | 1028 | struct pxa25x_udc *dev = m->private; |
1da177e4 | 1029 | unsigned long flags; |
040fa1b9 | 1030 | int i; |
1da177e4 LT |
1031 | u32 tmp; |
1032 | ||
1da177e4 LT |
1033 | local_irq_save(flags); |
1034 | ||
1035 | /* basic device status */ | |
040fa1b9 | 1036 | seq_printf(m, DRIVER_DESC "\n" |
1da177e4 | 1037 | "%s version: %s\nGadget driver: %s\nHost %s\n\n", |
ad8c623f | 1038 | driver_name, DRIVER_VERSION SIZE_STR "(pio)", |
1da177e4 | 1039 | dev->driver ? dev->driver->driver.name : "(none)", |
a8ecc860 | 1040 | dev->gadget.speed == USB_SPEED_FULL ? "full speed" : "disconnected"); |
1da177e4 LT |
1041 | |
1042 | /* registers for device and ep0 */ | |
040fa1b9 | 1043 | seq_printf(m, |
1da177e4 LT |
1044 | "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n", |
1045 | UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL); | |
1da177e4 LT |
1046 | |
1047 | tmp = UDCCR; | |
040fa1b9 | 1048 | seq_printf(m, |
1da177e4 LT |
1049 | "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp, |
1050 | (tmp & UDCCR_REM) ? " rem" : "", | |
1051 | (tmp & UDCCR_RSTIR) ? " rstir" : "", | |
1052 | (tmp & UDCCR_SRM) ? " srm" : "", | |
1053 | (tmp & UDCCR_SUSIR) ? " susir" : "", | |
1054 | (tmp & UDCCR_RESIR) ? " resir" : "", | |
1055 | (tmp & UDCCR_RSM) ? " rsm" : "", | |
1056 | (tmp & UDCCR_UDA) ? " uda" : "", | |
1057 | (tmp & UDCCR_UDE) ? " ude" : ""); | |
1da177e4 LT |
1058 | |
1059 | tmp = UDCCS0; | |
040fa1b9 | 1060 | seq_printf(m, |
1da177e4 LT |
1061 | "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp, |
1062 | (tmp & UDCCS0_SA) ? " sa" : "", | |
1063 | (tmp & UDCCS0_RNE) ? " rne" : "", | |
1064 | (tmp & UDCCS0_FST) ? " fst" : "", | |
1065 | (tmp & UDCCS0_SST) ? " sst" : "", | |
1066 | (tmp & UDCCS0_DRWF) ? " dwrf" : "", | |
1067 | (tmp & UDCCS0_FTF) ? " ftf" : "", | |
1068 | (tmp & UDCCS0_IPR) ? " ipr" : "", | |
1069 | (tmp & UDCCS0_OPR) ? " opr" : ""); | |
1da177e4 LT |
1070 | |
1071 | if (dev->has_cfr) { | |
1072 | tmp = UDCCFR; | |
040fa1b9 | 1073 | seq_printf(m, |
1da177e4 LT |
1074 | "udccfr %02X =%s%s\n", tmp, |
1075 | (tmp & UDCCFR_AREN) ? " aren" : "", | |
1076 | (tmp & UDCCFR_ACM) ? " acm" : ""); | |
1da177e4 LT |
1077 | } |
1078 | ||
a8ecc860 | 1079 | if (dev->gadget.speed != USB_SPEED_FULL || !dev->driver) |
1da177e4 LT |
1080 | goto done; |
1081 | ||
040fa1b9 | 1082 | seq_printf(m, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n", |
1da177e4 LT |
1083 | dev->stats.write.bytes, dev->stats.write.ops, |
1084 | dev->stats.read.bytes, dev->stats.read.ops, | |
1085 | dev->stats.irqs); | |
1da177e4 LT |
1086 | |
1087 | /* dump endpoint queues */ | |
1088 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { | |
7a857620 PZ |
1089 | struct pxa25x_ep *ep = &dev->ep [i]; |
1090 | struct pxa25x_request *req; | |
1da177e4 LT |
1091 | |
1092 | if (i != 0) { | |
040fa1b9 | 1093 | const struct usb_endpoint_descriptor *desc; |
1da177e4 | 1094 | |
040fa1b9 DES |
1095 | desc = ep->desc; |
1096 | if (!desc) | |
1da177e4 LT |
1097 | continue; |
1098 | tmp = *dev->ep [i].reg_udccs; | |
040fa1b9 | 1099 | seq_printf(m, |
ad8c623f | 1100 | "%s max %d %s udccs %02x irqs %lu\n", |
040fa1b9 | 1101 | ep->ep.name, le16_to_cpu(desc->wMaxPacketSize), |
ad8c623f | 1102 | "pio", tmp, ep->pio_irqs); |
1da177e4 LT |
1103 | /* TODO translate all five groups of udccs bits! */ |
1104 | ||
1105 | } else /* ep0 should only have one transfer queued */ | |
040fa1b9 | 1106 | seq_printf(m, "ep0 max 16 pio irqs %lu\n", |
1da177e4 | 1107 | ep->pio_irqs); |
1da177e4 LT |
1108 | |
1109 | if (list_empty(&ep->queue)) { | |
040fa1b9 | 1110 | seq_printf(m, "\t(nothing queued)\n"); |
1da177e4 LT |
1111 | continue; |
1112 | } | |
1113 | list_for_each_entry(req, &ep->queue, queue) { | |
040fa1b9 | 1114 | seq_printf(m, |
1da177e4 LT |
1115 | "\treq %p len %d/%d buf %p\n", |
1116 | &req->req, req->req.actual, | |
1117 | req->req.length, req->req.buf); | |
1da177e4 LT |
1118 | } |
1119 | } | |
1120 | ||
1121 | done: | |
1122 | local_irq_restore(flags); | |
040fa1b9 | 1123 | return 0; |
1da177e4 LT |
1124 | } |
1125 | ||
040fa1b9 DES |
1126 | static int |
1127 | udc_debugfs_open(struct inode *inode, struct file *file) | |
1128 | { | |
1129 | return single_open(file, udc_seq_show, inode->i_private); | |
1130 | } | |
1131 | ||
1132 | static const struct file_operations debug_fops = { | |
1133 | .open = udc_debugfs_open, | |
1134 | .read = seq_read, | |
1135 | .llseek = seq_lseek, | |
1136 | .release = single_release, | |
1137 | .owner = THIS_MODULE, | |
1138 | }; | |
1139 | ||
1140 | #define create_debug_files(dev) \ | |
1141 | do { \ | |
1142 | dev->debugfs_udc = debugfs_create_file(dev->gadget.name, \ | |
1143 | S_IRUGO, NULL, dev, &debug_fops); \ | |
1144 | } while (0) | |
1145 | #define remove_debug_files(dev) \ | |
1146 | do { \ | |
1147 | if (dev->debugfs_udc) \ | |
1148 | debugfs_remove(dev->debugfs_udc); \ | |
1149 | } while (0) | |
1da177e4 LT |
1150 | |
1151 | #else /* !CONFIG_USB_GADGET_DEBUG_FILES */ | |
1152 | ||
040fa1b9 DES |
1153 | #define create_debug_files(dev) do {} while (0) |
1154 | #define remove_debug_files(dev) do {} while (0) | |
1da177e4 LT |
1155 | |
1156 | #endif /* CONFIG_USB_GADGET_DEBUG_FILES */ | |
1157 | ||
1da177e4 LT |
1158 | /*-------------------------------------------------------------------------*/ |
1159 | ||
1160 | /* | |
34ebcd28 | 1161 | * udc_disable - disable USB device controller |
1da177e4 | 1162 | */ |
7a857620 | 1163 | static void udc_disable(struct pxa25x_udc *dev) |
1da177e4 LT |
1164 | { |
1165 | /* block all irqs */ | |
1166 | udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM); | |
1167 | UICR0 = UICR1 = 0xff; | |
1168 | UFNRH = UFNRH_SIM; | |
1169 | ||
1170 | /* if hardware supports it, disconnect from usb */ | |
91987693 | 1171 | pullup_off(); |
1da177e4 LT |
1172 | |
1173 | udc_clear_mask_UDCCR(UDCCR_UDE); | |
1174 | ||
1da177e4 LT |
1175 | ep0_idle (dev); |
1176 | dev->gadget.speed = USB_SPEED_UNKNOWN; | |
1da177e4 LT |
1177 | } |
1178 | ||
1179 | ||
1180 | /* | |
34ebcd28 | 1181 | * udc_reinit - initialize software state |
1da177e4 | 1182 | */ |
7a857620 | 1183 | static void udc_reinit(struct pxa25x_udc *dev) |
1da177e4 LT |
1184 | { |
1185 | u32 i; | |
1186 | ||
1187 | /* device/ep0 records init */ | |
1188 | INIT_LIST_HEAD (&dev->gadget.ep_list); | |
1189 | INIT_LIST_HEAD (&dev->gadget.ep0->ep_list); | |
1190 | dev->ep0state = EP0_IDLE; | |
1191 | ||
1192 | /* basic endpoint records init */ | |
1193 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { | |
7a857620 | 1194 | struct pxa25x_ep *ep = &dev->ep[i]; |
1da177e4 LT |
1195 | |
1196 | if (i != 0) | |
1197 | list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list); | |
1198 | ||
1199 | ep->desc = NULL; | |
1200 | ep->stopped = 0; | |
1201 | INIT_LIST_HEAD (&ep->queue); | |
ad8c623f | 1202 | ep->pio_irqs = 0; |
1da177e4 LT |
1203 | } |
1204 | ||
1205 | /* the rest was statically initialized, and is read-only */ | |
1206 | } | |
1207 | ||
1208 | /* until it's enabled, this UDC should be completely invisible | |
1209 | * to any USB host. | |
1210 | */ | |
7a857620 | 1211 | static void udc_enable (struct pxa25x_udc *dev) |
1da177e4 LT |
1212 | { |
1213 | udc_clear_mask_UDCCR(UDCCR_UDE); | |
1214 | ||
1da177e4 LT |
1215 | /* try to clear these bits before we enable the udc */ |
1216 | udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR); | |
1217 | ||
1218 | ep0_idle(dev); | |
1219 | dev->gadget.speed = USB_SPEED_UNKNOWN; | |
1220 | dev->stats.irqs = 0; | |
1221 | ||
1222 | /* | |
1223 | * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual: | |
1224 | * - enable UDC | |
1225 | * - if RESET is already in progress, ack interrupt | |
1226 | * - unmask reset interrupt | |
1227 | */ | |
1228 | udc_set_mask_UDCCR(UDCCR_UDE); | |
1229 | if (!(UDCCR & UDCCR_UDA)) | |
1230 | udc_ack_int_UDCCR(UDCCR_RSTIR); | |
1231 | ||
1232 | if (dev->has_cfr /* UDC_RES2 is defined */) { | |
1233 | /* pxa255 (a0+) can avoid a set_config race that could | |
1234 | * prevent gadget drivers from configuring correctly | |
1235 | */ | |
1236 | UDCCFR = UDCCFR_ACM | UDCCFR_MB1; | |
1237 | } else { | |
1238 | /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1) | |
1239 | * which could result in missing packets and interrupts. | |
1240 | * supposedly one bit per endpoint, controlling whether it | |
1241 | * double buffers or not; ACM/AREN bits fit into the holes. | |
1242 | * zero bits (like USIR0_IRx) disable double buffering. | |
1243 | */ | |
1244 | UDC_RES1 = 0x00; | |
1245 | UDC_RES2 = 0x00; | |
1246 | } | |
1247 | ||
1da177e4 LT |
1248 | /* enable suspend/resume and reset irqs */ |
1249 | udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM); | |
1250 | ||
1251 | /* enable ep0 irqs */ | |
1252 | UICR0 &= ~UICR0_IM0; | |
1253 | ||
1254 | /* if hardware supports it, pullup D+ and wait for reset */ | |
91987693 | 1255 | pullup_on(); |
1da177e4 LT |
1256 | } |
1257 | ||
1258 | ||
1259 | /* when a driver is successfully registered, it will receive | |
1260 | * control requests including set_configuration(), which enables | |
1261 | * non-control requests. then usb traffic follows until a | |
1262 | * disconnect is reported. then a host may connect again, or | |
1263 | * the driver might get unbound. | |
1264 | */ | |
b0fca50f UKK |
1265 | int usb_gadget_probe_driver(struct usb_gadget_driver *driver, |
1266 | int (*bind)(struct usb_gadget *)) | |
1da177e4 | 1267 | { |
7a857620 | 1268 | struct pxa25x_udc *dev = the_controller; |
1da177e4 LT |
1269 | int retval; |
1270 | ||
1271 | if (!driver | |
7c0642c1 | 1272 | || driver->speed < USB_SPEED_FULL |
b0fca50f | 1273 | || !bind |
1da177e4 LT |
1274 | || !driver->disconnect |
1275 | || !driver->setup) | |
1276 | return -EINVAL; | |
1277 | if (!dev) | |
1278 | return -ENODEV; | |
1279 | if (dev->driver) | |
1280 | return -EBUSY; | |
1281 | ||
1282 | /* first hook up the driver ... */ | |
1283 | dev->driver = driver; | |
1284 | dev->gadget.dev.driver = &driver->driver; | |
1285 | dev->pullup = 1; | |
1286 | ||
34ebcd28 DB |
1287 | retval = device_add (&dev->gadget.dev); |
1288 | if (retval) { | |
1289 | fail: | |
1290 | dev->driver = NULL; | |
1291 | dev->gadget.dev.driver = NULL; | |
1292 | return retval; | |
1293 | } | |
b0fca50f | 1294 | retval = bind(&dev->gadget); |
1da177e4 LT |
1295 | if (retval) { |
1296 | DMSG("bind to driver %s --> error %d\n", | |
1297 | driver->driver.name, retval); | |
1298 | device_del (&dev->gadget.dev); | |
34ebcd28 | 1299 | goto fail; |
1da177e4 | 1300 | } |
1da177e4 LT |
1301 | |
1302 | /* ... then enable host detection and ep0; and we're ready | |
1303 | * for set_configuration as well as eventual disconnect. | |
1304 | */ | |
1305 | DMSG("registered gadget driver '%s'\n", driver->driver.name); | |
ab26d20f PZ |
1306 | |
1307 | /* connect to bus through transceiver */ | |
1308 | if (dev->transceiver) { | |
1309 | retval = otg_set_peripheral(dev->transceiver, &dev->gadget); | |
1310 | if (retval) { | |
1311 | DMSG("can't bind to transceiver\n"); | |
1312 | if (driver->unbind) | |
1313 | driver->unbind(&dev->gadget); | |
1314 | goto bind_fail; | |
1315 | } | |
1316 | } | |
1317 | ||
64cc2dd9 | 1318 | pullup(dev); |
1da177e4 LT |
1319 | dump_state(dev); |
1320 | return 0; | |
ab26d20f PZ |
1321 | bind_fail: |
1322 | return retval; | |
1da177e4 | 1323 | } |
b0fca50f | 1324 | EXPORT_SYMBOL(usb_gadget_probe_driver); |
1da177e4 LT |
1325 | |
1326 | static void | |
7a857620 | 1327 | stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver) |
1da177e4 LT |
1328 | { |
1329 | int i; | |
1330 | ||
1331 | /* don't disconnect drivers more than once */ | |
1332 | if (dev->gadget.speed == USB_SPEED_UNKNOWN) | |
1333 | driver = NULL; | |
1334 | dev->gadget.speed = USB_SPEED_UNKNOWN; | |
1335 | ||
1336 | /* prevent new request submissions, kill any outstanding requests */ | |
1337 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { | |
7a857620 | 1338 | struct pxa25x_ep *ep = &dev->ep[i]; |
1da177e4 LT |
1339 | |
1340 | ep->stopped = 1; | |
1341 | nuke(ep, -ESHUTDOWN); | |
1342 | } | |
1343 | del_timer_sync(&dev->timer); | |
1344 | ||
1345 | /* report disconnect; the driver is already quiesced */ | |
1da177e4 LT |
1346 | if (driver) |
1347 | driver->disconnect(&dev->gadget); | |
1348 | ||
1349 | /* re-init driver-visible data structures */ | |
1350 | udc_reinit(dev); | |
1351 | } | |
1352 | ||
1353 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) | |
1354 | { | |
7a857620 | 1355 | struct pxa25x_udc *dev = the_controller; |
1da177e4 LT |
1356 | |
1357 | if (!dev) | |
1358 | return -ENODEV; | |
6bea476c | 1359 | if (!driver || driver != dev->driver || !driver->unbind) |
1da177e4 LT |
1360 | return -EINVAL; |
1361 | ||
1362 | local_irq_disable(); | |
64cc2dd9 DES |
1363 | dev->pullup = 0; |
1364 | pullup(dev); | |
1da177e4 LT |
1365 | stop_activity(dev, driver); |
1366 | local_irq_enable(); | |
1367 | ||
ab26d20f PZ |
1368 | if (dev->transceiver) |
1369 | (void) otg_set_peripheral(dev->transceiver, NULL); | |
1370 | ||
1da177e4 | 1371 | driver->unbind(&dev->gadget); |
eb0be47d | 1372 | dev->gadget.dev.driver = NULL; |
1da177e4 LT |
1373 | dev->driver = NULL; |
1374 | ||
1375 | device_del (&dev->gadget.dev); | |
1da177e4 LT |
1376 | |
1377 | DMSG("unregistered gadget driver '%s'\n", driver->driver.name); | |
1378 | dump_state(dev); | |
1379 | return 0; | |
1380 | } | |
1381 | EXPORT_SYMBOL(usb_gadget_unregister_driver); | |
1382 | ||
1383 | ||
1384 | /*-------------------------------------------------------------------------*/ | |
1385 | ||
1386 | #ifdef CONFIG_ARCH_LUBBOCK | |
1387 | ||
1388 | /* Lubbock has separate connect and disconnect irqs. More typical designs | |
1389 | * use one GPIO as the VBUS IRQ, and another to control the D+ pullup. | |
1390 | */ | |
1391 | ||
1392 | static irqreturn_t | |
7d12e780 | 1393 | lubbock_vbus_irq(int irq, void *_dev) |
1da177e4 | 1394 | { |
7a857620 | 1395 | struct pxa25x_udc *dev = _dev; |
1da177e4 LT |
1396 | int vbus; |
1397 | ||
1398 | dev->stats.irqs++; | |
1da177e4 LT |
1399 | switch (irq) { |
1400 | case LUBBOCK_USB_IRQ: | |
1da177e4 LT |
1401 | vbus = 1; |
1402 | disable_irq(LUBBOCK_USB_IRQ); | |
1403 | enable_irq(LUBBOCK_USB_DISC_IRQ); | |
1404 | break; | |
1405 | case LUBBOCK_USB_DISC_IRQ: | |
1da177e4 LT |
1406 | vbus = 0; |
1407 | disable_irq(LUBBOCK_USB_DISC_IRQ); | |
1408 | enable_irq(LUBBOCK_USB_IRQ); | |
1409 | break; | |
1410 | default: | |
1411 | return IRQ_NONE; | |
1412 | } | |
1413 | ||
7a857620 | 1414 | pxa25x_udc_vbus_session(&dev->gadget, vbus); |
1da177e4 LT |
1415 | return IRQ_HANDLED; |
1416 | } | |
1417 | ||
1418 | #endif | |
1419 | ||
1420 | ||
1421 | /*-------------------------------------------------------------------------*/ | |
1422 | ||
7a857620 | 1423 | static inline void clear_ep_state (struct pxa25x_udc *dev) |
1da177e4 LT |
1424 | { |
1425 | unsigned i; | |
1426 | ||
1427 | /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint | |
1428 | * fifos, and pending transactions mustn't be continued in any case. | |
1429 | */ | |
1430 | for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) | |
1431 | nuke(&dev->ep[i], -ECONNABORTED); | |
1432 | } | |
1433 | ||
1434 | static void udc_watchdog(unsigned long _dev) | |
1435 | { | |
7a857620 | 1436 | struct pxa25x_udc *dev = (void *)_dev; |
1da177e4 LT |
1437 | |
1438 | local_irq_disable(); | |
1439 | if (dev->ep0state == EP0_STALL | |
1440 | && (UDCCS0 & UDCCS0_FST) == 0 | |
1441 | && (UDCCS0 & UDCCS0_SST) == 0) { | |
1442 | UDCCS0 = UDCCS0_FST|UDCCS0_FTF; | |
1443 | DBG(DBG_VERBOSE, "ep0 re-stall\n"); | |
1444 | start_watchdog(dev); | |
1445 | } | |
1446 | local_irq_enable(); | |
1447 | } | |
1448 | ||
7a857620 | 1449 | static void handle_ep0 (struct pxa25x_udc *dev) |
1da177e4 LT |
1450 | { |
1451 | u32 udccs0 = UDCCS0; | |
7a857620 PZ |
1452 | struct pxa25x_ep *ep = &dev->ep [0]; |
1453 | struct pxa25x_request *req; | |
1da177e4 LT |
1454 | union { |
1455 | struct usb_ctrlrequest r; | |
1456 | u8 raw [8]; | |
1457 | u32 word [2]; | |
1458 | } u; | |
1459 | ||
1460 | if (list_empty(&ep->queue)) | |
1461 | req = NULL; | |
1462 | else | |
7a857620 | 1463 | req = list_entry(ep->queue.next, struct pxa25x_request, queue); |
1da177e4 LT |
1464 | |
1465 | /* clear stall status */ | |
1466 | if (udccs0 & UDCCS0_SST) { | |
1467 | nuke(ep, -EPIPE); | |
1468 | UDCCS0 = UDCCS0_SST; | |
1469 | del_timer(&dev->timer); | |
1470 | ep0_idle(dev); | |
1471 | } | |
1472 | ||
1473 | /* previous request unfinished? non-error iff back-to-back ... */ | |
1474 | if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { | |
1475 | nuke(ep, 0); | |
1476 | del_timer(&dev->timer); | |
1477 | ep0_idle(dev); | |
1478 | } | |
1479 | ||
1480 | switch (dev->ep0state) { | |
1481 | case EP0_IDLE: | |
1482 | /* late-breaking status? */ | |
1483 | udccs0 = UDCCS0; | |
1484 | ||
1485 | /* start control request? */ | |
1486 | if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE)) | |
1487 | == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) { | |
1488 | int i; | |
1489 | ||
1490 | nuke (ep, -EPROTO); | |
1491 | ||
1492 | /* read SETUP packet */ | |
1493 | for (i = 0; i < 8; i++) { | |
1494 | if (unlikely(!(UDCCS0 & UDCCS0_RNE))) { | |
1495 | bad_setup: | |
1496 | DMSG("SETUP %d!\n", i); | |
1497 | goto stall; | |
1498 | } | |
1499 | u.raw [i] = (u8) UDDR0; | |
1500 | } | |
1501 | if (unlikely((UDCCS0 & UDCCS0_RNE) != 0)) | |
1502 | goto bad_setup; | |
1503 | ||
1504 | got_setup: | |
1505 | DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n", | |
1506 | u.r.bRequestType, u.r.bRequest, | |
1507 | le16_to_cpu(u.r.wValue), | |
1508 | le16_to_cpu(u.r.wIndex), | |
1509 | le16_to_cpu(u.r.wLength)); | |
1510 | ||
1511 | /* cope with automagic for some standard requests. */ | |
1512 | dev->req_std = (u.r.bRequestType & USB_TYPE_MASK) | |
1513 | == USB_TYPE_STANDARD; | |
1514 | dev->req_config = 0; | |
1515 | dev->req_pending = 1; | |
1516 | switch (u.r.bRequest) { | |
1517 | /* hardware restricts gadget drivers here! */ | |
1518 | case USB_REQ_SET_CONFIGURATION: | |
1519 | if (u.r.bRequestType == USB_RECIP_DEVICE) { | |
1520 | /* reflect hardware's automagic | |
1521 | * up to the gadget driver. | |
1522 | */ | |
1523 | config_change: | |
1524 | dev->req_config = 1; | |
1525 | clear_ep_state(dev); | |
1526 | /* if !has_cfr, there's no synch | |
1527 | * else use AREN (later) not SA|OPR | |
1528 | * USIR0_IR0 acts edge sensitive | |
1529 | */ | |
1530 | } | |
1531 | break; | |
1532 | /* ... and here, even more ... */ | |
1533 | case USB_REQ_SET_INTERFACE: | |
1534 | if (u.r.bRequestType == USB_RECIP_INTERFACE) { | |
1535 | /* udc hardware is broken by design: | |
1536 | * - altsetting may only be zero; | |
1537 | * - hw resets all interfaces' eps; | |
1538 | * - ep reset doesn't include halt(?). | |
1539 | */ | |
1540 | DMSG("broken set_interface (%d/%d)\n", | |
1541 | le16_to_cpu(u.r.wIndex), | |
1542 | le16_to_cpu(u.r.wValue)); | |
1543 | goto config_change; | |
1544 | } | |
1545 | break; | |
1546 | /* hardware was supposed to hide this */ | |
1547 | case USB_REQ_SET_ADDRESS: | |
1548 | if (u.r.bRequestType == USB_RECIP_DEVICE) { | |
1549 | ep0start(dev, 0, "address"); | |
1550 | return; | |
1551 | } | |
1552 | break; | |
1553 | } | |
1554 | ||
1555 | if (u.r.bRequestType & USB_DIR_IN) | |
1556 | dev->ep0state = EP0_IN_DATA_PHASE; | |
1557 | else | |
1558 | dev->ep0state = EP0_OUT_DATA_PHASE; | |
1559 | ||
1560 | i = dev->driver->setup(&dev->gadget, &u.r); | |
1561 | if (i < 0) { | |
1562 | /* hardware automagic preventing STALL... */ | |
1563 | if (dev->req_config) { | |
1564 | /* hardware sometimes neglects to tell | |
1565 | * tell us about config change events, | |
1566 | * so later ones may fail... | |
1567 | */ | |
b6c63937 | 1568 | WARNING("config change %02x fail %d?\n", |
1da177e4 LT |
1569 | u.r.bRequest, i); |
1570 | return; | |
1571 | /* TODO experiment: if has_cfr, | |
1572 | * hardware didn't ACK; maybe we | |
1573 | * could actually STALL! | |
1574 | */ | |
1575 | } | |
1576 | DBG(DBG_VERBOSE, "protocol STALL, " | |
1577 | "%02x err %d\n", UDCCS0, i); | |
1578 | stall: | |
1579 | /* the watchdog timer helps deal with cases | |
1580 | * where udc seems to clear FST wrongly, and | |
1581 | * then NAKs instead of STALLing. | |
1582 | */ | |
1583 | ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall"); | |
1584 | start_watchdog(dev); | |
1585 | dev->ep0state = EP0_STALL; | |
1586 | ||
1587 | /* deferred i/o == no response yet */ | |
1588 | } else if (dev->req_pending) { | |
1589 | if (likely(dev->ep0state == EP0_IN_DATA_PHASE | |
1590 | || dev->req_std || u.r.wLength)) | |
1591 | ep0start(dev, 0, "defer"); | |
1592 | else | |
1593 | ep0start(dev, UDCCS0_IPR, "defer/IPR"); | |
1594 | } | |
1595 | ||
1596 | /* expect at least one data or status stage irq */ | |
1597 | return; | |
1598 | ||
1599 | } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA)) | |
1600 | == (UDCCS0_OPR|UDCCS0_SA))) { | |
1601 | unsigned i; | |
1602 | ||
1603 | /* pxa210/250 erratum 131 for B0/B1 says RNE lies. | |
1604 | * still observed on a pxa255 a0. | |
1605 | */ | |
1606 | DBG(DBG_VERBOSE, "e131\n"); | |
1607 | nuke(ep, -EPROTO); | |
1608 | ||
1609 | /* read SETUP data, but don't trust it too much */ | |
1610 | for (i = 0; i < 8; i++) | |
1611 | u.raw [i] = (u8) UDDR0; | |
1612 | if ((u.r.bRequestType & USB_RECIP_MASK) | |
1613 | > USB_RECIP_OTHER) | |
1614 | goto stall; | |
1615 | if (u.word [0] == 0 && u.word [1] == 0) | |
1616 | goto stall; | |
1617 | goto got_setup; | |
1618 | } else { | |
1619 | /* some random early IRQ: | |
1620 | * - we acked FST | |
1621 | * - IPR cleared | |
1622 | * - OPR got set, without SA (likely status stage) | |
1623 | */ | |
1624 | UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR); | |
1625 | } | |
1626 | break; | |
1627 | case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */ | |
1628 | if (udccs0 & UDCCS0_OPR) { | |
1629 | UDCCS0 = UDCCS0_OPR|UDCCS0_FTF; | |
1630 | DBG(DBG_VERBOSE, "ep0in premature status\n"); | |
1631 | if (req) | |
1632 | done(ep, req, 0); | |
1633 | ep0_idle(dev); | |
1634 | } else /* irq was IPR clearing */ { | |
1635 | if (req) { | |
1636 | /* this IN packet might finish the request */ | |
1637 | (void) write_ep0_fifo(ep, req); | |
1638 | } /* else IN token before response was written */ | |
1639 | } | |
1640 | break; | |
1641 | case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */ | |
1642 | if (udccs0 & UDCCS0_OPR) { | |
1643 | if (req) { | |
1644 | /* this OUT packet might finish the request */ | |
1645 | if (read_ep0_fifo(ep, req)) | |
1646 | done(ep, req, 0); | |
1647 | /* else more OUT packets expected */ | |
1648 | } /* else OUT token before read was issued */ | |
1649 | } else /* irq was IPR clearing */ { | |
1650 | DBG(DBG_VERBOSE, "ep0out premature status\n"); | |
1651 | if (req) | |
1652 | done(ep, req, 0); | |
1653 | ep0_idle(dev); | |
1654 | } | |
1655 | break; | |
1656 | case EP0_END_XFER: | |
1657 | if (req) | |
1658 | done(ep, req, 0); | |
1659 | /* ack control-IN status (maybe in-zlp was skipped) | |
1660 | * also appears after some config change events. | |
1661 | */ | |
1662 | if (udccs0 & UDCCS0_OPR) | |
1663 | UDCCS0 = UDCCS0_OPR; | |
1664 | ep0_idle(dev); | |
1665 | break; | |
1666 | case EP0_STALL: | |
1667 | UDCCS0 = UDCCS0_FST; | |
1668 | break; | |
1669 | } | |
1670 | USIR0 = USIR0_IR0; | |
1671 | } | |
1672 | ||
7a857620 | 1673 | static void handle_ep(struct pxa25x_ep *ep) |
1da177e4 | 1674 | { |
7a857620 | 1675 | struct pxa25x_request *req; |
1da177e4 LT |
1676 | int is_in = ep->bEndpointAddress & USB_DIR_IN; |
1677 | int completed; | |
1678 | u32 udccs, tmp; | |
1679 | ||
1680 | do { | |
1681 | completed = 0; | |
1682 | if (likely (!list_empty(&ep->queue))) | |
1683 | req = list_entry(ep->queue.next, | |
7a857620 | 1684 | struct pxa25x_request, queue); |
1da177e4 LT |
1685 | else |
1686 | req = NULL; | |
1687 | ||
1688 | // TODO check FST handling | |
1689 | ||
1690 | udccs = *ep->reg_udccs; | |
1691 | if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */ | |
1692 | tmp = UDCCS_BI_TUR; | |
1693 | if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) | |
1694 | tmp |= UDCCS_BI_SST; | |
1695 | tmp &= udccs; | |
1696 | if (likely (tmp)) | |
1697 | *ep->reg_udccs = tmp; | |
1698 | if (req && likely ((udccs & UDCCS_BI_TFS) != 0)) | |
1699 | completed = write_fifo(ep, req); | |
1700 | ||
1701 | } else { /* irq from RPC (or for ISO, ROF) */ | |
1702 | if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) | |
1703 | tmp = UDCCS_BO_SST | UDCCS_BO_DME; | |
1704 | else | |
1705 | tmp = UDCCS_IO_ROF | UDCCS_IO_DME; | |
1706 | tmp &= udccs; | |
1707 | if (likely(tmp)) | |
1708 | *ep->reg_udccs = tmp; | |
1709 | ||
1710 | /* fifos can hold packets, ready for reading... */ | |
1711 | if (likely(req)) { | |
1da177e4 LT |
1712 | completed = read_fifo(ep, req); |
1713 | } else | |
1714 | pio_irq_disable (ep->bEndpointAddress); | |
1715 | } | |
1716 | ep->pio_irqs++; | |
1717 | } while (completed); | |
1718 | } | |
1719 | ||
1720 | /* | |
7a857620 | 1721 | * pxa25x_udc_irq - interrupt handler |
1da177e4 LT |
1722 | * |
1723 | * avoid delays in ep0 processing. the control handshaking isn't always | |
1724 | * under software control (pxa250c0 and the pxa255 are better), and delays | |
1725 | * could cause usb protocol errors. | |
1726 | */ | |
1727 | static irqreturn_t | |
7a857620 | 1728 | pxa25x_udc_irq(int irq, void *_dev) |
1da177e4 | 1729 | { |
7a857620 | 1730 | struct pxa25x_udc *dev = _dev; |
1da177e4 LT |
1731 | int handled; |
1732 | ||
1733 | dev->stats.irqs++; | |
1da177e4 LT |
1734 | do { |
1735 | u32 udccr = UDCCR; | |
1736 | ||
1737 | handled = 0; | |
1738 | ||
1739 | /* SUSpend Interrupt Request */ | |
1740 | if (unlikely(udccr & UDCCR_SUSIR)) { | |
1741 | udc_ack_int_UDCCR(UDCCR_SUSIR); | |
1742 | handled = 1; | |
a8ecc860 | 1743 | DBG(DBG_VERBOSE, "USB suspend\n"); |
1da177e4 | 1744 | |
a8ecc860 | 1745 | if (dev->gadget.speed != USB_SPEED_UNKNOWN |
1da177e4 LT |
1746 | && dev->driver |
1747 | && dev->driver->suspend) | |
1748 | dev->driver->suspend(&dev->gadget); | |
1749 | ep0_idle (dev); | |
1750 | } | |
1751 | ||
1752 | /* RESume Interrupt Request */ | |
1753 | if (unlikely(udccr & UDCCR_RESIR)) { | |
1754 | udc_ack_int_UDCCR(UDCCR_RESIR); | |
1755 | handled = 1; | |
1756 | DBG(DBG_VERBOSE, "USB resume\n"); | |
1757 | ||
1758 | if (dev->gadget.speed != USB_SPEED_UNKNOWN | |
1759 | && dev->driver | |
a8ecc860 | 1760 | && dev->driver->resume) |
1da177e4 LT |
1761 | dev->driver->resume(&dev->gadget); |
1762 | } | |
1763 | ||
1764 | /* ReSeT Interrupt Request - USB reset */ | |
1765 | if (unlikely(udccr & UDCCR_RSTIR)) { | |
1766 | udc_ack_int_UDCCR(UDCCR_RSTIR); | |
1767 | handled = 1; | |
1768 | ||
1769 | if ((UDCCR & UDCCR_UDA) == 0) { | |
1770 | DBG(DBG_VERBOSE, "USB reset start\n"); | |
1771 | ||
1772 | /* reset driver and endpoints, | |
1773 | * in case that's not yet done | |
1774 | */ | |
1775 | stop_activity (dev, dev->driver); | |
1776 | ||
1777 | } else { | |
1778 | DBG(DBG_VERBOSE, "USB reset end\n"); | |
1779 | dev->gadget.speed = USB_SPEED_FULL; | |
1da177e4 LT |
1780 | memset(&dev->stats, 0, sizeof dev->stats); |
1781 | /* driver and endpoints are still reset */ | |
1782 | } | |
1783 | ||
1784 | } else { | |
1785 | u32 usir0 = USIR0 & ~UICR0; | |
1786 | u32 usir1 = USIR1 & ~UICR1; | |
1787 | int i; | |
1788 | ||
1789 | if (unlikely (!usir0 && !usir1)) | |
1790 | continue; | |
1791 | ||
1792 | DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0); | |
1793 | ||
1794 | /* control traffic */ | |
1795 | if (usir0 & USIR0_IR0) { | |
1796 | dev->ep[0].pio_irqs++; | |
1797 | handle_ep0(dev); | |
1798 | handled = 1; | |
1799 | } | |
1800 | ||
1801 | /* endpoint data transfers */ | |
1802 | for (i = 0; i < 8; i++) { | |
1803 | u32 tmp = 1 << i; | |
1804 | ||
1805 | if (i && (usir0 & tmp)) { | |
1806 | handle_ep(&dev->ep[i]); | |
1807 | USIR0 |= tmp; | |
1808 | handled = 1; | |
1809 | } | |
6d84599b | 1810 | #ifndef CONFIG_USB_PXA25X_SMALL |
1da177e4 LT |
1811 | if (usir1 & tmp) { |
1812 | handle_ep(&dev->ep[i+8]); | |
1813 | USIR1 |= tmp; | |
1814 | handled = 1; | |
1815 | } | |
6d84599b | 1816 | #endif |
1da177e4 LT |
1817 | } |
1818 | } | |
1819 | ||
1820 | /* we could also ask for 1 msec SOF (SIR) interrupts */ | |
1821 | ||
1822 | } while (handled); | |
1823 | return IRQ_HANDLED; | |
1824 | } | |
1825 | ||
1826 | /*-------------------------------------------------------------------------*/ | |
1827 | ||
1828 | static void nop_release (struct device *dev) | |
1829 | { | |
7071a3ce | 1830 | DMSG("%s %s\n", __func__, dev_name(dev)); |
1da177e4 LT |
1831 | } |
1832 | ||
1833 | /* this uses load-time allocation and initialization (instead of | |
1834 | * doing it at run-time) to save code, eliminate fault paths, and | |
1835 | * be more obviously correct. | |
1836 | */ | |
7a857620 | 1837 | static struct pxa25x_udc memory = { |
1da177e4 | 1838 | .gadget = { |
7a857620 | 1839 | .ops = &pxa25x_udc_ops, |
1da177e4 LT |
1840 | .ep0 = &memory.ep[0].ep, |
1841 | .name = driver_name, | |
1842 | .dev = { | |
c682b170 | 1843 | .init_name = "gadget", |
1da177e4 LT |
1844 | .release = nop_release, |
1845 | }, | |
1846 | }, | |
1847 | ||
1848 | /* control endpoint */ | |
1849 | .ep[0] = { | |
1850 | .ep = { | |
1851 | .name = ep0name, | |
7a857620 | 1852 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
1853 | .maxpacket = EP0_FIFO_SIZE, |
1854 | }, | |
1855 | .dev = &memory, | |
1856 | .reg_udccs = &UDCCS0, | |
1857 | .reg_uddr = &UDDR0, | |
1858 | }, | |
1859 | ||
1860 | /* first group of endpoints */ | |
1861 | .ep[1] = { | |
1862 | .ep = { | |
1863 | .name = "ep1in-bulk", | |
7a857620 | 1864 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
1865 | .maxpacket = BULK_FIFO_SIZE, |
1866 | }, | |
1867 | .dev = &memory, | |
1868 | .fifo_size = BULK_FIFO_SIZE, | |
1869 | .bEndpointAddress = USB_DIR_IN | 1, | |
1870 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
1871 | .reg_udccs = &UDCCS1, | |
1872 | .reg_uddr = &UDDR1, | |
1da177e4 LT |
1873 | }, |
1874 | .ep[2] = { | |
1875 | .ep = { | |
1876 | .name = "ep2out-bulk", | |
7a857620 | 1877 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
1878 | .maxpacket = BULK_FIFO_SIZE, |
1879 | }, | |
1880 | .dev = &memory, | |
1881 | .fifo_size = BULK_FIFO_SIZE, | |
1882 | .bEndpointAddress = 2, | |
1883 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
1884 | .reg_udccs = &UDCCS2, | |
1885 | .reg_ubcr = &UBCR2, | |
1886 | .reg_uddr = &UDDR2, | |
1da177e4 | 1887 | }, |
7a857620 | 1888 | #ifndef CONFIG_USB_PXA25X_SMALL |
1da177e4 LT |
1889 | .ep[3] = { |
1890 | .ep = { | |
1891 | .name = "ep3in-iso", | |
7a857620 | 1892 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
1893 | .maxpacket = ISO_FIFO_SIZE, |
1894 | }, | |
1895 | .dev = &memory, | |
1896 | .fifo_size = ISO_FIFO_SIZE, | |
1897 | .bEndpointAddress = USB_DIR_IN | 3, | |
1898 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, | |
1899 | .reg_udccs = &UDCCS3, | |
1900 | .reg_uddr = &UDDR3, | |
1da177e4 LT |
1901 | }, |
1902 | .ep[4] = { | |
1903 | .ep = { | |
1904 | .name = "ep4out-iso", | |
7a857620 | 1905 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
1906 | .maxpacket = ISO_FIFO_SIZE, |
1907 | }, | |
1908 | .dev = &memory, | |
1909 | .fifo_size = ISO_FIFO_SIZE, | |
1910 | .bEndpointAddress = 4, | |
1911 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, | |
1912 | .reg_udccs = &UDCCS4, | |
1913 | .reg_ubcr = &UBCR4, | |
1914 | .reg_uddr = &UDDR4, | |
1da177e4 LT |
1915 | }, |
1916 | .ep[5] = { | |
1917 | .ep = { | |
1918 | .name = "ep5in-int", | |
7a857620 | 1919 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
1920 | .maxpacket = INT_FIFO_SIZE, |
1921 | }, | |
1922 | .dev = &memory, | |
1923 | .fifo_size = INT_FIFO_SIZE, | |
1924 | .bEndpointAddress = USB_DIR_IN | 5, | |
1925 | .bmAttributes = USB_ENDPOINT_XFER_INT, | |
1926 | .reg_udccs = &UDCCS5, | |
1927 | .reg_uddr = &UDDR5, | |
1928 | }, | |
1929 | ||
1930 | /* second group of endpoints */ | |
1931 | .ep[6] = { | |
1932 | .ep = { | |
1933 | .name = "ep6in-bulk", | |
7a857620 | 1934 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
1935 | .maxpacket = BULK_FIFO_SIZE, |
1936 | }, | |
1937 | .dev = &memory, | |
1938 | .fifo_size = BULK_FIFO_SIZE, | |
1939 | .bEndpointAddress = USB_DIR_IN | 6, | |
1940 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
1941 | .reg_udccs = &UDCCS6, | |
1942 | .reg_uddr = &UDDR6, | |
1da177e4 LT |
1943 | }, |
1944 | .ep[7] = { | |
1945 | .ep = { | |
1946 | .name = "ep7out-bulk", | |
7a857620 | 1947 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
1948 | .maxpacket = BULK_FIFO_SIZE, |
1949 | }, | |
1950 | .dev = &memory, | |
1951 | .fifo_size = BULK_FIFO_SIZE, | |
1952 | .bEndpointAddress = 7, | |
1953 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
1954 | .reg_udccs = &UDCCS7, | |
1955 | .reg_ubcr = &UBCR7, | |
1956 | .reg_uddr = &UDDR7, | |
1da177e4 LT |
1957 | }, |
1958 | .ep[8] = { | |
1959 | .ep = { | |
1960 | .name = "ep8in-iso", | |
7a857620 | 1961 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
1962 | .maxpacket = ISO_FIFO_SIZE, |
1963 | }, | |
1964 | .dev = &memory, | |
1965 | .fifo_size = ISO_FIFO_SIZE, | |
1966 | .bEndpointAddress = USB_DIR_IN | 8, | |
1967 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, | |
1968 | .reg_udccs = &UDCCS8, | |
1969 | .reg_uddr = &UDDR8, | |
1da177e4 LT |
1970 | }, |
1971 | .ep[9] = { | |
1972 | .ep = { | |
1973 | .name = "ep9out-iso", | |
7a857620 | 1974 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
1975 | .maxpacket = ISO_FIFO_SIZE, |
1976 | }, | |
1977 | .dev = &memory, | |
1978 | .fifo_size = ISO_FIFO_SIZE, | |
1979 | .bEndpointAddress = 9, | |
1980 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, | |
1981 | .reg_udccs = &UDCCS9, | |
1982 | .reg_ubcr = &UBCR9, | |
1983 | .reg_uddr = &UDDR9, | |
1da177e4 LT |
1984 | }, |
1985 | .ep[10] = { | |
1986 | .ep = { | |
1987 | .name = "ep10in-int", | |
7a857620 | 1988 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
1989 | .maxpacket = INT_FIFO_SIZE, |
1990 | }, | |
1991 | .dev = &memory, | |
1992 | .fifo_size = INT_FIFO_SIZE, | |
1993 | .bEndpointAddress = USB_DIR_IN | 10, | |
1994 | .bmAttributes = USB_ENDPOINT_XFER_INT, | |
1995 | .reg_udccs = &UDCCS10, | |
1996 | .reg_uddr = &UDDR10, | |
1997 | }, | |
1998 | ||
1999 | /* third group of endpoints */ | |
2000 | .ep[11] = { | |
2001 | .ep = { | |
2002 | .name = "ep11in-bulk", | |
7a857620 | 2003 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
2004 | .maxpacket = BULK_FIFO_SIZE, |
2005 | }, | |
2006 | .dev = &memory, | |
2007 | .fifo_size = BULK_FIFO_SIZE, | |
2008 | .bEndpointAddress = USB_DIR_IN | 11, | |
2009 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
2010 | .reg_udccs = &UDCCS11, | |
2011 | .reg_uddr = &UDDR11, | |
1da177e4 LT |
2012 | }, |
2013 | .ep[12] = { | |
2014 | .ep = { | |
2015 | .name = "ep12out-bulk", | |
7a857620 | 2016 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
2017 | .maxpacket = BULK_FIFO_SIZE, |
2018 | }, | |
2019 | .dev = &memory, | |
2020 | .fifo_size = BULK_FIFO_SIZE, | |
2021 | .bEndpointAddress = 12, | |
2022 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
2023 | .reg_udccs = &UDCCS12, | |
2024 | .reg_ubcr = &UBCR12, | |
2025 | .reg_uddr = &UDDR12, | |
1da177e4 LT |
2026 | }, |
2027 | .ep[13] = { | |
2028 | .ep = { | |
2029 | .name = "ep13in-iso", | |
7a857620 | 2030 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
2031 | .maxpacket = ISO_FIFO_SIZE, |
2032 | }, | |
2033 | .dev = &memory, | |
2034 | .fifo_size = ISO_FIFO_SIZE, | |
2035 | .bEndpointAddress = USB_DIR_IN | 13, | |
2036 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, | |
2037 | .reg_udccs = &UDCCS13, | |
2038 | .reg_uddr = &UDDR13, | |
1da177e4 LT |
2039 | }, |
2040 | .ep[14] = { | |
2041 | .ep = { | |
2042 | .name = "ep14out-iso", | |
7a857620 | 2043 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
2044 | .maxpacket = ISO_FIFO_SIZE, |
2045 | }, | |
2046 | .dev = &memory, | |
2047 | .fifo_size = ISO_FIFO_SIZE, | |
2048 | .bEndpointAddress = 14, | |
2049 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, | |
2050 | .reg_udccs = &UDCCS14, | |
2051 | .reg_ubcr = &UBCR14, | |
2052 | .reg_uddr = &UDDR14, | |
1da177e4 LT |
2053 | }, |
2054 | .ep[15] = { | |
2055 | .ep = { | |
2056 | .name = "ep15in-int", | |
7a857620 | 2057 | .ops = &pxa25x_ep_ops, |
1da177e4 LT |
2058 | .maxpacket = INT_FIFO_SIZE, |
2059 | }, | |
2060 | .dev = &memory, | |
2061 | .fifo_size = INT_FIFO_SIZE, | |
2062 | .bEndpointAddress = USB_DIR_IN | 15, | |
2063 | .bmAttributes = USB_ENDPOINT_XFER_INT, | |
2064 | .reg_udccs = &UDCCS15, | |
2065 | .reg_uddr = &UDDR15, | |
2066 | }, | |
7a857620 | 2067 | #endif /* !CONFIG_USB_PXA25X_SMALL */ |
1da177e4 LT |
2068 | }; |
2069 | ||
2070 | #define CP15R0_VENDOR_MASK 0xffffe000 | |
2071 | ||
2072 | #if defined(CONFIG_ARCH_PXA) | |
2073 | #define CP15R0_XSCALE_VALUE 0x69052000 /* intel/arm/xscale */ | |
2074 | ||
2075 | #elif defined(CONFIG_ARCH_IXP4XX) | |
2076 | #define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/ixp4xx */ | |
2077 | ||
2078 | #endif | |
2079 | ||
2080 | #define CP15R0_PROD_MASK 0x000003f0 | |
2081 | #define PXA25x 0x00000100 /* and PXA26x */ | |
2082 | #define PXA210 0x00000120 | |
2083 | ||
2084 | #define CP15R0_REV_MASK 0x0000000f | |
2085 | ||
2086 | #define CP15R0_PRODREV_MASK (CP15R0_PROD_MASK | CP15R0_REV_MASK) | |
2087 | ||
2088 | #define PXA255_A0 0x00000106 /* or PXA260_B1 */ | |
2089 | #define PXA250_C0 0x00000105 /* or PXA26x_B0 */ | |
2090 | #define PXA250_B2 0x00000104 | |
2091 | #define PXA250_B1 0x00000103 /* or PXA260_A0 */ | |
2092 | #define PXA250_B0 0x00000102 | |
2093 | #define PXA250_A1 0x00000101 | |
2094 | #define PXA250_A0 0x00000100 | |
2095 | ||
2096 | #define PXA210_C0 0x00000125 | |
2097 | #define PXA210_B2 0x00000124 | |
2098 | #define PXA210_B1 0x00000123 | |
2099 | #define PXA210_B0 0x00000122 | |
2100 | #define IXP425_A0 0x000001c1 | |
827982c5 | 2101 | #define IXP425_B0 0x000001f1 |
043ea18b | 2102 | #define IXP465_AD 0x00000200 |
1da177e4 LT |
2103 | |
2104 | /* | |
34ebcd28 | 2105 | * probe - binds to the platform device |
1da177e4 | 2106 | */ |
7a857620 | 2107 | static int __init pxa25x_udc_probe(struct platform_device *pdev) |
1da177e4 | 2108 | { |
7a857620 | 2109 | struct pxa25x_udc *dev = &memory; |
a8ecc860 | 2110 | int retval, irq; |
1da177e4 LT |
2111 | u32 chiprev; |
2112 | ||
2113 | /* insist on Intel/ARM/XScale */ | |
2114 | asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev)); | |
2115 | if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) { | |
00274921 | 2116 | pr_err("%s: not XScale!\n", driver_name); |
1da177e4 LT |
2117 | return -ENODEV; |
2118 | } | |
2119 | ||
2120 | /* trigger chiprev-specific logic */ | |
2121 | switch (chiprev & CP15R0_PRODREV_MASK) { | |
2122 | #if defined(CONFIG_ARCH_PXA) | |
2123 | case PXA255_A0: | |
2124 | dev->has_cfr = 1; | |
2125 | break; | |
2126 | case PXA250_A0: | |
2127 | case PXA250_A1: | |
2128 | /* A0/A1 "not released"; ep 13, 15 unusable */ | |
2129 | /* fall through */ | |
2130 | case PXA250_B2: case PXA210_B2: | |
2131 | case PXA250_B1: case PXA210_B1: | |
2132 | case PXA250_B0: case PXA210_B0: | |
ad8c623f | 2133 | /* OUT-DMA is broken ... */ |
1da177e4 LT |
2134 | /* fall through */ |
2135 | case PXA250_C0: case PXA210_C0: | |
2136 | break; | |
2137 | #elif defined(CONFIG_ARCH_IXP4XX) | |
2138 | case IXP425_A0: | |
827982c5 | 2139 | case IXP425_B0: |
043ea18b MS |
2140 | case IXP465_AD: |
2141 | dev->has_cfr = 1; | |
1da177e4 LT |
2142 | break; |
2143 | #endif | |
2144 | default: | |
00274921 | 2145 | pr_err("%s: unrecognized processor: %08x\n", |
1da177e4 LT |
2146 | driver_name, chiprev); |
2147 | /* iop3xx, ixp4xx, ... */ | |
2148 | return -ENODEV; | |
2149 | } | |
2150 | ||
34ebcd28 DB |
2151 | irq = platform_get_irq(pdev, 0); |
2152 | if (irq < 0) | |
2153 | return -ENODEV; | |
2154 | ||
e0d8b13a | 2155 | dev->clk = clk_get(&pdev->dev, NULL); |
6549e6c9 RK |
2156 | if (IS_ERR(dev->clk)) { |
2157 | retval = PTR_ERR(dev->clk); | |
2158 | goto err_clk; | |
2159 | } | |
6549e6c9 | 2160 | |
ad8c623f | 2161 | pr_debug("%s: IRQ %d%s%s\n", driver_name, irq, |
1da177e4 | 2162 | dev->has_cfr ? "" : " (!cfr)", |
ad8c623f | 2163 | SIZE_STR "(pio)" |
1da177e4 LT |
2164 | ); |
2165 | ||
1da177e4 | 2166 | /* other non-static parts of init */ |
3ae5eaec RK |
2167 | dev->dev = &pdev->dev; |
2168 | dev->mach = pdev->dev.platform_data; | |
9068a4c6 | 2169 | |
ab26d20f PZ |
2170 | dev->transceiver = otg_get_transceiver(); |
2171 | ||
56a075dc | 2172 | if (gpio_is_valid(dev->mach->gpio_pullup)) { |
9068a4c6 | 2173 | if ((retval = gpio_request(dev->mach->gpio_pullup, |
7a857620 | 2174 | "pca25x_udc GPIO PULLUP"))) { |
9068a4c6 MS |
2175 | dev_dbg(&pdev->dev, |
2176 | "can't get pullup gpio %d, err: %d\n", | |
2177 | dev->mach->gpio_pullup, retval); | |
6549e6c9 | 2178 | goto err_gpio_pullup; |
9068a4c6 MS |
2179 | } |
2180 | gpio_direction_output(dev->mach->gpio_pullup, 0); | |
2181 | } | |
1da177e4 LT |
2182 | |
2183 | init_timer(&dev->timer); | |
2184 | dev->timer.function = udc_watchdog; | |
2185 | dev->timer.data = (unsigned long) dev; | |
2186 | ||
2187 | device_initialize(&dev->gadget.dev); | |
3ae5eaec RK |
2188 | dev->gadget.dev.parent = &pdev->dev; |
2189 | dev->gadget.dev.dma_mask = pdev->dev.dma_mask; | |
1da177e4 LT |
2190 | |
2191 | the_controller = dev; | |
3ae5eaec | 2192 | platform_set_drvdata(pdev, dev); |
1da177e4 LT |
2193 | |
2194 | udc_disable(dev); | |
2195 | udc_reinit(dev); | |
2196 | ||
a8ecc860 | 2197 | dev->vbus = 0; |
1da177e4 LT |
2198 | |
2199 | /* irq setup after old hardware state is cleaned up */ | |
7a857620 | 2200 | retval = request_irq(irq, pxa25x_udc_irq, |
d54b5caa | 2201 | IRQF_DISABLED, driver_name, dev); |
1da177e4 | 2202 | if (retval != 0) { |
00274921 | 2203 | pr_err("%s: can't get irq %d, err %d\n", |
34ebcd28 | 2204 | driver_name, irq, retval); |
6549e6c9 | 2205 | goto err_irq1; |
1da177e4 LT |
2206 | } |
2207 | dev->got_irq = 1; | |
2208 | ||
2209 | #ifdef CONFIG_ARCH_LUBBOCK | |
2210 | if (machine_is_lubbock()) { | |
2211 | retval = request_irq(LUBBOCK_USB_DISC_IRQ, | |
2212 | lubbock_vbus_irq, | |
d54b5caa | 2213 | IRQF_DISABLED | IRQF_SAMPLE_RANDOM, |
1da177e4 LT |
2214 | driver_name, dev); |
2215 | if (retval != 0) { | |
00274921 | 2216 | pr_err("%s: can't get irq %i, err %d\n", |
1da177e4 LT |
2217 | driver_name, LUBBOCK_USB_DISC_IRQ, retval); |
2218 | lubbock_fail0: | |
6549e6c9 | 2219 | goto err_irq_lub; |
1da177e4 LT |
2220 | } |
2221 | retval = request_irq(LUBBOCK_USB_IRQ, | |
2222 | lubbock_vbus_irq, | |
d54b5caa | 2223 | IRQF_DISABLED | IRQF_SAMPLE_RANDOM, |
1da177e4 LT |
2224 | driver_name, dev); |
2225 | if (retval != 0) { | |
00274921 | 2226 | pr_err("%s: can't get irq %i, err %d\n", |
1da177e4 LT |
2227 | driver_name, LUBBOCK_USB_IRQ, retval); |
2228 | free_irq(LUBBOCK_USB_DISC_IRQ, dev); | |
2229 | goto lubbock_fail0; | |
2230 | } | |
b2bbb20b | 2231 | } else |
1da177e4 | 2232 | #endif |
040fa1b9 | 2233 | create_debug_files(dev); |
1da177e4 LT |
2234 | |
2235 | return 0; | |
6549e6c9 | 2236 | |
6549e6c9 RK |
2237 | #ifdef CONFIG_ARCH_LUBBOCK |
2238 | free_irq(LUBBOCK_USB_DISC_IRQ, dev); | |
2239 | err_irq_lub: | |
2240 | #endif | |
2241 | free_irq(irq, dev); | |
2242 | err_irq1: | |
56a075dc | 2243 | if (gpio_is_valid(dev->mach->gpio_pullup)) |
6549e6c9 RK |
2244 | gpio_free(dev->mach->gpio_pullup); |
2245 | err_gpio_pullup: | |
ab26d20f PZ |
2246 | if (dev->transceiver) { |
2247 | otg_put_transceiver(dev->transceiver); | |
2248 | dev->transceiver = NULL; | |
2249 | } | |
6549e6c9 RK |
2250 | clk_put(dev->clk); |
2251 | err_clk: | |
6549e6c9 | 2252 | return retval; |
1da177e4 | 2253 | } |
91987693 | 2254 | |
7a857620 | 2255 | static void pxa25x_udc_shutdown(struct platform_device *_dev) |
91987693 DB |
2256 | { |
2257 | pullup_off(); | |
2258 | } | |
2259 | ||
7a857620 | 2260 | static int __exit pxa25x_udc_remove(struct platform_device *pdev) |
1da177e4 | 2261 | { |
7a857620 | 2262 | struct pxa25x_udc *dev = platform_get_drvdata(pdev); |
1da177e4 | 2263 | |
6bea476c DB |
2264 | if (dev->driver) |
2265 | return -EBUSY; | |
2266 | ||
64cc2dd9 DES |
2267 | dev->pullup = 0; |
2268 | pullup(dev); | |
2269 | ||
040fa1b9 | 2270 | remove_debug_files(dev); |
1da177e4 LT |
2271 | |
2272 | if (dev->got_irq) { | |
34ebcd28 | 2273 | free_irq(platform_get_irq(pdev, 0), dev); |
1da177e4 LT |
2274 | dev->got_irq = 0; |
2275 | } | |
44df45a0 | 2276 | #ifdef CONFIG_ARCH_LUBBOCK |
1da177e4 LT |
2277 | if (machine_is_lubbock()) { |
2278 | free_irq(LUBBOCK_USB_DISC_IRQ, dev); | |
2279 | free_irq(LUBBOCK_USB_IRQ, dev); | |
2280 | } | |
44df45a0 | 2281 | #endif |
56a075dc | 2282 | if (gpio_is_valid(dev->mach->gpio_pullup)) |
9068a4c6 MS |
2283 | gpio_free(dev->mach->gpio_pullup); |
2284 | ||
6549e6c9 | 2285 | clk_put(dev->clk); |
6549e6c9 | 2286 | |
ab26d20f PZ |
2287 | if (dev->transceiver) { |
2288 | otg_put_transceiver(dev->transceiver); | |
2289 | dev->transceiver = NULL; | |
2290 | } | |
2291 | ||
3ae5eaec | 2292 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
2293 | the_controller = NULL; |
2294 | return 0; | |
2295 | } | |
2296 | ||
2297 | /*-------------------------------------------------------------------------*/ | |
2298 | ||
2299 | #ifdef CONFIG_PM | |
2300 | ||
2301 | /* USB suspend (controlled by the host) and system suspend (controlled | |
2302 | * by the PXA) don't necessarily work well together. If USB is active, | |
2303 | * the 48 MHz clock is required; so the system can't enter 33 MHz idle | |
2304 | * mode, or any deeper PM saving state. | |
2305 | * | |
2306 | * For now, we punt and forcibly disconnect from the USB host when PXA | |
2307 | * enters any suspend state. While we're disconnected, we always disable | |
34ebcd28 | 2308 | * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states. |
1da177e4 LT |
2309 | * Boards without software pullup control shouldn't use those states. |
2310 | * VBUS IRQs should probably be ignored so that the PXA device just acts | |
2311 | * "dead" to USB hosts until system resume. | |
2312 | */ | |
7a857620 | 2313 | static int pxa25x_udc_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 2314 | { |
7a857620 | 2315 | struct pxa25x_udc *udc = platform_get_drvdata(dev); |
64cc2dd9 | 2316 | unsigned long flags; |
1da177e4 | 2317 | |
56a075dc | 2318 | if (!gpio_is_valid(udc->mach->gpio_pullup) && !udc->mach->udc_command) |
b6c63937 | 2319 | WARNING("USB host won't detect disconnect!\n"); |
64cc2dd9 DES |
2320 | udc->suspended = 1; |
2321 | ||
2322 | local_irq_save(flags); | |
2323 | pullup(udc); | |
2324 | local_irq_restore(flags); | |
9480e307 | 2325 | |
1da177e4 LT |
2326 | return 0; |
2327 | } | |
2328 | ||
7a857620 | 2329 | static int pxa25x_udc_resume(struct platform_device *dev) |
1da177e4 | 2330 | { |
7a857620 | 2331 | struct pxa25x_udc *udc = platform_get_drvdata(dev); |
64cc2dd9 | 2332 | unsigned long flags; |
1da177e4 | 2333 | |
64cc2dd9 DES |
2334 | udc->suspended = 0; |
2335 | local_irq_save(flags); | |
2336 | pullup(udc); | |
2337 | local_irq_restore(flags); | |
9480e307 | 2338 | |
1da177e4 LT |
2339 | return 0; |
2340 | } | |
2341 | ||
2342 | #else | |
7a857620 PZ |
2343 | #define pxa25x_udc_suspend NULL |
2344 | #define pxa25x_udc_resume NULL | |
1da177e4 LT |
2345 | #endif |
2346 | ||
2347 | /*-------------------------------------------------------------------------*/ | |
2348 | ||
3ae5eaec | 2349 | static struct platform_driver udc_driver = { |
7a857620 PZ |
2350 | .shutdown = pxa25x_udc_shutdown, |
2351 | .remove = __exit_p(pxa25x_udc_remove), | |
2352 | .suspend = pxa25x_udc_suspend, | |
2353 | .resume = pxa25x_udc_resume, | |
3ae5eaec RK |
2354 | .driver = { |
2355 | .owner = THIS_MODULE, | |
7a857620 | 2356 | .name = "pxa25x-udc", |
3ae5eaec | 2357 | }, |
1da177e4 LT |
2358 | }; |
2359 | ||
2360 | static int __init udc_init(void) | |
2361 | { | |
00274921 | 2362 | pr_info("%s: version %s\n", driver_name, DRIVER_VERSION); |
7a857620 | 2363 | return platform_driver_probe(&udc_driver, pxa25x_udc_probe); |
1da177e4 LT |
2364 | } |
2365 | module_init(udc_init); | |
2366 | ||
2367 | static void __exit udc_exit(void) | |
2368 | { | |
3ae5eaec | 2369 | platform_driver_unregister(&udc_driver); |
1da177e4 LT |
2370 | } |
2371 | module_exit(udc_exit); | |
2372 | ||
2373 | MODULE_DESCRIPTION(DRIVER_DESC); | |
2374 | MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell"); | |
2375 | MODULE_LICENSE("GPL"); | |
7a857620 | 2376 | MODULE_ALIAS("platform:pxa25x-udc"); |