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usb: gadget: fusb300_udc: drop dead code
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / langwell_udc.c
CommitLineData
5be19a9d
XS		 1/*
2 * Intel Langwell USB Device Controller driver
3 * Copyright (C) 2008-2009, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20
21/* #undef DEBUG */
5f81f4b0 22/* #undef VERBOSE_DEBUG */
5be19a9d
XS		 23
24#if defined(CONFIG_USB_LANGWELL_OTG)
25#define OTG_TRANSCEIVER
26#endif
27
28
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/kernel.h>
33#include <linux/delay.h>
34#include <linux/ioport.h>
35#include <linux/sched.h>
36#include <linux/slab.h>
5be19a9d
XS		 37#include <linux/errno.h>
38#include <linux/init.h>
39#include <linux/timer.h>
40#include <linux/list.h>
41#include <linux/interrupt.h>
42#include <linux/moduleparam.h>
43#include <linux/device.h>
44#include <linux/usb/ch9.h>
45#include <linux/usb/gadget.h>
46#include <linux/usb/otg.h>
47#include <linux/pm.h>
48#include <linux/io.h>
49#include <linux/irq.h>
50#include <asm/system.h>
51#include <asm/unaligned.h>
52
53#include "langwell_udc.h"
54
55
56#define DRIVER_DESC "Intel Langwell USB Device Controller driver"
57#define DRIVER_VERSION "16 May 2009"
58
59static const char driver_name[] = "langwell_udc";
60static const char driver_desc[] = DRIVER_DESC;
61
62
63/* controller device global variable */
64static struct langwell_udc *the_controller;
65
66/* for endpoint 0 operations */
67static const struct usb_endpoint_descriptor
68langwell_ep0_desc = {
69 .bLength = USB_DT_ENDPOINT_SIZE,
70 .bDescriptorType = USB_DT_ENDPOINT,
71 .bEndpointAddress = 0,
72 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
73 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
74};
75
76
77/*-------------------------------------------------------------------------*/
78/* debugging */
79
5f81f4b0 80#ifdef VERBOSE_DEBUG
5be19a9d
XS		 81static inline void print_all_registers(struct langwell_udc *dev)
82{
83 int i;
84
85 /* Capability Registers */
5f81f4b0
J		 86 dev_dbg(&dev->pdev->dev,
87 "Capability Registers (offset: 0x%04x, length: 0x%08x)\n",
88 CAP_REG_OFFSET, (u32)sizeof(struct langwell_cap_regs));
89 dev_dbg(&dev->pdev->dev, "caplength=0x%02x\n",
5be19a9d 90 readb(&dev->cap_regs->caplength));
5f81f4b0 91 dev_dbg(&dev->pdev->dev, "hciversion=0x%04x\n",
5be19a9d 92 readw(&dev->cap_regs->hciversion));
5f81f4b0 93 dev_dbg(&dev->pdev->dev, "hcsparams=0x%08x\n",
5be19a9d 94 readl(&dev->cap_regs->hcsparams));
5f81f4b0 95 dev_dbg(&dev->pdev->dev, "hccparams=0x%08x\n",
5be19a9d 96 readl(&dev->cap_regs->hccparams));
5f81f4b0 97 dev_dbg(&dev->pdev->dev, "dciversion=0x%04x\n",
5be19a9d 98 readw(&dev->cap_regs->dciversion));
5f81f4b0 99 dev_dbg(&dev->pdev->dev, "dccparams=0x%08x\n",
5be19a9d
XS		 100 readl(&dev->cap_regs->dccparams));
101
102 /* Operational Registers */
5f81f4b0
J		 103 dev_dbg(&dev->pdev->dev,
104 "Operational Registers (offset: 0x%04x, length: 0x%08x)\n",
105 OP_REG_OFFSET, (u32)sizeof(struct langwell_op_regs));
106 dev_dbg(&dev->pdev->dev, "extsts=0x%08x\n",
5be19a9d 107 readl(&dev->op_regs->extsts));
5f81f4b0 108 dev_dbg(&dev->pdev->dev, "extintr=0x%08x\n",
5be19a9d 109 readl(&dev->op_regs->extintr));
5f81f4b0 110 dev_dbg(&dev->pdev->dev, "usbcmd=0x%08x\n",
5be19a9d 111 readl(&dev->op_regs->usbcmd));
5f81f4b0 112 dev_dbg(&dev->pdev->dev, "usbsts=0x%08x\n",
5be19a9d 113 readl(&dev->op_regs->usbsts));
5f81f4b0 114 dev_dbg(&dev->pdev->dev, "usbintr=0x%08x\n",
5be19a9d 115 readl(&dev->op_regs->usbintr));
5f81f4b0 116 dev_dbg(&dev->pdev->dev, "frindex=0x%08x\n",
5be19a9d 117 readl(&dev->op_regs->frindex));
5f81f4b0 118 dev_dbg(&dev->pdev->dev, "ctrldssegment=0x%08x\n",
5be19a9d 119 readl(&dev->op_regs->ctrldssegment));
5f81f4b0 120 dev_dbg(&dev->pdev->dev, "deviceaddr=0x%08x\n",
5be19a9d 121 readl(&dev->op_regs->deviceaddr));
5f81f4b0 122 dev_dbg(&dev->pdev->dev, "endpointlistaddr=0x%08x\n",
5be19a9d 123 readl(&dev->op_regs->endpointlistaddr));
5f81f4b0 124 dev_dbg(&dev->pdev->dev, "ttctrl=0x%08x\n",
5be19a9d 125 readl(&dev->op_regs->ttctrl));
5f81f4b0 126 dev_dbg(&dev->pdev->dev, "burstsize=0x%08x\n",
5be19a9d 127 readl(&dev->op_regs->burstsize));
5f81f4b0 128 dev_dbg(&dev->pdev->dev, "txfilltuning=0x%08x\n",
5be19a9d 129 readl(&dev->op_regs->txfilltuning));
5f81f4b0 130 dev_dbg(&dev->pdev->dev, "txttfilltuning=0x%08x\n",
5be19a9d 131 readl(&dev->op_regs->txttfilltuning));
5f81f4b0 132 dev_dbg(&dev->pdev->dev, "ic_usb=0x%08x\n",
5be19a9d 133 readl(&dev->op_regs->ic_usb));
5f81f4b0 134 dev_dbg(&dev->pdev->dev, "ulpi_viewport=0x%08x\n",
5be19a9d 135 readl(&dev->op_regs->ulpi_viewport));
5f81f4b0 136 dev_dbg(&dev->pdev->dev, "configflag=0x%08x\n",
5be19a9d 137 readl(&dev->op_regs->configflag));
5f81f4b0 138 dev_dbg(&dev->pdev->dev, "portsc1=0x%08x\n",
5be19a9d 139 readl(&dev->op_regs->portsc1));
5f81f4b0 140 dev_dbg(&dev->pdev->dev, "devlc=0x%08x\n",
5be19a9d 141 readl(&dev->op_regs->devlc));
5f81f4b0 142 dev_dbg(&dev->pdev->dev, "otgsc=0x%08x\n",
5be19a9d 143 readl(&dev->op_regs->otgsc));
5f81f4b0 144 dev_dbg(&dev->pdev->dev, "usbmode=0x%08x\n",
5be19a9d 145 readl(&dev->op_regs->usbmode));
5f81f4b0 146 dev_dbg(&dev->pdev->dev, "endptnak=0x%08x\n",
5be19a9d 147 readl(&dev->op_regs->endptnak));
5f81f4b0 148 dev_dbg(&dev->pdev->dev, "endptnaken=0x%08x\n",
5be19a9d 149 readl(&dev->op_regs->endptnaken));
5f81f4b0 150 dev_dbg(&dev->pdev->dev, "endptsetupstat=0x%08x\n",
5be19a9d 151 readl(&dev->op_regs->endptsetupstat));
5f81f4b0 152 dev_dbg(&dev->pdev->dev, "endptprime=0x%08x\n",
5be19a9d 153 readl(&dev->op_regs->endptprime));
5f81f4b0 154 dev_dbg(&dev->pdev->dev, "endptflush=0x%08x\n",
5be19a9d 155 readl(&dev->op_regs->endptflush));
5f81f4b0 156 dev_dbg(&dev->pdev->dev, "endptstat=0x%08x\n",
5be19a9d 157 readl(&dev->op_regs->endptstat));
5f81f4b0 158 dev_dbg(&dev->pdev->dev, "endptcomplete=0x%08x\n",
5be19a9d
XS		 159 readl(&dev->op_regs->endptcomplete));
160
161 for (i = 0; i < dev->ep_max / 2; i++) {
5f81f4b0 162 dev_dbg(&dev->pdev->dev, "endptctrl[%d]=0x%08x\n",
5be19a9d
XS		 163 i, readl(&dev->op_regs->endptctrl[i]));
164 }
165}
5f81f4b0
J		 166#else
167
168#define print_all_registers(dev) do { } while (0)
169
170#endif /* VERBOSE_DEBUG */
5be19a9d
XS		 171
172
173/*-------------------------------------------------------------------------*/
174
5f81f4b0
J		 175#define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
176 USB_DIR_IN) : (usb_endpoint_dir_in((ep)->desc)))
5be19a9d 177
5f81f4b0 178#define DIR_STRING(ep) (is_in(ep) ? "in" : "out")
5be19a9d
XS		 179
180
5f81f4b0 181static char *type_string(const struct usb_endpoint_descriptor *desc)
5be19a9d 182{
5f81f4b0 183 switch (usb_endpoint_type(desc)) {
5be19a9d
XS		 184 case USB_ENDPOINT_XFER_BULK:
185 return "bulk";
186 case USB_ENDPOINT_XFER_ISOC:
187 return "iso";
188 case USB_ENDPOINT_XFER_INT:
189 return "int";
190 };
191
192 return "control";
193}
5be19a9d
XS		 194
195
196/* configure endpoint control registers */
197static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
198 unsigned char is_in, unsigned char ep_type)
199{
200 struct langwell_udc *dev;
201 u32 endptctrl;
202
203 dev = ep->dev;
5f81f4b0 204 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 205
206 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
207 if (is_in) { /* TX */
208 if (ep_num)
209 endptctrl |= EPCTRL_TXR;
210 endptctrl |= EPCTRL_TXE;
211 endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
212 } else { /* RX */
213 if (ep_num)
214 endptctrl |= EPCTRL_RXR;
215 endptctrl |= EPCTRL_RXE;
216 endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
217 }
218
219 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
220
5f81f4b0 221 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 222}
223
224
225/* reset ep0 dQH and endptctrl */
226static void ep0_reset(struct langwell_udc *dev)
227{
228 struct langwell_ep *ep;
229 int i;
230
5f81f4b0 231 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 232
233 /* ep0 in and out */
234 for (i = 0; i < 2; i++) {
235 ep = &dev->ep[i];
236 ep->dev = dev;
237
238 /* ep0 dQH */
239 ep->dqh = &dev->ep_dqh[i];
240
241 /* configure ep0 endpoint capabilities in dQH */
242 ep->dqh->dqh_ios = 1;
243 ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
244
3eed298f 245 /* enable ep0-in HW zero length termination select */
5be19a9d
XS		 246 if (is_in(ep))
247 ep->dqh->dqh_zlt = 0;
248 ep->dqh->dqh_mult = 0;
249
3eed298f
J		 250 ep->dqh->dtd_next = DTD_TERM;
251
5be19a9d
XS		 252 /* configure ep0 control registers */
253 ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
254 }
255
5f81f4b0 256 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 257}
258
259
260/*-------------------------------------------------------------------------*/
261
262/* endpoints operations */
263
264/* configure endpoint, making it usable */
265static int langwell_ep_enable(struct usb_ep *_ep,
266 const struct usb_endpoint_descriptor *desc)
267{
268 struct langwell_udc *dev;
269 struct langwell_ep *ep;
270 u16 max = 0;
271 unsigned long flags;
3eed298f 272 int i, retval = 0;
5be19a9d
XS		 273 unsigned char zlt, ios = 0, mult = 0;
274
275 ep = container_of(_ep, struct langwell_ep, ep);
276 dev = ep->dev;
5f81f4b0 277 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 278
279 if (!_ep || !desc || ep->desc
280 || desc->bDescriptorType != USB_DT_ENDPOINT)
281 return -EINVAL;
282
283 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
284 return -ESHUTDOWN;
285
286 max = le16_to_cpu(desc->wMaxPacketSize);
287
288 /*
289 * disable HW zero length termination select
290 * driver handles zero length packet through req->req.zero
291 */
292 zlt = 1;
293
294 /*
295 * sanity check type, direction, address, and then
296 * initialize the endpoint capabilities fields in dQH
297 */
5f81f4b0 298 switch (usb_endpoint_type(desc)) {
5be19a9d
XS		 299 case USB_ENDPOINT_XFER_CONTROL:
300 ios = 1;
301 break;
302 case USB_ENDPOINT_XFER_BULK:
303 if ((dev->gadget.speed == USB_SPEED_HIGH
304 && max != 512)
305 || (dev->gadget.speed == USB_SPEED_FULL
306 && max > 64)) {
307 goto done;
308 }
309 break;
310 case USB_ENDPOINT_XFER_INT:
311 if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
312 goto done;
313
314 switch (dev->gadget.speed) {
315 case USB_SPEED_HIGH:
316 if (max <= 1024)
317 break;
318 case USB_SPEED_FULL:
319 if (max <= 64)
320 break;
321 default:
322 if (max <= 8)
323 break;
324 goto done;
325 }
326 break;
327 case USB_ENDPOINT_XFER_ISOC:
328 if (strstr(ep->ep.name, "-bulk")
329 || strstr(ep->ep.name, "-int"))
330 goto done;
331
332 switch (dev->gadget.speed) {
333 case USB_SPEED_HIGH:
334 if (max <= 1024)
335 break;
336 case USB_SPEED_FULL:
337 if (max <= 1023)
338 break;
339 default:
340 goto done;
341 }
342 /*
343 * FIXME:
344 * calculate transactions needed for high bandwidth iso
345 */
346 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
347 max = max & 0x8ff; /* bit 0~10 */
348 /* 3 transactions at most */
349 if (mult > 3)
350 goto done;
351 break;
352 default:
353 goto done;
354 }
355
356 spin_lock_irqsave(&dev->lock, flags);
357
5be19a9d
XS		 358 ep->ep.maxpacket = max;
359 ep->desc = desc;
360 ep->stopped = 0;
5f81f4b0 361 ep->ep_num = usb_endpoint_num(desc);
5be19a9d
XS		 362
363 /* ep_type */
5f81f4b0 364 ep->ep_type = usb_endpoint_type(desc);
5be19a9d
XS		 365
366 /* configure endpoint control registers */
367 ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
368
3eed298f
J		 369 /* configure endpoint capabilities in dQH */
370 i = ep->ep_num * 2 + is_in(ep);
371 ep->dqh = &dev->ep_dqh[i];
372 ep->dqh->dqh_ios = ios;
373 ep->dqh->dqh_mpl = cpu_to_le16(max);
374 ep->dqh->dqh_zlt = zlt;
375 ep->dqh->dqh_mult = mult;
376 ep->dqh->dtd_next = DTD_TERM;
377
5f81f4b0 378 dev_dbg(&dev->pdev->dev, "enabled %s (ep%d%s-%s), max %04x\n",
5be19a9d
XS		 379 _ep->name,
380 ep->ep_num,
5f81f4b0
J		 381 DIR_STRING(ep),
382 type_string(desc),
5be19a9d
XS		 383 max);
384
385 spin_unlock_irqrestore(&dev->lock, flags);
386done:
5f81f4b0 387 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 388 return retval;
389}
390
391
392/*-------------------------------------------------------------------------*/
393
394/* retire a request */
395static void done(struct langwell_ep *ep, struct langwell_request *req,
396 int status)
397{
398 struct langwell_udc *dev = ep->dev;
399 unsigned stopped = ep->stopped;
400 struct langwell_dtd *curr_dtd, *next_dtd;
401 int i;
402
5f81f4b0 403 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 404
405 /* remove the req from ep->queue */
406 list_del_init(&req->queue);
407
408 if (req->req.status == -EINPROGRESS)
409 req->req.status = status;
410 else
411 status = req->req.status;
412
413 /* free dTD for the request */
414 next_dtd = req->head;
415 for (i = 0; i < req->dtd_count; i++) {
416 curr_dtd = next_dtd;
417 if (i != req->dtd_count - 1)
418 next_dtd = curr_dtd->next_dtd_virt;
419 dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
420 }
421
422 if (req->mapped) {
5f81f4b0
J		 423 dma_unmap_single(&dev->pdev->dev,
424 req->req.dma, req->req.length,
5be19a9d
XS		 425 is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
426 req->req.dma = DMA_ADDR_INVALID;
427 req->mapped = 0;
428 } else
429 dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma,
430 req->req.length,
431 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
432
433 if (status != -ESHUTDOWN)
5f81f4b0
J		 434 dev_dbg(&dev->pdev->dev,
435 "complete %s, req %p, stat %d, len %u/%u\n",
436 ep->ep.name, &req->req, status,
437 req->req.actual, req->req.length);
5be19a9d
XS		 438
439 /* don't modify queue heads during completion callback */
440 ep->stopped = 1;
441
442 spin_unlock(&dev->lock);
443 /* complete routine from gadget driver */
444 if (req->req.complete)
445 req->req.complete(&ep->ep, &req->req);
446
447 spin_lock(&dev->lock);
448 ep->stopped = stopped;
449
5f81f4b0 450 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 451}
452
453
454static void langwell_ep_fifo_flush(struct usb_ep *_ep);
455
456/* delete all endpoint requests, called with spinlock held */
457static void nuke(struct langwell_ep *ep, int status)
458{
459 /* called with spinlock held */
460 ep->stopped = 1;
461
462 /* endpoint fifo flush */
463 if (&ep->ep && ep->desc)
464 langwell_ep_fifo_flush(&ep->ep);
465
466 while (!list_empty(&ep->queue)) {
467 struct langwell_request *req = NULL;
468 req = list_entry(ep->queue.next, struct langwell_request,
469 queue);
470 done(ep, req, status);
471 }
472}
473
474
475/*-------------------------------------------------------------------------*/
476
477/* endpoint is no longer usable */
478static int langwell_ep_disable(struct usb_ep *_ep)
479{
480 struct langwell_ep *ep;
481 unsigned long flags;
482 struct langwell_udc *dev;
483 int ep_num;
484 u32 endptctrl;
485
486 ep = container_of(_ep, struct langwell_ep, ep);
487 dev = ep->dev;
5f81f4b0 488 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 489
490 if (!_ep || !ep->desc)
491 return -EINVAL;
492
493 spin_lock_irqsave(&dev->lock, flags);
494
495 /* disable endpoint control register */
496 ep_num = ep->ep_num;
497 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
498 if (is_in(ep))
499 endptctrl &= ~EPCTRL_TXE;
500 else
501 endptctrl &= ~EPCTRL_RXE;
502 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
503
504 /* nuke all pending requests (does flush) */
505 nuke(ep, -ESHUTDOWN);
506
507 ep->desc = NULL;
508 ep->stopped = 1;
509
510 spin_unlock_irqrestore(&dev->lock, flags);
511
5f81f4b0
J		 512 dev_dbg(&dev->pdev->dev, "disabled %s\n", _ep->name);
513 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 514
515 return 0;
516}
517
518
519/* allocate a request object to use with this endpoint */
520static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
521 gfp_t gfp_flags)
522{
523 struct langwell_ep *ep;
524 struct langwell_udc *dev;
525 struct langwell_request *req = NULL;
526
527 if (!_ep)
528 return NULL;
529
530 ep = container_of(_ep, struct langwell_ep, ep);
531 dev = ep->dev;
5f81f4b0 532 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 533
534 req = kzalloc(sizeof(*req), gfp_flags);
535 if (!req)
536 return NULL;
537
538 req->req.dma = DMA_ADDR_INVALID;
539 INIT_LIST_HEAD(&req->queue);
540
5f81f4b0
J		 541 dev_vdbg(&dev->pdev->dev, "alloc request for %s\n", _ep->name);
542 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 543 return &req->req;
544}
545
546
547/* free a request object */
548static void langwell_free_request(struct usb_ep *_ep,
549 struct usb_request *_req)
550{
551 struct langwell_ep *ep;
552 struct langwell_udc *dev;
553 struct langwell_request *req = NULL;
554
555 ep = container_of(_ep, struct langwell_ep, ep);
556 dev = ep->dev;
5f81f4b0 557 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 558
559 if (!_ep || !_req)
560 return;
561
562 req = container_of(_req, struct langwell_request, req);
563 WARN_ON(!list_empty(&req->queue));
564
565 if (_req)
566 kfree(req);
567
5f81f4b0
J		 568 dev_vdbg(&dev->pdev->dev, "free request for %s\n", _ep->name);
569 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 570}
571
572
573/*-------------------------------------------------------------------------*/
574
575/* queue dTD and PRIME endpoint */
576static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
577{
578 u32 bit_mask, usbcmd, endptstat, dtd_dma;
579 u8 dtd_status;
580 int i;
581 struct langwell_dqh *dqh;
582 struct langwell_udc *dev;
583
584 dev = ep->dev;
5f81f4b0 585 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 586
587 i = ep->ep_num * 2 + is_in(ep);
588 dqh = &dev->ep_dqh[i];
589
590 if (ep->ep_num)
5f81f4b0 591 dev_vdbg(&dev->pdev->dev, "%s\n", ep->name);
5be19a9d
XS		 592 else
593 /* ep0 */
5f81f4b0 594 dev_vdbg(&dev->pdev->dev, "%s-%s\n", ep->name, DIR_STRING(ep));
5be19a9d 595
5f81f4b0
J		 596 dev_vdbg(&dev->pdev->dev, "ep_dqh[%d] addr: 0x%08x\n",
597 i, (u32)&(dev->ep_dqh[i]));
5be19a9d
XS		 598
599 bit_mask = is_in(ep) ?
600 (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
601
5f81f4b0 602 dev_vdbg(&dev->pdev->dev, "bit_mask = 0x%08x\n", bit_mask);
5be19a9d
XS		 603
604 /* check if the pipe is empty */
605 if (!(list_empty(&ep->queue))) {
606 /* add dTD to the end of linked list */
607 struct langwell_request *lastreq;
608 lastreq = list_entry(ep->queue.prev,
609 struct langwell_request, queue);
610
611 lastreq->tail->dtd_next =
612 cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
613
614 /* read prime bit, if 1 goto out */
615 if (readl(&dev->op_regs->endptprime) & bit_mask)
616 goto out;
617
618 do {
619 /* set ATDTW bit in USBCMD */
620 usbcmd = readl(&dev->op_regs->usbcmd);
621 writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
622
623 /* read correct status bit */
624 endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
625
626 } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
627
628 /* write ATDTW bit to 0 */
629 usbcmd = readl(&dev->op_regs->usbcmd);
630 writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
631
632 if (endptstat)
633 goto out;
634 }
635
636 /* write dQH next pointer and terminate bit to 0 */
637 dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
638 dqh->dtd_next = cpu_to_le32(dtd_dma);
639
640 /* clear active and halt bit */
641 dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
642 dqh->dtd_status &= dtd_status;
5f81f4b0
J		 643 dev_vdbg(&dev->pdev->dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
644
25985edc 645 /* ensure that updates to the dQH will occur before priming */
5f81f4b0 646 wmb();
5be19a9d
XS		 647
648 /* write 1 to endptprime register to PRIME endpoint */
649 bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
5f81f4b0 650 dev_vdbg(&dev->pdev->dev, "endprime bit_mask = 0x%08x\n", bit_mask);
5be19a9d
XS		 651 writel(bit_mask, &dev->op_regs->endptprime);
652out:
5f81f4b0 653 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 654 return 0;
655}
656
657
658/* fill in the dTD structure to build a transfer descriptor */
659static struct langwell_dtd *build_dtd(struct langwell_request *req,
660 unsigned *length, dma_addr_t *dma, int *is_last)
661{
662 u32 buf_ptr;
663 struct langwell_dtd *dtd;
664 struct langwell_udc *dev;
665 int i;
666
667 dev = req->ep->dev;
5f81f4b0 668 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 669
670 /* the maximum transfer length, up to 16k bytes */
671 *length = min(req->req.length - req->req.actual,
672 (unsigned)DTD_MAX_TRANSFER_LENGTH);
673
674 /* create dTD dma_pool resource */
675 dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
676 if (dtd == NULL)
677 return dtd;
678 dtd->dtd_dma = *dma;
679
680 /* initialize buffer page pointers */
681 buf_ptr = (u32)(req->req.dma + req->req.actual);
682 for (i = 0; i < 5; i++)
683 dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
684
685 req->req.actual += *length;
686
687 /* fill in total bytes with transfer size */
688 dtd->dtd_total = cpu_to_le16(*length);
5f81f4b0 689 dev_vdbg(&dev->pdev->dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
5be19a9d
XS		 690
691 /* set is_last flag if req->req.zero is set or not */
692 if (req->req.zero) {
693 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
694 *is_last = 1;
695 else
696 *is_last = 0;
697 } else if (req->req.length == req->req.actual) {
698 *is_last = 1;
699 } else
700 *is_last = 0;
701
702 if (*is_last == 0)
5f81f4b0 703 dev_vdbg(&dev->pdev->dev, "multi-dtd request!\n");
5be19a9d
XS		 704
705 /* set interrupt on complete bit for the last dTD */
706 if (*is_last && !req->req.no_interrupt)
707 dtd->dtd_ioc = 1;
708
709 /* set multiplier override 0 for non-ISO and non-TX endpoint */
710 dtd->dtd_multo = 0;
711
712 /* set the active bit of status field to 1 */
713 dtd->dtd_status = DTD_STS_ACTIVE;
5f81f4b0
J		 714 dev_vdbg(&dev->pdev->dev, "dtd->dtd_status = 0x%02x\n",
715 dtd->dtd_status);
5be19a9d 716
5f81f4b0
J		 717 dev_vdbg(&dev->pdev->dev, "length = %d, dma addr= 0x%08x\n",
718 *length, (int)*dma);
719 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 720 return dtd;
721}
722
723
724/* generate dTD linked list for a request */
725static int req_to_dtd(struct langwell_request *req)
726{
727 unsigned count;
728 int is_last, is_first = 1;
729 struct langwell_dtd *dtd, *last_dtd = NULL;
730 struct langwell_udc *dev;
731 dma_addr_t dma;
732
733 dev = req->ep->dev;
5f81f4b0 734 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 735 do {
736 dtd = build_dtd(req, &count, &dma, &is_last);
737 if (dtd == NULL)
738 return -ENOMEM;
739
740 if (is_first) {
741 is_first = 0;
742 req->head = dtd;
743 } else {
744 last_dtd->dtd_next = cpu_to_le32(dma);
745 last_dtd->next_dtd_virt = dtd;
746 }
747 last_dtd = dtd;
748 req->dtd_count++;
749 } while (!is_last);
750
751 /* set terminate bit to 1 for the last dTD */
752 dtd->dtd_next = DTD_TERM;
753
754 req->tail = dtd;
755
5f81f4b0 756 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 757 return 0;
758}
759
760/*-------------------------------------------------------------------------*/
761
762/* queue (submits) an I/O requests to an endpoint */
763static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
764 gfp_t gfp_flags)
765{
766 struct langwell_request *req;
767 struct langwell_ep *ep;
768 struct langwell_udc *dev;
769 unsigned long flags;
770 int is_iso = 0, zlflag = 0;
771
772 /* always require a cpu-view buffer */
773 req = container_of(_req, struct langwell_request, req);
774 ep = container_of(_ep, struct langwell_ep, ep);
775
776 if (!_req || !_req->complete || !_req->buf
777 || !list_empty(&req->queue)) {
778 return -EINVAL;
779 }
780
781 if (unlikely(!_ep || !ep->desc))
782 return -EINVAL;
783
784 dev = ep->dev;
785 req->ep = ep;
5f81f4b0 786 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 787
5f81f4b0 788 if (usb_endpoint_xfer_isoc(ep->desc)) {
5be19a9d
XS		 789 if (req->req.length > ep->ep.maxpacket)
790 return -EMSGSIZE;
791 is_iso = 1;
792 }
793
794 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
795 return -ESHUTDOWN;
796
797 /* set up dma mapping in case the caller didn't */
798 if (_req->dma == DMA_ADDR_INVALID) {
799 /* WORKAROUND: WARN_ON(size == 0) */
800 if (_req->length == 0) {
5f81f4b0 801 dev_vdbg(&dev->pdev->dev, "req->length: 0->1\n");
5be19a9d
XS		 802 zlflag = 1;
803 _req->length++;
804 }
805
806 _req->dma = dma_map_single(&dev->pdev->dev,
807 _req->buf, _req->length,
808 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
809 if (zlflag && (_req->length == 1)) {
5f81f4b0 810 dev_vdbg(&dev->pdev->dev, "req->length: 1->0\n");
5be19a9d
XS		 811 zlflag = 0;
812 _req->length = 0;
813 }
814
815 req->mapped = 1;
5f81f4b0 816 dev_vdbg(&dev->pdev->dev, "req->mapped = 1\n");
5be19a9d
XS		 817 } else {
818 dma_sync_single_for_device(&dev->pdev->dev,
819 _req->dma, _req->length,
820 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
821 req->mapped = 0;
5f81f4b0 822 dev_vdbg(&dev->pdev->dev, "req->mapped = 0\n");
5be19a9d
XS		 823 }
824
5f81f4b0
J		 825 dev_dbg(&dev->pdev->dev,
826 "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
827 _ep->name,
828 _req, _req->length, _req->buf, (int)_req->dma);
5be19a9d
XS		 829
830 _req->status = -EINPROGRESS;
831 _req->actual = 0;
832 req->dtd_count = 0;
833
834 spin_lock_irqsave(&dev->lock, flags);
835
836 /* build and put dTDs to endpoint queue */
837 if (!req_to_dtd(req)) {
838 queue_dtd(ep, req);
839 } else {
840 spin_unlock_irqrestore(&dev->lock, flags);
841 return -ENOMEM;
842 }
843
844 /* update ep0 state */
845 if (ep->ep_num == 0)
846 dev->ep0_state = DATA_STATE_XMIT;
847
848 if (likely(req != NULL)) {
849 list_add_tail(&req->queue, &ep->queue);
5f81f4b0 850 dev_vdbg(&dev->pdev->dev, "list_add_tail()\n");
5be19a9d
XS		 851 }
852
853 spin_unlock_irqrestore(&dev->lock, flags);
854
5f81f4b0 855 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 856 return 0;
857}
858
859
860/* dequeue (cancels, unlinks) an I/O request from an endpoint */
861static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
862{
863 struct langwell_ep *ep;
864 struct langwell_udc *dev;
865 struct langwell_request *req;
866 unsigned long flags;
867 int stopped, ep_num, retval = 0;
868 u32 endptctrl;
869
870 ep = container_of(_ep, struct langwell_ep, ep);
871 dev = ep->dev;
5f81f4b0 872 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 873
874 if (!_ep || !ep->desc || !_req)
875 return -EINVAL;
876
877 if (!dev->driver)
878 return -ESHUTDOWN;
879
880 spin_lock_irqsave(&dev->lock, flags);
881 stopped = ep->stopped;
882
883 /* quiesce dma while we patch the queue */
884 ep->stopped = 1;
885 ep_num = ep->ep_num;
886
887 /* disable endpoint control register */
888 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
889 if (is_in(ep))
890 endptctrl &= ~EPCTRL_TXE;
891 else
892 endptctrl &= ~EPCTRL_RXE;
893 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
894
895 /* make sure it's still queued on this endpoint */
896 list_for_each_entry(req, &ep->queue, queue) {
897 if (&req->req == _req)
898 break;
899 }
900
901 if (&req->req != _req) {
902 retval = -EINVAL;
903 goto done;
904 }
905
906 /* queue head may be partially complete. */
907 if (ep->queue.next == &req->queue) {
5f81f4b0 908 dev_dbg(&dev->pdev->dev, "unlink (%s) dma\n", _ep->name);
5be19a9d
XS		 909 _req->status = -ECONNRESET;
910 langwell_ep_fifo_flush(&ep->ep);
911
912 /* not the last request in endpoint queue */
913 if (likely(ep->queue.next == &req->queue)) {
914 struct langwell_dqh *dqh;
915 struct langwell_request *next_req;
916
917 dqh = ep->dqh;
918 next_req = list_entry(req->queue.next,
919 struct langwell_request, queue);
920
921 /* point the dQH to the first dTD of next request */
922 writel((u32) next_req->head, &dqh->dqh_current);
923 }
924 } else {
925 struct langwell_request *prev_req;
926
927 prev_req = list_entry(req->queue.prev,
928 struct langwell_request, queue);
929 writel(readl(&req->tail->dtd_next),
930 &prev_req->tail->dtd_next);
931 }
932
933 done(ep, req, -ECONNRESET);
934
935done:
936 /* enable endpoint again */
937 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
938 if (is_in(ep))
939 endptctrl |= EPCTRL_TXE;
940 else
941 endptctrl |= EPCTRL_RXE;
942 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
943
944 ep->stopped = stopped;
945 spin_unlock_irqrestore(&dev->lock, flags);
946
5f81f4b0 947 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 948 return retval;
949}
950
951
952/*-------------------------------------------------------------------------*/
953
954/* endpoint set/clear halt */
955static void ep_set_halt(struct langwell_ep *ep, int value)
956{
957 u32 endptctrl = 0;
958 int ep_num;
959 struct langwell_udc *dev = ep->dev;
5f81f4b0 960 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 961
962 ep_num = ep->ep_num;
963 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
964
965 /* value: 1 - set halt, 0 - clear halt */
966 if (value) {
967 /* set the stall bit */
968 if (is_in(ep))
969 endptctrl |= EPCTRL_TXS;
970 else
971 endptctrl |= EPCTRL_RXS;
972 } else {
973 /* clear the stall bit and reset data toggle */
974 if (is_in(ep)) {
975 endptctrl &= ~EPCTRL_TXS;
976 endptctrl |= EPCTRL_TXR;
977 } else {
978 endptctrl &= ~EPCTRL_RXS;
979 endptctrl |= EPCTRL_RXR;
980 }
981 }
982
983 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
984
5f81f4b0 985 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 986}
987
988
989/* set the endpoint halt feature */
990static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
991{
992 struct langwell_ep *ep;
993 struct langwell_udc *dev;
994 unsigned long flags;
995 int retval = 0;
996
997 ep = container_of(_ep, struct langwell_ep, ep);
998 dev = ep->dev;
999
5f81f4b0 1000 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1001
1002 if (!_ep || !ep->desc)
1003 return -EINVAL;
1004
1005 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1006 return -ESHUTDOWN;
1007
5f81f4b0 1008 if (usb_endpoint_xfer_isoc(ep->desc))
5be19a9d
XS		 1009 return -EOPNOTSUPP;
1010
1011 spin_lock_irqsave(&dev->lock, flags);
1012
1013 /*
1014 * attempt to halt IN ep will fail if any transfer requests
1015 * are still queue
1016 */
1017 if (!list_empty(&ep->queue) && is_in(ep) && value) {
1018 /* IN endpoint FIFO holds bytes */
5f81f4b0 1019 dev_dbg(&dev->pdev->dev, "%s FIFO holds bytes\n", _ep->name);
5be19a9d
XS		 1020 retval = -EAGAIN;
1021 goto done;
1022 }
1023
1024 /* endpoint set/clear halt */
1025 if (ep->ep_num) {
1026 ep_set_halt(ep, value);
1027 } else { /* endpoint 0 */
1028 dev->ep0_state = WAIT_FOR_SETUP;
1029 dev->ep0_dir = USB_DIR_OUT;
1030 }
1031done:
1032 spin_unlock_irqrestore(&dev->lock, flags);
5f81f4b0
J		 1033 dev_dbg(&dev->pdev->dev, "%s %s halt\n",
1034 _ep->name, value ? "set" : "clear");
1035 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1036 return retval;
1037}
1038
1039
1040/* set the halt feature and ignores clear requests */
1041static int langwell_ep_set_wedge(struct usb_ep *_ep)
1042{
1043 struct langwell_ep *ep;
1044 struct langwell_udc *dev;
1045
1046 ep = container_of(_ep, struct langwell_ep, ep);
1047 dev = ep->dev;
1048
5f81f4b0 1049 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1050
1051 if (!_ep || !ep->desc)
1052 return -EINVAL;
1053
5f81f4b0 1054 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1055 return usb_ep_set_halt(_ep);
1056}
1057
1058
1059/* flush contents of a fifo */
1060static void langwell_ep_fifo_flush(struct usb_ep *_ep)
1061{
1062 struct langwell_ep *ep;
1063 struct langwell_udc *dev;
1064 u32 flush_bit;
1065 unsigned long timeout;
1066
1067 ep = container_of(_ep, struct langwell_ep, ep);
1068 dev = ep->dev;
1069
5f81f4b0 1070 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1071
1072 if (!_ep || !ep->desc) {
5f81f4b0
J		 1073 dev_vdbg(&dev->pdev->dev, "ep or ep->desc is NULL\n");
1074 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1075 return;
1076 }
1077
5f81f4b0
J		 1078 dev_vdbg(&dev->pdev->dev, "%s-%s fifo flush\n",
1079 _ep->name, DIR_STRING(ep));
5be19a9d
XS		 1080
1081 /* flush endpoint buffer */
1082 if (ep->ep_num == 0)
1083 flush_bit = (1 << 16) | 1;
1084 else if (is_in(ep))
1085 flush_bit = 1 << (ep->ep_num + 16); /* TX */
1086 else
1087 flush_bit = 1 << ep->ep_num; /* RX */
1088
1089 /* wait until flush complete */
1090 timeout = jiffies + FLUSH_TIMEOUT;
1091 do {
1092 writel(flush_bit, &dev->op_regs->endptflush);
1093 while (readl(&dev->op_regs->endptflush)) {
1094 if (time_after(jiffies, timeout)) {
5f81f4b0 1095 dev_err(&dev->pdev->dev, "ep flush timeout\n");
5be19a9d
XS		 1096 goto done;
1097 }
1098 cpu_relax();
1099 }
1100 } while (readl(&dev->op_regs->endptstat) & flush_bit);
1101done:
5f81f4b0 1102 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1103}
1104
1105
1106/* endpoints operations structure */
1107static const struct usb_ep_ops langwell_ep_ops = {
1108
1109 /* configure endpoint, making it usable */
1110 .enable = langwell_ep_enable,
1111
1112 /* endpoint is no longer usable */
1113 .disable = langwell_ep_disable,
1114
1115 /* allocate a request object to use with this endpoint */
1116 .alloc_request = langwell_alloc_request,
1117
1118 /* free a request object */
1119 .free_request = langwell_free_request,
1120
1121 /* queue (submits) an I/O requests to an endpoint */
1122 .queue = langwell_ep_queue,
1123
1124 /* dequeue (cancels, unlinks) an I/O request from an endpoint */
1125 .dequeue = langwell_ep_dequeue,
1126
1127 /* set the endpoint halt feature */
1128 .set_halt = langwell_ep_set_halt,
1129
1130 /* set the halt feature and ignores clear requests */
1131 .set_wedge = langwell_ep_set_wedge,
1132
1133 /* flush contents of a fifo */
1134 .fifo_flush = langwell_ep_fifo_flush,
1135};
1136
1137
1138/*-------------------------------------------------------------------------*/
1139
1140/* device controller usb_gadget_ops structure */
1141
1142/* returns the current frame number */
1143static int langwell_get_frame(struct usb_gadget *_gadget)
1144{
1145 struct langwell_udc *dev;
1146 u16 retval;
1147
1148 if (!_gadget)
1149 return -ENODEV;
1150
1151 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1152 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1153
1154 retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
1155
5f81f4b0 1156 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1157 return retval;
1158}
1159
1160
513b91b6
J		 1161/* enter or exit PHY low power state */
1162static void langwell_phy_low_power(struct langwell_udc *dev, bool flag)
1163{
1164 u32 devlc;
1165 u8 devlc_byte2;
1166 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
1167
1168 devlc = readl(&dev->op_regs->devlc);
1169 dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
1170
1171 if (flag)
1172 devlc |= LPM_PHCD;
1173 else
1174 devlc &= ~LPM_PHCD;
1175
1176 /* FIXME: workaround for Langwell A1/A2/A3 sighting */
1177 devlc_byte2 = (devlc >> 16) & 0xff;
1178 writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
1179
1180 devlc = readl(&dev->op_regs->devlc);
1181 dev_vdbg(&dev->pdev->dev,
1182 "%s PHY low power suspend, devlc = 0x%08x\n",
1183 flag ? "enter" : "exit", devlc);
1184}
1185
1186
5be19a9d
XS		 1187/* tries to wake up the host connected to this gadget */
1188static int langwell_wakeup(struct usb_gadget *_gadget)
1189{
1190 struct langwell_udc *dev;
513b91b6 1191 u32 portsc1;
5f81f4b0 1192 unsigned long flags;
5be19a9d
XS		 1193
1194 if (!_gadget)
1195 return 0;
1196
1197 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1198 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 1199
5f81f4b0
J		 1200 /* remote wakeup feature not enabled by host */
1201 if (!dev->remote_wakeup) {
1202 dev_info(&dev->pdev->dev, "remote wakeup is disabled\n");
5be19a9d 1203 return -ENOTSUPP;
5f81f4b0 1204 }
5be19a9d
XS		 1205
1206 spin_lock_irqsave(&dev->lock, flags);
1207
1208 portsc1 = readl(&dev->op_regs->portsc1);
1209 if (!(portsc1 & PORTS_SUSP)) {
1210 spin_unlock_irqrestore(&dev->lock, flags);
1211 return 0;
1212 }
1213
513b91b6
J		 1214 /* LPM L1 to L0 or legacy remote wakeup */
1215 if (dev->lpm && dev->lpm_state == LPM_L1)
1216 dev_info(&dev->pdev->dev, "LPM L1 to L0 remote wakeup\n");
1217 else
1218 dev_info(&dev->pdev->dev, "device remote wakeup\n");
5be19a9d
XS		 1219
1220 /* exit PHY low power suspend */
513b91b6
J		 1221 if (dev->pdev->device != 0x0829)
1222 langwell_phy_low_power(dev, 0);
1223
1224 /* force port resume */
1225 portsc1 |= PORTS_FPR;
1226 writel(portsc1, &dev->op_regs->portsc1);
5be19a9d
XS		 1227
1228 spin_unlock_irqrestore(&dev->lock, flags);
1229
5f81f4b0 1230 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1231 return 0;
1232}
1233
1234
1235/* notify controller that VBUS is powered or not */
1236static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
1237{
1238 struct langwell_udc *dev;
1239 unsigned long flags;
5f81f4b0 1240 u32 usbcmd;
5be19a9d
XS		 1241
1242 if (!_gadget)
1243 return -ENODEV;
1244
1245 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1246 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1247
1248 spin_lock_irqsave(&dev->lock, flags);
5f81f4b0
J		 1249 dev_vdbg(&dev->pdev->dev, "VBUS status: %s\n",
1250 is_active ? "on" : "off");
5be19a9d
XS		 1251
1252 dev->vbus_active = (is_active != 0);
1253 if (dev->driver && dev->softconnected && dev->vbus_active) {
1254 usbcmd = readl(&dev->op_regs->usbcmd);
1255 usbcmd |= CMD_RUNSTOP;
1256 writel(usbcmd, &dev->op_regs->usbcmd);
1257 } else {
1258 usbcmd = readl(&dev->op_regs->usbcmd);
1259 usbcmd &= ~CMD_RUNSTOP;
1260 writel(usbcmd, &dev->op_regs->usbcmd);
1261 }
1262
1263 spin_unlock_irqrestore(&dev->lock, flags);
1264
5f81f4b0 1265 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1266 return 0;
1267}
1268
1269
1270/* constrain controller's VBUS power usage */
1271static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1272{
1273 struct langwell_udc *dev;
1274
1275 if (!_gadget)
1276 return -ENODEV;
1277
1278 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1279 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1280
1281 if (dev->transceiver) {
5f81f4b0
J		 1282 dev_vdbg(&dev->pdev->dev, "otg_set_power\n");
1283 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1284 return otg_set_power(dev->transceiver, mA);
1285 }
1286
5f81f4b0 1287 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1288 return -ENOTSUPP;
1289}
1290
1291
1292/* D+ pullup, software-controlled connect/disconnect to USB host */
1293static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
1294{
1295 struct langwell_udc *dev;
5f81f4b0
J		 1296 u32 usbcmd;
1297 unsigned long flags;
5be19a9d
XS		 1298
1299 if (!_gadget)
1300 return -ENODEV;
1301
1302 dev = container_of(_gadget, struct langwell_udc, gadget);
1303
5f81f4b0 1304 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1305
1306 spin_lock_irqsave(&dev->lock, flags);
1307 dev->softconnected = (is_on != 0);
1308
1309 if (dev->driver && dev->softconnected && dev->vbus_active) {
1310 usbcmd = readl(&dev->op_regs->usbcmd);
1311 usbcmd |= CMD_RUNSTOP;
1312 writel(usbcmd, &dev->op_regs->usbcmd);
1313 } else {
1314 usbcmd = readl(&dev->op_regs->usbcmd);
1315 usbcmd &= ~CMD_RUNSTOP;
1316 writel(usbcmd, &dev->op_regs->usbcmd);
1317 }
1318 spin_unlock_irqrestore(&dev->lock, flags);
1319
5f81f4b0 1320 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1321 return 0;
1322}
1323
0f91349b
SAS		 1324static int langwell_start(struct usb_gadget_driver *driver,
1325 int (*bind)(struct usb_gadget *));
1326static int langwell_stop(struct usb_gadget_driver *driver);
5be19a9d
XS		 1327/* device controller usb_gadget_ops structure */
1328static const struct usb_gadget_ops langwell_ops = {
1329
1330 /* returns the current frame number */
1331 .get_frame = langwell_get_frame,
1332
1333 /* tries to wake up the host connected to this gadget */
1334 .wakeup = langwell_wakeup,
1335
1336 /* set the device selfpowered feature, always selfpowered */
1337 /* .set_selfpowered = langwell_set_selfpowered, */
1338
1339 /* notify controller that VBUS is powered or not */
1340 .vbus_session = langwell_vbus_session,
1341
1342 /* constrain controller's VBUS power usage */
1343 .vbus_draw = langwell_vbus_draw,
1344
1345 /* D+ pullup, software-controlled connect/disconnect to USB host */
1346 .pullup = langwell_pullup,
0f91349b
SAS		 1347
1348 .start = langwell_start,
1349 .stop = langwell_stop,
5be19a9d
XS		 1350};
1351
1352
1353/*-------------------------------------------------------------------------*/
1354
1355/* device controller operations */
1356
1357/* reset device controller */
1358static int langwell_udc_reset(struct langwell_udc *dev)
1359{
1360 u32 usbcmd, usbmode, devlc, endpointlistaddr;
513b91b6 1361 u8 devlc_byte0, devlc_byte2;
5be19a9d
XS		 1362 unsigned long timeout;
1363
1364 if (!dev)
1365 return -EINVAL;
1366
5f81f4b0 1367 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1368
1369 /* set controller to stop state */
1370 usbcmd = readl(&dev->op_regs->usbcmd);
1371 usbcmd &= ~CMD_RUNSTOP;
1372 writel(usbcmd, &dev->op_regs->usbcmd);
1373
1374 /* reset device controller */
1375 usbcmd = readl(&dev->op_regs->usbcmd);
1376 usbcmd |= CMD_RST;
1377 writel(usbcmd, &dev->op_regs->usbcmd);
1378
1379 /* wait for reset to complete */
1380 timeout = jiffies + RESET_TIMEOUT;
1381 while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
1382 if (time_after(jiffies, timeout)) {
5f81f4b0 1383 dev_err(&dev->pdev->dev, "device reset timeout\n");
5be19a9d
XS		 1384 return -ETIMEDOUT;
1385 }
1386 cpu_relax();
1387 }
1388
1389 /* set controller to device mode */
1390 usbmode = readl(&dev->op_regs->usbmode);
1391 usbmode |= MODE_DEVICE;
1392
1393 /* turn setup lockout off, require setup tripwire in usbcmd */
1394 usbmode |= MODE_SLOM;
1395
1396 writel(usbmode, &dev->op_regs->usbmode);
1397 usbmode = readl(&dev->op_regs->usbmode);
5f81f4b0 1398 dev_vdbg(&dev->pdev->dev, "usbmode=0x%08x\n", usbmode);
5be19a9d
XS		 1399
1400 /* Write-Clear setup status */
1401 writel(0, &dev->op_regs->usbsts);
1402
1403 /* if support USB LPM, ACK all LPM token */
1404 if (dev->lpm) {
1405 devlc = readl(&dev->op_regs->devlc);
513b91b6
J		 1406 dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
1407 /* FIXME: workaround for Langwell A1/A2/A3 sighting */
5be19a9d
XS		 1408 devlc &= ~LPM_STL; /* don't STALL LPM token */
1409 devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
513b91b6
J		 1410 devlc_byte0 = devlc & 0xff;
1411 devlc_byte2 = (devlc >> 16) & 0xff;
1412 writeb(devlc_byte0, (u8 *)&dev->op_regs->devlc);
1413 writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
1414 devlc = readl(&dev->op_regs->devlc);
1415 dev_vdbg(&dev->pdev->dev,
1416 "ACK LPM token, devlc = 0x%08x\n", devlc);
5be19a9d
XS		 1417 }
1418
1419 /* fill endpointlistaddr register */
1420 endpointlistaddr = dev->ep_dqh_dma;
1421 endpointlistaddr &= ENDPOINTLISTADDR_MASK;
1422 writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
1423
5f81f4b0
J		 1424 dev_vdbg(&dev->pdev->dev,
1425 "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
1426 dev->ep_dqh, endpointlistaddr,
1427 readl(&dev->op_regs->endpointlistaddr));
1428 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1429 return 0;
1430}
1431
1432
1433/* reinitialize device controller endpoints */
1434static int eps_reinit(struct langwell_udc *dev)
1435{
1436 struct langwell_ep *ep;
1437 char name[14];
1438 int i;
1439
5f81f4b0 1440 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1441
1442 /* initialize ep0 */
1443 ep = &dev->ep[0];
1444 ep->dev = dev;
1445 strncpy(ep->name, "ep0", sizeof(ep->name));
1446 ep->ep.name = ep->name;
1447 ep->ep.ops = &langwell_ep_ops;
1448 ep->stopped = 0;
1449 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1450 ep->ep_num = 0;
1451 ep->desc = &langwell_ep0_desc;
1452 INIT_LIST_HEAD(&ep->queue);
1453
1454 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1455
1456 /* initialize other endpoints */
1457 for (i = 2; i < dev->ep_max; i++) {
1458 ep = &dev->ep[i];
1459 if (i % 2)
1460 snprintf(name, sizeof(name), "ep%din", i / 2);
1461 else
1462 snprintf(name, sizeof(name), "ep%dout", i / 2);
1463 ep->dev = dev;
1464 strncpy(ep->name, name, sizeof(ep->name));
1465 ep->ep.name = ep->name;
1466
1467 ep->ep.ops = &langwell_ep_ops;
1468 ep->stopped = 0;
1469 ep->ep.maxpacket = (unsigned short) ~0;
1470 ep->ep_num = i / 2;
1471
1472 INIT_LIST_HEAD(&ep->queue);
1473 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
5be19a9d
XS		 1474 }
1475
5f81f4b0 1476 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1477 return 0;
1478}
1479
1480
1481/* enable interrupt and set controller to run state */
1482static void langwell_udc_start(struct langwell_udc *dev)
1483{
1484 u32 usbintr, usbcmd;
5f81f4b0 1485 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1486
1487 /* enable interrupts */
1488 usbintr = INTR_ULPIE /* ULPI */
1489 | INTR_SLE /* suspend */
1490 /* | INTR_SRE SOF received */
1491 | INTR_URE /* USB reset */
1492 | INTR_AAE /* async advance */
1493 | INTR_SEE /* system error */
1494 | INTR_FRE /* frame list rollover */
1495 | INTR_PCE /* port change detect */
1496 | INTR_UEE /* USB error interrupt */
1497 | INTR_UE; /* USB interrupt */
1498 writel(usbintr, &dev->op_regs->usbintr);
1499
1500 /* clear stopped bit */
1501 dev->stopped = 0;
1502
1503 /* set controller to run */
1504 usbcmd = readl(&dev->op_regs->usbcmd);
1505 usbcmd |= CMD_RUNSTOP;
1506 writel(usbcmd, &dev->op_regs->usbcmd);
1507
5f81f4b0 1508 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1509}
1510
1511
1512/* disable interrupt and set controller to stop state */
1513static void langwell_udc_stop(struct langwell_udc *dev)
1514{
1515 u32 usbcmd;
1516
5f81f4b0 1517 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1518
1519 /* disable all interrupts */
1520 writel(0, &dev->op_regs->usbintr);
1521
1522 /* set stopped bit */
1523 dev->stopped = 1;
1524
1525 /* set controller to stop state */
1526 usbcmd = readl(&dev->op_regs->usbcmd);
1527 usbcmd &= ~CMD_RUNSTOP;
1528 writel(usbcmd, &dev->op_regs->usbcmd);
1529
5f81f4b0 1530 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1531}
1532
1533
1534/* stop all USB activities */
1535static void stop_activity(struct langwell_udc *dev,
1536 struct usb_gadget_driver *driver)
1537{
1538 struct langwell_ep *ep;
5f81f4b0 1539 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1540
1541 nuke(&dev->ep[0], -ESHUTDOWN);
1542
1543 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
1544 nuke(ep, -ESHUTDOWN);
1545 }
1546
1547 /* report disconnect; the driver is already quiesced */
1548 if (driver) {
1549 spin_unlock(&dev->lock);
1550 driver->disconnect(&dev->gadget);
1551 spin_lock(&dev->lock);
1552 }
1553
5f81f4b0 1554 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1555}
1556
1557
1558/*-------------------------------------------------------------------------*/
1559
1560/* device "function" sysfs attribute file */
1561static ssize_t show_function(struct device *_dev,
1562 struct device_attribute *attr, char *buf)
1563{
1564 struct langwell_udc *dev = the_controller;
1565
1566 if (!dev->driver || !dev->driver->function
1567 || strlen(dev->driver->function) > PAGE_SIZE)
1568 return 0;
1569
1570 return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
1571}
1572static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
1573
1574
1575/* device "langwell_udc" sysfs attribute file */
1576static ssize_t show_langwell_udc(struct device *_dev,
1577 struct device_attribute *attr, char *buf)
1578{
1579 struct langwell_udc *dev = the_controller;
1580 struct langwell_request *req;
1581 struct langwell_ep *ep = NULL;
1582 char *next;
1583 unsigned size;
1584 unsigned t;
1585 unsigned i;
1586 unsigned long flags;
1587 u32 tmp_reg;
1588
1589 next = buf;
1590 size = PAGE_SIZE;
1591 spin_lock_irqsave(&dev->lock, flags);
1592
1593 /* driver basic information */
1594 t = scnprintf(next, size,
1595 DRIVER_DESC "\n"
1596 "%s version: %s\n"
1597 "Gadget driver: %s\n\n",
1598 driver_name, DRIVER_VERSION,
1599 dev->driver ? dev->driver->driver.name : "(none)");
1600 size -= t;
1601 next += t;
1602
1603 /* device registers */
1604 tmp_reg = readl(&dev->op_regs->usbcmd);
1605 t = scnprintf(next, size,
1606 "USBCMD reg:\n"
1607 "SetupTW: %d\n"
1608 "Run/Stop: %s\n\n",
1609 (tmp_reg & CMD_SUTW) ? 1 : 0,
1610 (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
1611 size -= t;
1612 next += t;
1613
1614 tmp_reg = readl(&dev->op_regs->usbsts);
1615 t = scnprintf(next, size,
1616 "USB Status Reg:\n"
1617 "Device Suspend: %d\n"
1618 "Reset Received: %d\n"
1619 "System Error: %s\n"
1620 "USB Error Interrupt: %s\n\n",
1621 (tmp_reg & STS_SLI) ? 1 : 0,
1622 (tmp_reg & STS_URI) ? 1 : 0,
1623 (tmp_reg & STS_SEI) ? "Error" : "No error",
1624 (tmp_reg & STS_UEI) ? "Error detected" : "No error");
1625 size -= t;
1626 next += t;
1627
1628 tmp_reg = readl(&dev->op_regs->usbintr);
1629 t = scnprintf(next, size,
1630 "USB Intrrupt Enable Reg:\n"
1631 "Sleep Enable: %d\n"
1632 "SOF Received Enable: %d\n"
1633 "Reset Enable: %d\n"
1634 "System Error Enable: %d\n"
1635 "Port Change Dectected Enable: %d\n"
1636 "USB Error Intr Enable: %d\n"
1637 "USB Intr Enable: %d\n\n",
1638 (tmp_reg & INTR_SLE) ? 1 : 0,
1639 (tmp_reg & INTR_SRE) ? 1 : 0,
1640 (tmp_reg & INTR_URE) ? 1 : 0,
1641 (tmp_reg & INTR_SEE) ? 1 : 0,
1642 (tmp_reg & INTR_PCE) ? 1 : 0,
1643 (tmp_reg & INTR_UEE) ? 1 : 0,
1644 (tmp_reg & INTR_UE) ? 1 : 0);
1645 size -= t;
1646 next += t;
1647
1648 tmp_reg = readl(&dev->op_regs->frindex);
1649 t = scnprintf(next, size,
1650 "USB Frame Index Reg:\n"
1651 "Frame Number is 0x%08x\n\n",
1652 (tmp_reg & FRINDEX_MASK));
1653 size -= t;
1654 next += t;
1655
1656 tmp_reg = readl(&dev->op_regs->deviceaddr);
1657 t = scnprintf(next, size,
1658 "USB Device Address Reg:\n"
1659 "Device Addr is 0x%x\n\n",
1660 USBADR(tmp_reg));
1661 size -= t;
1662 next += t;
1663
1664 tmp_reg = readl(&dev->op_regs->endpointlistaddr);
1665 t = scnprintf(next, size,
1666 "USB Endpoint List Address Reg:\n"
1667 "Endpoint List Pointer is 0x%x\n\n",
1668 EPBASE(tmp_reg));
1669 size -= t;
1670 next += t;
1671
1672 tmp_reg = readl(&dev->op_regs->portsc1);
1673 t = scnprintf(next, size,
1674 "USB Port Status & Control Reg:\n"
1675 "Port Reset: %s\n"
1676 "Port Suspend Mode: %s\n"
1677 "Over-current Change: %s\n"
1678 "Port Enable/Disable Change: %s\n"
1679 "Port Enabled/Disabled: %s\n"
5f81f4b0
J		 1680 "Current Connect Status: %s\n"
1681 "LPM Suspend Status: %s\n\n",
5be19a9d
XS		 1682 (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
1683 (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
1684 (tmp_reg & PORTS_OCC) ? "Detected" : "No",
1685 (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
1686 (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
5f81f4b0
J		 1687 (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached",
1688 (tmp_reg & PORTS_SLP) ? "LPM L1" : "LPM L0");
5be19a9d
XS		 1689 size -= t;
1690 next += t;
1691
1692 tmp_reg = readl(&dev->op_regs->devlc);
1693 t = scnprintf(next, size,
1694 "Device LPM Control Reg:\n"
1695 "Parallel Transceiver : %d\n"
1696 "Serial Transceiver : %d\n"
1697 "Port Speed: %s\n"
1698 "Port Force Full Speed Connenct: %s\n"
5f81f4b0 1699 "PHY Low Power Suspend Clock: %s\n"
5be19a9d
XS		 1700 "BmAttributes: %d\n\n",
1701 LPM_PTS(tmp_reg),
1702 (tmp_reg & LPM_STS) ? 1 : 0,
1703 ({
1704 char *s;
1705 switch (LPM_PSPD(tmp_reg)) {
1706 case LPM_SPEED_FULL:
1707 s = "Full Speed"; break;
1708 case LPM_SPEED_LOW:
1709 s = "Low Speed"; break;
1710 case LPM_SPEED_HIGH:
1711 s = "High Speed"; break;
1712 default:
1713 s = "Unknown Speed"; break;
1714 }
1715 s;
1716 }),
1717 (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
1718 (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
1719 LPM_BA(tmp_reg));
1720 size -= t;
1721 next += t;
1722
1723 tmp_reg = readl(&dev->op_regs->usbmode);
1724 t = scnprintf(next, size,
1725 "USB Mode Reg:\n"
1726 "Controller Mode is : %s\n\n", ({
1727 char *s;
1728 switch (MODE_CM(tmp_reg)) {
1729 case MODE_IDLE:
1730 s = "Idle"; break;
1731 case MODE_DEVICE:
1732 s = "Device Controller"; break;
1733 case MODE_HOST:
1734 s = "Host Controller"; break;
1735 default:
1736 s = "None"; break;
1737 }
1738 s;
1739 }));
1740 size -= t;
1741 next += t;
1742
1743 tmp_reg = readl(&dev->op_regs->endptsetupstat);
1744 t = scnprintf(next, size,
1745 "Endpoint Setup Status Reg:\n"
1746 "SETUP on ep 0x%04x\n\n",
1747 tmp_reg & SETUPSTAT_MASK);
1748 size -= t;
1749 next += t;
1750
1751 for (i = 0; i < dev->ep_max / 2; i++) {
1752 tmp_reg = readl(&dev->op_regs->endptctrl[i]);
1753 t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
1754 i, tmp_reg);
1755 size -= t;
1756 next += t;
1757 }
1758 tmp_reg = readl(&dev->op_regs->endptprime);
1759 t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
1760 size -= t;
1761 next += t;
1762
1763 /* langwell_udc, langwell_ep, langwell_request structure information */
1764 ep = &dev->ep[0];
1765 t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
1766 ep->ep.name, ep->ep.maxpacket, ep->ep_num);
1767 size -= t;
1768 next += t;
1769
1770 if (list_empty(&ep->queue)) {
1771 t = scnprintf(next, size, "its req queue is empty\n\n");
1772 size -= t;
1773 next += t;
1774 } else {
1775 list_for_each_entry(req, &ep->queue, queue) {
1776 t = scnprintf(next, size,
1777 "req %p actual 0x%x length 0x%x buf %p\n",
1778 &req->req, req->req.actual,
1779 req->req.length, req->req.buf);
1780 size -= t;
1781 next += t;
1782 }
1783 }
1784 /* other gadget->eplist ep */
1785 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
1786 if (ep->desc) {
1787 t = scnprintf(next, size,
1788 "\n%s MaxPacketSize: 0x%x, "
1789 "ep_num: %d\n",
1790 ep->ep.name, ep->ep.maxpacket,
1791 ep->ep_num);
1792 size -= t;
1793 next += t;
1794
1795 if (list_empty(&ep->queue)) {
1796 t = scnprintf(next, size,
1797 "its req queue is empty\n\n");
1798 size -= t;
1799 next += t;
1800 } else {
1801 list_for_each_entry(req, &ep->queue, queue) {
1802 t = scnprintf(next, size,
1803 "req %p actual 0x%x length "
1804 "0x%x buf %p\n",
1805 &req->req, req->req.actual,
1806 req->req.length, req->req.buf);
1807 size -= t;
1808 next += t;
1809 }
1810 }
1811 }
1812 }
1813
1814 spin_unlock_irqrestore(&dev->lock, flags);
1815 return PAGE_SIZE - size;
1816}
1817static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
1818
1819
3211cbc2
J		 1820/* device "remote_wakeup" sysfs attribute file */
1821static ssize_t store_remote_wakeup(struct device *_dev,
1822 struct device_attribute *attr, const char *buf, size_t count)
1823{
1824 struct langwell_udc *dev = the_controller;
1825 unsigned long flags;
1826 ssize_t rc = count;
1827
1828 if (count > 2)
1829 return -EINVAL;
1830
1831 if (count > 0 && buf[count-1] == '\n')
1832 ((char *) buf)[count-1] = 0;
1833
1834 if (buf[0] != '1')
1835 return -EINVAL;
1836
1837 /* force remote wakeup enabled in case gadget driver doesn't support */
1838 spin_lock_irqsave(&dev->lock, flags);
1839 dev->remote_wakeup = 1;
1840 dev->dev_status |= (1 << USB_DEVICE_REMOTE_WAKEUP);
1841 spin_unlock_irqrestore(&dev->lock, flags);
1842
1843 langwell_wakeup(&dev->gadget);
1844
1845 return rc;
1846}
1847static DEVICE_ATTR(remote_wakeup, S_IWUSR, NULL, store_remote_wakeup);
1848
1849
5be19a9d
XS		 1850/*-------------------------------------------------------------------------*/
1851
1852/*
1853 * when a driver is successfully registered, it will receive
1854 * control requests including set_configuration(), which enables
1855 * non-control requests. then usb traffic follows until a
1856 * disconnect is reported. then a host may connect again, or
1857 * the driver might get unbound.
1858 */
1859
0f91349b 1860static int langwell_start(struct usb_gadget_driver *driver,
b0fca50f 1861 int (*bind)(struct usb_gadget *))
5be19a9d
XS		 1862{
1863 struct langwell_udc *dev = the_controller;
1864 unsigned long flags;
1865 int retval;
1866
1867 if (!dev)
1868 return -ENODEV;
1869
5f81f4b0 1870 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1871
1872 if (dev->driver)
1873 return -EBUSY;
1874
1875 spin_lock_irqsave(&dev->lock, flags);
1876
1877 /* hook up the driver ... */
1878 driver->driver.bus = NULL;
1879 dev->driver = driver;
1880 dev->gadget.dev.driver = &driver->driver;
1881
1882 spin_unlock_irqrestore(&dev->lock, flags);
1883
b0fca50f 1884 retval = bind(&dev->gadget);
5be19a9d 1885 if (retval) {
5f81f4b0 1886 dev_dbg(&dev->pdev->dev, "bind to driver %s --> %d\n",
5be19a9d
XS		 1887 driver->driver.name, retval);
1888 dev->driver = NULL;
1889 dev->gadget.dev.driver = NULL;
1890 return retval;
1891 }
1892
1893 retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
1894 if (retval)
1895 goto err_unbind;
1896
1897 dev->usb_state = USB_STATE_ATTACHED;
1898 dev->ep0_state = WAIT_FOR_SETUP;
1899 dev->ep0_dir = USB_DIR_OUT;
1900
1901 /* enable interrupt and set controller to run state */
1902 if (dev->got_irq)
1903 langwell_udc_start(dev);
1904
5f81f4b0
J		 1905 dev_vdbg(&dev->pdev->dev,
1906 "After langwell_udc_start(), print all registers:\n");
5be19a9d 1907 print_all_registers(dev);
5be19a9d 1908
5f81f4b0
J		 1909 dev_info(&dev->pdev->dev, "register driver: %s\n",
1910 driver->driver.name);
1911 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1912 return 0;
1913
1914err_unbind:
1915 driver->unbind(&dev->gadget);
1916 dev->gadget.dev.driver = NULL;
1917 dev->driver = NULL;
1918
5f81f4b0 1919 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1920 return retval;
1921}
5be19a9d
XS		 1922
1923/* unregister gadget driver */
0f91349b 1924static int langwell_stop(struct usb_gadget_driver *driver)
5be19a9d
XS		 1925{
1926 struct langwell_udc *dev = the_controller;
1927 unsigned long flags;
1928
1929 if (!dev)
1930 return -ENODEV;
1931
5f81f4b0 1932 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 1933
b0fca50f 1934 if (unlikely(!driver || !driver->unbind))
5be19a9d
XS		 1935 return -EINVAL;
1936
513b91b6
J		 1937 /* exit PHY low power suspend */
1938 if (dev->pdev->device != 0x0829)
1939 langwell_phy_low_power(dev, 0);
1940
5be19a9d
XS		 1941 /* unbind OTG transceiver */
1942 if (dev->transceiver)
1943 (void)otg_set_peripheral(dev->transceiver, 0);
1944
1945 /* disable interrupt and set controller to stop state */
1946 langwell_udc_stop(dev);
1947
1948 dev->usb_state = USB_STATE_ATTACHED;
1949 dev->ep0_state = WAIT_FOR_SETUP;
1950 dev->ep0_dir = USB_DIR_OUT;
1951
1952 spin_lock_irqsave(&dev->lock, flags);
1953
1954 /* stop all usb activities */
1955 dev->gadget.speed = USB_SPEED_UNKNOWN;
1956 stop_activity(dev, driver);
1957 spin_unlock_irqrestore(&dev->lock, flags);
1958
1959 /* unbind gadget driver */
1960 driver->unbind(&dev->gadget);
1961 dev->gadget.dev.driver = NULL;
1962 dev->driver = NULL;
1963
1964 device_remove_file(&dev->pdev->dev, &dev_attr_function);
1965
5f81f4b0
J		 1966 dev_info(&dev->pdev->dev, "unregistered driver '%s'\n",
1967 driver->driver.name);
1968 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1969 return 0;
1970}
5be19a9d
XS		 1971
1972/*-------------------------------------------------------------------------*/
1973
1974/*
1975 * setup tripwire is used as a semaphore to ensure that the setup data
1976 * payload is extracted from a dQH without being corrupted
1977 */
1978static void setup_tripwire(struct langwell_udc *dev)
1979{
1980 u32 usbcmd,
1981 endptsetupstat;
1982 unsigned long timeout;
1983 struct langwell_dqh *dqh;
1984
5f81f4b0 1985 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1986
1987 /* ep0 OUT dQH */
1988 dqh = &dev->ep_dqh[EP_DIR_OUT];
1989
1990 /* Write-Clear endptsetupstat */
1991 endptsetupstat = readl(&dev->op_regs->endptsetupstat);
1992 writel(endptsetupstat, &dev->op_regs->endptsetupstat);
1993
1994 /* wait until endptsetupstat is cleared */
1995 timeout = jiffies + SETUPSTAT_TIMEOUT;
1996 while (readl(&dev->op_regs->endptsetupstat)) {
1997 if (time_after(jiffies, timeout)) {
5f81f4b0 1998 dev_err(&dev->pdev->dev, "setup_tripwire timeout\n");
5be19a9d
XS		 1999 break;
2000 }
2001 cpu_relax();
2002 }
2003
2004 /* while a hazard exists when setup packet arrives */
2005 do {
2006 /* set setup tripwire bit */
2007 usbcmd = readl(&dev->op_regs->usbcmd);
2008 writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
2009
2010 /* copy the setup packet to local buffer */
2011 memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
2012 } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
2013
2014 /* Write-Clear setup tripwire bit */
2015 usbcmd = readl(&dev->op_regs->usbcmd);
2016 writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
2017
5f81f4b0 2018 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2019}
2020
2021
2022/* protocol ep0 stall, will automatically be cleared on new transaction */
2023static void ep0_stall(struct langwell_udc *dev)
2024{
2025 u32 endptctrl;
2026
5f81f4b0 2027 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2028
2029 /* set TX and RX to stall */
2030 endptctrl = readl(&dev->op_regs->endptctrl[0]);
2031 endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
2032 writel(endptctrl, &dev->op_regs->endptctrl[0]);
2033
2034 /* update ep0 state */
2035 dev->ep0_state = WAIT_FOR_SETUP;
2036 dev->ep0_dir = USB_DIR_OUT;
2037
5f81f4b0 2038 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2039}
2040
2041
2042/* PRIME a status phase for ep0 */
2043static int prime_status_phase(struct langwell_udc *dev, int dir)
2044{
2045 struct langwell_request *req;
2046 struct langwell_ep *ep;
2047 int status = 0;
2048
5f81f4b0 2049 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2050
2051 if (dir == EP_DIR_IN)
2052 dev->ep0_dir = USB_DIR_IN;
2053 else
2054 dev->ep0_dir = USB_DIR_OUT;
2055
2056 ep = &dev->ep[0];
2057 dev->ep0_state = WAIT_FOR_OUT_STATUS;
2058
2059 req = dev->status_req;
2060
2061 req->ep = ep;
2062 req->req.length = 0;
2063 req->req.status = -EINPROGRESS;
2064 req->req.actual = 0;
2065 req->req.complete = NULL;
2066 req->dtd_count = 0;
2067
2068 if (!req_to_dtd(req))
2069 status = queue_dtd(ep, req);
2070 else
2071 return -ENOMEM;
2072
2073 if (status)
5f81f4b0 2074 dev_err(&dev->pdev->dev, "can't queue ep0 status request\n");
5be19a9d
XS		 2075
2076 list_add_tail(&req->queue, &ep->queue);
2077
5f81f4b0 2078 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2079 return status;
2080}
2081
2082
2083/* SET_ADDRESS request routine */
2084static void set_address(struct langwell_udc *dev, u16 value,
2085 u16 index, u16 length)
2086{
5f81f4b0 2087 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2088
2089 /* save the new address to device struct */
2090 dev->dev_addr = (u8) value;
5f81f4b0 2091 dev_vdbg(&dev->pdev->dev, "dev->dev_addr = %d\n", dev->dev_addr);
5be19a9d
XS		 2092
2093 /* update usb state */
2094 dev->usb_state = USB_STATE_ADDRESS;
2095
2096 /* STATUS phase */
2097 if (prime_status_phase(dev, EP_DIR_IN))
2098 ep0_stall(dev);
2099
5f81f4b0 2100 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2101}
2102
2103
2104/* return endpoint by windex */
2105static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
2106 u16 wIndex)
2107{
2108 struct langwell_ep *ep;
5f81f4b0 2109 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2110
2111 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
2112 return &dev->ep[0];
2113
2114 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
2115 u8 bEndpointAddress;
2116 if (!ep->desc)
2117 continue;
2118
2119 bEndpointAddress = ep->desc->bEndpointAddress;
2120 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
2121 continue;
2122
2123 if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
2124 == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
2125 return ep;
2126 }
2127
5f81f4b0 2128 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2129 return NULL;
2130}
2131
2132
2133/* return whether endpoint is stalled, 0: not stalled; 1: stalled */
2134static int ep_is_stall(struct langwell_ep *ep)
2135{
2136 struct langwell_udc *dev = ep->dev;
2137 u32 endptctrl;
2138 int retval;
2139
5f81f4b0 2140 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2141
2142 endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
2143 if (is_in(ep))
2144 retval = endptctrl & EPCTRL_TXS ? 1 : 0;
2145 else
2146 retval = endptctrl & EPCTRL_RXS ? 1 : 0;
2147
5f81f4b0 2148 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2149 return retval;
2150}
2151
2152
2153/* GET_STATUS request routine */
2154static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
2155 u16 index, u16 length)
2156{
2157 struct langwell_request *req;
2158 struct langwell_ep *ep;
2159 u16 status_data = 0; /* 16 bits cpu view status data */
2160 int status = 0;
2161
5f81f4b0 2162 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2163
2164 ep = &dev->ep[0];
2165
2166 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
2167 /* get device status */
3211cbc2 2168 status_data = dev->dev_status;
5be19a9d
XS		 2169 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
2170 /* get interface status */
2171 status_data = 0;
2172 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
2173 /* get endpoint status */
2174 struct langwell_ep *epn;
2175 epn = get_ep_by_windex(dev, index);
2176 /* stall if endpoint doesn't exist */
2177 if (!epn)
2178 goto stall;
2179
2180 status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
2181 }
2182
5f81f4b0
J		 2183 dev_dbg(&dev->pdev->dev, "get status data: 0x%04x\n", status_data);
2184
5be19a9d
XS		 2185 dev->ep0_dir = USB_DIR_IN;
2186
2187 /* borrow the per device status_req */
2188 req = dev->status_req;
2189
2190 /* fill in the reqest structure */
2191 *((u16 *) req->req.buf) = cpu_to_le16(status_data);
2192 req->ep = ep;
2193 req->req.length = 2;
2194 req->req.status = -EINPROGRESS;
2195 req->req.actual = 0;
2196 req->req.complete = NULL;
2197 req->dtd_count = 0;
2198
2199 /* prime the data phase */
2200 if (!req_to_dtd(req))
2201 status = queue_dtd(ep, req);
2202 else /* no mem */
2203 goto stall;
2204
2205 if (status) {
5f81f4b0
J		 2206 dev_err(&dev->pdev->dev,
2207 "response error on GET_STATUS request\n");
5be19a9d
XS		 2208 goto stall;
2209 }
2210
2211 list_add_tail(&req->queue, &ep->queue);
2212 dev->ep0_state = DATA_STATE_XMIT;
2213
5f81f4b0 2214 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2215 return;
2216stall:
2217 ep0_stall(dev);
5f81f4b0 2218 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2219}
2220
2221
2222/* setup packet interrupt handler */
2223static void handle_setup_packet(struct langwell_udc *dev,
2224 struct usb_ctrlrequest *setup)
2225{
2226 u16 wValue = le16_to_cpu(setup->wValue);
2227 u16 wIndex = le16_to_cpu(setup->wIndex);
2228 u16 wLength = le16_to_cpu(setup->wLength);
7fc56f0d 2229 u32 portsc1;
5be19a9d 2230
5f81f4b0 2231 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2232
2233 /* ep0 fifo flush */
2234 nuke(&dev->ep[0], -ESHUTDOWN);
2235
5f81f4b0 2236 dev_dbg(&dev->pdev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
5be19a9d
XS		 2237 setup->bRequestType, setup->bRequest,
2238 wValue, wIndex, wLength);
2239
2240 /* RNDIS gadget delegate */
2241 if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
2242 /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
2243 goto delegate;
2244 }
2245
2246 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
2247 if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
2248 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
2249 goto delegate;
2250 }
2251
2252 /* We process some stardard setup requests here */
2253 switch (setup->bRequest) {
2254 case USB_REQ_GET_STATUS:
5f81f4b0 2255 dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_GET_STATUS\n");
5be19a9d
XS		 2256 /* get status, DATA and STATUS phase */
2257 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
2258 != (USB_DIR_IN | USB_TYPE_STANDARD))
2259 break;
2260 get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
2261 goto end;
2262
2263 case USB_REQ_SET_ADDRESS:
5f81f4b0 2264 dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_SET_ADDRESS\n");
5be19a9d
XS		 2265 /* STATUS phase */
2266 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
2267 | USB_RECIP_DEVICE))
2268 break;
2269 set_address(dev, wValue, wIndex, wLength);
2270 goto end;
2271
2272 case USB_REQ_CLEAR_FEATURE:
2273 case USB_REQ_SET_FEATURE:
2274 /* STATUS phase */
2275 {
2276 int rc = -EOPNOTSUPP;
2277 if (setup->bRequest == USB_REQ_SET_FEATURE)
5f81f4b0
J		 2278 dev_dbg(&dev->pdev->dev,
2279 "SETUP: USB_REQ_SET_FEATURE\n");
5be19a9d 2280 else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
5f81f4b0
J		 2281 dev_dbg(&dev->pdev->dev,
2282 "SETUP: USB_REQ_CLEAR_FEATURE\n");
5be19a9d
XS		 2283
2284 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
2285 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
2286 struct langwell_ep *epn;
2287 epn = get_ep_by_windex(dev, wIndex);
2288 /* stall if endpoint doesn't exist */
2289 if (!epn) {
2290 ep0_stall(dev);
2291 goto end;
2292 }
2293
2294 if (wValue != 0 || wLength != 0
2295 || epn->ep_num > dev->ep_max)
2296 break;
2297
2298 spin_unlock(&dev->lock);
2299 rc = langwell_ep_set_halt(&epn->ep,
5f81f4b0
J		 2300 (setup->bRequest == USB_REQ_SET_FEATURE)
2301 ? 1 : 0);
5be19a9d
XS		 2302 spin_lock(&dev->lock);
2303
2304 } else if ((setup->bRequestType & (USB_RECIP_MASK
2305 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
2306 | USB_TYPE_STANDARD)) {
3211cbc2
J		 2307 rc = 0;
2308 switch (wValue) {
2309 case USB_DEVICE_REMOTE_WAKEUP:
2310 if (setup->bRequest == USB_REQ_SET_FEATURE) {
2311 dev->remote_wakeup = 1;
2312 dev->dev_status |= (1 << wValue);
2313 } else {
2314 dev->remote_wakeup = 0;
2315 dev->dev_status &= ~(1 << wValue);
2316 }
2317 break;
7fc56f0d
LA		 2318 case USB_DEVICE_TEST_MODE:
2319 dev_dbg(&dev->pdev->dev, "SETUP: TEST MODE\n");
2320 if ((wIndex & 0xff) ||
2321 (dev->gadget.speed != USB_SPEED_HIGH))
2322 ep0_stall(dev);
2323
2324 switch (wIndex >> 8) {
2325 case TEST_J:
2326 case TEST_K:
2327 case TEST_SE0_NAK:
2328 case TEST_PACKET:
2329 case TEST_FORCE_EN:
2330 if (prime_status_phase(dev, EP_DIR_IN))
2331 ep0_stall(dev);
2332 portsc1 = readl(&dev->op_regs->portsc1);
2333 portsc1 |= (wIndex & 0xf00) << 8;
2334 writel(portsc1, &dev->op_regs->portsc1);
2335 goto end;
2336 default:
2337 rc = -EOPNOTSUPP;
2338 }
2339 break;
3211cbc2
J		 2340 default:
2341 rc = -EOPNOTSUPP;
2342 break;
2343 }
2344
5be19a9d
XS		 2345 if (!gadget_is_otg(&dev->gadget))
2346 break;
2347 else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) {
2348 dev->gadget.b_hnp_enable = 1;
2349#ifdef OTG_TRANSCEIVER
2350 if (!dev->lotg->otg.default_a)
2351 dev->lotg->hsm.b_hnp_enable = 1;
2352#endif
2353 } else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
2354 dev->gadget.a_hnp_support = 1;
2355 else if (setup->bRequest ==
2356 USB_DEVICE_A_ALT_HNP_SUPPORT)
2357 dev->gadget.a_alt_hnp_support = 1;
2358 else
2359 break;
5be19a9d
XS		 2360 } else
2361 break;
2362
2363 if (rc == 0) {
2364 if (prime_status_phase(dev, EP_DIR_IN))
2365 ep0_stall(dev);
2366 }
2367 goto end;
2368 }
2369
2370 case USB_REQ_GET_DESCRIPTOR:
5f81f4b0
J		 2371 dev_dbg(&dev->pdev->dev,
2372 "SETUP: USB_REQ_GET_DESCRIPTOR\n");
5be19a9d
XS		 2373 goto delegate;
2374
2375 case USB_REQ_SET_DESCRIPTOR:
5f81f4b0
J		 2376 dev_dbg(&dev->pdev->dev,
2377 "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
5be19a9d
XS		 2378 goto delegate;
2379
2380 case USB_REQ_GET_CONFIGURATION:
5f81f4b0
J		 2381 dev_dbg(&dev->pdev->dev,
2382 "SETUP: USB_REQ_GET_CONFIGURATION\n");
5be19a9d
XS		 2383 goto delegate;
2384
2385 case USB_REQ_SET_CONFIGURATION:
5f81f4b0
J		 2386 dev_dbg(&dev->pdev->dev,
2387 "SETUP: USB_REQ_SET_CONFIGURATION\n");
5be19a9d
XS		 2388 goto delegate;
2389
2390 case USB_REQ_GET_INTERFACE:
5f81f4b0
J		 2391 dev_dbg(&dev->pdev->dev,
2392 "SETUP: USB_REQ_GET_INTERFACE\n");
5be19a9d
XS		 2393 goto delegate;
2394
2395 case USB_REQ_SET_INTERFACE:
5f81f4b0
J		 2396 dev_dbg(&dev->pdev->dev,
2397 "SETUP: USB_REQ_SET_INTERFACE\n");
5be19a9d
XS		 2398 goto delegate;
2399
2400 case USB_REQ_SYNCH_FRAME:
5f81f4b0
J		 2401 dev_dbg(&dev->pdev->dev,
2402 "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
5be19a9d
XS		 2403 goto delegate;
2404
2405 default:
2406 /* delegate USB standard requests to the gadget driver */
2407 goto delegate;
2408delegate:
2409 /* USB requests handled by gadget */
2410 if (wLength) {
2411 /* DATA phase from gadget, STATUS phase from udc */
2412 dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
2413 ? USB_DIR_IN : USB_DIR_OUT;
5f81f4b0
J		 2414 dev_vdbg(&dev->pdev->dev,
2415 "dev->ep0_dir = 0x%x, wLength = %d\n",
5be19a9d
XS		 2416 dev->ep0_dir, wLength);
2417 spin_unlock(&dev->lock);
2418 if (dev->driver->setup(&dev->gadget,
2419 &dev->local_setup_buff) < 0)
2420 ep0_stall(dev);
2421 spin_lock(&dev->lock);
2422 dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
2423 ? DATA_STATE_XMIT : DATA_STATE_RECV;
2424 } else {
2425 /* no DATA phase, IN STATUS phase from gadget */
2426 dev->ep0_dir = USB_DIR_IN;
5f81f4b0
J		 2427 dev_vdbg(&dev->pdev->dev,
2428 "dev->ep0_dir = 0x%x, wLength = %d\n",
5be19a9d
XS		 2429 dev->ep0_dir, wLength);
2430 spin_unlock(&dev->lock);
2431 if (dev->driver->setup(&dev->gadget,
2432 &dev->local_setup_buff) < 0)
2433 ep0_stall(dev);
2434 spin_lock(&dev->lock);
2435 dev->ep0_state = WAIT_FOR_OUT_STATUS;
2436 }
2437 break;
2438 }
2439end:
5f81f4b0 2440 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2441}
2442
2443
2444/* transfer completion, process endpoint request and free the completed dTDs
2445 * for this request
2446 */
2447static int process_ep_req(struct langwell_udc *dev, int index,
2448 struct langwell_request *curr_req)
2449{
2450 struct langwell_dtd *curr_dtd;
2451 struct langwell_dqh *curr_dqh;
2452 int td_complete, actual, remaining_length;
2453 int i, dir;
2454 u8 dtd_status = 0;
2455 int retval = 0;
2456
2457 curr_dqh = &dev->ep_dqh[index];
2458 dir = index % 2;
2459
2460 curr_dtd = curr_req->head;
2461 td_complete = 0;
2462 actual = curr_req->req.length;
2463
5f81f4b0 2464 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2465
2466 for (i = 0; i < curr_req->dtd_count; i++) {
5be19a9d
XS		 2467
2468 /* command execution states by dTD */
2469 dtd_status = curr_dtd->dtd_status;
2470
c8458d59
CL		 2471 barrier();
2472 remaining_length = le16_to_cpu(curr_dtd->dtd_total);
2473 actual -= remaining_length;
2474
5be19a9d
XS		 2475 if (!dtd_status) {
2476 /* transfers completed successfully */
2477 if (!remaining_length) {
2478 td_complete++;
5f81f4b0
J		 2479 dev_vdbg(&dev->pdev->dev,
2480 "dTD transmitted successfully\n");
5be19a9d
XS		 2481 } else {
2482 if (dir) {
5f81f4b0
J		 2483 dev_vdbg(&dev->pdev->dev,
2484 "TX dTD remains data\n");
5be19a9d
XS		 2485 retval = -EPROTO;
2486 break;
2487
2488 } else {
2489 td_complete++;
2490 break;
2491 }
2492 }
2493 } else {
2494 /* transfers completed with errors */
2495 if (dtd_status & DTD_STS_ACTIVE) {
5f81f4b0
J		 2496 dev_dbg(&dev->pdev->dev,
2497 "dTD status ACTIVE dQH[%d]\n", index);
5be19a9d
XS		 2498 retval = 1;
2499 return retval;
2500 } else if (dtd_status & DTD_STS_HALTED) {
5f81f4b0
J		 2501 dev_err(&dev->pdev->dev,
2502 "dTD error %08x dQH[%d]\n",
2503 dtd_status, index);
5be19a9d
XS		 2504 /* clear the errors and halt condition */
2505 curr_dqh->dtd_status = 0;
2506 retval = -EPIPE;
2507 break;
2508 } else if (dtd_status & DTD_STS_DBE) {
5f81f4b0
J		 2509 dev_dbg(&dev->pdev->dev,
2510 "data buffer (overflow) error\n");
5be19a9d
XS		 2511 retval = -EPROTO;
2512 break;
2513 } else if (dtd_status & DTD_STS_TRE) {
5f81f4b0
J		 2514 dev_dbg(&dev->pdev->dev,
2515 "transaction(ISO) error\n");
5be19a9d
XS		 2516 retval = -EILSEQ;
2517 break;
2518 } else
5f81f4b0
J		 2519 dev_err(&dev->pdev->dev,
2520 "unknown error (0x%x)!\n",
2521 dtd_status);
5be19a9d
XS		 2522 }
2523
2524 if (i != curr_req->dtd_count - 1)
2525 curr_dtd = (struct langwell_dtd *)
2526 curr_dtd->next_dtd_virt;
2527 }
2528
2529 if (retval)
2530 return retval;
2531
2532 curr_req->req.actual = actual;
2533
5f81f4b0 2534 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2535 return 0;
2536}
2537
2538
2539/* complete DATA or STATUS phase of ep0 prime status phase if needed */
2540static void ep0_req_complete(struct langwell_udc *dev,
2541 struct langwell_ep *ep0, struct langwell_request *req)
2542{
2543 u32 new_addr;
5f81f4b0 2544 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2545
2546 if (dev->usb_state == USB_STATE_ADDRESS) {
2547 /* set the new address */
2548 new_addr = (u32)dev->dev_addr;
2549 writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
2550
2551 new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
5f81f4b0 2552 dev_vdbg(&dev->pdev->dev, "new_addr = %d\n", new_addr);
5be19a9d
XS		 2553 }
2554
2555 done(ep0, req, 0);
2556
2557 switch (dev->ep0_state) {
2558 case DATA_STATE_XMIT:
2559 /* receive status phase */
2560 if (prime_status_phase(dev, EP_DIR_OUT))
2561 ep0_stall(dev);
2562 break;
2563 case DATA_STATE_RECV:
2564 /* send status phase */
2565 if (prime_status_phase(dev, EP_DIR_IN))
2566 ep0_stall(dev);
2567 break;
2568 case WAIT_FOR_OUT_STATUS:
2569 dev->ep0_state = WAIT_FOR_SETUP;
2570 break;
2571 case WAIT_FOR_SETUP:
5f81f4b0 2572 dev_err(&dev->pdev->dev, "unexpect ep0 packets\n");
5be19a9d
XS		 2573 break;
2574 default:
2575 ep0_stall(dev);
2576 break;
2577 }
2578
5f81f4b0 2579 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2580}
2581
2582
2583/* USB transfer completion interrupt */
2584static void handle_trans_complete(struct langwell_udc *dev)
2585{
2586 u32 complete_bits;
2587 int i, ep_num, dir, bit_mask, status;
2588 struct langwell_ep *epn;
2589 struct langwell_request *curr_req, *temp_req;
2590
5f81f4b0 2591 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2592
2593 complete_bits = readl(&dev->op_regs->endptcomplete);
5f81f4b0
J		 2594 dev_vdbg(&dev->pdev->dev, "endptcomplete register: 0x%08x\n",
2595 complete_bits);
5be19a9d
XS		 2596
2597 /* Write-Clear the bits in endptcomplete register */
2598 writel(complete_bits, &dev->op_regs->endptcomplete);
2599
2600 if (!complete_bits) {
5f81f4b0 2601 dev_dbg(&dev->pdev->dev, "complete_bits = 0\n");
5be19a9d
XS		 2602 goto done;
2603 }
2604
2605 for (i = 0; i < dev->ep_max; i++) {
2606 ep_num = i / 2;
2607 dir = i % 2;
2608
2609 bit_mask = 1 << (ep_num + 16 * dir);
2610
2611 if (!(complete_bits & bit_mask))
2612 continue;
2613
2614 /* ep0 */
2615 if (i == 1)
2616 epn = &dev->ep[0];
2617 else
2618 epn = &dev->ep[i];
2619
2620 if (epn->name == NULL) {
5f81f4b0 2621 dev_warn(&dev->pdev->dev, "invalid endpoint\n");
5be19a9d
XS		 2622 continue;
2623 }
2624
2625 if (i < 2)
2626 /* ep0 in and out */
5f81f4b0 2627 dev_dbg(&dev->pdev->dev, "%s-%s transfer completed\n",
5be19a9d
XS		 2628 epn->name,
2629 is_in(epn) ? "in" : "out");
2630 else
5f81f4b0
J		 2631 dev_dbg(&dev->pdev->dev, "%s transfer completed\n",
2632 epn->name);
5be19a9d
XS		 2633
2634 /* process the req queue until an uncomplete request */
2635 list_for_each_entry_safe(curr_req, temp_req,
2636 &epn->queue, queue) {
2637 status = process_ep_req(dev, i, curr_req);
5f81f4b0
J		 2638 dev_vdbg(&dev->pdev->dev, "%s req status: %d\n",
2639 epn->name, status);
5be19a9d
XS		 2640
2641 if (status)
2642 break;
2643
2644 /* write back status to req */
2645 curr_req->req.status = status;
2646
2647 /* ep0 request completion */
2648 if (ep_num == 0) {
2649 ep0_req_complete(dev, epn, curr_req);
2650 break;
2651 } else {
2652 done(epn, curr_req, status);
2653 }
2654 }
2655 }
2656done:
5f81f4b0 2657 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2658}
2659
2660
2661/* port change detect interrupt handler */
2662static void handle_port_change(struct langwell_udc *dev)
2663{
2664 u32 portsc1, devlc;
2665 u32 speed;
2666
5f81f4b0 2667 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2668
2669 if (dev->bus_reset)
2670 dev->bus_reset = 0;
2671
2672 portsc1 = readl(&dev->op_regs->portsc1);
2673 devlc = readl(&dev->op_regs->devlc);
5f81f4b0 2674 dev_vdbg(&dev->pdev->dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
5be19a9d
XS		 2675 portsc1, devlc);
2676
2677 /* bus reset is finished */
2678 if (!(portsc1 & PORTS_PR)) {
2679 /* get the speed */
2680 speed = LPM_PSPD(devlc);
2681 switch (speed) {
2682 case LPM_SPEED_HIGH:
2683 dev->gadget.speed = USB_SPEED_HIGH;
2684 break;
2685 case LPM_SPEED_FULL:
2686 dev->gadget.speed = USB_SPEED_FULL;
2687 break;
2688 case LPM_SPEED_LOW:
2689 dev->gadget.speed = USB_SPEED_LOW;
2690 break;
2691 default:
2692 dev->gadget.speed = USB_SPEED_UNKNOWN;
2693 break;
2694 }
5f81f4b0
J		 2695 dev_vdbg(&dev->pdev->dev,
2696 "speed = %d, dev->gadget.speed = %d\n",
5be19a9d
XS		 2697 speed, dev->gadget.speed);
2698 }
2699
2700 /* LPM L0 to L1 */
2701 if (dev->lpm && dev->lpm_state == LPM_L0)
2702 if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
5f81f4b0
J		 2703 dev_info(&dev->pdev->dev, "LPM L0 to L1\n");
2704 dev->lpm_state = LPM_L1;
5be19a9d
XS		 2705 }
2706
2707 /* LPM L1 to L0, force resume or remote wakeup finished */
2708 if (dev->lpm && dev->lpm_state == LPM_L1)
2709 if (!(portsc1 & PORTS_SUSP)) {
5f81f4b0 2710 dev_info(&dev->pdev->dev, "LPM L1 to L0\n");
5be19a9d
XS		 2711 dev->lpm_state = LPM_L0;
2712 }
2713
2714 /* update USB state */
2715 if (!dev->resume_state)
2716 dev->usb_state = USB_STATE_DEFAULT;
2717
5f81f4b0 2718 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2719}
2720
2721
2722/* USB reset interrupt handler */
2723static void handle_usb_reset(struct langwell_udc *dev)
2724{
2725 u32 deviceaddr,
2726 endptsetupstat,
2727 endptcomplete;
2728 unsigned long timeout;
2729
5f81f4b0 2730 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2731
2732 /* Write-Clear the device address */
2733 deviceaddr = readl(&dev->op_regs->deviceaddr);
2734 writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
2735
2736 dev->dev_addr = 0;
2737
2738 /* clear usb state */
2739 dev->resume_state = 0;
2740
2741 /* LPM L1 to L0, reset */
2742 if (dev->lpm)
2743 dev->lpm_state = LPM_L0;
2744
2745 dev->ep0_dir = USB_DIR_OUT;
2746 dev->ep0_state = WAIT_FOR_SETUP;
3211cbc2
J		 2747
2748 /* remote wakeup reset to 0 when the device is reset */
2749 dev->remote_wakeup = 0;
2750 dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
5be19a9d
XS		 2751 dev->gadget.b_hnp_enable = 0;
2752 dev->gadget.a_hnp_support = 0;
2753 dev->gadget.a_alt_hnp_support = 0;
2754
2755 /* Write-Clear all the setup token semaphores */
2756 endptsetupstat = readl(&dev->op_regs->endptsetupstat);
2757 writel(endptsetupstat, &dev->op_regs->endptsetupstat);
2758
2759 /* Write-Clear all the endpoint complete status bits */
2760 endptcomplete = readl(&dev->op_regs->endptcomplete);
2761 writel(endptcomplete, &dev->op_regs->endptcomplete);
2762
2763 /* wait until all endptprime bits cleared */
2764 timeout = jiffies + PRIME_TIMEOUT;
2765 while (readl(&dev->op_regs->endptprime)) {
2766 if (time_after(jiffies, timeout)) {
5f81f4b0 2767 dev_err(&dev->pdev->dev, "USB reset timeout\n");
5be19a9d
XS		 2768 break;
2769 }
2770 cpu_relax();
2771 }
2772
2773 /* write 1s to endptflush register to clear any primed buffers */
2774 writel((u32) ~0, &dev->op_regs->endptflush);
2775
2776 if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
5f81f4b0 2777 dev_vdbg(&dev->pdev->dev, "USB bus reset\n");
5be19a9d
XS		 2778 /* bus is reseting */
2779 dev->bus_reset = 1;
2780
2781 /* reset all the queues, stop all USB activities */
2782 stop_activity(dev, dev->driver);
2783 dev->usb_state = USB_STATE_DEFAULT;
2784 } else {
5f81f4b0 2785 dev_vdbg(&dev->pdev->dev, "device controller reset\n");
5be19a9d
XS		 2786 /* controller reset */
2787 langwell_udc_reset(dev);
2788
2789 /* reset all the queues, stop all USB activities */
2790 stop_activity(dev, dev->driver);
2791
2792 /* reset ep0 dQH and endptctrl */
2793 ep0_reset(dev);
2794
2795 /* enable interrupt and set controller to run state */
2796 langwell_udc_start(dev);
2797
2798 dev->usb_state = USB_STATE_ATTACHED;
2799 }
2800
2801#ifdef OTG_TRANSCEIVER
2802 /* refer to USB OTG 6.6.2.3 b_hnp_en is cleared */
2803 if (!dev->lotg->otg.default_a)
2804 dev->lotg->hsm.b_hnp_enable = 0;
2805#endif
2806
5f81f4b0 2807 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2808}
2809
2810
2811/* USB bus suspend/resume interrupt */
2812static void handle_bus_suspend(struct langwell_udc *dev)
2813{
5f81f4b0 2814 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2815
2816 dev->resume_state = dev->usb_state;
2817 dev->usb_state = USB_STATE_SUSPENDED;
2818
2819#ifdef OTG_TRANSCEIVER
2820 if (dev->lotg->otg.default_a) {
2821 if (dev->lotg->hsm.b_bus_suspend_vld == 1) {
2822 dev->lotg->hsm.b_bus_suspend = 1;
2823 /* notify transceiver the state changes */
2824 if (spin_trylock(&dev->lotg->wq_lock)) {
2825 langwell_update_transceiver();
2826 spin_unlock(&dev->lotg->wq_lock);
2827 }
2828 }
2829 dev->lotg->hsm.b_bus_suspend_vld++;
2830 } else {
2831 if (!dev->lotg->hsm.a_bus_suspend) {
2832 dev->lotg->hsm.a_bus_suspend = 1;
2833 /* notify transceiver the state changes */
2834 if (spin_trylock(&dev->lotg->wq_lock)) {
2835 langwell_update_transceiver();
2836 spin_unlock(&dev->lotg->wq_lock);
2837 }
2838 }
2839 }
2840#endif
2841
2842 /* report suspend to the driver */
2843 if (dev->driver) {
2844 if (dev->driver->suspend) {
2845 spin_unlock(&dev->lock);
2846 dev->driver->suspend(&dev->gadget);
2847 spin_lock(&dev->lock);
5f81f4b0
J		 2848 dev_dbg(&dev->pdev->dev, "suspend %s\n",
2849 dev->driver->driver.name);
5be19a9d
XS		 2850 }
2851 }
2852
2853 /* enter PHY low power suspend */
513b91b6
J		 2854 if (dev->pdev->device != 0x0829)
2855 langwell_phy_low_power(dev, 0);
5be19a9d 2856
5f81f4b0 2857 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2858}
2859
2860
2861static void handle_bus_resume(struct langwell_udc *dev)
2862{
5f81f4b0 2863 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2864
2865 dev->usb_state = dev->resume_state;
2866 dev->resume_state = 0;
2867
2868 /* exit PHY low power suspend */
513b91b6
J		 2869 if (dev->pdev->device != 0x0829)
2870 langwell_phy_low_power(dev, 0);
5be19a9d
XS		 2871
2872#ifdef OTG_TRANSCEIVER
2873 if (dev->lotg->otg.default_a == 0)
2874 dev->lotg->hsm.a_bus_suspend = 0;
2875#endif
2876
2877 /* report resume to the driver */
2878 if (dev->driver) {
2879 if (dev->driver->resume) {
2880 spin_unlock(&dev->lock);
2881 dev->driver->resume(&dev->gadget);
2882 spin_lock(&dev->lock);
5f81f4b0
J		 2883 dev_dbg(&dev->pdev->dev, "resume %s\n",
2884 dev->driver->driver.name);
5be19a9d
XS		 2885 }
2886 }
2887
5f81f4b0 2888 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2889}
2890
2891
2892/* USB device controller interrupt handler */
2893static irqreturn_t langwell_irq(int irq, void *_dev)
2894{
2895 struct langwell_udc *dev = _dev;
2896 u32 usbsts,
2897 usbintr,
2898 irq_sts,
2899 portsc1;
2900
5f81f4b0 2901 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2902
2903 if (dev->stopped) {
5f81f4b0
J		 2904 dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
2905 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2906 return IRQ_NONE;
2907 }
2908
2909 spin_lock(&dev->lock);
2910
2911 /* USB status */
2912 usbsts = readl(&dev->op_regs->usbsts);
2913
2914 /* USB interrupt enable */
2915 usbintr = readl(&dev->op_regs->usbintr);
2916
2917 irq_sts = usbsts & usbintr;
5f81f4b0
J		 2918 dev_vdbg(&dev->pdev->dev,
2919 "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
5be19a9d
XS		 2920 usbsts, usbintr, irq_sts);
2921
2922 if (!irq_sts) {
5f81f4b0
J		 2923 dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
2924 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2925 spin_unlock(&dev->lock);
2926 return IRQ_NONE;
2927 }
2928
2929 /* Write-Clear interrupt status bits */
2930 writel(irq_sts, &dev->op_regs->usbsts);
2931
2932 /* resume from suspend */
2933 portsc1 = readl(&dev->op_regs->portsc1);
2934 if (dev->usb_state == USB_STATE_SUSPENDED)
2935 if (!(portsc1 & PORTS_SUSP))
2936 handle_bus_resume(dev);
2937
2938 /* USB interrupt */
2939 if (irq_sts & STS_UI) {
5f81f4b0 2940 dev_vdbg(&dev->pdev->dev, "USB interrupt\n");
5be19a9d
XS		 2941
2942 /* setup packet received from ep0 */
2943 if (readl(&dev->op_regs->endptsetupstat)
2944 & EP0SETUPSTAT_MASK) {
5f81f4b0
J		 2945 dev_vdbg(&dev->pdev->dev,
2946 "USB SETUP packet received interrupt\n");
5be19a9d
XS		 2947 /* setup tripwire semaphone */
2948 setup_tripwire(dev);
2949 handle_setup_packet(dev, &dev->local_setup_buff);
2950 }
2951
2952 /* USB transfer completion */
2953 if (readl(&dev->op_regs->endptcomplete)) {
5f81f4b0
J		 2954 dev_vdbg(&dev->pdev->dev,
2955 "USB transfer completion interrupt\n");
5be19a9d
XS		 2956 handle_trans_complete(dev);
2957 }
2958 }
2959
2960 /* SOF received interrupt (for ISO transfer) */
2961 if (irq_sts & STS_SRI) {
2962 /* FIXME */
5f81f4b0 2963 /* dev_vdbg(&dev->pdev->dev, "SOF received interrupt\n"); */
5be19a9d
XS		 2964 }
2965
2966 /* port change detect interrupt */
2967 if (irq_sts & STS_PCI) {
5f81f4b0 2968 dev_vdbg(&dev->pdev->dev, "port change detect interrupt\n");
5be19a9d
XS		 2969 handle_port_change(dev);
2970 }
2971
2972 /* suspend interrrupt */
2973 if (irq_sts & STS_SLI) {
5f81f4b0 2974 dev_vdbg(&dev->pdev->dev, "suspend interrupt\n");
5be19a9d
XS		 2975 handle_bus_suspend(dev);
2976 }
2977
2978 /* USB reset interrupt */
2979 if (irq_sts & STS_URI) {
5f81f4b0 2980 dev_vdbg(&dev->pdev->dev, "USB reset interrupt\n");
5be19a9d
XS		 2981 handle_usb_reset(dev);
2982 }
2983
2984 /* USB error or system error interrupt */
2985 if (irq_sts & (STS_UEI | STS_SEI)) {
2986 /* FIXME */
5f81f4b0 2987 dev_warn(&dev->pdev->dev, "error IRQ, irq_sts: %x\n", irq_sts);
5be19a9d
XS		 2988 }
2989
2990 spin_unlock(&dev->lock);
2991
5f81f4b0 2992 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2993 return IRQ_HANDLED;
2994}
2995
2996
2997/*-------------------------------------------------------------------------*/
2998
2999/* release device structure */
3000static void gadget_release(struct device *_dev)
3001{
3002 struct langwell_udc *dev = the_controller;
3003
5f81f4b0 3004 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3005
3006 complete(dev->done);
3007
5f81f4b0 3008 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3009 kfree(dev);
3010}
3011
3012
912c93d1
J		 3013/* enable SRAM caching if SRAM detected */
3014static void sram_init(struct langwell_udc *dev)
3015{
3016 struct pci_dev *pdev = dev->pdev;
3017
3018 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
3019
3020 dev->sram_addr = pci_resource_start(pdev, 1);
3021 dev->sram_size = pci_resource_len(pdev, 1);
3022 dev_info(&dev->pdev->dev, "Found private SRAM at %x size:%x\n",
3023 dev->sram_addr, dev->sram_size);
3024 dev->got_sram = 1;
3025
3026 if (pci_request_region(pdev, 1, kobject_name(&pdev->dev.kobj))) {
3027 dev_warn(&dev->pdev->dev, "SRAM request failed\n");
3028 dev->got_sram = 0;
3029 } else if (!dma_declare_coherent_memory(&pdev->dev, dev->sram_addr,
3030 dev->sram_addr, dev->sram_size, DMA_MEMORY_MAP)) {
3031 dev_warn(&dev->pdev->dev, "SRAM DMA declare failed\n");
3032 pci_release_region(pdev, 1);
3033 dev->got_sram = 0;
3034 }
3035
3036 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
3037}
3038
3039
3040/* release SRAM caching */
3041static void sram_deinit(struct langwell_udc *dev)
3042{
3043 struct pci_dev *pdev = dev->pdev;
3044
3045 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
3046
3047 dma_release_declared_memory(&pdev->dev);
3048 pci_release_region(pdev, 1);
3049
3050 dev->got_sram = 0;
3051
3052 dev_info(&dev->pdev->dev, "release SRAM caching\n");
3053 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
3054}
3055
3056
5be19a9d
XS		 3057/* tear down the binding between this driver and the pci device */
3058static void langwell_udc_remove(struct pci_dev *pdev)
3059{
3060 struct langwell_udc *dev = the_controller;
3061
3062 DECLARE_COMPLETION(done);
3063
3064 BUG_ON(dev->driver);
5f81f4b0 3065 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3066
3067 dev->done = &done;
3068
912c93d1
J		 3069#ifndef OTG_TRANSCEIVER
3070 /* free dTD dma_pool and dQH */
5be19a9d
XS		 3071 if (dev->dtd_pool)
3072 dma_pool_destroy(dev->dtd_pool);
3073
912c93d1
J		 3074 if (dev->ep_dqh)
3075 dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
3076 dev->ep_dqh, dev->ep_dqh_dma);
3077
3078 /* release SRAM caching */
3079 if (dev->has_sram && dev->got_sram)
3080 sram_deinit(dev);
3081#endif
3082
5be19a9d
XS		 3083 if (dev->status_req) {
3084 kfree(dev->status_req->req.buf);
3085 kfree(dev->status_req);
3086 }
3087
5be19a9d
XS		 3088 kfree(dev->ep);
3089
48e34d0f 3090 /* disable IRQ handler */
5be19a9d
XS		 3091 if (dev->got_irq)
3092 free_irq(pdev->irq, dev);
3093
3094#ifndef OTG_TRANSCEIVER
3095 if (dev->cap_regs)
3096 iounmap(dev->cap_regs);
3097
3098 if (dev->region)
3099 release_mem_region(pci_resource_start(pdev, 0),
3100 pci_resource_len(pdev, 0));
3101
3102 if (dev->enabled)
3103 pci_disable_device(pdev);
3104#else
3105 if (dev->transceiver) {
3106 otg_put_transceiver(dev->transceiver);
3107 dev->transceiver = NULL;
3108 dev->lotg = NULL;
3109 }
3110#endif
3111
3112 dev->cap_regs = NULL;
3113
5f81f4b0
J		 3114 dev_info(&dev->pdev->dev, "unbind\n");
3115 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3116
3117 device_unregister(&dev->gadget.dev);
3118 device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
3211cbc2 3119 device_remove_file(&pdev->dev, &dev_attr_remote_wakeup);
5be19a9d
XS		 3120
3121#ifndef OTG_TRANSCEIVER
3122 pci_set_drvdata(pdev, NULL);
3123#endif
3124
3125 /* free dev, wait for the release() finished */
3126 wait_for_completion(&done);
3127
3128 the_controller = NULL;
3129}
3130
3131
3132/*
3133 * wrap this driver around the specified device, but
3134 * don't respond over USB until a gadget driver binds to us.
3135 */
3136static int langwell_udc_probe(struct pci_dev *pdev,
3137 const struct pci_device_id *id)
3138{
3139 struct langwell_udc *dev;
3140#ifndef OTG_TRANSCEIVER
3141 unsigned long resource, len;
3142#endif
3143 void __iomem *base = NULL;
3144 size_t size;
3145 int retval;
3146
3147 if (the_controller) {
3148 dev_warn(&pdev->dev, "ignoring\n");
3149 return -EBUSY;
3150 }
3151
3152 /* alloc, and start init */
3153 dev = kzalloc(sizeof *dev, GFP_KERNEL);
3154 if (dev == NULL) {
3155 retval = -ENOMEM;
3156 goto error;
3157 }
3158
3159 /* initialize device spinlock */
3160 spin_lock_init(&dev->lock);
3161
3162 dev->pdev = pdev;
5f81f4b0 3163 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3164
3165#ifdef OTG_TRANSCEIVER
3166 /* PCI device is already enabled by otg_transceiver driver */
3167 dev->enabled = 1;
3168
3169 /* mem region and register base */
3170 dev->region = 1;
3171 dev->transceiver = otg_get_transceiver();
3172 dev->lotg = otg_to_langwell(dev->transceiver);
3173 base = dev->lotg->regs;
3174#else
3175 pci_set_drvdata(pdev, dev);
3176
3177 /* now all the pci goodies ... */
3178 if (pci_enable_device(pdev) < 0) {
3179 retval = -ENODEV;
3180 goto error;
3181 }
3182 dev->enabled = 1;
3183
3184 /* control register: BAR 0 */
3185 resource = pci_resource_start(pdev, 0);
3186 len = pci_resource_len(pdev, 0);
3187 if (!request_mem_region(resource, len, driver_name)) {
5f81f4b0 3188 dev_err(&dev->pdev->dev, "controller already in use\n");
5be19a9d
XS		 3189 retval = -EBUSY;
3190 goto error;
3191 }
3192 dev->region = 1;
3193
3194 base = ioremap_nocache(resource, len);
3195#endif
3196 if (base == NULL) {
5f81f4b0 3197 dev_err(&dev->pdev->dev, "can't map memory\n");
5be19a9d
XS		 3198 retval = -EFAULT;
3199 goto error;
3200 }
3201
3202 dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
5f81f4b0 3203 dev_vdbg(&dev->pdev->dev, "dev->cap_regs: %p\n", dev->cap_regs);
5be19a9d
XS		 3204 dev->op_regs = (struct langwell_op_regs __iomem *)
3205 (base + OP_REG_OFFSET);
5f81f4b0 3206 dev_vdbg(&dev->pdev->dev, "dev->op_regs: %p\n", dev->op_regs);
5be19a9d
XS		 3207
3208 /* irq setup after old hardware is cleaned up */
3209 if (!pdev->irq) {
5f81f4b0 3210 dev_err(&dev->pdev->dev, "No IRQ. Check PCI setup!\n");
5be19a9d
XS		 3211 retval = -ENODEV;
3212 goto error;
3213 }
3214
912c93d1
J		 3215 dev->has_sram = 1;
3216 dev->got_sram = 0;
3217 dev_vdbg(&dev->pdev->dev, "dev->has_sram: %d\n", dev->has_sram);
3218
5be19a9d 3219#ifndef OTG_TRANSCEIVER
912c93d1
J		 3220 /* enable SRAM caching if detected */
3221 if (dev->has_sram && !dev->got_sram)
3222 sram_init(dev);
3223
5f81f4b0
J		 3224 dev_info(&dev->pdev->dev,
3225 "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
5be19a9d
XS		 3226 pdev->irq, resource, len, base);
3227 /* enables bus-mastering for device dev */
3228 pci_set_master(pdev);
3229
3230 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
3231 driver_name, dev) != 0) {
5f81f4b0
J		 3232 dev_err(&dev->pdev->dev,
3233 "request interrupt %d failed\n", pdev->irq);
5be19a9d
XS		 3234 retval = -EBUSY;
3235 goto error;
3236 }
3237 dev->got_irq = 1;
3238#endif
3239
3240 /* set stopped bit */
3241 dev->stopped = 1;
3242
3243 /* capabilities and endpoint number */
3244 dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
3245 dev->dciversion = readw(&dev->cap_regs->dciversion);
3246 dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
5f81f4b0
J		 3247 dev_vdbg(&dev->pdev->dev, "dev->lpm: %d\n", dev->lpm);
3248 dev_vdbg(&dev->pdev->dev, "dev->dciversion: 0x%04x\n",
3249 dev->dciversion);
3250 dev_vdbg(&dev->pdev->dev, "dccparams: 0x%08x\n",
3251 readl(&dev->cap_regs->dccparams));
3252 dev_vdbg(&dev->pdev->dev, "dev->devcap: %d\n", dev->devcap);
5be19a9d 3253 if (!dev->devcap) {
5f81f4b0 3254 dev_err(&dev->pdev->dev, "can't support device mode\n");
5be19a9d
XS		 3255 retval = -ENODEV;
3256 goto error;
3257 }
3258
3259 /* a pair of endpoints (out/in) for each address */
3260 dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
5f81f4b0 3261 dev_vdbg(&dev->pdev->dev, "dev->ep_max: %d\n", dev->ep_max);
5be19a9d
XS		 3262
3263 /* allocate endpoints memory */
3264 dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
3265 GFP_KERNEL);
3266 if (!dev->ep) {
5f81f4b0 3267 dev_err(&dev->pdev->dev, "allocate endpoints memory failed\n");
5be19a9d
XS		 3268 retval = -ENOMEM;
3269 goto error;
3270 }
3271
3272 /* allocate device dQH memory */
3273 size = dev->ep_max * sizeof(struct langwell_dqh);
5f81f4b0 3274 dev_vdbg(&dev->pdev->dev, "orig size = %d\n", size);
5be19a9d
XS		 3275 if (size < DQH_ALIGNMENT)
3276 size = DQH_ALIGNMENT;
3277 else if ((size % DQH_ALIGNMENT) != 0) {
3278 size += DQH_ALIGNMENT + 1;
3279 size &= ~(DQH_ALIGNMENT - 1);
3280 }
3281 dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
3282 &dev->ep_dqh_dma, GFP_KERNEL);
3283 if (!dev->ep_dqh) {
5f81f4b0 3284 dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
5be19a9d
XS		 3285 retval = -ENOMEM;
3286 goto error;
3287 }
3288 dev->ep_dqh_size = size;
5f81f4b0 3289 dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %d\n", dev->ep_dqh_size);
5be19a9d
XS		 3290
3291 /* initialize ep0 status request structure */
3292 dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
3293 if (!dev->status_req) {
5f81f4b0
J		 3294 dev_err(&dev->pdev->dev,
3295 "allocate status_req memory failed\n");
5be19a9d
XS		 3296 retval = -ENOMEM;
3297 goto error;
3298 }
3299 INIT_LIST_HEAD(&dev->status_req->queue);
3300
3301 /* allocate a small amount of memory to get valid address */
3302 dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
3303 dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
3304
3305 dev->resume_state = USB_STATE_NOTATTACHED;
3306 dev->usb_state = USB_STATE_POWERED;
3307 dev->ep0_dir = USB_DIR_OUT;
3211cbc2
J		 3308
3309 /* remote wakeup reset to 0 when the device is reset */
3310 dev->remote_wakeup = 0;
3311 dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
5be19a9d
XS		 3312
3313#ifndef OTG_TRANSCEIVER
3314 /* reset device controller */
3315 langwell_udc_reset(dev);
3316#endif
3317
3318 /* initialize gadget structure */
3319 dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
3320 dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
3321 INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
3322 dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
3323 dev->gadget.is_dualspeed = 1; /* support dual speed */
3324#ifdef OTG_TRANSCEIVER
3325 dev->gadget.is_otg = 1; /* support otg mode */
3326#endif
3327
3328 /* the "gadget" abstracts/virtualizes the controller */
3329 dev_set_name(&dev->gadget.dev, "gadget");
3330 dev->gadget.dev.parent = &pdev->dev;
3331 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3332 dev->gadget.dev.release = gadget_release;
3333 dev->gadget.name = driver_name; /* gadget name */
3334
3335 /* controller endpoints reinit */
3336 eps_reinit(dev);
3337
3338#ifndef OTG_TRANSCEIVER
3339 /* reset ep0 dQH and endptctrl */
3340 ep0_reset(dev);
3341#endif
3342
3343 /* create dTD dma_pool resource */
3344 dev->dtd_pool = dma_pool_create("langwell_dtd",
3345 &dev->pdev->dev,
3346 sizeof(struct langwell_dtd),
3347 DTD_ALIGNMENT,
3348 DMA_BOUNDARY);
3349
3350 if (!dev->dtd_pool) {
3351 retval = -ENOMEM;
3352 goto error;
3353 }
3354
3355 /* done */
5f81f4b0
J		 3356 dev_info(&dev->pdev->dev, "%s\n", driver_desc);
3357 dev_info(&dev->pdev->dev, "irq %d, pci mem %p\n", pdev->irq, base);
3358 dev_info(&dev->pdev->dev, "Driver version: " DRIVER_VERSION "\n");
3359 dev_info(&dev->pdev->dev, "Support (max) %d endpoints\n", dev->ep_max);
3360 dev_info(&dev->pdev->dev, "Device interface version: 0x%04x\n",
3361 dev->dciversion);
3362 dev_info(&dev->pdev->dev, "Controller mode: %s\n",
3363 dev->devcap ? "Device" : "Host");
3364 dev_info(&dev->pdev->dev, "Support USB LPM: %s\n",
3365 dev->lpm ? "Yes" : "No");
3366
3367 dev_vdbg(&dev->pdev->dev,
3368 "After langwell_udc_probe(), print all registers:\n");
5be19a9d 3369 print_all_registers(dev);
5be19a9d
XS		 3370
3371 the_controller = dev;
3372
3373 retval = device_register(&dev->gadget.dev);
3374 if (retval)
3375 goto error;
3376
0f91349b
SAS		 3377 retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
3378 if (retval)
3379 goto error;
3380
5be19a9d
XS		 3381 retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
3382 if (retval)
3383 goto error;
3384
3211cbc2
J		 3385 retval = device_create_file(&pdev->dev, &dev_attr_remote_wakeup);
3386 if (retval)
3387 goto error_attr1;
3388
5f81f4b0 3389 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3390 return 0;
3391
3211cbc2
J		 3392error_attr1:
3393 device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
5be19a9d
XS		 3394error:
3395 if (dev) {
5f81f4b0 3396 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3397 langwell_udc_remove(pdev);
3398 }
3399
3400 return retval;
3401}
3402
3403
3404/* device controller suspend */
3405static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
3406{
3407 struct langwell_udc *dev = the_controller;
5be19a9d 3408
5f81f4b0 3409 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 3410
0f91349b 3411 usb_del_gadget_udc(&dev->gadget);
5be19a9d
XS		 3412 /* disable interrupt and set controller to stop state */
3413 langwell_udc_stop(dev);
3414
48e34d0f 3415 /* disable IRQ handler */
5be19a9d
XS		 3416 if (dev->got_irq)
3417 free_irq(pdev->irq, dev);
3418 dev->got_irq = 0;
3419
5be19a9d
XS		 3420 /* save PCI state */
3421 pci_save_state(pdev);
3422
cf7d3c8e
PS		 3423 spin_lock_irq(&dev->lock);
3424 /* stop all usb activities */
3425 stop_activity(dev, dev->driver);
3426 spin_unlock_irq(&dev->lock);
3427
912c93d1
J		 3428 /* free dTD dma_pool and dQH */
3429 if (dev->dtd_pool)
3430 dma_pool_destroy(dev->dtd_pool);
3431
3432 if (dev->ep_dqh)
3433 dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
3434 dev->ep_dqh, dev->ep_dqh_dma);
3435
3436 /* release SRAM caching */
3437 if (dev->has_sram && dev->got_sram)
3438 sram_deinit(dev);
3439
5be19a9d
XS		 3440 /* set device power state */
3441 pci_set_power_state(pdev, PCI_D3hot);
3442
3443 /* enter PHY low power suspend */
513b91b6
J		 3444 if (dev->pdev->device != 0x0829)
3445 langwell_phy_low_power(dev, 1);
5be19a9d 3446
5f81f4b0 3447 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3448 return 0;
3449}
3450
3451
3452/* device controller resume */
3453static int langwell_udc_resume(struct pci_dev *pdev)
3454{
3455 struct langwell_udc *dev = the_controller;
912c93d1 3456 size_t size;
5be19a9d 3457
5f81f4b0 3458 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3459
3460 /* exit PHY low power suspend */
513b91b6
J		 3461 if (dev->pdev->device != 0x0829)
3462 langwell_phy_low_power(dev, 0);
5be19a9d
XS		 3463
3464 /* set device D0 power state */
3465 pci_set_power_state(pdev, PCI_D0);
3466
912c93d1
J		 3467 /* enable SRAM caching if detected */
3468 if (dev->has_sram && !dev->got_sram)
3469 sram_init(dev);
3470
3471 /* allocate device dQH memory */
3472 size = dev->ep_max * sizeof(struct langwell_dqh);
3473 dev_vdbg(&dev->pdev->dev, "orig size = %d\n", size);
3474 if (size < DQH_ALIGNMENT)
3475 size = DQH_ALIGNMENT;
3476 else if ((size % DQH_ALIGNMENT) != 0) {
3477 size += DQH_ALIGNMENT + 1;
3478 size &= ~(DQH_ALIGNMENT - 1);
3479 }
3480 dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
3481 &dev->ep_dqh_dma, GFP_KERNEL);
3482 if (!dev->ep_dqh) {
3483 dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
3484 return -ENOMEM;
3485 }
3486 dev->ep_dqh_size = size;
3487 dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %d\n", dev->ep_dqh_size);
3488
3489 /* create dTD dma_pool resource */
3490 dev->dtd_pool = dma_pool_create("langwell_dtd",
3491 &dev->pdev->dev,
3492 sizeof(struct langwell_dtd),
3493 DTD_ALIGNMENT,
3494 DMA_BOUNDARY);
3495
3496 if (!dev->dtd_pool)
3497 return -ENOMEM;
3498
5be19a9d
XS		 3499 /* restore PCI state */
3500 pci_restore_state(pdev);
3501
3502 /* enable IRQ handler */
5f81f4b0
J		 3503 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
3504 driver_name, dev) != 0) {
3505 dev_err(&dev->pdev->dev, "request interrupt %d failed\n",
3506 pdev->irq);
3507 return -EBUSY;
5be19a9d
XS		 3508 }
3509 dev->got_irq = 1;
3510
3511 /* reset and start controller to run state */
3512 if (dev->stopped) {
3513 /* reset device controller */
3514 langwell_udc_reset(dev);
3515
3516 /* reset ep0 dQH and endptctrl */
3517 ep0_reset(dev);
3518
3519 /* start device if gadget is loaded */
3520 if (dev->driver)
3521 langwell_udc_start(dev);
3522 }
3523
3524 /* reset USB status */
3525 dev->usb_state = USB_STATE_ATTACHED;
3526 dev->ep0_state = WAIT_FOR_SETUP;
3527 dev->ep0_dir = USB_DIR_OUT;
3528
5f81f4b0 3529 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3530 return 0;
3531}
3532
3533
3534/* pci driver shutdown */
3535static void langwell_udc_shutdown(struct pci_dev *pdev)
3536{
3537 struct langwell_udc *dev = the_controller;
3538 u32 usbmode;
3539
5f81f4b0 3540 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3541
3542 /* reset controller mode to IDLE */
3543 usbmode = readl(&dev->op_regs->usbmode);
5f81f4b0 3544 dev_dbg(&dev->pdev->dev, "usbmode = 0x%08x\n", usbmode);
5be19a9d
XS		 3545 usbmode &= (~3 | MODE_IDLE);
3546 writel(usbmode, &dev->op_regs->usbmode);
3547
5f81f4b0 3548 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3549}
3550
3551/*-------------------------------------------------------------------------*/
3552
3553static const struct pci_device_id pci_ids[] = { {
3554 .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
3555 .class_mask = ~0,
3556 .vendor = 0x8086,
3557 .device = 0x0811,
3558 .subvendor = PCI_ANY_ID,
3559 .subdevice = PCI_ANY_ID,
3560}, { /* end: all zeroes */ }
3561};
3562
5be19a9d
XS		 3563MODULE_DEVICE_TABLE(pci, pci_ids);
3564
3565
3566static struct pci_driver langwell_pci_driver = {
3567 .name = (char *) driver_name,
3568 .id_table = pci_ids,
3569
3570 .probe = langwell_udc_probe,
3571 .remove = langwell_udc_remove,
3572
3573 /* device controller suspend/resume */
3574 .suspend = langwell_udc_suspend,
3575 .resume = langwell_udc_resume,
3576
3577 .shutdown = langwell_udc_shutdown,
3578};
3579
3580
5be19a9d
XS		 3581static int __init init(void)
3582{
3583#ifdef OTG_TRANSCEIVER
3584 return langwell_register_peripheral(&langwell_pci_driver);
3585#else
3586 return pci_register_driver(&langwell_pci_driver);
3587#endif
3588}
3589module_init(init);
3590
3591
3592static void __exit cleanup(void)
3593{
3594#ifdef OTG_TRANSCEIVER
3595 return langwell_unregister_peripheral(&langwell_pci_driver);
3596#else
3597 pci_unregister_driver(&langwell_pci_driver);
3598#endif
3599}
3600module_exit(cleanup);
3601
5f81f4b0
J		 3602
3603MODULE_DESCRIPTION(DRIVER_DESC);
3604MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
3605MODULE_VERSION(DRIVER_VERSION);
3606MODULE_LICENSE("GPL");
3607
kernel source for telekom puls (alcatel/mediatek)