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USB: langwell: USB Client Remote Wakeup Support
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / langwell_udc.c
CommitLineData
5be19a9d
XS		 1/*
2 * Intel Langwell USB Device Controller driver
3 * Copyright (C) 2008-2009, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20
21/* #undef DEBUG */
5f81f4b0 22/* #undef VERBOSE_DEBUG */
5be19a9d
XS		 23
24#if defined(CONFIG_USB_LANGWELL_OTG)
25#define OTG_TRANSCEIVER
26#endif
27
28
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/kernel.h>
33#include <linux/delay.h>
34#include <linux/ioport.h>
35#include <linux/sched.h>
36#include <linux/slab.h>
5be19a9d
XS		 37#include <linux/errno.h>
38#include <linux/init.h>
39#include <linux/timer.h>
40#include <linux/list.h>
41#include <linux/interrupt.h>
42#include <linux/moduleparam.h>
43#include <linux/device.h>
44#include <linux/usb/ch9.h>
45#include <linux/usb/gadget.h>
46#include <linux/usb/otg.h>
47#include <linux/pm.h>
48#include <linux/io.h>
49#include <linux/irq.h>
50#include <asm/system.h>
51#include <asm/unaligned.h>
52
53#include "langwell_udc.h"
54
55
56#define DRIVER_DESC "Intel Langwell USB Device Controller driver"
57#define DRIVER_VERSION "16 May 2009"
58
59static const char driver_name[] = "langwell_udc";
60static const char driver_desc[] = DRIVER_DESC;
61
62
63/* controller device global variable */
64static struct langwell_udc *the_controller;
65
66/* for endpoint 0 operations */
67static const struct usb_endpoint_descriptor
68langwell_ep0_desc = {
69 .bLength = USB_DT_ENDPOINT_SIZE,
70 .bDescriptorType = USB_DT_ENDPOINT,
71 .bEndpointAddress = 0,
72 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
73 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
74};
75
76
77/*-------------------------------------------------------------------------*/
78/* debugging */
79
5f81f4b0 80#ifdef VERBOSE_DEBUG
5be19a9d
XS		 81static inline void print_all_registers(struct langwell_udc *dev)
82{
83 int i;
84
85 /* Capability Registers */
5f81f4b0
J		 86 dev_dbg(&dev->pdev->dev,
87 "Capability Registers (offset: 0x%04x, length: 0x%08x)\n",
88 CAP_REG_OFFSET, (u32)sizeof(struct langwell_cap_regs));
89 dev_dbg(&dev->pdev->dev, "caplength=0x%02x\n",
5be19a9d 90 readb(&dev->cap_regs->caplength));
5f81f4b0 91 dev_dbg(&dev->pdev->dev, "hciversion=0x%04x\n",
5be19a9d 92 readw(&dev->cap_regs->hciversion));
5f81f4b0 93 dev_dbg(&dev->pdev->dev, "hcsparams=0x%08x\n",
5be19a9d 94 readl(&dev->cap_regs->hcsparams));
5f81f4b0 95 dev_dbg(&dev->pdev->dev, "hccparams=0x%08x\n",
5be19a9d 96 readl(&dev->cap_regs->hccparams));
5f81f4b0 97 dev_dbg(&dev->pdev->dev, "dciversion=0x%04x\n",
5be19a9d 98 readw(&dev->cap_regs->dciversion));
5f81f4b0 99 dev_dbg(&dev->pdev->dev, "dccparams=0x%08x\n",
5be19a9d
XS		 100 readl(&dev->cap_regs->dccparams));
101
102 /* Operational Registers */
5f81f4b0
J		 103 dev_dbg(&dev->pdev->dev,
104 "Operational Registers (offset: 0x%04x, length: 0x%08x)\n",
105 OP_REG_OFFSET, (u32)sizeof(struct langwell_op_regs));
106 dev_dbg(&dev->pdev->dev, "extsts=0x%08x\n",
5be19a9d 107 readl(&dev->op_regs->extsts));
5f81f4b0 108 dev_dbg(&dev->pdev->dev, "extintr=0x%08x\n",
5be19a9d 109 readl(&dev->op_regs->extintr));
5f81f4b0 110 dev_dbg(&dev->pdev->dev, "usbcmd=0x%08x\n",
5be19a9d 111 readl(&dev->op_regs->usbcmd));
5f81f4b0 112 dev_dbg(&dev->pdev->dev, "usbsts=0x%08x\n",
5be19a9d 113 readl(&dev->op_regs->usbsts));
5f81f4b0 114 dev_dbg(&dev->pdev->dev, "usbintr=0x%08x\n",
5be19a9d 115 readl(&dev->op_regs->usbintr));
5f81f4b0 116 dev_dbg(&dev->pdev->dev, "frindex=0x%08x\n",
5be19a9d 117 readl(&dev->op_regs->frindex));
5f81f4b0 118 dev_dbg(&dev->pdev->dev, "ctrldssegment=0x%08x\n",
5be19a9d 119 readl(&dev->op_regs->ctrldssegment));
5f81f4b0 120 dev_dbg(&dev->pdev->dev, "deviceaddr=0x%08x\n",
5be19a9d 121 readl(&dev->op_regs->deviceaddr));
5f81f4b0 122 dev_dbg(&dev->pdev->dev, "endpointlistaddr=0x%08x\n",
5be19a9d 123 readl(&dev->op_regs->endpointlistaddr));
5f81f4b0 124 dev_dbg(&dev->pdev->dev, "ttctrl=0x%08x\n",
5be19a9d 125 readl(&dev->op_regs->ttctrl));
5f81f4b0 126 dev_dbg(&dev->pdev->dev, "burstsize=0x%08x\n",
5be19a9d 127 readl(&dev->op_regs->burstsize));
5f81f4b0 128 dev_dbg(&dev->pdev->dev, "txfilltuning=0x%08x\n",
5be19a9d 129 readl(&dev->op_regs->txfilltuning));
5f81f4b0 130 dev_dbg(&dev->pdev->dev, "txttfilltuning=0x%08x\n",
5be19a9d 131 readl(&dev->op_regs->txttfilltuning));
5f81f4b0 132 dev_dbg(&dev->pdev->dev, "ic_usb=0x%08x\n",
5be19a9d 133 readl(&dev->op_regs->ic_usb));
5f81f4b0 134 dev_dbg(&dev->pdev->dev, "ulpi_viewport=0x%08x\n",
5be19a9d 135 readl(&dev->op_regs->ulpi_viewport));
5f81f4b0 136 dev_dbg(&dev->pdev->dev, "configflag=0x%08x\n",
5be19a9d 137 readl(&dev->op_regs->configflag));
5f81f4b0 138 dev_dbg(&dev->pdev->dev, "portsc1=0x%08x\n",
5be19a9d 139 readl(&dev->op_regs->portsc1));
5f81f4b0 140 dev_dbg(&dev->pdev->dev, "devlc=0x%08x\n",
5be19a9d 141 readl(&dev->op_regs->devlc));
5f81f4b0 142 dev_dbg(&dev->pdev->dev, "otgsc=0x%08x\n",
5be19a9d 143 readl(&dev->op_regs->otgsc));
5f81f4b0 144 dev_dbg(&dev->pdev->dev, "usbmode=0x%08x\n",
5be19a9d 145 readl(&dev->op_regs->usbmode));
5f81f4b0 146 dev_dbg(&dev->pdev->dev, "endptnak=0x%08x\n",
5be19a9d 147 readl(&dev->op_regs->endptnak));
5f81f4b0 148 dev_dbg(&dev->pdev->dev, "endptnaken=0x%08x\n",
5be19a9d 149 readl(&dev->op_regs->endptnaken));
5f81f4b0 150 dev_dbg(&dev->pdev->dev, "endptsetupstat=0x%08x\n",
5be19a9d 151 readl(&dev->op_regs->endptsetupstat));
5f81f4b0 152 dev_dbg(&dev->pdev->dev, "endptprime=0x%08x\n",
5be19a9d 153 readl(&dev->op_regs->endptprime));
5f81f4b0 154 dev_dbg(&dev->pdev->dev, "endptflush=0x%08x\n",
5be19a9d 155 readl(&dev->op_regs->endptflush));
5f81f4b0 156 dev_dbg(&dev->pdev->dev, "endptstat=0x%08x\n",
5be19a9d 157 readl(&dev->op_regs->endptstat));
5f81f4b0 158 dev_dbg(&dev->pdev->dev, "endptcomplete=0x%08x\n",
5be19a9d
XS		 159 readl(&dev->op_regs->endptcomplete));
160
161 for (i = 0; i < dev->ep_max / 2; i++) {
5f81f4b0 162 dev_dbg(&dev->pdev->dev, "endptctrl[%d]=0x%08x\n",
5be19a9d
XS		 163 i, readl(&dev->op_regs->endptctrl[i]));
164 }
165}
5f81f4b0
J		 166#else
167
168#define print_all_registers(dev) do { } while (0)
169
170#endif /* VERBOSE_DEBUG */
5be19a9d
XS		 171
172
173/*-------------------------------------------------------------------------*/
174
5f81f4b0
J		 175#define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
176 USB_DIR_IN) : (usb_endpoint_dir_in((ep)->desc)))
5be19a9d 177
5f81f4b0 178#define DIR_STRING(ep) (is_in(ep) ? "in" : "out")
5be19a9d
XS		 179
180
5f81f4b0 181static char *type_string(const struct usb_endpoint_descriptor *desc)
5be19a9d 182{
5f81f4b0 183 switch (usb_endpoint_type(desc)) {
5be19a9d
XS		 184 case USB_ENDPOINT_XFER_BULK:
185 return "bulk";
186 case USB_ENDPOINT_XFER_ISOC:
187 return "iso";
188 case USB_ENDPOINT_XFER_INT:
189 return "int";
190 };
191
192 return "control";
193}
5be19a9d
XS		 194
195
196/* configure endpoint control registers */
197static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
198 unsigned char is_in, unsigned char ep_type)
199{
200 struct langwell_udc *dev;
201 u32 endptctrl;
202
203 dev = ep->dev;
5f81f4b0 204 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 205
206 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
207 if (is_in) { /* TX */
208 if (ep_num)
209 endptctrl |= EPCTRL_TXR;
210 endptctrl |= EPCTRL_TXE;
211 endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
212 } else { /* RX */
213 if (ep_num)
214 endptctrl |= EPCTRL_RXR;
215 endptctrl |= EPCTRL_RXE;
216 endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
217 }
218
219 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
220
5f81f4b0 221 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 222}
223
224
225/* reset ep0 dQH and endptctrl */
226static void ep0_reset(struct langwell_udc *dev)
227{
228 struct langwell_ep *ep;
229 int i;
230
5f81f4b0 231 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 232
233 /* ep0 in and out */
234 for (i = 0; i < 2; i++) {
235 ep = &dev->ep[i];
236 ep->dev = dev;
237
238 /* ep0 dQH */
239 ep->dqh = &dev->ep_dqh[i];
240
241 /* configure ep0 endpoint capabilities in dQH */
242 ep->dqh->dqh_ios = 1;
243 ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
244
3eed298f 245 /* enable ep0-in HW zero length termination select */
5be19a9d
XS		 246 if (is_in(ep))
247 ep->dqh->dqh_zlt = 0;
248 ep->dqh->dqh_mult = 0;
249
3eed298f
J		 250 ep->dqh->dtd_next = DTD_TERM;
251
5be19a9d
XS		 252 /* configure ep0 control registers */
253 ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
254 }
255
5f81f4b0 256 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 257 return;
258}
259
260
261/*-------------------------------------------------------------------------*/
262
263/* endpoints operations */
264
265/* configure endpoint, making it usable */
266static int langwell_ep_enable(struct usb_ep *_ep,
267 const struct usb_endpoint_descriptor *desc)
268{
269 struct langwell_udc *dev;
270 struct langwell_ep *ep;
271 u16 max = 0;
272 unsigned long flags;
3eed298f 273 int i, retval = 0;
5be19a9d
XS		 274 unsigned char zlt, ios = 0, mult = 0;
275
276 ep = container_of(_ep, struct langwell_ep, ep);
277 dev = ep->dev;
5f81f4b0 278 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 279
280 if (!_ep || !desc || ep->desc
281 || desc->bDescriptorType != USB_DT_ENDPOINT)
282 return -EINVAL;
283
284 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
285 return -ESHUTDOWN;
286
287 max = le16_to_cpu(desc->wMaxPacketSize);
288
289 /*
290 * disable HW zero length termination select
291 * driver handles zero length packet through req->req.zero
292 */
293 zlt = 1;
294
295 /*
296 * sanity check type, direction, address, and then
297 * initialize the endpoint capabilities fields in dQH
298 */
5f81f4b0 299 switch (usb_endpoint_type(desc)) {
5be19a9d
XS		 300 case USB_ENDPOINT_XFER_CONTROL:
301 ios = 1;
302 break;
303 case USB_ENDPOINT_XFER_BULK:
304 if ((dev->gadget.speed == USB_SPEED_HIGH
305 && max != 512)
306 || (dev->gadget.speed == USB_SPEED_FULL
307 && max > 64)) {
308 goto done;
309 }
310 break;
311 case USB_ENDPOINT_XFER_INT:
312 if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
313 goto done;
314
315 switch (dev->gadget.speed) {
316 case USB_SPEED_HIGH:
317 if (max <= 1024)
318 break;
319 case USB_SPEED_FULL:
320 if (max <= 64)
321 break;
322 default:
323 if (max <= 8)
324 break;
325 goto done;
326 }
327 break;
328 case USB_ENDPOINT_XFER_ISOC:
329 if (strstr(ep->ep.name, "-bulk")
330 || strstr(ep->ep.name, "-int"))
331 goto done;
332
333 switch (dev->gadget.speed) {
334 case USB_SPEED_HIGH:
335 if (max <= 1024)
336 break;
337 case USB_SPEED_FULL:
338 if (max <= 1023)
339 break;
340 default:
341 goto done;
342 }
343 /*
344 * FIXME:
345 * calculate transactions needed for high bandwidth iso
346 */
347 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
348 max = max & 0x8ff; /* bit 0~10 */
349 /* 3 transactions at most */
350 if (mult > 3)
351 goto done;
352 break;
353 default:
354 goto done;
355 }
356
357 spin_lock_irqsave(&dev->lock, flags);
358
5be19a9d
XS		 359 ep->ep.maxpacket = max;
360 ep->desc = desc;
361 ep->stopped = 0;
5f81f4b0 362 ep->ep_num = usb_endpoint_num(desc);
5be19a9d
XS		 363
364 /* ep_type */
5f81f4b0 365 ep->ep_type = usb_endpoint_type(desc);
5be19a9d
XS		 366
367 /* configure endpoint control registers */
368 ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
369
3eed298f
J		 370 /* configure endpoint capabilities in dQH */
371 i = ep->ep_num * 2 + is_in(ep);
372 ep->dqh = &dev->ep_dqh[i];
373 ep->dqh->dqh_ios = ios;
374 ep->dqh->dqh_mpl = cpu_to_le16(max);
375 ep->dqh->dqh_zlt = zlt;
376 ep->dqh->dqh_mult = mult;
377 ep->dqh->dtd_next = DTD_TERM;
378
5f81f4b0 379 dev_dbg(&dev->pdev->dev, "enabled %s (ep%d%s-%s), max %04x\n",
5be19a9d
XS		 380 _ep->name,
381 ep->ep_num,
5f81f4b0
J		 382 DIR_STRING(ep),
383 type_string(desc),
5be19a9d
XS		 384 max);
385
386 spin_unlock_irqrestore(&dev->lock, flags);
387done:
5f81f4b0 388 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 389 return retval;
390}
391
392
393/*-------------------------------------------------------------------------*/
394
395/* retire a request */
396static void done(struct langwell_ep *ep, struct langwell_request *req,
397 int status)
398{
399 struct langwell_udc *dev = ep->dev;
400 unsigned stopped = ep->stopped;
401 struct langwell_dtd *curr_dtd, *next_dtd;
402 int i;
403
5f81f4b0 404 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 405
406 /* remove the req from ep->queue */
407 list_del_init(&req->queue);
408
409 if (req->req.status == -EINPROGRESS)
410 req->req.status = status;
411 else
412 status = req->req.status;
413
414 /* free dTD for the request */
415 next_dtd = req->head;
416 for (i = 0; i < req->dtd_count; i++) {
417 curr_dtd = next_dtd;
418 if (i != req->dtd_count - 1)
419 next_dtd = curr_dtd->next_dtd_virt;
420 dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
421 }
422
423 if (req->mapped) {
5f81f4b0
J		 424 dma_unmap_single(&dev->pdev->dev,
425 req->req.dma, req->req.length,
5be19a9d
XS		 426 is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
427 req->req.dma = DMA_ADDR_INVALID;
428 req->mapped = 0;
429 } else
430 dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma,
431 req->req.length,
432 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
433
434 if (status != -ESHUTDOWN)
5f81f4b0
J		 435 dev_dbg(&dev->pdev->dev,
436 "complete %s, req %p, stat %d, len %u/%u\n",
437 ep->ep.name, &req->req, status,
438 req->req.actual, req->req.length);
5be19a9d
XS		 439
440 /* don't modify queue heads during completion callback */
441 ep->stopped = 1;
442
443 spin_unlock(&dev->lock);
444 /* complete routine from gadget driver */
445 if (req->req.complete)
446 req->req.complete(&ep->ep, &req->req);
447
448 spin_lock(&dev->lock);
449 ep->stopped = stopped;
450
5f81f4b0 451 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 452}
453
454
455static void langwell_ep_fifo_flush(struct usb_ep *_ep);
456
457/* delete all endpoint requests, called with spinlock held */
458static void nuke(struct langwell_ep *ep, int status)
459{
460 /* called with spinlock held */
461 ep->stopped = 1;
462
463 /* endpoint fifo flush */
464 if (&ep->ep && ep->desc)
465 langwell_ep_fifo_flush(&ep->ep);
466
467 while (!list_empty(&ep->queue)) {
468 struct langwell_request *req = NULL;
469 req = list_entry(ep->queue.next, struct langwell_request,
470 queue);
471 done(ep, req, status);
472 }
473}
474
475
476/*-------------------------------------------------------------------------*/
477
478/* endpoint is no longer usable */
479static int langwell_ep_disable(struct usb_ep *_ep)
480{
481 struct langwell_ep *ep;
482 unsigned long flags;
483 struct langwell_udc *dev;
484 int ep_num;
485 u32 endptctrl;
486
487 ep = container_of(_ep, struct langwell_ep, ep);
488 dev = ep->dev;
5f81f4b0 489 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 490
491 if (!_ep || !ep->desc)
492 return -EINVAL;
493
494 spin_lock_irqsave(&dev->lock, flags);
495
496 /* disable endpoint control register */
497 ep_num = ep->ep_num;
498 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
499 if (is_in(ep))
500 endptctrl &= ~EPCTRL_TXE;
501 else
502 endptctrl &= ~EPCTRL_RXE;
503 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
504
505 /* nuke all pending requests (does flush) */
506 nuke(ep, -ESHUTDOWN);
507
508 ep->desc = NULL;
509 ep->stopped = 1;
510
511 spin_unlock_irqrestore(&dev->lock, flags);
512
5f81f4b0
J		 513 dev_dbg(&dev->pdev->dev, "disabled %s\n", _ep->name);
514 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 515
516 return 0;
517}
518
519
520/* allocate a request object to use with this endpoint */
521static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
522 gfp_t gfp_flags)
523{
524 struct langwell_ep *ep;
525 struct langwell_udc *dev;
526 struct langwell_request *req = NULL;
527
528 if (!_ep)
529 return NULL;
530
531 ep = container_of(_ep, struct langwell_ep, ep);
532 dev = ep->dev;
5f81f4b0 533 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 534
535 req = kzalloc(sizeof(*req), gfp_flags);
536 if (!req)
537 return NULL;
538
539 req->req.dma = DMA_ADDR_INVALID;
540 INIT_LIST_HEAD(&req->queue);
541
5f81f4b0
J		 542 dev_vdbg(&dev->pdev->dev, "alloc request for %s\n", _ep->name);
543 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 544 return &req->req;
545}
546
547
548/* free a request object */
549static void langwell_free_request(struct usb_ep *_ep,
550 struct usb_request *_req)
551{
552 struct langwell_ep *ep;
553 struct langwell_udc *dev;
554 struct langwell_request *req = NULL;
555
556 ep = container_of(_ep, struct langwell_ep, ep);
557 dev = ep->dev;
5f81f4b0 558 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 559
560 if (!_ep || !_req)
561 return;
562
563 req = container_of(_req, struct langwell_request, req);
564 WARN_ON(!list_empty(&req->queue));
565
566 if (_req)
567 kfree(req);
568
5f81f4b0
J		 569 dev_vdbg(&dev->pdev->dev, "free request for %s\n", _ep->name);
570 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 571}
572
573
574/*-------------------------------------------------------------------------*/
575
576/* queue dTD and PRIME endpoint */
577static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
578{
579 u32 bit_mask, usbcmd, endptstat, dtd_dma;
580 u8 dtd_status;
581 int i;
582 struct langwell_dqh *dqh;
583 struct langwell_udc *dev;
584
585 dev = ep->dev;
5f81f4b0 586 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 587
588 i = ep->ep_num * 2 + is_in(ep);
589 dqh = &dev->ep_dqh[i];
590
591 if (ep->ep_num)
5f81f4b0 592 dev_vdbg(&dev->pdev->dev, "%s\n", ep->name);
5be19a9d
XS		 593 else
594 /* ep0 */
5f81f4b0 595 dev_vdbg(&dev->pdev->dev, "%s-%s\n", ep->name, DIR_STRING(ep));
5be19a9d 596
5f81f4b0
J		 597 dev_vdbg(&dev->pdev->dev, "ep_dqh[%d] addr: 0x%08x\n",
598 i, (u32)&(dev->ep_dqh[i]));
5be19a9d
XS		 599
600 bit_mask = is_in(ep) ?
601 (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
602
5f81f4b0 603 dev_vdbg(&dev->pdev->dev, "bit_mask = 0x%08x\n", bit_mask);
5be19a9d
XS		 604
605 /* check if the pipe is empty */
606 if (!(list_empty(&ep->queue))) {
607 /* add dTD to the end of linked list */
608 struct langwell_request *lastreq;
609 lastreq = list_entry(ep->queue.prev,
610 struct langwell_request, queue);
611
612 lastreq->tail->dtd_next =
613 cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
614
615 /* read prime bit, if 1 goto out */
616 if (readl(&dev->op_regs->endptprime) & bit_mask)
617 goto out;
618
619 do {
620 /* set ATDTW bit in USBCMD */
621 usbcmd = readl(&dev->op_regs->usbcmd);
622 writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
623
624 /* read correct status bit */
625 endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
626
627 } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
628
629 /* write ATDTW bit to 0 */
630 usbcmd = readl(&dev->op_regs->usbcmd);
631 writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
632
633 if (endptstat)
634 goto out;
635 }
636
637 /* write dQH next pointer and terminate bit to 0 */
638 dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
639 dqh->dtd_next = cpu_to_le32(dtd_dma);
640
641 /* clear active and halt bit */
642 dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
643 dqh->dtd_status &= dtd_status;
5f81f4b0
J		 644 dev_vdbg(&dev->pdev->dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
645
646 /* ensure that updates to the dQH will occure before priming */
647 wmb();
5be19a9d
XS		 648
649 /* write 1 to endptprime register to PRIME endpoint */
650 bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
5f81f4b0 651 dev_vdbg(&dev->pdev->dev, "endprime bit_mask = 0x%08x\n", bit_mask);
5be19a9d
XS		 652 writel(bit_mask, &dev->op_regs->endptprime);
653out:
5f81f4b0 654 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 655 return 0;
656}
657
658
659/* fill in the dTD structure to build a transfer descriptor */
660static struct langwell_dtd *build_dtd(struct langwell_request *req,
661 unsigned *length, dma_addr_t *dma, int *is_last)
662{
663 u32 buf_ptr;
664 struct langwell_dtd *dtd;
665 struct langwell_udc *dev;
666 int i;
667
668 dev = req->ep->dev;
5f81f4b0 669 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 670
671 /* the maximum transfer length, up to 16k bytes */
672 *length = min(req->req.length - req->req.actual,
673 (unsigned)DTD_MAX_TRANSFER_LENGTH);
674
675 /* create dTD dma_pool resource */
676 dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
677 if (dtd == NULL)
678 return dtd;
679 dtd->dtd_dma = *dma;
680
681 /* initialize buffer page pointers */
682 buf_ptr = (u32)(req->req.dma + req->req.actual);
683 for (i = 0; i < 5; i++)
684 dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
685
686 req->req.actual += *length;
687
688 /* fill in total bytes with transfer size */
689 dtd->dtd_total = cpu_to_le16(*length);
5f81f4b0 690 dev_vdbg(&dev->pdev->dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
5be19a9d
XS		 691
692 /* set is_last flag if req->req.zero is set or not */
693 if (req->req.zero) {
694 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
695 *is_last = 1;
696 else
697 *is_last = 0;
698 } else if (req->req.length == req->req.actual) {
699 *is_last = 1;
700 } else
701 *is_last = 0;
702
703 if (*is_last == 0)
5f81f4b0 704 dev_vdbg(&dev->pdev->dev, "multi-dtd request!\n");
5be19a9d
XS		 705
706 /* set interrupt on complete bit for the last dTD */
707 if (*is_last && !req->req.no_interrupt)
708 dtd->dtd_ioc = 1;
709
710 /* set multiplier override 0 for non-ISO and non-TX endpoint */
711 dtd->dtd_multo = 0;
712
713 /* set the active bit of status field to 1 */
714 dtd->dtd_status = DTD_STS_ACTIVE;
5f81f4b0
J		 715 dev_vdbg(&dev->pdev->dev, "dtd->dtd_status = 0x%02x\n",
716 dtd->dtd_status);
5be19a9d 717
5f81f4b0
J		 718 dev_vdbg(&dev->pdev->dev, "length = %d, dma addr= 0x%08x\n",
719 *length, (int)*dma);
720 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 721 return dtd;
722}
723
724
725/* generate dTD linked list for a request */
726static int req_to_dtd(struct langwell_request *req)
727{
728 unsigned count;
729 int is_last, is_first = 1;
730 struct langwell_dtd *dtd, *last_dtd = NULL;
731 struct langwell_udc *dev;
732 dma_addr_t dma;
733
734 dev = req->ep->dev;
5f81f4b0 735 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 736 do {
737 dtd = build_dtd(req, &count, &dma, &is_last);
738 if (dtd == NULL)
739 return -ENOMEM;
740
741 if (is_first) {
742 is_first = 0;
743 req->head = dtd;
744 } else {
745 last_dtd->dtd_next = cpu_to_le32(dma);
746 last_dtd->next_dtd_virt = dtd;
747 }
748 last_dtd = dtd;
749 req->dtd_count++;
750 } while (!is_last);
751
752 /* set terminate bit to 1 for the last dTD */
753 dtd->dtd_next = DTD_TERM;
754
755 req->tail = dtd;
756
5f81f4b0 757 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 758 return 0;
759}
760
761/*-------------------------------------------------------------------------*/
762
763/* queue (submits) an I/O requests to an endpoint */
764static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
765 gfp_t gfp_flags)
766{
767 struct langwell_request *req;
768 struct langwell_ep *ep;
769 struct langwell_udc *dev;
770 unsigned long flags;
771 int is_iso = 0, zlflag = 0;
772
773 /* always require a cpu-view buffer */
774 req = container_of(_req, struct langwell_request, req);
775 ep = container_of(_ep, struct langwell_ep, ep);
776
777 if (!_req || !_req->complete || !_req->buf
778 || !list_empty(&req->queue)) {
779 return -EINVAL;
780 }
781
782 if (unlikely(!_ep || !ep->desc))
783 return -EINVAL;
784
785 dev = ep->dev;
786 req->ep = ep;
5f81f4b0 787 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 788
5f81f4b0 789 if (usb_endpoint_xfer_isoc(ep->desc)) {
5be19a9d
XS		 790 if (req->req.length > ep->ep.maxpacket)
791 return -EMSGSIZE;
792 is_iso = 1;
793 }
794
795 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
796 return -ESHUTDOWN;
797
798 /* set up dma mapping in case the caller didn't */
799 if (_req->dma == DMA_ADDR_INVALID) {
800 /* WORKAROUND: WARN_ON(size == 0) */
801 if (_req->length == 0) {
5f81f4b0 802 dev_vdbg(&dev->pdev->dev, "req->length: 0->1\n");
5be19a9d
XS		 803 zlflag = 1;
804 _req->length++;
805 }
806
807 _req->dma = dma_map_single(&dev->pdev->dev,
808 _req->buf, _req->length,
809 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
810 if (zlflag && (_req->length == 1)) {
5f81f4b0 811 dev_vdbg(&dev->pdev->dev, "req->length: 1->0\n");
5be19a9d
XS		 812 zlflag = 0;
813 _req->length = 0;
814 }
815
816 req->mapped = 1;
5f81f4b0 817 dev_vdbg(&dev->pdev->dev, "req->mapped = 1\n");
5be19a9d
XS		 818 } else {
819 dma_sync_single_for_device(&dev->pdev->dev,
820 _req->dma, _req->length,
821 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
822 req->mapped = 0;
5f81f4b0 823 dev_vdbg(&dev->pdev->dev, "req->mapped = 0\n");
5be19a9d
XS		 824 }
825
5f81f4b0
J		 826 dev_dbg(&dev->pdev->dev,
827 "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
828 _ep->name,
829 _req, _req->length, _req->buf, (int)_req->dma);
5be19a9d
XS		 830
831 _req->status = -EINPROGRESS;
832 _req->actual = 0;
833 req->dtd_count = 0;
834
835 spin_lock_irqsave(&dev->lock, flags);
836
837 /* build and put dTDs to endpoint queue */
838 if (!req_to_dtd(req)) {
839 queue_dtd(ep, req);
840 } else {
841 spin_unlock_irqrestore(&dev->lock, flags);
842 return -ENOMEM;
843 }
844
845 /* update ep0 state */
846 if (ep->ep_num == 0)
847 dev->ep0_state = DATA_STATE_XMIT;
848
849 if (likely(req != NULL)) {
850 list_add_tail(&req->queue, &ep->queue);
5f81f4b0 851 dev_vdbg(&dev->pdev->dev, "list_add_tail()\n");
5be19a9d
XS		 852 }
853
854 spin_unlock_irqrestore(&dev->lock, flags);
855
5f81f4b0 856 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 857 return 0;
858}
859
860
861/* dequeue (cancels, unlinks) an I/O request from an endpoint */
862static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
863{
864 struct langwell_ep *ep;
865 struct langwell_udc *dev;
866 struct langwell_request *req;
867 unsigned long flags;
868 int stopped, ep_num, retval = 0;
869 u32 endptctrl;
870
871 ep = container_of(_ep, struct langwell_ep, ep);
872 dev = ep->dev;
5f81f4b0 873 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 874
875 if (!_ep || !ep->desc || !_req)
876 return -EINVAL;
877
878 if (!dev->driver)
879 return -ESHUTDOWN;
880
881 spin_lock_irqsave(&dev->lock, flags);
882 stopped = ep->stopped;
883
884 /* quiesce dma while we patch the queue */
885 ep->stopped = 1;
886 ep_num = ep->ep_num;
887
888 /* disable endpoint control register */
889 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
890 if (is_in(ep))
891 endptctrl &= ~EPCTRL_TXE;
892 else
893 endptctrl &= ~EPCTRL_RXE;
894 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
895
896 /* make sure it's still queued on this endpoint */
897 list_for_each_entry(req, &ep->queue, queue) {
898 if (&req->req == _req)
899 break;
900 }
901
902 if (&req->req != _req) {
903 retval = -EINVAL;
904 goto done;
905 }
906
907 /* queue head may be partially complete. */
908 if (ep->queue.next == &req->queue) {
5f81f4b0 909 dev_dbg(&dev->pdev->dev, "unlink (%s) dma\n", _ep->name);
5be19a9d
XS		 910 _req->status = -ECONNRESET;
911 langwell_ep_fifo_flush(&ep->ep);
912
913 /* not the last request in endpoint queue */
914 if (likely(ep->queue.next == &req->queue)) {
915 struct langwell_dqh *dqh;
916 struct langwell_request *next_req;
917
918 dqh = ep->dqh;
919 next_req = list_entry(req->queue.next,
920 struct langwell_request, queue);
921
922 /* point the dQH to the first dTD of next request */
923 writel((u32) next_req->head, &dqh->dqh_current);
924 }
925 } else {
926 struct langwell_request *prev_req;
927
928 prev_req = list_entry(req->queue.prev,
929 struct langwell_request, queue);
930 writel(readl(&req->tail->dtd_next),
931 &prev_req->tail->dtd_next);
932 }
933
934 done(ep, req, -ECONNRESET);
935
936done:
937 /* enable endpoint again */
938 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
939 if (is_in(ep))
940 endptctrl |= EPCTRL_TXE;
941 else
942 endptctrl |= EPCTRL_RXE;
943 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
944
945 ep->stopped = stopped;
946 spin_unlock_irqrestore(&dev->lock, flags);
947
5f81f4b0 948 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 949 return retval;
950}
951
952
953/*-------------------------------------------------------------------------*/
954
955/* endpoint set/clear halt */
956static void ep_set_halt(struct langwell_ep *ep, int value)
957{
958 u32 endptctrl = 0;
959 int ep_num;
960 struct langwell_udc *dev = ep->dev;
5f81f4b0 961 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 962
963 ep_num = ep->ep_num;
964 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
965
966 /* value: 1 - set halt, 0 - clear halt */
967 if (value) {
968 /* set the stall bit */
969 if (is_in(ep))
970 endptctrl |= EPCTRL_TXS;
971 else
972 endptctrl |= EPCTRL_RXS;
973 } else {
974 /* clear the stall bit and reset data toggle */
975 if (is_in(ep)) {
976 endptctrl &= ~EPCTRL_TXS;
977 endptctrl |= EPCTRL_TXR;
978 } else {
979 endptctrl &= ~EPCTRL_RXS;
980 endptctrl |= EPCTRL_RXR;
981 }
982 }
983
984 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
985
5f81f4b0 986 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 987}
988
989
990/* set the endpoint halt feature */
991static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
992{
993 struct langwell_ep *ep;
994 struct langwell_udc *dev;
995 unsigned long flags;
996 int retval = 0;
997
998 ep = container_of(_ep, struct langwell_ep, ep);
999 dev = ep->dev;
1000
5f81f4b0 1001 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1002
1003 if (!_ep || !ep->desc)
1004 return -EINVAL;
1005
1006 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1007 return -ESHUTDOWN;
1008
5f81f4b0 1009 if (usb_endpoint_xfer_isoc(ep->desc))
5be19a9d
XS		 1010 return -EOPNOTSUPP;
1011
1012 spin_lock_irqsave(&dev->lock, flags);
1013
1014 /*
1015 * attempt to halt IN ep will fail if any transfer requests
1016 * are still queue
1017 */
1018 if (!list_empty(&ep->queue) && is_in(ep) && value) {
1019 /* IN endpoint FIFO holds bytes */
5f81f4b0 1020 dev_dbg(&dev->pdev->dev, "%s FIFO holds bytes\n", _ep->name);
5be19a9d
XS		 1021 retval = -EAGAIN;
1022 goto done;
1023 }
1024
1025 /* endpoint set/clear halt */
1026 if (ep->ep_num) {
1027 ep_set_halt(ep, value);
1028 } else { /* endpoint 0 */
1029 dev->ep0_state = WAIT_FOR_SETUP;
1030 dev->ep0_dir = USB_DIR_OUT;
1031 }
1032done:
1033 spin_unlock_irqrestore(&dev->lock, flags);
5f81f4b0
J		 1034 dev_dbg(&dev->pdev->dev, "%s %s halt\n",
1035 _ep->name, value ? "set" : "clear");
1036 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1037 return retval;
1038}
1039
1040
1041/* set the halt feature and ignores clear requests */
1042static int langwell_ep_set_wedge(struct usb_ep *_ep)
1043{
1044 struct langwell_ep *ep;
1045 struct langwell_udc *dev;
1046
1047 ep = container_of(_ep, struct langwell_ep, ep);
1048 dev = ep->dev;
1049
5f81f4b0 1050 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1051
1052 if (!_ep || !ep->desc)
1053 return -EINVAL;
1054
5f81f4b0 1055 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1056 return usb_ep_set_halt(_ep);
1057}
1058
1059
1060/* flush contents of a fifo */
1061static void langwell_ep_fifo_flush(struct usb_ep *_ep)
1062{
1063 struct langwell_ep *ep;
1064 struct langwell_udc *dev;
1065 u32 flush_bit;
1066 unsigned long timeout;
1067
1068 ep = container_of(_ep, struct langwell_ep, ep);
1069 dev = ep->dev;
1070
5f81f4b0 1071 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1072
1073 if (!_ep || !ep->desc) {
5f81f4b0
J		 1074 dev_vdbg(&dev->pdev->dev, "ep or ep->desc is NULL\n");
1075 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1076 return;
1077 }
1078
5f81f4b0
J		 1079 dev_vdbg(&dev->pdev->dev, "%s-%s fifo flush\n",
1080 _ep->name, DIR_STRING(ep));
5be19a9d
XS		 1081
1082 /* flush endpoint buffer */
1083 if (ep->ep_num == 0)
1084 flush_bit = (1 << 16) | 1;
1085 else if (is_in(ep))
1086 flush_bit = 1 << (ep->ep_num + 16); /* TX */
1087 else
1088 flush_bit = 1 << ep->ep_num; /* RX */
1089
1090 /* wait until flush complete */
1091 timeout = jiffies + FLUSH_TIMEOUT;
1092 do {
1093 writel(flush_bit, &dev->op_regs->endptflush);
1094 while (readl(&dev->op_regs->endptflush)) {
1095 if (time_after(jiffies, timeout)) {
5f81f4b0 1096 dev_err(&dev->pdev->dev, "ep flush timeout\n");
5be19a9d
XS		 1097 goto done;
1098 }
1099 cpu_relax();
1100 }
1101 } while (readl(&dev->op_regs->endptstat) & flush_bit);
1102done:
5f81f4b0 1103 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1104}
1105
1106
1107/* endpoints operations structure */
1108static const struct usb_ep_ops langwell_ep_ops = {
1109
1110 /* configure endpoint, making it usable */
1111 .enable = langwell_ep_enable,
1112
1113 /* endpoint is no longer usable */
1114 .disable = langwell_ep_disable,
1115
1116 /* allocate a request object to use with this endpoint */
1117 .alloc_request = langwell_alloc_request,
1118
1119 /* free a request object */
1120 .free_request = langwell_free_request,
1121
1122 /* queue (submits) an I/O requests to an endpoint */
1123 .queue = langwell_ep_queue,
1124
1125 /* dequeue (cancels, unlinks) an I/O request from an endpoint */
1126 .dequeue = langwell_ep_dequeue,
1127
1128 /* set the endpoint halt feature */
1129 .set_halt = langwell_ep_set_halt,
1130
1131 /* set the halt feature and ignores clear requests */
1132 .set_wedge = langwell_ep_set_wedge,
1133
1134 /* flush contents of a fifo */
1135 .fifo_flush = langwell_ep_fifo_flush,
1136};
1137
1138
1139/*-------------------------------------------------------------------------*/
1140
1141/* device controller usb_gadget_ops structure */
1142
1143/* returns the current frame number */
1144static int langwell_get_frame(struct usb_gadget *_gadget)
1145{
1146 struct langwell_udc *dev;
1147 u16 retval;
1148
1149 if (!_gadget)
1150 return -ENODEV;
1151
1152 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1153 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1154
1155 retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
1156
5f81f4b0 1157 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1158 return retval;
1159}
1160
1161
513b91b6
J		 1162/* enter or exit PHY low power state */
1163static void langwell_phy_low_power(struct langwell_udc *dev, bool flag)
1164{
1165 u32 devlc;
1166 u8 devlc_byte2;
1167 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
1168
1169 devlc = readl(&dev->op_regs->devlc);
1170 dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
1171
1172 if (flag)
1173 devlc |= LPM_PHCD;
1174 else
1175 devlc &= ~LPM_PHCD;
1176
1177 /* FIXME: workaround for Langwell A1/A2/A3 sighting */
1178 devlc_byte2 = (devlc >> 16) & 0xff;
1179 writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
1180
1181 devlc = readl(&dev->op_regs->devlc);
1182 dev_vdbg(&dev->pdev->dev,
1183 "%s PHY low power suspend, devlc = 0x%08x\n",
1184 flag ? "enter" : "exit", devlc);
1185}
1186
1187
5be19a9d
XS		 1188/* tries to wake up the host connected to this gadget */
1189static int langwell_wakeup(struct usb_gadget *_gadget)
1190{
1191 struct langwell_udc *dev;
513b91b6 1192 u32 portsc1;
5f81f4b0 1193 unsigned long flags;
5be19a9d
XS		 1194
1195 if (!_gadget)
1196 return 0;
1197
1198 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1199 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 1200
5f81f4b0
J		 1201 /* remote wakeup feature not enabled by host */
1202 if (!dev->remote_wakeup) {
1203 dev_info(&dev->pdev->dev, "remote wakeup is disabled\n");
5be19a9d 1204 return -ENOTSUPP;
5f81f4b0 1205 }
5be19a9d
XS		 1206
1207 spin_lock_irqsave(&dev->lock, flags);
1208
1209 portsc1 = readl(&dev->op_regs->portsc1);
1210 if (!(portsc1 & PORTS_SUSP)) {
1211 spin_unlock_irqrestore(&dev->lock, flags);
1212 return 0;
1213 }
1214
513b91b6
J		 1215 /* LPM L1 to L0 or legacy remote wakeup */
1216 if (dev->lpm && dev->lpm_state == LPM_L1)
1217 dev_info(&dev->pdev->dev, "LPM L1 to L0 remote wakeup\n");
1218 else
1219 dev_info(&dev->pdev->dev, "device remote wakeup\n");
5be19a9d
XS		 1220
1221 /* exit PHY low power suspend */
513b91b6
J		 1222 if (dev->pdev->device != 0x0829)
1223 langwell_phy_low_power(dev, 0);
1224
1225 /* force port resume */
1226 portsc1 |= PORTS_FPR;
1227 writel(portsc1, &dev->op_regs->portsc1);
5be19a9d
XS		 1228
1229 spin_unlock_irqrestore(&dev->lock, flags);
1230
5f81f4b0 1231 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1232 return 0;
1233}
1234
1235
1236/* notify controller that VBUS is powered or not */
1237static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
1238{
1239 struct langwell_udc *dev;
1240 unsigned long flags;
5f81f4b0 1241 u32 usbcmd;
5be19a9d
XS		 1242
1243 if (!_gadget)
1244 return -ENODEV;
1245
1246 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1247 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1248
1249 spin_lock_irqsave(&dev->lock, flags);
5f81f4b0
J		 1250 dev_vdbg(&dev->pdev->dev, "VBUS status: %s\n",
1251 is_active ? "on" : "off");
5be19a9d
XS		 1252
1253 dev->vbus_active = (is_active != 0);
1254 if (dev->driver && dev->softconnected && dev->vbus_active) {
1255 usbcmd = readl(&dev->op_regs->usbcmd);
1256 usbcmd |= CMD_RUNSTOP;
1257 writel(usbcmd, &dev->op_regs->usbcmd);
1258 } else {
1259 usbcmd = readl(&dev->op_regs->usbcmd);
1260 usbcmd &= ~CMD_RUNSTOP;
1261 writel(usbcmd, &dev->op_regs->usbcmd);
1262 }
1263
1264 spin_unlock_irqrestore(&dev->lock, flags);
1265
5f81f4b0 1266 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1267 return 0;
1268}
1269
1270
1271/* constrain controller's VBUS power usage */
1272static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1273{
1274 struct langwell_udc *dev;
1275
1276 if (!_gadget)
1277 return -ENODEV;
1278
1279 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1280 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1281
1282 if (dev->transceiver) {
5f81f4b0
J		 1283 dev_vdbg(&dev->pdev->dev, "otg_set_power\n");
1284 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1285 return otg_set_power(dev->transceiver, mA);
1286 }
1287
5f81f4b0 1288 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1289 return -ENOTSUPP;
1290}
1291
1292
1293/* D+ pullup, software-controlled connect/disconnect to USB host */
1294static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
1295{
1296 struct langwell_udc *dev;
5f81f4b0
J		 1297 u32 usbcmd;
1298 unsigned long flags;
5be19a9d
XS		 1299
1300 if (!_gadget)
1301 return -ENODEV;
1302
1303 dev = container_of(_gadget, struct langwell_udc, gadget);
1304
5f81f4b0 1305 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1306
1307 spin_lock_irqsave(&dev->lock, flags);
1308 dev->softconnected = (is_on != 0);
1309
1310 if (dev->driver && dev->softconnected && dev->vbus_active) {
1311 usbcmd = readl(&dev->op_regs->usbcmd);
1312 usbcmd |= CMD_RUNSTOP;
1313 writel(usbcmd, &dev->op_regs->usbcmd);
1314 } else {
1315 usbcmd = readl(&dev->op_regs->usbcmd);
1316 usbcmd &= ~CMD_RUNSTOP;
1317 writel(usbcmd, &dev->op_regs->usbcmd);
1318 }
1319 spin_unlock_irqrestore(&dev->lock, flags);
1320
5f81f4b0 1321 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1322 return 0;
1323}
1324
1325
1326/* device controller usb_gadget_ops structure */
1327static const struct usb_gadget_ops langwell_ops = {
1328
1329 /* returns the current frame number */
1330 .get_frame = langwell_get_frame,
1331
1332 /* tries to wake up the host connected to this gadget */
1333 .wakeup = langwell_wakeup,
1334
1335 /* set the device selfpowered feature, always selfpowered */
1336 /* .set_selfpowered = langwell_set_selfpowered, */
1337
1338 /* notify controller that VBUS is powered or not */
1339 .vbus_session = langwell_vbus_session,
1340
1341 /* constrain controller's VBUS power usage */
1342 .vbus_draw = langwell_vbus_draw,
1343
1344 /* D+ pullup, software-controlled connect/disconnect to USB host */
1345 .pullup = langwell_pullup,
1346};
1347
1348
1349/*-------------------------------------------------------------------------*/
1350
1351/* device controller operations */
1352
1353/* reset device controller */
1354static int langwell_udc_reset(struct langwell_udc *dev)
1355{
1356 u32 usbcmd, usbmode, devlc, endpointlistaddr;
513b91b6 1357 u8 devlc_byte0, devlc_byte2;
5be19a9d
XS		 1358 unsigned long timeout;
1359
1360 if (!dev)
1361 return -EINVAL;
1362
5f81f4b0 1363 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1364
1365 /* set controller to stop state */
1366 usbcmd = readl(&dev->op_regs->usbcmd);
1367 usbcmd &= ~CMD_RUNSTOP;
1368 writel(usbcmd, &dev->op_regs->usbcmd);
1369
1370 /* reset device controller */
1371 usbcmd = readl(&dev->op_regs->usbcmd);
1372 usbcmd |= CMD_RST;
1373 writel(usbcmd, &dev->op_regs->usbcmd);
1374
1375 /* wait for reset to complete */
1376 timeout = jiffies + RESET_TIMEOUT;
1377 while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
1378 if (time_after(jiffies, timeout)) {
5f81f4b0 1379 dev_err(&dev->pdev->dev, "device reset timeout\n");
5be19a9d
XS		 1380 return -ETIMEDOUT;
1381 }
1382 cpu_relax();
1383 }
1384
1385 /* set controller to device mode */
1386 usbmode = readl(&dev->op_regs->usbmode);
1387 usbmode |= MODE_DEVICE;
1388
1389 /* turn setup lockout off, require setup tripwire in usbcmd */
1390 usbmode |= MODE_SLOM;
1391
1392 writel(usbmode, &dev->op_regs->usbmode);
1393 usbmode = readl(&dev->op_regs->usbmode);
5f81f4b0 1394 dev_vdbg(&dev->pdev->dev, "usbmode=0x%08x\n", usbmode);
5be19a9d
XS		 1395
1396 /* Write-Clear setup status */
1397 writel(0, &dev->op_regs->usbsts);
1398
1399 /* if support USB LPM, ACK all LPM token */
1400 if (dev->lpm) {
1401 devlc = readl(&dev->op_regs->devlc);
513b91b6
J		 1402 dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
1403 /* FIXME: workaround for Langwell A1/A2/A3 sighting */
5be19a9d
XS		 1404 devlc &= ~LPM_STL; /* don't STALL LPM token */
1405 devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
513b91b6
J		 1406 devlc_byte0 = devlc & 0xff;
1407 devlc_byte2 = (devlc >> 16) & 0xff;
1408 writeb(devlc_byte0, (u8 *)&dev->op_regs->devlc);
1409 writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
1410 devlc = readl(&dev->op_regs->devlc);
1411 dev_vdbg(&dev->pdev->dev,
1412 "ACK LPM token, devlc = 0x%08x\n", devlc);
5be19a9d
XS		 1413 }
1414
1415 /* fill endpointlistaddr register */
1416 endpointlistaddr = dev->ep_dqh_dma;
1417 endpointlistaddr &= ENDPOINTLISTADDR_MASK;
1418 writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
1419
5f81f4b0
J		 1420 dev_vdbg(&dev->pdev->dev,
1421 "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
1422 dev->ep_dqh, endpointlistaddr,
1423 readl(&dev->op_regs->endpointlistaddr));
1424 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1425 return 0;
1426}
1427
1428
1429/* reinitialize device controller endpoints */
1430static int eps_reinit(struct langwell_udc *dev)
1431{
1432 struct langwell_ep *ep;
1433 char name[14];
1434 int i;
1435
5f81f4b0 1436 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1437
1438 /* initialize ep0 */
1439 ep = &dev->ep[0];
1440 ep->dev = dev;
1441 strncpy(ep->name, "ep0", sizeof(ep->name));
1442 ep->ep.name = ep->name;
1443 ep->ep.ops = &langwell_ep_ops;
1444 ep->stopped = 0;
1445 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1446 ep->ep_num = 0;
1447 ep->desc = &langwell_ep0_desc;
1448 INIT_LIST_HEAD(&ep->queue);
1449
1450 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1451
1452 /* initialize other endpoints */
1453 for (i = 2; i < dev->ep_max; i++) {
1454 ep = &dev->ep[i];
1455 if (i % 2)
1456 snprintf(name, sizeof(name), "ep%din", i / 2);
1457 else
1458 snprintf(name, sizeof(name), "ep%dout", i / 2);
1459 ep->dev = dev;
1460 strncpy(ep->name, name, sizeof(ep->name));
1461 ep->ep.name = ep->name;
1462
1463 ep->ep.ops = &langwell_ep_ops;
1464 ep->stopped = 0;
1465 ep->ep.maxpacket = (unsigned short) ~0;
1466 ep->ep_num = i / 2;
1467
1468 INIT_LIST_HEAD(&ep->queue);
1469 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
5be19a9d
XS		 1470 }
1471
5f81f4b0 1472 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1473 return 0;
1474}
1475
1476
1477/* enable interrupt and set controller to run state */
1478static void langwell_udc_start(struct langwell_udc *dev)
1479{
1480 u32 usbintr, usbcmd;
5f81f4b0 1481 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1482
1483 /* enable interrupts */
1484 usbintr = INTR_ULPIE /* ULPI */
1485 | INTR_SLE /* suspend */
1486 /* | INTR_SRE SOF received */
1487 | INTR_URE /* USB reset */
1488 | INTR_AAE /* async advance */
1489 | INTR_SEE /* system error */
1490 | INTR_FRE /* frame list rollover */
1491 | INTR_PCE /* port change detect */
1492 | INTR_UEE /* USB error interrupt */
1493 | INTR_UE; /* USB interrupt */
1494 writel(usbintr, &dev->op_regs->usbintr);
1495
1496 /* clear stopped bit */
1497 dev->stopped = 0;
1498
1499 /* set controller to run */
1500 usbcmd = readl(&dev->op_regs->usbcmd);
1501 usbcmd |= CMD_RUNSTOP;
1502 writel(usbcmd, &dev->op_regs->usbcmd);
1503
5f81f4b0 1504 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1505 return;
1506}
1507
1508
1509/* disable interrupt and set controller to stop state */
1510static void langwell_udc_stop(struct langwell_udc *dev)
1511{
1512 u32 usbcmd;
1513
5f81f4b0 1514 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1515
1516 /* disable all interrupts */
1517 writel(0, &dev->op_regs->usbintr);
1518
1519 /* set stopped bit */
1520 dev->stopped = 1;
1521
1522 /* set controller to stop state */
1523 usbcmd = readl(&dev->op_regs->usbcmd);
1524 usbcmd &= ~CMD_RUNSTOP;
1525 writel(usbcmd, &dev->op_regs->usbcmd);
1526
5f81f4b0 1527 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1528 return;
1529}
1530
1531
1532/* stop all USB activities */
1533static void stop_activity(struct langwell_udc *dev,
1534 struct usb_gadget_driver *driver)
1535{
1536 struct langwell_ep *ep;
5f81f4b0 1537 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1538
1539 nuke(&dev->ep[0], -ESHUTDOWN);
1540
1541 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
1542 nuke(ep, -ESHUTDOWN);
1543 }
1544
1545 /* report disconnect; the driver is already quiesced */
1546 if (driver) {
1547 spin_unlock(&dev->lock);
1548 driver->disconnect(&dev->gadget);
1549 spin_lock(&dev->lock);
1550 }
1551
5f81f4b0 1552 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1553}
1554
1555
1556/*-------------------------------------------------------------------------*/
1557
1558/* device "function" sysfs attribute file */
1559static ssize_t show_function(struct device *_dev,
1560 struct device_attribute *attr, char *buf)
1561{
1562 struct langwell_udc *dev = the_controller;
1563
1564 if (!dev->driver || !dev->driver->function
1565 || strlen(dev->driver->function) > PAGE_SIZE)
1566 return 0;
1567
1568 return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
1569}
1570static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
1571
1572
1573/* device "langwell_udc" sysfs attribute file */
1574static ssize_t show_langwell_udc(struct device *_dev,
1575 struct device_attribute *attr, char *buf)
1576{
1577 struct langwell_udc *dev = the_controller;
1578 struct langwell_request *req;
1579 struct langwell_ep *ep = NULL;
1580 char *next;
1581 unsigned size;
1582 unsigned t;
1583 unsigned i;
1584 unsigned long flags;
1585 u32 tmp_reg;
1586
1587 next = buf;
1588 size = PAGE_SIZE;
1589 spin_lock_irqsave(&dev->lock, flags);
1590
1591 /* driver basic information */
1592 t = scnprintf(next, size,
1593 DRIVER_DESC "\n"
1594 "%s version: %s\n"
1595 "Gadget driver: %s\n\n",
1596 driver_name, DRIVER_VERSION,
1597 dev->driver ? dev->driver->driver.name : "(none)");
1598 size -= t;
1599 next += t;
1600
1601 /* device registers */
1602 tmp_reg = readl(&dev->op_regs->usbcmd);
1603 t = scnprintf(next, size,
1604 "USBCMD reg:\n"
1605 "SetupTW: %d\n"
1606 "Run/Stop: %s\n\n",
1607 (tmp_reg & CMD_SUTW) ? 1 : 0,
1608 (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
1609 size -= t;
1610 next += t;
1611
1612 tmp_reg = readl(&dev->op_regs->usbsts);
1613 t = scnprintf(next, size,
1614 "USB Status Reg:\n"
1615 "Device Suspend: %d\n"
1616 "Reset Received: %d\n"
1617 "System Error: %s\n"
1618 "USB Error Interrupt: %s\n\n",
1619 (tmp_reg & STS_SLI) ? 1 : 0,
1620 (tmp_reg & STS_URI) ? 1 : 0,
1621 (tmp_reg & STS_SEI) ? "Error" : "No error",
1622 (tmp_reg & STS_UEI) ? "Error detected" : "No error");
1623 size -= t;
1624 next += t;
1625
1626 tmp_reg = readl(&dev->op_regs->usbintr);
1627 t = scnprintf(next, size,
1628 "USB Intrrupt Enable Reg:\n"
1629 "Sleep Enable: %d\n"
1630 "SOF Received Enable: %d\n"
1631 "Reset Enable: %d\n"
1632 "System Error Enable: %d\n"
1633 "Port Change Dectected Enable: %d\n"
1634 "USB Error Intr Enable: %d\n"
1635 "USB Intr Enable: %d\n\n",
1636 (tmp_reg & INTR_SLE) ? 1 : 0,
1637 (tmp_reg & INTR_SRE) ? 1 : 0,
1638 (tmp_reg & INTR_URE) ? 1 : 0,
1639 (tmp_reg & INTR_SEE) ? 1 : 0,
1640 (tmp_reg & INTR_PCE) ? 1 : 0,
1641 (tmp_reg & INTR_UEE) ? 1 : 0,
1642 (tmp_reg & INTR_UE) ? 1 : 0);
1643 size -= t;
1644 next += t;
1645
1646 tmp_reg = readl(&dev->op_regs->frindex);
1647 t = scnprintf(next, size,
1648 "USB Frame Index Reg:\n"
1649 "Frame Number is 0x%08x\n\n",
1650 (tmp_reg & FRINDEX_MASK));
1651 size -= t;
1652 next += t;
1653
1654 tmp_reg = readl(&dev->op_regs->deviceaddr);
1655 t = scnprintf(next, size,
1656 "USB Device Address Reg:\n"
1657 "Device Addr is 0x%x\n\n",
1658 USBADR(tmp_reg));
1659 size -= t;
1660 next += t;
1661
1662 tmp_reg = readl(&dev->op_regs->endpointlistaddr);
1663 t = scnprintf(next, size,
1664 "USB Endpoint List Address Reg:\n"
1665 "Endpoint List Pointer is 0x%x\n\n",
1666 EPBASE(tmp_reg));
1667 size -= t;
1668 next += t;
1669
1670 tmp_reg = readl(&dev->op_regs->portsc1);
1671 t = scnprintf(next, size,
1672 "USB Port Status & Control Reg:\n"
1673 "Port Reset: %s\n"
1674 "Port Suspend Mode: %s\n"
1675 "Over-current Change: %s\n"
1676 "Port Enable/Disable Change: %s\n"
1677 "Port Enabled/Disabled: %s\n"
5f81f4b0
J		 1678 "Current Connect Status: %s\n"
1679 "LPM Suspend Status: %s\n\n",
5be19a9d
XS		 1680 (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
1681 (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
1682 (tmp_reg & PORTS_OCC) ? "Detected" : "No",
1683 (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
1684 (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
5f81f4b0
J		 1685 (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached",
1686 (tmp_reg & PORTS_SLP) ? "LPM L1" : "LPM L0");
5be19a9d
XS		 1687 size -= t;
1688 next += t;
1689
1690 tmp_reg = readl(&dev->op_regs->devlc);
1691 t = scnprintf(next, size,
1692 "Device LPM Control Reg:\n"
1693 "Parallel Transceiver : %d\n"
1694 "Serial Transceiver : %d\n"
1695 "Port Speed: %s\n"
1696 "Port Force Full Speed Connenct: %s\n"
5f81f4b0 1697 "PHY Low Power Suspend Clock: %s\n"
5be19a9d
XS		 1698 "BmAttributes: %d\n\n",
1699 LPM_PTS(tmp_reg),
1700 (tmp_reg & LPM_STS) ? 1 : 0,
1701 ({
1702 char *s;
1703 switch (LPM_PSPD(tmp_reg)) {
1704 case LPM_SPEED_FULL:
1705 s = "Full Speed"; break;
1706 case LPM_SPEED_LOW:
1707 s = "Low Speed"; break;
1708 case LPM_SPEED_HIGH:
1709 s = "High Speed"; break;
1710 default:
1711 s = "Unknown Speed"; break;
1712 }
1713 s;
1714 }),
1715 (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
1716 (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
1717 LPM_BA(tmp_reg));
1718 size -= t;
1719 next += t;
1720
1721 tmp_reg = readl(&dev->op_regs->usbmode);
1722 t = scnprintf(next, size,
1723 "USB Mode Reg:\n"
1724 "Controller Mode is : %s\n\n", ({
1725 char *s;
1726 switch (MODE_CM(tmp_reg)) {
1727 case MODE_IDLE:
1728 s = "Idle"; break;
1729 case MODE_DEVICE:
1730 s = "Device Controller"; break;
1731 case MODE_HOST:
1732 s = "Host Controller"; break;
1733 default:
1734 s = "None"; break;
1735 }
1736 s;
1737 }));
1738 size -= t;
1739 next += t;
1740
1741 tmp_reg = readl(&dev->op_regs->endptsetupstat);
1742 t = scnprintf(next, size,
1743 "Endpoint Setup Status Reg:\n"
1744 "SETUP on ep 0x%04x\n\n",
1745 tmp_reg & SETUPSTAT_MASK);
1746 size -= t;
1747 next += t;
1748
1749 for (i = 0; i < dev->ep_max / 2; i++) {
1750 tmp_reg = readl(&dev->op_regs->endptctrl[i]);
1751 t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
1752 i, tmp_reg);
1753 size -= t;
1754 next += t;
1755 }
1756 tmp_reg = readl(&dev->op_regs->endptprime);
1757 t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
1758 size -= t;
1759 next += t;
1760
1761 /* langwell_udc, langwell_ep, langwell_request structure information */
1762 ep = &dev->ep[0];
1763 t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
1764 ep->ep.name, ep->ep.maxpacket, ep->ep_num);
1765 size -= t;
1766 next += t;
1767
1768 if (list_empty(&ep->queue)) {
1769 t = scnprintf(next, size, "its req queue is empty\n\n");
1770 size -= t;
1771 next += t;
1772 } else {
1773 list_for_each_entry(req, &ep->queue, queue) {
1774 t = scnprintf(next, size,
1775 "req %p actual 0x%x length 0x%x buf %p\n",
1776 &req->req, req->req.actual,
1777 req->req.length, req->req.buf);
1778 size -= t;
1779 next += t;
1780 }
1781 }
1782 /* other gadget->eplist ep */
1783 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
1784 if (ep->desc) {
1785 t = scnprintf(next, size,
1786 "\n%s MaxPacketSize: 0x%x, "
1787 "ep_num: %d\n",
1788 ep->ep.name, ep->ep.maxpacket,
1789 ep->ep_num);
1790 size -= t;
1791 next += t;
1792
1793 if (list_empty(&ep->queue)) {
1794 t = scnprintf(next, size,
1795 "its req queue is empty\n\n");
1796 size -= t;
1797 next += t;
1798 } else {
1799 list_for_each_entry(req, &ep->queue, queue) {
1800 t = scnprintf(next, size,
1801 "req %p actual 0x%x length "
1802 "0x%x buf %p\n",
1803 &req->req, req->req.actual,
1804 req->req.length, req->req.buf);
1805 size -= t;
1806 next += t;
1807 }
1808 }
1809 }
1810 }
1811
1812 spin_unlock_irqrestore(&dev->lock, flags);
1813 return PAGE_SIZE - size;
1814}
1815static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
1816
1817
3211cbc2
J		 1818/* device "remote_wakeup" sysfs attribute file */
1819static ssize_t store_remote_wakeup(struct device *_dev,
1820 struct device_attribute *attr, const char *buf, size_t count)
1821{
1822 struct langwell_udc *dev = the_controller;
1823 unsigned long flags;
1824 ssize_t rc = count;
1825
1826 if (count > 2)
1827 return -EINVAL;
1828
1829 if (count > 0 && buf[count-1] == '\n')
1830 ((char *) buf)[count-1] = 0;
1831
1832 if (buf[0] != '1')
1833 return -EINVAL;
1834
1835 /* force remote wakeup enabled in case gadget driver doesn't support */
1836 spin_lock_irqsave(&dev->lock, flags);
1837 dev->remote_wakeup = 1;
1838 dev->dev_status |= (1 << USB_DEVICE_REMOTE_WAKEUP);
1839 spin_unlock_irqrestore(&dev->lock, flags);
1840
1841 langwell_wakeup(&dev->gadget);
1842
1843 return rc;
1844}
1845static DEVICE_ATTR(remote_wakeup, S_IWUSR, NULL, store_remote_wakeup);
1846
1847
5be19a9d
XS		 1848/*-------------------------------------------------------------------------*/
1849
1850/*
1851 * when a driver is successfully registered, it will receive
1852 * control requests including set_configuration(), which enables
1853 * non-control requests. then usb traffic follows until a
1854 * disconnect is reported. then a host may connect again, or
1855 * the driver might get unbound.
1856 */
1857
1858int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1859{
1860 struct langwell_udc *dev = the_controller;
1861 unsigned long flags;
1862 int retval;
1863
1864 if (!dev)
1865 return -ENODEV;
1866
5f81f4b0 1867 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1868
1869 if (dev->driver)
1870 return -EBUSY;
1871
1872 spin_lock_irqsave(&dev->lock, flags);
1873
1874 /* hook up the driver ... */
1875 driver->driver.bus = NULL;
1876 dev->driver = driver;
1877 dev->gadget.dev.driver = &driver->driver;
1878
1879 spin_unlock_irqrestore(&dev->lock, flags);
1880
1881 retval = driver->bind(&dev->gadget);
1882 if (retval) {
5f81f4b0 1883 dev_dbg(&dev->pdev->dev, "bind to driver %s --> %d\n",
5be19a9d
XS		 1884 driver->driver.name, retval);
1885 dev->driver = NULL;
1886 dev->gadget.dev.driver = NULL;
1887 return retval;
1888 }
1889
1890 retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
1891 if (retval)
1892 goto err_unbind;
1893
1894 dev->usb_state = USB_STATE_ATTACHED;
1895 dev->ep0_state = WAIT_FOR_SETUP;
1896 dev->ep0_dir = USB_DIR_OUT;
1897
1898 /* enable interrupt and set controller to run state */
1899 if (dev->got_irq)
1900 langwell_udc_start(dev);
1901
5f81f4b0
J		 1902 dev_vdbg(&dev->pdev->dev,
1903 "After langwell_udc_start(), print all registers:\n");
5be19a9d 1904 print_all_registers(dev);
5be19a9d 1905
5f81f4b0
J		 1906 dev_info(&dev->pdev->dev, "register driver: %s\n",
1907 driver->driver.name);
1908 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1909 return 0;
1910
1911err_unbind:
1912 driver->unbind(&dev->gadget);
1913 dev->gadget.dev.driver = NULL;
1914 dev->driver = NULL;
1915
5f81f4b0 1916 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1917 return retval;
1918}
1919EXPORT_SYMBOL(usb_gadget_register_driver);
1920
1921
1922/* unregister gadget driver */
1923int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1924{
1925 struct langwell_udc *dev = the_controller;
1926 unsigned long flags;
1927
1928 if (!dev)
1929 return -ENODEV;
1930
5f81f4b0 1931 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1932
1933 if (unlikely(!driver || !driver->bind || !driver->unbind))
1934 return -EINVAL;
1935
513b91b6
J		 1936 /* exit PHY low power suspend */
1937 if (dev->pdev->device != 0x0829)
1938 langwell_phy_low_power(dev, 0);
1939
5be19a9d
XS		 1940 /* unbind OTG transceiver */
1941 if (dev->transceiver)
1942 (void)otg_set_peripheral(dev->transceiver, 0);
1943
1944 /* disable interrupt and set controller to stop state */
1945 langwell_udc_stop(dev);
1946
1947 dev->usb_state = USB_STATE_ATTACHED;
1948 dev->ep0_state = WAIT_FOR_SETUP;
1949 dev->ep0_dir = USB_DIR_OUT;
1950
1951 spin_lock_irqsave(&dev->lock, flags);
1952
1953 /* stop all usb activities */
1954 dev->gadget.speed = USB_SPEED_UNKNOWN;
1955 stop_activity(dev, driver);
1956 spin_unlock_irqrestore(&dev->lock, flags);
1957
1958 /* unbind gadget driver */
1959 driver->unbind(&dev->gadget);
1960 dev->gadget.dev.driver = NULL;
1961 dev->driver = NULL;
1962
1963 device_remove_file(&dev->pdev->dev, &dev_attr_function);
1964
5f81f4b0
J		 1965 dev_info(&dev->pdev->dev, "unregistered driver '%s'\n",
1966 driver->driver.name);
1967 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1968 return 0;
1969}
1970EXPORT_SYMBOL(usb_gadget_unregister_driver);
1971
1972
1973/*-------------------------------------------------------------------------*/
1974
1975/*
1976 * setup tripwire is used as a semaphore to ensure that the setup data
1977 * payload is extracted from a dQH without being corrupted
1978 */
1979static void setup_tripwire(struct langwell_udc *dev)
1980{
1981 u32 usbcmd,
1982 endptsetupstat;
1983 unsigned long timeout;
1984 struct langwell_dqh *dqh;
1985
5f81f4b0 1986 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1987
1988 /* ep0 OUT dQH */
1989 dqh = &dev->ep_dqh[EP_DIR_OUT];
1990
1991 /* Write-Clear endptsetupstat */
1992 endptsetupstat = readl(&dev->op_regs->endptsetupstat);
1993 writel(endptsetupstat, &dev->op_regs->endptsetupstat);
1994
1995 /* wait until endptsetupstat is cleared */
1996 timeout = jiffies + SETUPSTAT_TIMEOUT;
1997 while (readl(&dev->op_regs->endptsetupstat)) {
1998 if (time_after(jiffies, timeout)) {
5f81f4b0 1999 dev_err(&dev->pdev->dev, "setup_tripwire timeout\n");
5be19a9d
XS		 2000 break;
2001 }
2002 cpu_relax();
2003 }
2004
2005 /* while a hazard exists when setup packet arrives */
2006 do {
2007 /* set setup tripwire bit */
2008 usbcmd = readl(&dev->op_regs->usbcmd);
2009 writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
2010
2011 /* copy the setup packet to local buffer */
2012 memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
2013 } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
2014
2015 /* Write-Clear setup tripwire bit */
2016 usbcmd = readl(&dev->op_regs->usbcmd);
2017 writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
2018
5f81f4b0 2019 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2020}
2021
2022
2023/* protocol ep0 stall, will automatically be cleared on new transaction */
2024static void ep0_stall(struct langwell_udc *dev)
2025{
2026 u32 endptctrl;
2027
5f81f4b0 2028 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2029
2030 /* set TX and RX to stall */
2031 endptctrl = readl(&dev->op_regs->endptctrl[0]);
2032 endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
2033 writel(endptctrl, &dev->op_regs->endptctrl[0]);
2034
2035 /* update ep0 state */
2036 dev->ep0_state = WAIT_FOR_SETUP;
2037 dev->ep0_dir = USB_DIR_OUT;
2038
5f81f4b0 2039 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2040}
2041
2042
2043/* PRIME a status phase for ep0 */
2044static int prime_status_phase(struct langwell_udc *dev, int dir)
2045{
2046 struct langwell_request *req;
2047 struct langwell_ep *ep;
2048 int status = 0;
2049
5f81f4b0 2050 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2051
2052 if (dir == EP_DIR_IN)
2053 dev->ep0_dir = USB_DIR_IN;
2054 else
2055 dev->ep0_dir = USB_DIR_OUT;
2056
2057 ep = &dev->ep[0];
2058 dev->ep0_state = WAIT_FOR_OUT_STATUS;
2059
2060 req = dev->status_req;
2061
2062 req->ep = ep;
2063 req->req.length = 0;
2064 req->req.status = -EINPROGRESS;
2065 req->req.actual = 0;
2066 req->req.complete = NULL;
2067 req->dtd_count = 0;
2068
2069 if (!req_to_dtd(req))
2070 status = queue_dtd(ep, req);
2071 else
2072 return -ENOMEM;
2073
2074 if (status)
5f81f4b0 2075 dev_err(&dev->pdev->dev, "can't queue ep0 status request\n");
5be19a9d
XS		 2076
2077 list_add_tail(&req->queue, &ep->queue);
2078
5f81f4b0 2079 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2080 return status;
2081}
2082
2083
2084/* SET_ADDRESS request routine */
2085static void set_address(struct langwell_udc *dev, u16 value,
2086 u16 index, u16 length)
2087{
5f81f4b0 2088 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2089
2090 /* save the new address to device struct */
2091 dev->dev_addr = (u8) value;
5f81f4b0 2092 dev_vdbg(&dev->pdev->dev, "dev->dev_addr = %d\n", dev->dev_addr);
5be19a9d
XS		 2093
2094 /* update usb state */
2095 dev->usb_state = USB_STATE_ADDRESS;
2096
2097 /* STATUS phase */
2098 if (prime_status_phase(dev, EP_DIR_IN))
2099 ep0_stall(dev);
2100
5f81f4b0 2101 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2102}
2103
2104
2105/* return endpoint by windex */
2106static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
2107 u16 wIndex)
2108{
2109 struct langwell_ep *ep;
5f81f4b0 2110 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2111
2112 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
2113 return &dev->ep[0];
2114
2115 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
2116 u8 bEndpointAddress;
2117 if (!ep->desc)
2118 continue;
2119
2120 bEndpointAddress = ep->desc->bEndpointAddress;
2121 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
2122 continue;
2123
2124 if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
2125 == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
2126 return ep;
2127 }
2128
5f81f4b0 2129 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2130 return NULL;
2131}
2132
2133
2134/* return whether endpoint is stalled, 0: not stalled; 1: stalled */
2135static int ep_is_stall(struct langwell_ep *ep)
2136{
2137 struct langwell_udc *dev = ep->dev;
2138 u32 endptctrl;
2139 int retval;
2140
5f81f4b0 2141 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2142
2143 endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
2144 if (is_in(ep))
2145 retval = endptctrl & EPCTRL_TXS ? 1 : 0;
2146 else
2147 retval = endptctrl & EPCTRL_RXS ? 1 : 0;
2148
5f81f4b0 2149 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2150 return retval;
2151}
2152
2153
2154/* GET_STATUS request routine */
2155static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
2156 u16 index, u16 length)
2157{
2158 struct langwell_request *req;
2159 struct langwell_ep *ep;
2160 u16 status_data = 0; /* 16 bits cpu view status data */
2161 int status = 0;
2162
5f81f4b0 2163 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2164
2165 ep = &dev->ep[0];
2166
2167 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
2168 /* get device status */
3211cbc2 2169 status_data = dev->dev_status;
5be19a9d
XS		 2170 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
2171 /* get interface status */
2172 status_data = 0;
2173 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
2174 /* get endpoint status */
2175 struct langwell_ep *epn;
2176 epn = get_ep_by_windex(dev, index);
2177 /* stall if endpoint doesn't exist */
2178 if (!epn)
2179 goto stall;
2180
2181 status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
2182 }
2183
5f81f4b0
J		 2184 dev_dbg(&dev->pdev->dev, "get status data: 0x%04x\n", status_data);
2185
5be19a9d
XS		 2186 dev->ep0_dir = USB_DIR_IN;
2187
2188 /* borrow the per device status_req */
2189 req = dev->status_req;
2190
2191 /* fill in the reqest structure */
2192 *((u16 *) req->req.buf) = cpu_to_le16(status_data);
2193 req->ep = ep;
2194 req->req.length = 2;
2195 req->req.status = -EINPROGRESS;
2196 req->req.actual = 0;
2197 req->req.complete = NULL;
2198 req->dtd_count = 0;
2199
2200 /* prime the data phase */
2201 if (!req_to_dtd(req))
2202 status = queue_dtd(ep, req);
2203 else /* no mem */
2204 goto stall;
2205
2206 if (status) {
5f81f4b0
J		 2207 dev_err(&dev->pdev->dev,
2208 "response error on GET_STATUS request\n");
5be19a9d
XS		 2209 goto stall;
2210 }
2211
2212 list_add_tail(&req->queue, &ep->queue);
2213 dev->ep0_state = DATA_STATE_XMIT;
2214
5f81f4b0 2215 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2216 return;
2217stall:
2218 ep0_stall(dev);
5f81f4b0 2219 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2220}
2221
2222
2223/* setup packet interrupt handler */
2224static void handle_setup_packet(struct langwell_udc *dev,
2225 struct usb_ctrlrequest *setup)
2226{
2227 u16 wValue = le16_to_cpu(setup->wValue);
2228 u16 wIndex = le16_to_cpu(setup->wIndex);
2229 u16 wLength = le16_to_cpu(setup->wLength);
2230
5f81f4b0 2231 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2232
2233 /* ep0 fifo flush */
2234 nuke(&dev->ep[0], -ESHUTDOWN);
2235
5f81f4b0 2236 dev_dbg(&dev->pdev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
5be19a9d
XS		 2237 setup->bRequestType, setup->bRequest,
2238 wValue, wIndex, wLength);
2239
2240 /* RNDIS gadget delegate */
2241 if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
2242 /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
2243 goto delegate;
2244 }
2245
2246 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
2247 if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
2248 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
2249 goto delegate;
2250 }
2251
2252 /* We process some stardard setup requests here */
2253 switch (setup->bRequest) {
2254 case USB_REQ_GET_STATUS:
5f81f4b0 2255 dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_GET_STATUS\n");
5be19a9d
XS		 2256 /* get status, DATA and STATUS phase */
2257 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
2258 != (USB_DIR_IN | USB_TYPE_STANDARD))
2259 break;
2260 get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
2261 goto end;
2262
2263 case USB_REQ_SET_ADDRESS:
5f81f4b0 2264 dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_SET_ADDRESS\n");
5be19a9d
XS		 2265 /* STATUS phase */
2266 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
2267 | USB_RECIP_DEVICE))
2268 break;
2269 set_address(dev, wValue, wIndex, wLength);
2270 goto end;
2271
2272 case USB_REQ_CLEAR_FEATURE:
2273 case USB_REQ_SET_FEATURE:
2274 /* STATUS phase */
2275 {
2276 int rc = -EOPNOTSUPP;
2277 if (setup->bRequest == USB_REQ_SET_FEATURE)
5f81f4b0
J		 2278 dev_dbg(&dev->pdev->dev,
2279 "SETUP: USB_REQ_SET_FEATURE\n");
5be19a9d 2280 else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
5f81f4b0
J		 2281 dev_dbg(&dev->pdev->dev,
2282 "SETUP: USB_REQ_CLEAR_FEATURE\n");
5be19a9d
XS		 2283
2284 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
2285 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
2286 struct langwell_ep *epn;
2287 epn = get_ep_by_windex(dev, wIndex);
2288 /* stall if endpoint doesn't exist */
2289 if (!epn) {
2290 ep0_stall(dev);
2291 goto end;
2292 }
2293
2294 if (wValue != 0 || wLength != 0
2295 || epn->ep_num > dev->ep_max)
2296 break;
2297
2298 spin_unlock(&dev->lock);
2299 rc = langwell_ep_set_halt(&epn->ep,
5f81f4b0
J		 2300 (setup->bRequest == USB_REQ_SET_FEATURE)
2301 ? 1 : 0);
5be19a9d
XS		 2302 spin_lock(&dev->lock);
2303
2304 } else if ((setup->bRequestType & (USB_RECIP_MASK
2305 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
2306 | USB_TYPE_STANDARD)) {
3211cbc2
J		 2307 rc = 0;
2308 switch (wValue) {
2309 case USB_DEVICE_REMOTE_WAKEUP:
2310 if (setup->bRequest == USB_REQ_SET_FEATURE) {
2311 dev->remote_wakeup = 1;
2312 dev->dev_status |= (1 << wValue);
2313 } else {
2314 dev->remote_wakeup = 0;
2315 dev->dev_status &= ~(1 << wValue);
2316 }
2317 break;
2318 default:
2319 rc = -EOPNOTSUPP;
2320 break;
2321 }
2322
5be19a9d
XS		 2323 if (!gadget_is_otg(&dev->gadget))
2324 break;
2325 else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) {
2326 dev->gadget.b_hnp_enable = 1;
2327#ifdef OTG_TRANSCEIVER
2328 if (!dev->lotg->otg.default_a)
2329 dev->lotg->hsm.b_hnp_enable = 1;
2330#endif
2331 } else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
2332 dev->gadget.a_hnp_support = 1;
2333 else if (setup->bRequest ==
2334 USB_DEVICE_A_ALT_HNP_SUPPORT)
2335 dev->gadget.a_alt_hnp_support = 1;
2336 else
2337 break;
5be19a9d
XS		 2338 } else
2339 break;
2340
2341 if (rc == 0) {
2342 if (prime_status_phase(dev, EP_DIR_IN))
2343 ep0_stall(dev);
2344 }
2345 goto end;
2346 }
2347
2348 case USB_REQ_GET_DESCRIPTOR:
5f81f4b0
J		 2349 dev_dbg(&dev->pdev->dev,
2350 "SETUP: USB_REQ_GET_DESCRIPTOR\n");
5be19a9d
XS		 2351 goto delegate;
2352
2353 case USB_REQ_SET_DESCRIPTOR:
5f81f4b0
J		 2354 dev_dbg(&dev->pdev->dev,
2355 "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
5be19a9d
XS		 2356 goto delegate;
2357
2358 case USB_REQ_GET_CONFIGURATION:
5f81f4b0
J		 2359 dev_dbg(&dev->pdev->dev,
2360 "SETUP: USB_REQ_GET_CONFIGURATION\n");
5be19a9d
XS		 2361 goto delegate;
2362
2363 case USB_REQ_SET_CONFIGURATION:
5f81f4b0
J		 2364 dev_dbg(&dev->pdev->dev,
2365 "SETUP: USB_REQ_SET_CONFIGURATION\n");
5be19a9d
XS		 2366 goto delegate;
2367
2368 case USB_REQ_GET_INTERFACE:
5f81f4b0
J		 2369 dev_dbg(&dev->pdev->dev,
2370 "SETUP: USB_REQ_GET_INTERFACE\n");
5be19a9d
XS		 2371 goto delegate;
2372
2373 case USB_REQ_SET_INTERFACE:
5f81f4b0
J		 2374 dev_dbg(&dev->pdev->dev,
2375 "SETUP: USB_REQ_SET_INTERFACE\n");
5be19a9d
XS		 2376 goto delegate;
2377
2378 case USB_REQ_SYNCH_FRAME:
5f81f4b0
J		 2379 dev_dbg(&dev->pdev->dev,
2380 "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
5be19a9d
XS		 2381 goto delegate;
2382
2383 default:
2384 /* delegate USB standard requests to the gadget driver */
2385 goto delegate;
2386delegate:
2387 /* USB requests handled by gadget */
2388 if (wLength) {
2389 /* DATA phase from gadget, STATUS phase from udc */
2390 dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
2391 ? USB_DIR_IN : USB_DIR_OUT;
5f81f4b0
J		 2392 dev_vdbg(&dev->pdev->dev,
2393 "dev->ep0_dir = 0x%x, wLength = %d\n",
5be19a9d
XS		 2394 dev->ep0_dir, wLength);
2395 spin_unlock(&dev->lock);
2396 if (dev->driver->setup(&dev->gadget,
2397 &dev->local_setup_buff) < 0)
2398 ep0_stall(dev);
2399 spin_lock(&dev->lock);
2400 dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
2401 ? DATA_STATE_XMIT : DATA_STATE_RECV;
2402 } else {
2403 /* no DATA phase, IN STATUS phase from gadget */
2404 dev->ep0_dir = USB_DIR_IN;
5f81f4b0
J		 2405 dev_vdbg(&dev->pdev->dev,
2406 "dev->ep0_dir = 0x%x, wLength = %d\n",
5be19a9d
XS		 2407 dev->ep0_dir, wLength);
2408 spin_unlock(&dev->lock);
2409 if (dev->driver->setup(&dev->gadget,
2410 &dev->local_setup_buff) < 0)
2411 ep0_stall(dev);
2412 spin_lock(&dev->lock);
2413 dev->ep0_state = WAIT_FOR_OUT_STATUS;
2414 }
2415 break;
2416 }
2417end:
5f81f4b0 2418 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2419 return;
2420}
2421
2422
2423/* transfer completion, process endpoint request and free the completed dTDs
2424 * for this request
2425 */
2426static int process_ep_req(struct langwell_udc *dev, int index,
2427 struct langwell_request *curr_req)
2428{
2429 struct langwell_dtd *curr_dtd;
2430 struct langwell_dqh *curr_dqh;
2431 int td_complete, actual, remaining_length;
2432 int i, dir;
2433 u8 dtd_status = 0;
2434 int retval = 0;
2435
2436 curr_dqh = &dev->ep_dqh[index];
2437 dir = index % 2;
2438
2439 curr_dtd = curr_req->head;
2440 td_complete = 0;
2441 actual = curr_req->req.length;
2442
5f81f4b0 2443 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2444
2445 for (i = 0; i < curr_req->dtd_count; i++) {
2446 remaining_length = le16_to_cpu(curr_dtd->dtd_total);
2447 actual -= remaining_length;
2448
2449 /* command execution states by dTD */
2450 dtd_status = curr_dtd->dtd_status;
2451
2452 if (!dtd_status) {
2453 /* transfers completed successfully */
2454 if (!remaining_length) {
2455 td_complete++;
5f81f4b0
J		 2456 dev_vdbg(&dev->pdev->dev,
2457 "dTD transmitted successfully\n");
5be19a9d
XS		 2458 } else {
2459 if (dir) {
5f81f4b0
J		 2460 dev_vdbg(&dev->pdev->dev,
2461 "TX dTD remains data\n");
5be19a9d
XS		 2462 retval = -EPROTO;
2463 break;
2464
2465 } else {
2466 td_complete++;
2467 break;
2468 }
2469 }
2470 } else {
2471 /* transfers completed with errors */
2472 if (dtd_status & DTD_STS_ACTIVE) {
5f81f4b0
J		 2473 dev_dbg(&dev->pdev->dev,
2474 "dTD status ACTIVE dQH[%d]\n", index);
5be19a9d
XS		 2475 retval = 1;
2476 return retval;
2477 } else if (dtd_status & DTD_STS_HALTED) {
5f81f4b0
J		 2478 dev_err(&dev->pdev->dev,
2479 "dTD error %08x dQH[%d]\n",
2480 dtd_status, index);
5be19a9d
XS		 2481 /* clear the errors and halt condition */
2482 curr_dqh->dtd_status = 0;
2483 retval = -EPIPE;
2484 break;
2485 } else if (dtd_status & DTD_STS_DBE) {
5f81f4b0
J		 2486 dev_dbg(&dev->pdev->dev,
2487 "data buffer (overflow) error\n");
5be19a9d
XS		 2488 retval = -EPROTO;
2489 break;
2490 } else if (dtd_status & DTD_STS_TRE) {
5f81f4b0
J		 2491 dev_dbg(&dev->pdev->dev,
2492 "transaction(ISO) error\n");
5be19a9d
XS		 2493 retval = -EILSEQ;
2494 break;
2495 } else
5f81f4b0
J		 2496 dev_err(&dev->pdev->dev,
2497 "unknown error (0x%x)!\n",
2498 dtd_status);
5be19a9d
XS		 2499 }
2500
2501 if (i != curr_req->dtd_count - 1)
2502 curr_dtd = (struct langwell_dtd *)
2503 curr_dtd->next_dtd_virt;
2504 }
2505
2506 if (retval)
2507 return retval;
2508
2509 curr_req->req.actual = actual;
2510
5f81f4b0 2511 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2512 return 0;
2513}
2514
2515
2516/* complete DATA or STATUS phase of ep0 prime status phase if needed */
2517static void ep0_req_complete(struct langwell_udc *dev,
2518 struct langwell_ep *ep0, struct langwell_request *req)
2519{
2520 u32 new_addr;
5f81f4b0 2521 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2522
2523 if (dev->usb_state == USB_STATE_ADDRESS) {
2524 /* set the new address */
2525 new_addr = (u32)dev->dev_addr;
2526 writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
2527
2528 new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
5f81f4b0 2529 dev_vdbg(&dev->pdev->dev, "new_addr = %d\n", new_addr);
5be19a9d
XS		 2530 }
2531
2532 done(ep0, req, 0);
2533
2534 switch (dev->ep0_state) {
2535 case DATA_STATE_XMIT:
2536 /* receive status phase */
2537 if (prime_status_phase(dev, EP_DIR_OUT))
2538 ep0_stall(dev);
2539 break;
2540 case DATA_STATE_RECV:
2541 /* send status phase */
2542 if (prime_status_phase(dev, EP_DIR_IN))
2543 ep0_stall(dev);
2544 break;
2545 case WAIT_FOR_OUT_STATUS:
2546 dev->ep0_state = WAIT_FOR_SETUP;
2547 break;
2548 case WAIT_FOR_SETUP:
5f81f4b0 2549 dev_err(&dev->pdev->dev, "unexpect ep0 packets\n");
5be19a9d
XS		 2550 break;
2551 default:
2552 ep0_stall(dev);
2553 break;
2554 }
2555
5f81f4b0 2556 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2557}
2558
2559
2560/* USB transfer completion interrupt */
2561static void handle_trans_complete(struct langwell_udc *dev)
2562{
2563 u32 complete_bits;
2564 int i, ep_num, dir, bit_mask, status;
2565 struct langwell_ep *epn;
2566 struct langwell_request *curr_req, *temp_req;
2567
5f81f4b0 2568 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2569
2570 complete_bits = readl(&dev->op_regs->endptcomplete);
5f81f4b0
J		 2571 dev_vdbg(&dev->pdev->dev, "endptcomplete register: 0x%08x\n",
2572 complete_bits);
5be19a9d
XS		 2573
2574 /* Write-Clear the bits in endptcomplete register */
2575 writel(complete_bits, &dev->op_regs->endptcomplete);
2576
2577 if (!complete_bits) {
5f81f4b0 2578 dev_dbg(&dev->pdev->dev, "complete_bits = 0\n");
5be19a9d
XS		 2579 goto done;
2580 }
2581
2582 for (i = 0; i < dev->ep_max; i++) {
2583 ep_num = i / 2;
2584 dir = i % 2;
2585
2586 bit_mask = 1 << (ep_num + 16 * dir);
2587
2588 if (!(complete_bits & bit_mask))
2589 continue;
2590
2591 /* ep0 */
2592 if (i == 1)
2593 epn = &dev->ep[0];
2594 else
2595 epn = &dev->ep[i];
2596
2597 if (epn->name == NULL) {
5f81f4b0 2598 dev_warn(&dev->pdev->dev, "invalid endpoint\n");
5be19a9d
XS		 2599 continue;
2600 }
2601
2602 if (i < 2)
2603 /* ep0 in and out */
5f81f4b0 2604 dev_dbg(&dev->pdev->dev, "%s-%s transfer completed\n",
5be19a9d
XS		 2605 epn->name,
2606 is_in(epn) ? "in" : "out");
2607 else
5f81f4b0
J		 2608 dev_dbg(&dev->pdev->dev, "%s transfer completed\n",
2609 epn->name);
5be19a9d
XS		 2610
2611 /* process the req queue until an uncomplete request */
2612 list_for_each_entry_safe(curr_req, temp_req,
2613 &epn->queue, queue) {
2614 status = process_ep_req(dev, i, curr_req);
5f81f4b0
J		 2615 dev_vdbg(&dev->pdev->dev, "%s req status: %d\n",
2616 epn->name, status);
5be19a9d
XS		 2617
2618 if (status)
2619 break;
2620
2621 /* write back status to req */
2622 curr_req->req.status = status;
2623
2624 /* ep0 request completion */
2625 if (ep_num == 0) {
2626 ep0_req_complete(dev, epn, curr_req);
2627 break;
2628 } else {
2629 done(epn, curr_req, status);
2630 }
2631 }
2632 }
2633done:
5f81f4b0 2634 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2635 return;
2636}
2637
2638
2639/* port change detect interrupt handler */
2640static void handle_port_change(struct langwell_udc *dev)
2641{
2642 u32 portsc1, devlc;
2643 u32 speed;
2644
5f81f4b0 2645 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2646
2647 if (dev->bus_reset)
2648 dev->bus_reset = 0;
2649
2650 portsc1 = readl(&dev->op_regs->portsc1);
2651 devlc = readl(&dev->op_regs->devlc);
5f81f4b0 2652 dev_vdbg(&dev->pdev->dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
5be19a9d
XS		 2653 portsc1, devlc);
2654
2655 /* bus reset is finished */
2656 if (!(portsc1 & PORTS_PR)) {
2657 /* get the speed */
2658 speed = LPM_PSPD(devlc);
2659 switch (speed) {
2660 case LPM_SPEED_HIGH:
2661 dev->gadget.speed = USB_SPEED_HIGH;
2662 break;
2663 case LPM_SPEED_FULL:
2664 dev->gadget.speed = USB_SPEED_FULL;
2665 break;
2666 case LPM_SPEED_LOW:
2667 dev->gadget.speed = USB_SPEED_LOW;
2668 break;
2669 default:
2670 dev->gadget.speed = USB_SPEED_UNKNOWN;
2671 break;
2672 }
5f81f4b0
J		 2673 dev_vdbg(&dev->pdev->dev,
2674 "speed = %d, dev->gadget.speed = %d\n",
5be19a9d
XS		 2675 speed, dev->gadget.speed);
2676 }
2677
2678 /* LPM L0 to L1 */
2679 if (dev->lpm && dev->lpm_state == LPM_L0)
2680 if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
5f81f4b0
J		 2681 dev_info(&dev->pdev->dev, "LPM L0 to L1\n");
2682 dev->lpm_state = LPM_L1;
5be19a9d
XS		 2683 }
2684
2685 /* LPM L1 to L0, force resume or remote wakeup finished */
2686 if (dev->lpm && dev->lpm_state == LPM_L1)
2687 if (!(portsc1 & PORTS_SUSP)) {
5f81f4b0 2688 dev_info(&dev->pdev->dev, "LPM L1 to L0\n");
5be19a9d
XS		 2689 dev->lpm_state = LPM_L0;
2690 }
2691
2692 /* update USB state */
2693 if (!dev->resume_state)
2694 dev->usb_state = USB_STATE_DEFAULT;
2695
5f81f4b0 2696 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2697}
2698
2699
2700/* USB reset interrupt handler */
2701static void handle_usb_reset(struct langwell_udc *dev)
2702{
2703 u32 deviceaddr,
2704 endptsetupstat,
2705 endptcomplete;
2706 unsigned long timeout;
2707
5f81f4b0 2708 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2709
2710 /* Write-Clear the device address */
2711 deviceaddr = readl(&dev->op_regs->deviceaddr);
2712 writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
2713
2714 dev->dev_addr = 0;
2715
2716 /* clear usb state */
2717 dev->resume_state = 0;
2718
2719 /* LPM L1 to L0, reset */
2720 if (dev->lpm)
2721 dev->lpm_state = LPM_L0;
2722
2723 dev->ep0_dir = USB_DIR_OUT;
2724 dev->ep0_state = WAIT_FOR_SETUP;
3211cbc2
J		 2725
2726 /* remote wakeup reset to 0 when the device is reset */
2727 dev->remote_wakeup = 0;
2728 dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
5be19a9d
XS		 2729 dev->gadget.b_hnp_enable = 0;
2730 dev->gadget.a_hnp_support = 0;
2731 dev->gadget.a_alt_hnp_support = 0;
2732
2733 /* Write-Clear all the setup token semaphores */
2734 endptsetupstat = readl(&dev->op_regs->endptsetupstat);
2735 writel(endptsetupstat, &dev->op_regs->endptsetupstat);
2736
2737 /* Write-Clear all the endpoint complete status bits */
2738 endptcomplete = readl(&dev->op_regs->endptcomplete);
2739 writel(endptcomplete, &dev->op_regs->endptcomplete);
2740
2741 /* wait until all endptprime bits cleared */
2742 timeout = jiffies + PRIME_TIMEOUT;
2743 while (readl(&dev->op_regs->endptprime)) {
2744 if (time_after(jiffies, timeout)) {
5f81f4b0 2745 dev_err(&dev->pdev->dev, "USB reset timeout\n");
5be19a9d
XS		 2746 break;
2747 }
2748 cpu_relax();
2749 }
2750
2751 /* write 1s to endptflush register to clear any primed buffers */
2752 writel((u32) ~0, &dev->op_regs->endptflush);
2753
2754 if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
5f81f4b0 2755 dev_vdbg(&dev->pdev->dev, "USB bus reset\n");
5be19a9d
XS		 2756 /* bus is reseting */
2757 dev->bus_reset = 1;
2758
2759 /* reset all the queues, stop all USB activities */
2760 stop_activity(dev, dev->driver);
2761 dev->usb_state = USB_STATE_DEFAULT;
2762 } else {
5f81f4b0 2763 dev_vdbg(&dev->pdev->dev, "device controller reset\n");
5be19a9d
XS		 2764 /* controller reset */
2765 langwell_udc_reset(dev);
2766
2767 /* reset all the queues, stop all USB activities */
2768 stop_activity(dev, dev->driver);
2769
2770 /* reset ep0 dQH and endptctrl */
2771 ep0_reset(dev);
2772
2773 /* enable interrupt and set controller to run state */
2774 langwell_udc_start(dev);
2775
2776 dev->usb_state = USB_STATE_ATTACHED;
2777 }
2778
2779#ifdef OTG_TRANSCEIVER
2780 /* refer to USB OTG 6.6.2.3 b_hnp_en is cleared */
2781 if (!dev->lotg->otg.default_a)
2782 dev->lotg->hsm.b_hnp_enable = 0;
2783#endif
2784
5f81f4b0 2785 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2786}
2787
2788
2789/* USB bus suspend/resume interrupt */
2790static void handle_bus_suspend(struct langwell_udc *dev)
2791{
5f81f4b0 2792 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2793
2794 dev->resume_state = dev->usb_state;
2795 dev->usb_state = USB_STATE_SUSPENDED;
2796
2797#ifdef OTG_TRANSCEIVER
2798 if (dev->lotg->otg.default_a) {
2799 if (dev->lotg->hsm.b_bus_suspend_vld == 1) {
2800 dev->lotg->hsm.b_bus_suspend = 1;
2801 /* notify transceiver the state changes */
2802 if (spin_trylock(&dev->lotg->wq_lock)) {
2803 langwell_update_transceiver();
2804 spin_unlock(&dev->lotg->wq_lock);
2805 }
2806 }
2807 dev->lotg->hsm.b_bus_suspend_vld++;
2808 } else {
2809 if (!dev->lotg->hsm.a_bus_suspend) {
2810 dev->lotg->hsm.a_bus_suspend = 1;
2811 /* notify transceiver the state changes */
2812 if (spin_trylock(&dev->lotg->wq_lock)) {
2813 langwell_update_transceiver();
2814 spin_unlock(&dev->lotg->wq_lock);
2815 }
2816 }
2817 }
2818#endif
2819
2820 /* report suspend to the driver */
2821 if (dev->driver) {
2822 if (dev->driver->suspend) {
2823 spin_unlock(&dev->lock);
2824 dev->driver->suspend(&dev->gadget);
2825 spin_lock(&dev->lock);
5f81f4b0
J		 2826 dev_dbg(&dev->pdev->dev, "suspend %s\n",
2827 dev->driver->driver.name);
5be19a9d
XS		 2828 }
2829 }
2830
2831 /* enter PHY low power suspend */
513b91b6
J		 2832 if (dev->pdev->device != 0x0829)
2833 langwell_phy_low_power(dev, 0);
5be19a9d 2834
5f81f4b0 2835 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2836}
2837
2838
2839static void handle_bus_resume(struct langwell_udc *dev)
2840{
5f81f4b0 2841 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2842
2843 dev->usb_state = dev->resume_state;
2844 dev->resume_state = 0;
2845
2846 /* exit PHY low power suspend */
513b91b6
J		 2847 if (dev->pdev->device != 0x0829)
2848 langwell_phy_low_power(dev, 0);
5be19a9d
XS		 2849
2850#ifdef OTG_TRANSCEIVER
2851 if (dev->lotg->otg.default_a == 0)
2852 dev->lotg->hsm.a_bus_suspend = 0;
2853#endif
2854
2855 /* report resume to the driver */
2856 if (dev->driver) {
2857 if (dev->driver->resume) {
2858 spin_unlock(&dev->lock);
2859 dev->driver->resume(&dev->gadget);
2860 spin_lock(&dev->lock);
5f81f4b0
J		 2861 dev_dbg(&dev->pdev->dev, "resume %s\n",
2862 dev->driver->driver.name);
5be19a9d
XS		 2863 }
2864 }
2865
5f81f4b0 2866 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2867}
2868
2869
2870/* USB device controller interrupt handler */
2871static irqreturn_t langwell_irq(int irq, void *_dev)
2872{
2873 struct langwell_udc *dev = _dev;
2874 u32 usbsts,
2875 usbintr,
2876 irq_sts,
2877 portsc1;
2878
5f81f4b0 2879 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2880
2881 if (dev->stopped) {
5f81f4b0
J		 2882 dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
2883 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2884 return IRQ_NONE;
2885 }
2886
2887 spin_lock(&dev->lock);
2888
2889 /* USB status */
2890 usbsts = readl(&dev->op_regs->usbsts);
2891
2892 /* USB interrupt enable */
2893 usbintr = readl(&dev->op_regs->usbintr);
2894
2895 irq_sts = usbsts & usbintr;
5f81f4b0
J		 2896 dev_vdbg(&dev->pdev->dev,
2897 "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
5be19a9d
XS		 2898 usbsts, usbintr, irq_sts);
2899
2900 if (!irq_sts) {
5f81f4b0
J		 2901 dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
2902 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2903 spin_unlock(&dev->lock);
2904 return IRQ_NONE;
2905 }
2906
2907 /* Write-Clear interrupt status bits */
2908 writel(irq_sts, &dev->op_regs->usbsts);
2909
2910 /* resume from suspend */
2911 portsc1 = readl(&dev->op_regs->portsc1);
2912 if (dev->usb_state == USB_STATE_SUSPENDED)
2913 if (!(portsc1 & PORTS_SUSP))
2914 handle_bus_resume(dev);
2915
2916 /* USB interrupt */
2917 if (irq_sts & STS_UI) {
5f81f4b0 2918 dev_vdbg(&dev->pdev->dev, "USB interrupt\n");
5be19a9d
XS		 2919
2920 /* setup packet received from ep0 */
2921 if (readl(&dev->op_regs->endptsetupstat)
2922 & EP0SETUPSTAT_MASK) {
5f81f4b0
J		 2923 dev_vdbg(&dev->pdev->dev,
2924 "USB SETUP packet received interrupt\n");
5be19a9d
XS		 2925 /* setup tripwire semaphone */
2926 setup_tripwire(dev);
2927 handle_setup_packet(dev, &dev->local_setup_buff);
2928 }
2929
2930 /* USB transfer completion */
2931 if (readl(&dev->op_regs->endptcomplete)) {
5f81f4b0
J		 2932 dev_vdbg(&dev->pdev->dev,
2933 "USB transfer completion interrupt\n");
5be19a9d
XS		 2934 handle_trans_complete(dev);
2935 }
2936 }
2937
2938 /* SOF received interrupt (for ISO transfer) */
2939 if (irq_sts & STS_SRI) {
2940 /* FIXME */
5f81f4b0 2941 /* dev_vdbg(&dev->pdev->dev, "SOF received interrupt\n"); */
5be19a9d
XS		 2942 }
2943
2944 /* port change detect interrupt */
2945 if (irq_sts & STS_PCI) {
5f81f4b0 2946 dev_vdbg(&dev->pdev->dev, "port change detect interrupt\n");
5be19a9d
XS		 2947 handle_port_change(dev);
2948 }
2949
2950 /* suspend interrrupt */
2951 if (irq_sts & STS_SLI) {
5f81f4b0 2952 dev_vdbg(&dev->pdev->dev, "suspend interrupt\n");
5be19a9d
XS		 2953 handle_bus_suspend(dev);
2954 }
2955
2956 /* USB reset interrupt */
2957 if (irq_sts & STS_URI) {
5f81f4b0 2958 dev_vdbg(&dev->pdev->dev, "USB reset interrupt\n");
5be19a9d
XS		 2959 handle_usb_reset(dev);
2960 }
2961
2962 /* USB error or system error interrupt */
2963 if (irq_sts & (STS_UEI | STS_SEI)) {
2964 /* FIXME */
5f81f4b0 2965 dev_warn(&dev->pdev->dev, "error IRQ, irq_sts: %x\n", irq_sts);
5be19a9d
XS		 2966 }
2967
2968 spin_unlock(&dev->lock);
2969
5f81f4b0 2970 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2971 return IRQ_HANDLED;
2972}
2973
2974
2975/*-------------------------------------------------------------------------*/
2976
2977/* release device structure */
2978static void gadget_release(struct device *_dev)
2979{
2980 struct langwell_udc *dev = the_controller;
2981
5f81f4b0 2982 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2983
2984 complete(dev->done);
2985
5f81f4b0 2986 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2987 kfree(dev);
2988}
2989
2990
2991/* tear down the binding between this driver and the pci device */
2992static void langwell_udc_remove(struct pci_dev *pdev)
2993{
2994 struct langwell_udc *dev = the_controller;
2995
2996 DECLARE_COMPLETION(done);
2997
2998 BUG_ON(dev->driver);
5f81f4b0 2999 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3000
3001 dev->done = &done;
3002
3003 /* free memory allocated in probe */
3004 if (dev->dtd_pool)
3005 dma_pool_destroy(dev->dtd_pool);
3006
3007 if (dev->status_req) {
3008 kfree(dev->status_req->req.buf);
3009 kfree(dev->status_req);
3010 }
3011
3012 if (dev->ep_dqh)
3013 dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
3014 dev->ep_dqh, dev->ep_dqh_dma);
3015
3016 kfree(dev->ep);
3017
3018 /* diable IRQ handler */
3019 if (dev->got_irq)
3020 free_irq(pdev->irq, dev);
3021
3022#ifndef OTG_TRANSCEIVER
3023 if (dev->cap_regs)
3024 iounmap(dev->cap_regs);
3025
3026 if (dev->region)
3027 release_mem_region(pci_resource_start(pdev, 0),
3028 pci_resource_len(pdev, 0));
3029
3030 if (dev->enabled)
3031 pci_disable_device(pdev);
3032#else
3033 if (dev->transceiver) {
3034 otg_put_transceiver(dev->transceiver);
3035 dev->transceiver = NULL;
3036 dev->lotg = NULL;
3037 }
3038#endif
3039
3040 dev->cap_regs = NULL;
3041
5f81f4b0
J		 3042 dev_info(&dev->pdev->dev, "unbind\n");
3043 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3044
3045 device_unregister(&dev->gadget.dev);
3046 device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
3211cbc2 3047 device_remove_file(&pdev->dev, &dev_attr_remote_wakeup);
5be19a9d
XS		 3048
3049#ifndef OTG_TRANSCEIVER
3050 pci_set_drvdata(pdev, NULL);
3051#endif
3052
3053 /* free dev, wait for the release() finished */
3054 wait_for_completion(&done);
3055
3056 the_controller = NULL;
3057}
3058
3059
3060/*
3061 * wrap this driver around the specified device, but
3062 * don't respond over USB until a gadget driver binds to us.
3063 */
3064static int langwell_udc_probe(struct pci_dev *pdev,
3065 const struct pci_device_id *id)
3066{
3067 struct langwell_udc *dev;
3068#ifndef OTG_TRANSCEIVER
3069 unsigned long resource, len;
3070#endif
3071 void __iomem *base = NULL;
3072 size_t size;
3073 int retval;
3074
3075 if (the_controller) {
3076 dev_warn(&pdev->dev, "ignoring\n");
3077 return -EBUSY;
3078 }
3079
3080 /* alloc, and start init */
3081 dev = kzalloc(sizeof *dev, GFP_KERNEL);
3082 if (dev == NULL) {
3083 retval = -ENOMEM;
3084 goto error;
3085 }
3086
3087 /* initialize device spinlock */
3088 spin_lock_init(&dev->lock);
3089
3090 dev->pdev = pdev;
5f81f4b0 3091 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3092
3093#ifdef OTG_TRANSCEIVER
3094 /* PCI device is already enabled by otg_transceiver driver */
3095 dev->enabled = 1;
3096
3097 /* mem region and register base */
3098 dev->region = 1;
3099 dev->transceiver = otg_get_transceiver();
3100 dev->lotg = otg_to_langwell(dev->transceiver);
3101 base = dev->lotg->regs;
3102#else
3103 pci_set_drvdata(pdev, dev);
3104
3105 /* now all the pci goodies ... */
3106 if (pci_enable_device(pdev) < 0) {
3107 retval = -ENODEV;
3108 goto error;
3109 }
3110 dev->enabled = 1;
3111
3112 /* control register: BAR 0 */
3113 resource = pci_resource_start(pdev, 0);
3114 len = pci_resource_len(pdev, 0);
3115 if (!request_mem_region(resource, len, driver_name)) {
5f81f4b0 3116 dev_err(&dev->pdev->dev, "controller already in use\n");
5be19a9d
XS		 3117 retval = -EBUSY;
3118 goto error;
3119 }
3120 dev->region = 1;
3121
3122 base = ioremap_nocache(resource, len);
3123#endif
3124 if (base == NULL) {
5f81f4b0 3125 dev_err(&dev->pdev->dev, "can't map memory\n");
5be19a9d
XS		 3126 retval = -EFAULT;
3127 goto error;
3128 }
3129
3130 dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
5f81f4b0 3131 dev_vdbg(&dev->pdev->dev, "dev->cap_regs: %p\n", dev->cap_regs);
5be19a9d
XS		 3132 dev->op_regs = (struct langwell_op_regs __iomem *)
3133 (base + OP_REG_OFFSET);
5f81f4b0 3134 dev_vdbg(&dev->pdev->dev, "dev->op_regs: %p\n", dev->op_regs);
5be19a9d
XS		 3135
3136 /* irq setup after old hardware is cleaned up */
3137 if (!pdev->irq) {
5f81f4b0 3138 dev_err(&dev->pdev->dev, "No IRQ. Check PCI setup!\n");
5be19a9d
XS		 3139 retval = -ENODEV;
3140 goto error;
3141 }
3142
3143#ifndef OTG_TRANSCEIVER
5f81f4b0
J		 3144 dev_info(&dev->pdev->dev,
3145 "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
5be19a9d
XS		 3146 pdev->irq, resource, len, base);
3147 /* enables bus-mastering for device dev */
3148 pci_set_master(pdev);
3149
3150 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
3151 driver_name, dev) != 0) {
5f81f4b0
J		 3152 dev_err(&dev->pdev->dev,
3153 "request interrupt %d failed\n", pdev->irq);
5be19a9d
XS		 3154 retval = -EBUSY;
3155 goto error;
3156 }
3157 dev->got_irq = 1;
3158#endif
3159
3160 /* set stopped bit */
3161 dev->stopped = 1;
3162
3163 /* capabilities and endpoint number */
3164 dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
3165 dev->dciversion = readw(&dev->cap_regs->dciversion);
3166 dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
5f81f4b0
J		 3167 dev_vdbg(&dev->pdev->dev, "dev->lpm: %d\n", dev->lpm);
3168 dev_vdbg(&dev->pdev->dev, "dev->dciversion: 0x%04x\n",
3169 dev->dciversion);
3170 dev_vdbg(&dev->pdev->dev, "dccparams: 0x%08x\n",
3171 readl(&dev->cap_regs->dccparams));
3172 dev_vdbg(&dev->pdev->dev, "dev->devcap: %d\n", dev->devcap);
5be19a9d 3173 if (!dev->devcap) {
5f81f4b0 3174 dev_err(&dev->pdev->dev, "can't support device mode\n");
5be19a9d
XS		 3175 retval = -ENODEV;
3176 goto error;
3177 }
3178
3179 /* a pair of endpoints (out/in) for each address */
3180 dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
5f81f4b0 3181 dev_vdbg(&dev->pdev->dev, "dev->ep_max: %d\n", dev->ep_max);
5be19a9d
XS		 3182
3183 /* allocate endpoints memory */
3184 dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
3185 GFP_KERNEL);
3186 if (!dev->ep) {
5f81f4b0 3187 dev_err(&dev->pdev->dev, "allocate endpoints memory failed\n");
5be19a9d
XS		 3188 retval = -ENOMEM;
3189 goto error;
3190 }
3191
3192 /* allocate device dQH memory */
3193 size = dev->ep_max * sizeof(struct langwell_dqh);
5f81f4b0 3194 dev_vdbg(&dev->pdev->dev, "orig size = %d\n", size);
5be19a9d
XS		 3195 if (size < DQH_ALIGNMENT)
3196 size = DQH_ALIGNMENT;
3197 else if ((size % DQH_ALIGNMENT) != 0) {
3198 size += DQH_ALIGNMENT + 1;
3199 size &= ~(DQH_ALIGNMENT - 1);
3200 }
3201 dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
3202 &dev->ep_dqh_dma, GFP_KERNEL);
3203 if (!dev->ep_dqh) {
5f81f4b0 3204 dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
5be19a9d
XS		 3205 retval = -ENOMEM;
3206 goto error;
3207 }
3208 dev->ep_dqh_size = size;
5f81f4b0 3209 dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %d\n", dev->ep_dqh_size);
5be19a9d
XS		 3210
3211 /* initialize ep0 status request structure */
3212 dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
3213 if (!dev->status_req) {
5f81f4b0
J		 3214 dev_err(&dev->pdev->dev,
3215 "allocate status_req memory failed\n");
5be19a9d
XS		 3216 retval = -ENOMEM;
3217 goto error;
3218 }
3219 INIT_LIST_HEAD(&dev->status_req->queue);
3220
3221 /* allocate a small amount of memory to get valid address */
3222 dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
3223 dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
3224
3225 dev->resume_state = USB_STATE_NOTATTACHED;
3226 dev->usb_state = USB_STATE_POWERED;
3227 dev->ep0_dir = USB_DIR_OUT;
3211cbc2
J		 3228
3229 /* remote wakeup reset to 0 when the device is reset */
3230 dev->remote_wakeup = 0;
3231 dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
5be19a9d
XS		 3232
3233#ifndef OTG_TRANSCEIVER
3234 /* reset device controller */
3235 langwell_udc_reset(dev);
3236#endif
3237
3238 /* initialize gadget structure */
3239 dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
3240 dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
3241 INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
3242 dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
3243 dev->gadget.is_dualspeed = 1; /* support dual speed */
3244#ifdef OTG_TRANSCEIVER
3245 dev->gadget.is_otg = 1; /* support otg mode */
3246#endif
3247
3248 /* the "gadget" abstracts/virtualizes the controller */
3249 dev_set_name(&dev->gadget.dev, "gadget");
3250 dev->gadget.dev.parent = &pdev->dev;
3251 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3252 dev->gadget.dev.release = gadget_release;
3253 dev->gadget.name = driver_name; /* gadget name */
3254
3255 /* controller endpoints reinit */
3256 eps_reinit(dev);
3257
3258#ifndef OTG_TRANSCEIVER
3259 /* reset ep0 dQH and endptctrl */
3260 ep0_reset(dev);
3261#endif
3262
3263 /* create dTD dma_pool resource */
3264 dev->dtd_pool = dma_pool_create("langwell_dtd",
3265 &dev->pdev->dev,
3266 sizeof(struct langwell_dtd),
3267 DTD_ALIGNMENT,
3268 DMA_BOUNDARY);
3269
3270 if (!dev->dtd_pool) {
3271 retval = -ENOMEM;
3272 goto error;
3273 }
3274
3275 /* done */
5f81f4b0
J		 3276 dev_info(&dev->pdev->dev, "%s\n", driver_desc);
3277 dev_info(&dev->pdev->dev, "irq %d, pci mem %p\n", pdev->irq, base);
3278 dev_info(&dev->pdev->dev, "Driver version: " DRIVER_VERSION "\n");
3279 dev_info(&dev->pdev->dev, "Support (max) %d endpoints\n", dev->ep_max);
3280 dev_info(&dev->pdev->dev, "Device interface version: 0x%04x\n",
3281 dev->dciversion);
3282 dev_info(&dev->pdev->dev, "Controller mode: %s\n",
3283 dev->devcap ? "Device" : "Host");
3284 dev_info(&dev->pdev->dev, "Support USB LPM: %s\n",
3285 dev->lpm ? "Yes" : "No");
3286
3287 dev_vdbg(&dev->pdev->dev,
3288 "After langwell_udc_probe(), print all registers:\n");
5be19a9d 3289 print_all_registers(dev);
5be19a9d
XS		 3290
3291 the_controller = dev;
3292
3293 retval = device_register(&dev->gadget.dev);
3294 if (retval)
3295 goto error;
3296
3297 retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
3298 if (retval)
3299 goto error;
3300
3211cbc2
J		 3301 retval = device_create_file(&pdev->dev, &dev_attr_remote_wakeup);
3302 if (retval)
3303 goto error_attr1;
3304
5f81f4b0 3305 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3306 return 0;
3307
3211cbc2
J		 3308error_attr1:
3309 device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
5be19a9d
XS		 3310error:
3311 if (dev) {
5f81f4b0 3312 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3313 langwell_udc_remove(pdev);
3314 }
3315
3316 return retval;
3317}
3318
3319
3320/* device controller suspend */
3321static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
3322{
3323 struct langwell_udc *dev = the_controller;
5be19a9d 3324
5f81f4b0 3325 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3326
3327 /* disable interrupt and set controller to stop state */
3328 langwell_udc_stop(dev);
3329
3330 /* diable IRQ handler */
3331 if (dev->got_irq)
3332 free_irq(pdev->irq, dev);
3333 dev->got_irq = 0;
3334
5be19a9d
XS		 3335 /* save PCI state */
3336 pci_save_state(pdev);
3337
3338 /* set device power state */
3339 pci_set_power_state(pdev, PCI_D3hot);
3340
3341 /* enter PHY low power suspend */
513b91b6
J		 3342 if (dev->pdev->device != 0x0829)
3343 langwell_phy_low_power(dev, 1);
5be19a9d 3344
5f81f4b0 3345 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3346 return 0;
3347}
3348
3349
3350/* device controller resume */
3351static int langwell_udc_resume(struct pci_dev *pdev)
3352{
3353 struct langwell_udc *dev = the_controller;
5be19a9d 3354
5f81f4b0 3355 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3356
3357 /* exit PHY low power suspend */
513b91b6
J		 3358 if (dev->pdev->device != 0x0829)
3359 langwell_phy_low_power(dev, 0);
5be19a9d
XS		 3360
3361 /* set device D0 power state */
3362 pci_set_power_state(pdev, PCI_D0);
3363
3364 /* restore PCI state */
3365 pci_restore_state(pdev);
3366
3367 /* enable IRQ handler */
5f81f4b0
J		 3368 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
3369 driver_name, dev) != 0) {
3370 dev_err(&dev->pdev->dev, "request interrupt %d failed\n",
3371 pdev->irq);
3372 return -EBUSY;
5be19a9d
XS		 3373 }
3374 dev->got_irq = 1;
3375
3376 /* reset and start controller to run state */
3377 if (dev->stopped) {
3378 /* reset device controller */
3379 langwell_udc_reset(dev);
3380
3381 /* reset ep0 dQH and endptctrl */
3382 ep0_reset(dev);
3383
3384 /* start device if gadget is loaded */
3385 if (dev->driver)
3386 langwell_udc_start(dev);
3387 }
3388
3389 /* reset USB status */
3390 dev->usb_state = USB_STATE_ATTACHED;
3391 dev->ep0_state = WAIT_FOR_SETUP;
3392 dev->ep0_dir = USB_DIR_OUT;
3393
5f81f4b0 3394 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3395 return 0;
3396}
3397
3398
3399/* pci driver shutdown */
3400static void langwell_udc_shutdown(struct pci_dev *pdev)
3401{
3402 struct langwell_udc *dev = the_controller;
3403 u32 usbmode;
3404
5f81f4b0 3405 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3406
3407 /* reset controller mode to IDLE */
3408 usbmode = readl(&dev->op_regs->usbmode);
5f81f4b0 3409 dev_dbg(&dev->pdev->dev, "usbmode = 0x%08x\n", usbmode);
5be19a9d
XS		 3410 usbmode &= (~3 | MODE_IDLE);
3411 writel(usbmode, &dev->op_regs->usbmode);
3412
5f81f4b0 3413 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3414}
3415
3416/*-------------------------------------------------------------------------*/
3417
3418static const struct pci_device_id pci_ids[] = { {
3419 .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
3420 .class_mask = ~0,
3421 .vendor = 0x8086,
3422 .device = 0x0811,
3423 .subvendor = PCI_ANY_ID,
3424 .subdevice = PCI_ANY_ID,
3425}, { /* end: all zeroes */ }
3426};
3427
5be19a9d
XS		 3428MODULE_DEVICE_TABLE(pci, pci_ids);
3429
3430
3431static struct pci_driver langwell_pci_driver = {
3432 .name = (char *) driver_name,
3433 .id_table = pci_ids,
3434
3435 .probe = langwell_udc_probe,
3436 .remove = langwell_udc_remove,
3437
3438 /* device controller suspend/resume */
3439 .suspend = langwell_udc_suspend,
3440 .resume = langwell_udc_resume,
3441
3442 .shutdown = langwell_udc_shutdown,
3443};
3444
3445
5be19a9d
XS		 3446static int __init init(void)
3447{
3448#ifdef OTG_TRANSCEIVER
3449 return langwell_register_peripheral(&langwell_pci_driver);
3450#else
3451 return pci_register_driver(&langwell_pci_driver);
3452#endif
3453}
3454module_init(init);
3455
3456
3457static void __exit cleanup(void)
3458{
3459#ifdef OTG_TRANSCEIVER
3460 return langwell_unregister_peripheral(&langwell_pci_driver);
3461#else
3462 pci_unregister_driver(&langwell_pci_driver);
3463#endif
3464}
3465module_exit(cleanup);
3466
5f81f4b0
J		 3467
3468MODULE_DESCRIPTION(DRIVER_DESC);
3469MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
3470MODULE_VERSION(DRIVER_VERSION);
3471MODULE_LICENSE("GPL");
3472
kernel source for telekom puls (alcatel/mediatek)