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usb: gadget: at91_udc: change french comments to english
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / langwell_udc.c
CommitLineData
5be19a9d
XS		 1/*
2 * Intel Langwell USB Device Controller driver
3 * Copyright (C) 2008-2009, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
5be19a9d
XS		 8 */
9
10
11/* #undef DEBUG */
5f81f4b0 12/* #undef VERBOSE_DEBUG */
5be19a9d
XS		 13
14#if defined(CONFIG_USB_LANGWELL_OTG)
15#define OTG_TRANSCEIVER
16#endif
17
18
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/dma-mapping.h>
22#include <linux/kernel.h>
23#include <linux/delay.h>
24#include <linux/ioport.h>
25#include <linux/sched.h>
26#include <linux/slab.h>
5be19a9d
XS		 27#include <linux/errno.h>
28#include <linux/init.h>
29#include <linux/timer.h>
30#include <linux/list.h>
31#include <linux/interrupt.h>
32#include <linux/moduleparam.h>
33#include <linux/device.h>
34#include <linux/usb/ch9.h>
35#include <linux/usb/gadget.h>
36#include <linux/usb/otg.h>
37#include <linux/pm.h>
38#include <linux/io.h>
39#include <linux/irq.h>
40#include <asm/system.h>
41#include <asm/unaligned.h>
42
43#include "langwell_udc.h"
44
45
46#define DRIVER_DESC "Intel Langwell USB Device Controller driver"
47#define DRIVER_VERSION "16 May 2009"
48
49static const char driver_name[] = "langwell_udc";
50static const char driver_desc[] = DRIVER_DESC;
51
52
53/* controller device global variable */
54static struct langwell_udc *the_controller;
55
56/* for endpoint 0 operations */
57static const struct usb_endpoint_descriptor
58langwell_ep0_desc = {
59 .bLength = USB_DT_ENDPOINT_SIZE,
60 .bDescriptorType = USB_DT_ENDPOINT,
61 .bEndpointAddress = 0,
62 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
63 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
64};
65
66
67/*-------------------------------------------------------------------------*/
68/* debugging */
69
5f81f4b0 70#ifdef VERBOSE_DEBUG
5be19a9d
XS		 71static inline void print_all_registers(struct langwell_udc *dev)
72{
73 int i;
74
75 /* Capability Registers */
5f81f4b0
J		 76 dev_dbg(&dev->pdev->dev,
77 "Capability Registers (offset: 0x%04x, length: 0x%08x)\n",
78 CAP_REG_OFFSET, (u32)sizeof(struct langwell_cap_regs));
79 dev_dbg(&dev->pdev->dev, "caplength=0x%02x\n",
5be19a9d 80 readb(&dev->cap_regs->caplength));
5f81f4b0 81 dev_dbg(&dev->pdev->dev, "hciversion=0x%04x\n",
5be19a9d 82 readw(&dev->cap_regs->hciversion));
5f81f4b0 83 dev_dbg(&dev->pdev->dev, "hcsparams=0x%08x\n",
5be19a9d 84 readl(&dev->cap_regs->hcsparams));
5f81f4b0 85 dev_dbg(&dev->pdev->dev, "hccparams=0x%08x\n",
5be19a9d 86 readl(&dev->cap_regs->hccparams));
5f81f4b0 87 dev_dbg(&dev->pdev->dev, "dciversion=0x%04x\n",
5be19a9d 88 readw(&dev->cap_regs->dciversion));
5f81f4b0 89 dev_dbg(&dev->pdev->dev, "dccparams=0x%08x\n",
5be19a9d
XS		 90 readl(&dev->cap_regs->dccparams));
91
92 /* Operational Registers */
5f81f4b0
J		 93 dev_dbg(&dev->pdev->dev,
94 "Operational Registers (offset: 0x%04x, length: 0x%08x)\n",
95 OP_REG_OFFSET, (u32)sizeof(struct langwell_op_regs));
96 dev_dbg(&dev->pdev->dev, "extsts=0x%08x\n",
5be19a9d 97 readl(&dev->op_regs->extsts));
5f81f4b0 98 dev_dbg(&dev->pdev->dev, "extintr=0x%08x\n",
5be19a9d 99 readl(&dev->op_regs->extintr));
5f81f4b0 100 dev_dbg(&dev->pdev->dev, "usbcmd=0x%08x\n",
5be19a9d 101 readl(&dev->op_regs->usbcmd));
5f81f4b0 102 dev_dbg(&dev->pdev->dev, "usbsts=0x%08x\n",
5be19a9d 103 readl(&dev->op_regs->usbsts));
5f81f4b0 104 dev_dbg(&dev->pdev->dev, "usbintr=0x%08x\n",
5be19a9d 105 readl(&dev->op_regs->usbintr));
5f81f4b0 106 dev_dbg(&dev->pdev->dev, "frindex=0x%08x\n",
5be19a9d 107 readl(&dev->op_regs->frindex));
5f81f4b0 108 dev_dbg(&dev->pdev->dev, "ctrldssegment=0x%08x\n",
5be19a9d 109 readl(&dev->op_regs->ctrldssegment));
5f81f4b0 110 dev_dbg(&dev->pdev->dev, "deviceaddr=0x%08x\n",
5be19a9d 111 readl(&dev->op_regs->deviceaddr));
5f81f4b0 112 dev_dbg(&dev->pdev->dev, "endpointlistaddr=0x%08x\n",
5be19a9d 113 readl(&dev->op_regs->endpointlistaddr));
5f81f4b0 114 dev_dbg(&dev->pdev->dev, "ttctrl=0x%08x\n",
5be19a9d 115 readl(&dev->op_regs->ttctrl));
5f81f4b0 116 dev_dbg(&dev->pdev->dev, "burstsize=0x%08x\n",
5be19a9d 117 readl(&dev->op_regs->burstsize));
5f81f4b0 118 dev_dbg(&dev->pdev->dev, "txfilltuning=0x%08x\n",
5be19a9d 119 readl(&dev->op_regs->txfilltuning));
5f81f4b0 120 dev_dbg(&dev->pdev->dev, "txttfilltuning=0x%08x\n",
5be19a9d 121 readl(&dev->op_regs->txttfilltuning));
5f81f4b0 122 dev_dbg(&dev->pdev->dev, "ic_usb=0x%08x\n",
5be19a9d 123 readl(&dev->op_regs->ic_usb));
5f81f4b0 124 dev_dbg(&dev->pdev->dev, "ulpi_viewport=0x%08x\n",
5be19a9d 125 readl(&dev->op_regs->ulpi_viewport));
5f81f4b0 126 dev_dbg(&dev->pdev->dev, "configflag=0x%08x\n",
5be19a9d 127 readl(&dev->op_regs->configflag));
5f81f4b0 128 dev_dbg(&dev->pdev->dev, "portsc1=0x%08x\n",
5be19a9d 129 readl(&dev->op_regs->portsc1));
5f81f4b0 130 dev_dbg(&dev->pdev->dev, "devlc=0x%08x\n",
5be19a9d 131 readl(&dev->op_regs->devlc));
5f81f4b0 132 dev_dbg(&dev->pdev->dev, "otgsc=0x%08x\n",
5be19a9d 133 readl(&dev->op_regs->otgsc));
5f81f4b0 134 dev_dbg(&dev->pdev->dev, "usbmode=0x%08x\n",
5be19a9d 135 readl(&dev->op_regs->usbmode));
5f81f4b0 136 dev_dbg(&dev->pdev->dev, "endptnak=0x%08x\n",
5be19a9d 137 readl(&dev->op_regs->endptnak));
5f81f4b0 138 dev_dbg(&dev->pdev->dev, "endptnaken=0x%08x\n",
5be19a9d 139 readl(&dev->op_regs->endptnaken));
5f81f4b0 140 dev_dbg(&dev->pdev->dev, "endptsetupstat=0x%08x\n",
5be19a9d 141 readl(&dev->op_regs->endptsetupstat));
5f81f4b0 142 dev_dbg(&dev->pdev->dev, "endptprime=0x%08x\n",
5be19a9d 143 readl(&dev->op_regs->endptprime));
5f81f4b0 144 dev_dbg(&dev->pdev->dev, "endptflush=0x%08x\n",
5be19a9d 145 readl(&dev->op_regs->endptflush));
5f81f4b0 146 dev_dbg(&dev->pdev->dev, "endptstat=0x%08x\n",
5be19a9d 147 readl(&dev->op_regs->endptstat));
5f81f4b0 148 dev_dbg(&dev->pdev->dev, "endptcomplete=0x%08x\n",
5be19a9d
XS		 149 readl(&dev->op_regs->endptcomplete));
150
151 for (i = 0; i < dev->ep_max / 2; i++) {
5f81f4b0 152 dev_dbg(&dev->pdev->dev, "endptctrl[%d]=0x%08x\n",
5be19a9d
XS		 153 i, readl(&dev->op_regs->endptctrl[i]));
154 }
155}
5f81f4b0
J		 156#else
157
158#define print_all_registers(dev) do { } while (0)
159
160#endif /* VERBOSE_DEBUG */
5be19a9d
XS		 161
162
163/*-------------------------------------------------------------------------*/
164
5f81f4b0
J		 165#define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
166 USB_DIR_IN) : (usb_endpoint_dir_in((ep)->desc)))
5be19a9d 167
5f81f4b0 168#define DIR_STRING(ep) (is_in(ep) ? "in" : "out")
5be19a9d
XS		 169
170
5f81f4b0 171static char *type_string(const struct usb_endpoint_descriptor *desc)
5be19a9d 172{
5f81f4b0 173 switch (usb_endpoint_type(desc)) {
5be19a9d
XS		 174 case USB_ENDPOINT_XFER_BULK:
175 return "bulk";
176 case USB_ENDPOINT_XFER_ISOC:
177 return "iso";
178 case USB_ENDPOINT_XFER_INT:
179 return "int";
180 };
181
182 return "control";
183}
5be19a9d
XS		 184
185
186/* configure endpoint control registers */
187static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
188 unsigned char is_in, unsigned char ep_type)
189{
190 struct langwell_udc *dev;
191 u32 endptctrl;
192
193 dev = ep->dev;
5f81f4b0 194 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 195
196 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
197 if (is_in) { /* TX */
198 if (ep_num)
199 endptctrl |= EPCTRL_TXR;
200 endptctrl |= EPCTRL_TXE;
201 endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
202 } else { /* RX */
203 if (ep_num)
204 endptctrl |= EPCTRL_RXR;
205 endptctrl |= EPCTRL_RXE;
206 endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
207 }
208
209 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
210
5f81f4b0 211 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 212}
213
214
215/* reset ep0 dQH and endptctrl */
216static void ep0_reset(struct langwell_udc *dev)
217{
218 struct langwell_ep *ep;
219 int i;
220
5f81f4b0 221 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 222
223 /* ep0 in and out */
224 for (i = 0; i < 2; i++) {
225 ep = &dev->ep[i];
226 ep->dev = dev;
227
228 /* ep0 dQH */
229 ep->dqh = &dev->ep_dqh[i];
230
231 /* configure ep0 endpoint capabilities in dQH */
232 ep->dqh->dqh_ios = 1;
233 ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
234
3eed298f 235 /* enable ep0-in HW zero length termination select */
5be19a9d
XS		 236 if (is_in(ep))
237 ep->dqh->dqh_zlt = 0;
238 ep->dqh->dqh_mult = 0;
239
3eed298f
J		 240 ep->dqh->dtd_next = DTD_TERM;
241
5be19a9d
XS		 242 /* configure ep0 control registers */
243 ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
244 }
245
5f81f4b0 246 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 247}
248
249
250/*-------------------------------------------------------------------------*/
251
252/* endpoints operations */
253
254/* configure endpoint, making it usable */
255static int langwell_ep_enable(struct usb_ep *_ep,
256 const struct usb_endpoint_descriptor *desc)
257{
258 struct langwell_udc *dev;
259 struct langwell_ep *ep;
260 u16 max = 0;
261 unsigned long flags;
3eed298f 262 int i, retval = 0;
5be19a9d
XS		 263 unsigned char zlt, ios = 0, mult = 0;
264
265 ep = container_of(_ep, struct langwell_ep, ep);
266 dev = ep->dev;
5f81f4b0 267 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 268
269 if (!_ep || !desc || ep->desc
270 || desc->bDescriptorType != USB_DT_ENDPOINT)
271 return -EINVAL;
272
273 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
274 return -ESHUTDOWN;
275
29cc8897 276 max = usb_endpoint_maxp(desc);
5be19a9d
XS		 277
278 /*
279 * disable HW zero length termination select
280 * driver handles zero length packet through req->req.zero
281 */
282 zlt = 1;
283
284 /*
285 * sanity check type, direction, address, and then
286 * initialize the endpoint capabilities fields in dQH
287 */
5f81f4b0 288 switch (usb_endpoint_type(desc)) {
5be19a9d
XS		 289 case USB_ENDPOINT_XFER_CONTROL:
290 ios = 1;
291 break;
292 case USB_ENDPOINT_XFER_BULK:
293 if ((dev->gadget.speed == USB_SPEED_HIGH
294 && max != 512)
295 || (dev->gadget.speed == USB_SPEED_FULL
296 && max > 64)) {
297 goto done;
298 }
299 break;
300 case USB_ENDPOINT_XFER_INT:
301 if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
302 goto done;
303
304 switch (dev->gadget.speed) {
305 case USB_SPEED_HIGH:
306 if (max <= 1024)
307 break;
308 case USB_SPEED_FULL:
309 if (max <= 64)
310 break;
311 default:
312 if (max <= 8)
313 break;
314 goto done;
315 }
316 break;
317 case USB_ENDPOINT_XFER_ISOC:
318 if (strstr(ep->ep.name, "-bulk")
319 || strstr(ep->ep.name, "-int"))
320 goto done;
321
322 switch (dev->gadget.speed) {
323 case USB_SPEED_HIGH:
324 if (max <= 1024)
325 break;
326 case USB_SPEED_FULL:
327 if (max <= 1023)
328 break;
329 default:
330 goto done;
331 }
332 /*
333 * FIXME:
334 * calculate transactions needed for high bandwidth iso
335 */
336 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
337 max = max & 0x8ff; /* bit 0~10 */
338 /* 3 transactions at most */
339 if (mult > 3)
340 goto done;
341 break;
342 default:
343 goto done;
344 }
345
346 spin_lock_irqsave(&dev->lock, flags);
347
5be19a9d
XS		 348 ep->ep.maxpacket = max;
349 ep->desc = desc;
350 ep->stopped = 0;
5f81f4b0 351 ep->ep_num = usb_endpoint_num(desc);
5be19a9d
XS		 352
353 /* ep_type */
5f81f4b0 354 ep->ep_type = usb_endpoint_type(desc);
5be19a9d
XS		 355
356 /* configure endpoint control registers */
357 ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
358
3eed298f
J		 359 /* configure endpoint capabilities in dQH */
360 i = ep->ep_num * 2 + is_in(ep);
361 ep->dqh = &dev->ep_dqh[i];
362 ep->dqh->dqh_ios = ios;
363 ep->dqh->dqh_mpl = cpu_to_le16(max);
364 ep->dqh->dqh_zlt = zlt;
365 ep->dqh->dqh_mult = mult;
366 ep->dqh->dtd_next = DTD_TERM;
367
5f81f4b0 368 dev_dbg(&dev->pdev->dev, "enabled %s (ep%d%s-%s), max %04x\n",
5be19a9d
XS		 369 _ep->name,
370 ep->ep_num,
5f81f4b0
J		 371 DIR_STRING(ep),
372 type_string(desc),
5be19a9d
XS		 373 max);
374
375 spin_unlock_irqrestore(&dev->lock, flags);
376done:
5f81f4b0 377 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 378 return retval;
379}
380
381
382/*-------------------------------------------------------------------------*/
383
384/* retire a request */
385static void done(struct langwell_ep *ep, struct langwell_request *req,
386 int status)
387{
388 struct langwell_udc *dev = ep->dev;
389 unsigned stopped = ep->stopped;
390 struct langwell_dtd *curr_dtd, *next_dtd;
391 int i;
392
5f81f4b0 393 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 394
395 /* remove the req from ep->queue */
396 list_del_init(&req->queue);
397
398 if (req->req.status == -EINPROGRESS)
399 req->req.status = status;
400 else
401 status = req->req.status;
402
403 /* free dTD for the request */
404 next_dtd = req->head;
405 for (i = 0; i < req->dtd_count; i++) {
406 curr_dtd = next_dtd;
407 if (i != req->dtd_count - 1)
408 next_dtd = curr_dtd->next_dtd_virt;
409 dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
410 }
411
412 if (req->mapped) {
5f81f4b0
J		 413 dma_unmap_single(&dev->pdev->dev,
414 req->req.dma, req->req.length,
5be19a9d
XS		 415 is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
416 req->req.dma = DMA_ADDR_INVALID;
417 req->mapped = 0;
418 } else
419 dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma,
420 req->req.length,
421 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
422
423 if (status != -ESHUTDOWN)
5f81f4b0
J		 424 dev_dbg(&dev->pdev->dev,
425 "complete %s, req %p, stat %d, len %u/%u\n",
426 ep->ep.name, &req->req, status,
427 req->req.actual, req->req.length);
5be19a9d
XS		 428
429 /* don't modify queue heads during completion callback */
430 ep->stopped = 1;
431
432 spin_unlock(&dev->lock);
433 /* complete routine from gadget driver */
434 if (req->req.complete)
435 req->req.complete(&ep->ep, &req->req);
436
437 spin_lock(&dev->lock);
438 ep->stopped = stopped;
439
5f81f4b0 440 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 441}
442
443
444static void langwell_ep_fifo_flush(struct usb_ep *_ep);
445
446/* delete all endpoint requests, called with spinlock held */
447static void nuke(struct langwell_ep *ep, int status)
448{
449 /* called with spinlock held */
450 ep->stopped = 1;
451
452 /* endpoint fifo flush */
453 if (&ep->ep && ep->desc)
454 langwell_ep_fifo_flush(&ep->ep);
455
456 while (!list_empty(&ep->queue)) {
457 struct langwell_request *req = NULL;
458 req = list_entry(ep->queue.next, struct langwell_request,
459 queue);
460 done(ep, req, status);
461 }
462}
463
464
465/*-------------------------------------------------------------------------*/
466
467/* endpoint is no longer usable */
468static int langwell_ep_disable(struct usb_ep *_ep)
469{
470 struct langwell_ep *ep;
471 unsigned long flags;
472 struct langwell_udc *dev;
473 int ep_num;
474 u32 endptctrl;
475
476 ep = container_of(_ep, struct langwell_ep, ep);
477 dev = ep->dev;
5f81f4b0 478 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 479
480 if (!_ep || !ep->desc)
481 return -EINVAL;
482
483 spin_lock_irqsave(&dev->lock, flags);
484
485 /* disable endpoint control register */
486 ep_num = ep->ep_num;
487 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
488 if (is_in(ep))
489 endptctrl &= ~EPCTRL_TXE;
490 else
491 endptctrl &= ~EPCTRL_RXE;
492 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
493
494 /* nuke all pending requests (does flush) */
495 nuke(ep, -ESHUTDOWN);
496
497 ep->desc = NULL;
498 ep->stopped = 1;
499
500 spin_unlock_irqrestore(&dev->lock, flags);
501
5f81f4b0
J		 502 dev_dbg(&dev->pdev->dev, "disabled %s\n", _ep->name);
503 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 504
505 return 0;
506}
507
508
509/* allocate a request object to use with this endpoint */
510static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
511 gfp_t gfp_flags)
512{
513 struct langwell_ep *ep;
514 struct langwell_udc *dev;
515 struct langwell_request *req = NULL;
516
517 if (!_ep)
518 return NULL;
519
520 ep = container_of(_ep, struct langwell_ep, ep);
521 dev = ep->dev;
5f81f4b0 522 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 523
524 req = kzalloc(sizeof(*req), gfp_flags);
525 if (!req)
526 return NULL;
527
528 req->req.dma = DMA_ADDR_INVALID;
529 INIT_LIST_HEAD(&req->queue);
530
5f81f4b0
J		 531 dev_vdbg(&dev->pdev->dev, "alloc request for %s\n", _ep->name);
532 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 533 return &req->req;
534}
535
536
537/* free a request object */
538static void langwell_free_request(struct usb_ep *_ep,
539 struct usb_request *_req)
540{
541 struct langwell_ep *ep;
542 struct langwell_udc *dev;
543 struct langwell_request *req = NULL;
544
545 ep = container_of(_ep, struct langwell_ep, ep);
546 dev = ep->dev;
5f81f4b0 547 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 548
549 if (!_ep || !_req)
550 return;
551
552 req = container_of(_req, struct langwell_request, req);
553 WARN_ON(!list_empty(&req->queue));
554
555 if (_req)
556 kfree(req);
557
5f81f4b0
J		 558 dev_vdbg(&dev->pdev->dev, "free request for %s\n", _ep->name);
559 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 560}
561
562
563/*-------------------------------------------------------------------------*/
564
565/* queue dTD and PRIME endpoint */
566static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
567{
568 u32 bit_mask, usbcmd, endptstat, dtd_dma;
569 u8 dtd_status;
570 int i;
571 struct langwell_dqh *dqh;
572 struct langwell_udc *dev;
573
574 dev = ep->dev;
5f81f4b0 575 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 576
577 i = ep->ep_num * 2 + is_in(ep);
578 dqh = &dev->ep_dqh[i];
579
580 if (ep->ep_num)
5f81f4b0 581 dev_vdbg(&dev->pdev->dev, "%s\n", ep->name);
5be19a9d
XS		 582 else
583 /* ep0 */
5f81f4b0 584 dev_vdbg(&dev->pdev->dev, "%s-%s\n", ep->name, DIR_STRING(ep));
5be19a9d 585
b9af9ea4
FB		 586 dev_vdbg(&dev->pdev->dev, "ep_dqh[%d] addr: 0x%p\n",
587 i, &(dev->ep_dqh[i]));
5be19a9d
XS		 588
589 bit_mask = is_in(ep) ?
590 (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
591
5f81f4b0 592 dev_vdbg(&dev->pdev->dev, "bit_mask = 0x%08x\n", bit_mask);
5be19a9d
XS		 593
594 /* check if the pipe is empty */
595 if (!(list_empty(&ep->queue))) {
596 /* add dTD to the end of linked list */
597 struct langwell_request *lastreq;
598 lastreq = list_entry(ep->queue.prev,
599 struct langwell_request, queue);
600
601 lastreq->tail->dtd_next =
602 cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
603
604 /* read prime bit, if 1 goto out */
605 if (readl(&dev->op_regs->endptprime) & bit_mask)
606 goto out;
607
608 do {
609 /* set ATDTW bit in USBCMD */
610 usbcmd = readl(&dev->op_regs->usbcmd);
611 writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
612
613 /* read correct status bit */
614 endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
615
616 } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
617
618 /* write ATDTW bit to 0 */
619 usbcmd = readl(&dev->op_regs->usbcmd);
620 writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
621
622 if (endptstat)
623 goto out;
624 }
625
626 /* write dQH next pointer and terminate bit to 0 */
627 dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
628 dqh->dtd_next = cpu_to_le32(dtd_dma);
629
630 /* clear active and halt bit */
631 dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
632 dqh->dtd_status &= dtd_status;
5f81f4b0
J		 633 dev_vdbg(&dev->pdev->dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
634
25985edc 635 /* ensure that updates to the dQH will occur before priming */
5f81f4b0 636 wmb();
5be19a9d
XS		 637
638 /* write 1 to endptprime register to PRIME endpoint */
639 bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
5f81f4b0 640 dev_vdbg(&dev->pdev->dev, "endprime bit_mask = 0x%08x\n", bit_mask);
5be19a9d
XS		 641 writel(bit_mask, &dev->op_regs->endptprime);
642out:
5f81f4b0 643 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 644 return 0;
645}
646
647
648/* fill in the dTD structure to build a transfer descriptor */
649static struct langwell_dtd *build_dtd(struct langwell_request *req,
650 unsigned *length, dma_addr_t *dma, int *is_last)
651{
652 u32 buf_ptr;
653 struct langwell_dtd *dtd;
654 struct langwell_udc *dev;
655 int i;
656
657 dev = req->ep->dev;
5f81f4b0 658 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 659
660 /* the maximum transfer length, up to 16k bytes */
661 *length = min(req->req.length - req->req.actual,
662 (unsigned)DTD_MAX_TRANSFER_LENGTH);
663
664 /* create dTD dma_pool resource */
665 dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
666 if (dtd == NULL)
667 return dtd;
668 dtd->dtd_dma = *dma;
669
670 /* initialize buffer page pointers */
671 buf_ptr = (u32)(req->req.dma + req->req.actual);
672 for (i = 0; i < 5; i++)
673 dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
674
675 req->req.actual += *length;
676
677 /* fill in total bytes with transfer size */
678 dtd->dtd_total = cpu_to_le16(*length);
5f81f4b0 679 dev_vdbg(&dev->pdev->dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
5be19a9d
XS		 680
681 /* set is_last flag if req->req.zero is set or not */
682 if (req->req.zero) {
683 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
684 *is_last = 1;
685 else
686 *is_last = 0;
687 } else if (req->req.length == req->req.actual) {
688 *is_last = 1;
689 } else
690 *is_last = 0;
691
692 if (*is_last == 0)
5f81f4b0 693 dev_vdbg(&dev->pdev->dev, "multi-dtd request!\n");
5be19a9d
XS		 694
695 /* set interrupt on complete bit for the last dTD */
696 if (*is_last && !req->req.no_interrupt)
697 dtd->dtd_ioc = 1;
698
699 /* set multiplier override 0 for non-ISO and non-TX endpoint */
700 dtd->dtd_multo = 0;
701
702 /* set the active bit of status field to 1 */
703 dtd->dtd_status = DTD_STS_ACTIVE;
5f81f4b0
J		 704 dev_vdbg(&dev->pdev->dev, "dtd->dtd_status = 0x%02x\n",
705 dtd->dtd_status);
5be19a9d 706
5f81f4b0
J		 707 dev_vdbg(&dev->pdev->dev, "length = %d, dma addr= 0x%08x\n",
708 *length, (int)*dma);
709 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 710 return dtd;
711}
712
713
714/* generate dTD linked list for a request */
715static int req_to_dtd(struct langwell_request *req)
716{
717 unsigned count;
718 int is_last, is_first = 1;
719 struct langwell_dtd *dtd, *last_dtd = NULL;
720 struct langwell_udc *dev;
721 dma_addr_t dma;
722
723 dev = req->ep->dev;
5f81f4b0 724 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 725 do {
726 dtd = build_dtd(req, &count, &dma, &is_last);
727 if (dtd == NULL)
728 return -ENOMEM;
729
730 if (is_first) {
731 is_first = 0;
732 req->head = dtd;
733 } else {
734 last_dtd->dtd_next = cpu_to_le32(dma);
735 last_dtd->next_dtd_virt = dtd;
736 }
737 last_dtd = dtd;
738 req->dtd_count++;
739 } while (!is_last);
740
741 /* set terminate bit to 1 for the last dTD */
742 dtd->dtd_next = DTD_TERM;
743
744 req->tail = dtd;
745
5f81f4b0 746 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 747 return 0;
748}
749
750/*-------------------------------------------------------------------------*/
751
752/* queue (submits) an I/O requests to an endpoint */
753static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
754 gfp_t gfp_flags)
755{
756 struct langwell_request *req;
757 struct langwell_ep *ep;
758 struct langwell_udc *dev;
759 unsigned long flags;
760 int is_iso = 0, zlflag = 0;
761
762 /* always require a cpu-view buffer */
763 req = container_of(_req, struct langwell_request, req);
764 ep = container_of(_ep, struct langwell_ep, ep);
765
766 if (!_req || !_req->complete || !_req->buf
767 || !list_empty(&req->queue)) {
768 return -EINVAL;
769 }
770
771 if (unlikely(!_ep || !ep->desc))
772 return -EINVAL;
773
774 dev = ep->dev;
775 req->ep = ep;
5f81f4b0 776 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 777
5f81f4b0 778 if (usb_endpoint_xfer_isoc(ep->desc)) {
5be19a9d
XS		 779 if (req->req.length > ep->ep.maxpacket)
780 return -EMSGSIZE;
781 is_iso = 1;
782 }
783
784 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
785 return -ESHUTDOWN;
786
787 /* set up dma mapping in case the caller didn't */
788 if (_req->dma == DMA_ADDR_INVALID) {
789 /* WORKAROUND: WARN_ON(size == 0) */
790 if (_req->length == 0) {
5f81f4b0 791 dev_vdbg(&dev->pdev->dev, "req->length: 0->1\n");
5be19a9d
XS		 792 zlflag = 1;
793 _req->length++;
794 }
795
796 _req->dma = dma_map_single(&dev->pdev->dev,
797 _req->buf, _req->length,
798 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
799 if (zlflag && (_req->length == 1)) {
5f81f4b0 800 dev_vdbg(&dev->pdev->dev, "req->length: 1->0\n");
5be19a9d
XS		 801 zlflag = 0;
802 _req->length = 0;
803 }
804
805 req->mapped = 1;
5f81f4b0 806 dev_vdbg(&dev->pdev->dev, "req->mapped = 1\n");
5be19a9d
XS		 807 } else {
808 dma_sync_single_for_device(&dev->pdev->dev,
809 _req->dma, _req->length,
810 is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
811 req->mapped = 0;
5f81f4b0 812 dev_vdbg(&dev->pdev->dev, "req->mapped = 0\n");
5be19a9d
XS		 813 }
814
5f81f4b0
J		 815 dev_dbg(&dev->pdev->dev,
816 "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
817 _ep->name,
818 _req, _req->length, _req->buf, (int)_req->dma);
5be19a9d
XS		 819
820 _req->status = -EINPROGRESS;
821 _req->actual = 0;
822 req->dtd_count = 0;
823
824 spin_lock_irqsave(&dev->lock, flags);
825
826 /* build and put dTDs to endpoint queue */
827 if (!req_to_dtd(req)) {
828 queue_dtd(ep, req);
829 } else {
830 spin_unlock_irqrestore(&dev->lock, flags);
831 return -ENOMEM;
832 }
833
834 /* update ep0 state */
835 if (ep->ep_num == 0)
836 dev->ep0_state = DATA_STATE_XMIT;
837
838 if (likely(req != NULL)) {
839 list_add_tail(&req->queue, &ep->queue);
5f81f4b0 840 dev_vdbg(&dev->pdev->dev, "list_add_tail()\n");
5be19a9d
XS		 841 }
842
843 spin_unlock_irqrestore(&dev->lock, flags);
844
5f81f4b0 845 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 846 return 0;
847}
848
849
850/* dequeue (cancels, unlinks) an I/O request from an endpoint */
851static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
852{
853 struct langwell_ep *ep;
854 struct langwell_udc *dev;
855 struct langwell_request *req;
856 unsigned long flags;
857 int stopped, ep_num, retval = 0;
858 u32 endptctrl;
859
860 ep = container_of(_ep, struct langwell_ep, ep);
861 dev = ep->dev;
5f81f4b0 862 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 863
864 if (!_ep || !ep->desc || !_req)
865 return -EINVAL;
866
867 if (!dev->driver)
868 return -ESHUTDOWN;
869
870 spin_lock_irqsave(&dev->lock, flags);
871 stopped = ep->stopped;
872
873 /* quiesce dma while we patch the queue */
874 ep->stopped = 1;
875 ep_num = ep->ep_num;
876
877 /* disable endpoint control register */
878 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
879 if (is_in(ep))
880 endptctrl &= ~EPCTRL_TXE;
881 else
882 endptctrl &= ~EPCTRL_RXE;
883 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
884
885 /* make sure it's still queued on this endpoint */
886 list_for_each_entry(req, &ep->queue, queue) {
887 if (&req->req == _req)
888 break;
889 }
890
891 if (&req->req != _req) {
892 retval = -EINVAL;
893 goto done;
894 }
895
896 /* queue head may be partially complete. */
897 if (ep->queue.next == &req->queue) {
5f81f4b0 898 dev_dbg(&dev->pdev->dev, "unlink (%s) dma\n", _ep->name);
5be19a9d
XS		 899 _req->status = -ECONNRESET;
900 langwell_ep_fifo_flush(&ep->ep);
901
902 /* not the last request in endpoint queue */
903 if (likely(ep->queue.next == &req->queue)) {
904 struct langwell_dqh *dqh;
905 struct langwell_request *next_req;
906
907 dqh = ep->dqh;
908 next_req = list_entry(req->queue.next,
909 struct langwell_request, queue);
910
911 /* point the dQH to the first dTD of next request */
912 writel((u32) next_req->head, &dqh->dqh_current);
913 }
914 } else {
915 struct langwell_request *prev_req;
916
917 prev_req = list_entry(req->queue.prev,
918 struct langwell_request, queue);
919 writel(readl(&req->tail->dtd_next),
920 &prev_req->tail->dtd_next);
921 }
922
923 done(ep, req, -ECONNRESET);
924
925done:
926 /* enable endpoint again */
927 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
928 if (is_in(ep))
929 endptctrl |= EPCTRL_TXE;
930 else
931 endptctrl |= EPCTRL_RXE;
932 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
933
934 ep->stopped = stopped;
935 spin_unlock_irqrestore(&dev->lock, flags);
936
5f81f4b0 937 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 938 return retval;
939}
940
941
942/*-------------------------------------------------------------------------*/
943
944/* endpoint set/clear halt */
945static void ep_set_halt(struct langwell_ep *ep, int value)
946{
947 u32 endptctrl = 0;
948 int ep_num;
949 struct langwell_udc *dev = ep->dev;
5f81f4b0 950 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 951
952 ep_num = ep->ep_num;
953 endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
954
955 /* value: 1 - set halt, 0 - clear halt */
956 if (value) {
957 /* set the stall bit */
958 if (is_in(ep))
959 endptctrl |= EPCTRL_TXS;
960 else
961 endptctrl |= EPCTRL_RXS;
962 } else {
963 /* clear the stall bit and reset data toggle */
964 if (is_in(ep)) {
965 endptctrl &= ~EPCTRL_TXS;
966 endptctrl |= EPCTRL_TXR;
967 } else {
968 endptctrl &= ~EPCTRL_RXS;
969 endptctrl |= EPCTRL_RXR;
970 }
971 }
972
973 writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
974
5f81f4b0 975 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 976}
977
978
979/* set the endpoint halt feature */
980static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
981{
982 struct langwell_ep *ep;
983 struct langwell_udc *dev;
984 unsigned long flags;
985 int retval = 0;
986
987 ep = container_of(_ep, struct langwell_ep, ep);
988 dev = ep->dev;
989
5f81f4b0 990 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 991
992 if (!_ep || !ep->desc)
993 return -EINVAL;
994
995 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
996 return -ESHUTDOWN;
997
5f81f4b0 998 if (usb_endpoint_xfer_isoc(ep->desc))
5be19a9d
XS		 999 return -EOPNOTSUPP;
1000
1001 spin_lock_irqsave(&dev->lock, flags);
1002
1003 /*
1004 * attempt to halt IN ep will fail if any transfer requests
1005 * are still queue
1006 */
1007 if (!list_empty(&ep->queue) && is_in(ep) && value) {
1008 /* IN endpoint FIFO holds bytes */
5f81f4b0 1009 dev_dbg(&dev->pdev->dev, "%s FIFO holds bytes\n", _ep->name);
5be19a9d
XS		 1010 retval = -EAGAIN;
1011 goto done;
1012 }
1013
1014 /* endpoint set/clear halt */
1015 if (ep->ep_num) {
1016 ep_set_halt(ep, value);
1017 } else { /* endpoint 0 */
1018 dev->ep0_state = WAIT_FOR_SETUP;
1019 dev->ep0_dir = USB_DIR_OUT;
1020 }
1021done:
1022 spin_unlock_irqrestore(&dev->lock, flags);
5f81f4b0
J		 1023 dev_dbg(&dev->pdev->dev, "%s %s halt\n",
1024 _ep->name, value ? "set" : "clear");
1025 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1026 return retval;
1027}
1028
1029
1030/* set the halt feature and ignores clear requests */
1031static int langwell_ep_set_wedge(struct usb_ep *_ep)
1032{
1033 struct langwell_ep *ep;
1034 struct langwell_udc *dev;
1035
1036 ep = container_of(_ep, struct langwell_ep, ep);
1037 dev = ep->dev;
1038
5f81f4b0 1039 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1040
1041 if (!_ep || !ep->desc)
1042 return -EINVAL;
1043
5f81f4b0 1044 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1045 return usb_ep_set_halt(_ep);
1046}
1047
1048
1049/* flush contents of a fifo */
1050static void langwell_ep_fifo_flush(struct usb_ep *_ep)
1051{
1052 struct langwell_ep *ep;
1053 struct langwell_udc *dev;
1054 u32 flush_bit;
1055 unsigned long timeout;
1056
1057 ep = container_of(_ep, struct langwell_ep, ep);
1058 dev = ep->dev;
1059
5f81f4b0 1060 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1061
1062 if (!_ep || !ep->desc) {
5f81f4b0
J		 1063 dev_vdbg(&dev->pdev->dev, "ep or ep->desc is NULL\n");
1064 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1065 return;
1066 }
1067
5f81f4b0
J		 1068 dev_vdbg(&dev->pdev->dev, "%s-%s fifo flush\n",
1069 _ep->name, DIR_STRING(ep));
5be19a9d
XS		 1070
1071 /* flush endpoint buffer */
1072 if (ep->ep_num == 0)
1073 flush_bit = (1 << 16) | 1;
1074 else if (is_in(ep))
1075 flush_bit = 1 << (ep->ep_num + 16); /* TX */
1076 else
1077 flush_bit = 1 << ep->ep_num; /* RX */
1078
1079 /* wait until flush complete */
1080 timeout = jiffies + FLUSH_TIMEOUT;
1081 do {
1082 writel(flush_bit, &dev->op_regs->endptflush);
1083 while (readl(&dev->op_regs->endptflush)) {
1084 if (time_after(jiffies, timeout)) {
5f81f4b0 1085 dev_err(&dev->pdev->dev, "ep flush timeout\n");
5be19a9d
XS		 1086 goto done;
1087 }
1088 cpu_relax();
1089 }
1090 } while (readl(&dev->op_regs->endptstat) & flush_bit);
1091done:
5f81f4b0 1092 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1093}
1094
1095
1096/* endpoints operations structure */
1097static const struct usb_ep_ops langwell_ep_ops = {
1098
1099 /* configure endpoint, making it usable */
1100 .enable = langwell_ep_enable,
1101
1102 /* endpoint is no longer usable */
1103 .disable = langwell_ep_disable,
1104
1105 /* allocate a request object to use with this endpoint */
1106 .alloc_request = langwell_alloc_request,
1107
1108 /* free a request object */
1109 .free_request = langwell_free_request,
1110
1111 /* queue (submits) an I/O requests to an endpoint */
1112 .queue = langwell_ep_queue,
1113
1114 /* dequeue (cancels, unlinks) an I/O request from an endpoint */
1115 .dequeue = langwell_ep_dequeue,
1116
1117 /* set the endpoint halt feature */
1118 .set_halt = langwell_ep_set_halt,
1119
1120 /* set the halt feature and ignores clear requests */
1121 .set_wedge = langwell_ep_set_wedge,
1122
1123 /* flush contents of a fifo */
1124 .fifo_flush = langwell_ep_fifo_flush,
1125};
1126
1127
1128/*-------------------------------------------------------------------------*/
1129
1130/* device controller usb_gadget_ops structure */
1131
1132/* returns the current frame number */
1133static int langwell_get_frame(struct usb_gadget *_gadget)
1134{
1135 struct langwell_udc *dev;
1136 u16 retval;
1137
1138 if (!_gadget)
1139 return -ENODEV;
1140
1141 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1142 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1143
1144 retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
1145
5f81f4b0 1146 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1147 return retval;
1148}
1149
1150
513b91b6
J		 1151/* enter or exit PHY low power state */
1152static void langwell_phy_low_power(struct langwell_udc *dev, bool flag)
1153{
1154 u32 devlc;
1155 u8 devlc_byte2;
1156 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
1157
1158 devlc = readl(&dev->op_regs->devlc);
1159 dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
1160
1161 if (flag)
1162 devlc |= LPM_PHCD;
1163 else
1164 devlc &= ~LPM_PHCD;
1165
1166 /* FIXME: workaround for Langwell A1/A2/A3 sighting */
1167 devlc_byte2 = (devlc >> 16) & 0xff;
1168 writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
1169
1170 devlc = readl(&dev->op_regs->devlc);
1171 dev_vdbg(&dev->pdev->dev,
1172 "%s PHY low power suspend, devlc = 0x%08x\n",
1173 flag ? "enter" : "exit", devlc);
1174}
1175
1176
5be19a9d
XS		 1177/* tries to wake up the host connected to this gadget */
1178static int langwell_wakeup(struct usb_gadget *_gadget)
1179{
1180 struct langwell_udc *dev;
513b91b6 1181 u32 portsc1;
5f81f4b0 1182 unsigned long flags;
5be19a9d
XS		 1183
1184 if (!_gadget)
1185 return 0;
1186
1187 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1188 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 1189
5f81f4b0
J		 1190 /* remote wakeup feature not enabled by host */
1191 if (!dev->remote_wakeup) {
1192 dev_info(&dev->pdev->dev, "remote wakeup is disabled\n");
5be19a9d 1193 return -ENOTSUPP;
5f81f4b0 1194 }
5be19a9d
XS		 1195
1196 spin_lock_irqsave(&dev->lock, flags);
1197
1198 portsc1 = readl(&dev->op_regs->portsc1);
1199 if (!(portsc1 & PORTS_SUSP)) {
1200 spin_unlock_irqrestore(&dev->lock, flags);
1201 return 0;
1202 }
1203
513b91b6
J		 1204 /* LPM L1 to L0 or legacy remote wakeup */
1205 if (dev->lpm && dev->lpm_state == LPM_L1)
1206 dev_info(&dev->pdev->dev, "LPM L1 to L0 remote wakeup\n");
1207 else
1208 dev_info(&dev->pdev->dev, "device remote wakeup\n");
5be19a9d
XS		 1209
1210 /* exit PHY low power suspend */
513b91b6
J		 1211 if (dev->pdev->device != 0x0829)
1212 langwell_phy_low_power(dev, 0);
1213
1214 /* force port resume */
1215 portsc1 |= PORTS_FPR;
1216 writel(portsc1, &dev->op_regs->portsc1);
5be19a9d
XS		 1217
1218 spin_unlock_irqrestore(&dev->lock, flags);
1219
5f81f4b0 1220 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1221 return 0;
1222}
1223
1224
1225/* notify controller that VBUS is powered or not */
1226static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
1227{
1228 struct langwell_udc *dev;
1229 unsigned long flags;
5f81f4b0 1230 u32 usbcmd;
5be19a9d
XS		 1231
1232 if (!_gadget)
1233 return -ENODEV;
1234
1235 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1236 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1237
1238 spin_lock_irqsave(&dev->lock, flags);
5f81f4b0
J		 1239 dev_vdbg(&dev->pdev->dev, "VBUS status: %s\n",
1240 is_active ? "on" : "off");
5be19a9d
XS		 1241
1242 dev->vbus_active = (is_active != 0);
1243 if (dev->driver && dev->softconnected && dev->vbus_active) {
1244 usbcmd = readl(&dev->op_regs->usbcmd);
1245 usbcmd |= CMD_RUNSTOP;
1246 writel(usbcmd, &dev->op_regs->usbcmd);
1247 } else {
1248 usbcmd = readl(&dev->op_regs->usbcmd);
1249 usbcmd &= ~CMD_RUNSTOP;
1250 writel(usbcmd, &dev->op_regs->usbcmd);
1251 }
1252
1253 spin_unlock_irqrestore(&dev->lock, flags);
1254
5f81f4b0 1255 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1256 return 0;
1257}
1258
1259
1260/* constrain controller's VBUS power usage */
1261static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1262{
1263 struct langwell_udc *dev;
1264
1265 if (!_gadget)
1266 return -ENODEV;
1267
1268 dev = container_of(_gadget, struct langwell_udc, gadget);
5f81f4b0 1269 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1270
1271 if (dev->transceiver) {
5f81f4b0
J		 1272 dev_vdbg(&dev->pdev->dev, "otg_set_power\n");
1273 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1274 return otg_set_power(dev->transceiver, mA);
1275 }
1276
5f81f4b0 1277 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1278 return -ENOTSUPP;
1279}
1280
1281
1282/* D+ pullup, software-controlled connect/disconnect to USB host */
1283static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
1284{
1285 struct langwell_udc *dev;
5f81f4b0
J		 1286 u32 usbcmd;
1287 unsigned long flags;
5be19a9d
XS		 1288
1289 if (!_gadget)
1290 return -ENODEV;
1291
1292 dev = container_of(_gadget, struct langwell_udc, gadget);
1293
5f81f4b0 1294 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1295
1296 spin_lock_irqsave(&dev->lock, flags);
1297 dev->softconnected = (is_on != 0);
1298
1299 if (dev->driver && dev->softconnected && dev->vbus_active) {
1300 usbcmd = readl(&dev->op_regs->usbcmd);
1301 usbcmd |= CMD_RUNSTOP;
1302 writel(usbcmd, &dev->op_regs->usbcmd);
1303 } else {
1304 usbcmd = readl(&dev->op_regs->usbcmd);
1305 usbcmd &= ~CMD_RUNSTOP;
1306 writel(usbcmd, &dev->op_regs->usbcmd);
1307 }
1308 spin_unlock_irqrestore(&dev->lock, flags);
1309
5f81f4b0 1310 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1311 return 0;
1312}
1313
0f91349b
SAS		 1314static int langwell_start(struct usb_gadget_driver *driver,
1315 int (*bind)(struct usb_gadget *));
1316static int langwell_stop(struct usb_gadget_driver *driver);
5be19a9d
XS		 1317/* device controller usb_gadget_ops structure */
1318static const struct usb_gadget_ops langwell_ops = {
1319
1320 /* returns the current frame number */
1321 .get_frame = langwell_get_frame,
1322
1323 /* tries to wake up the host connected to this gadget */
1324 .wakeup = langwell_wakeup,
1325
1326 /* set the device selfpowered feature, always selfpowered */
1327 /* .set_selfpowered = langwell_set_selfpowered, */
1328
1329 /* notify controller that VBUS is powered or not */
1330 .vbus_session = langwell_vbus_session,
1331
1332 /* constrain controller's VBUS power usage */
1333 .vbus_draw = langwell_vbus_draw,
1334
1335 /* D+ pullup, software-controlled connect/disconnect to USB host */
1336 .pullup = langwell_pullup,
0f91349b
SAS		 1337
1338 .start = langwell_start,
1339 .stop = langwell_stop,
5be19a9d
XS		 1340};
1341
1342
1343/*-------------------------------------------------------------------------*/
1344
1345/* device controller operations */
1346
1347/* reset device controller */
1348static int langwell_udc_reset(struct langwell_udc *dev)
1349{
1350 u32 usbcmd, usbmode, devlc, endpointlistaddr;
513b91b6 1351 u8 devlc_byte0, devlc_byte2;
5be19a9d
XS		 1352 unsigned long timeout;
1353
1354 if (!dev)
1355 return -EINVAL;
1356
5f81f4b0 1357 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1358
1359 /* set controller to stop state */
1360 usbcmd = readl(&dev->op_regs->usbcmd);
1361 usbcmd &= ~CMD_RUNSTOP;
1362 writel(usbcmd, &dev->op_regs->usbcmd);
1363
1364 /* reset device controller */
1365 usbcmd = readl(&dev->op_regs->usbcmd);
1366 usbcmd |= CMD_RST;
1367 writel(usbcmd, &dev->op_regs->usbcmd);
1368
1369 /* wait for reset to complete */
1370 timeout = jiffies + RESET_TIMEOUT;
1371 while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
1372 if (time_after(jiffies, timeout)) {
5f81f4b0 1373 dev_err(&dev->pdev->dev, "device reset timeout\n");
5be19a9d
XS		 1374 return -ETIMEDOUT;
1375 }
1376 cpu_relax();
1377 }
1378
1379 /* set controller to device mode */
1380 usbmode = readl(&dev->op_regs->usbmode);
1381 usbmode |= MODE_DEVICE;
1382
1383 /* turn setup lockout off, require setup tripwire in usbcmd */
1384 usbmode |= MODE_SLOM;
1385
1386 writel(usbmode, &dev->op_regs->usbmode);
1387 usbmode = readl(&dev->op_regs->usbmode);
5f81f4b0 1388 dev_vdbg(&dev->pdev->dev, "usbmode=0x%08x\n", usbmode);
5be19a9d
XS		 1389
1390 /* Write-Clear setup status */
1391 writel(0, &dev->op_regs->usbsts);
1392
1393 /* if support USB LPM, ACK all LPM token */
1394 if (dev->lpm) {
1395 devlc = readl(&dev->op_regs->devlc);
513b91b6
J		 1396 dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
1397 /* FIXME: workaround for Langwell A1/A2/A3 sighting */
5be19a9d
XS		 1398 devlc &= ~LPM_STL; /* don't STALL LPM token */
1399 devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
513b91b6
J		 1400 devlc_byte0 = devlc & 0xff;
1401 devlc_byte2 = (devlc >> 16) & 0xff;
1402 writeb(devlc_byte0, (u8 *)&dev->op_regs->devlc);
1403 writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
1404 devlc = readl(&dev->op_regs->devlc);
1405 dev_vdbg(&dev->pdev->dev,
1406 "ACK LPM token, devlc = 0x%08x\n", devlc);
5be19a9d
XS		 1407 }
1408
1409 /* fill endpointlistaddr register */
1410 endpointlistaddr = dev->ep_dqh_dma;
1411 endpointlistaddr &= ENDPOINTLISTADDR_MASK;
1412 writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
1413
5f81f4b0
J		 1414 dev_vdbg(&dev->pdev->dev,
1415 "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
1416 dev->ep_dqh, endpointlistaddr,
1417 readl(&dev->op_regs->endpointlistaddr));
1418 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1419 return 0;
1420}
1421
1422
1423/* reinitialize device controller endpoints */
1424static int eps_reinit(struct langwell_udc *dev)
1425{
1426 struct langwell_ep *ep;
1427 char name[14];
1428 int i;
1429
5f81f4b0 1430 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1431
1432 /* initialize ep0 */
1433 ep = &dev->ep[0];
1434 ep->dev = dev;
1435 strncpy(ep->name, "ep0", sizeof(ep->name));
1436 ep->ep.name = ep->name;
1437 ep->ep.ops = &langwell_ep_ops;
1438 ep->stopped = 0;
1439 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1440 ep->ep_num = 0;
1441 ep->desc = &langwell_ep0_desc;
1442 INIT_LIST_HEAD(&ep->queue);
1443
1444 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1445
1446 /* initialize other endpoints */
1447 for (i = 2; i < dev->ep_max; i++) {
1448 ep = &dev->ep[i];
1449 if (i % 2)
1450 snprintf(name, sizeof(name), "ep%din", i / 2);
1451 else
1452 snprintf(name, sizeof(name), "ep%dout", i / 2);
1453 ep->dev = dev;
1454 strncpy(ep->name, name, sizeof(ep->name));
1455 ep->ep.name = ep->name;
1456
1457 ep->ep.ops = &langwell_ep_ops;
1458 ep->stopped = 0;
1459 ep->ep.maxpacket = (unsigned short) ~0;
1460 ep->ep_num = i / 2;
1461
1462 INIT_LIST_HEAD(&ep->queue);
1463 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
5be19a9d
XS		 1464 }
1465
5f81f4b0 1466 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1467 return 0;
1468}
1469
1470
1471/* enable interrupt and set controller to run state */
1472static void langwell_udc_start(struct langwell_udc *dev)
1473{
1474 u32 usbintr, usbcmd;
5f81f4b0 1475 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1476
1477 /* enable interrupts */
1478 usbintr = INTR_ULPIE /* ULPI */
1479 | INTR_SLE /* suspend */
1480 /* | INTR_SRE SOF received */
1481 | INTR_URE /* USB reset */
1482 | INTR_AAE /* async advance */
1483 | INTR_SEE /* system error */
1484 | INTR_FRE /* frame list rollover */
1485 | INTR_PCE /* port change detect */
1486 | INTR_UEE /* USB error interrupt */
1487 | INTR_UE; /* USB interrupt */
1488 writel(usbintr, &dev->op_regs->usbintr);
1489
1490 /* clear stopped bit */
1491 dev->stopped = 0;
1492
1493 /* set controller to run */
1494 usbcmd = readl(&dev->op_regs->usbcmd);
1495 usbcmd |= CMD_RUNSTOP;
1496 writel(usbcmd, &dev->op_regs->usbcmd);
1497
5f81f4b0 1498 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1499}
1500
1501
1502/* disable interrupt and set controller to stop state */
1503static void langwell_udc_stop(struct langwell_udc *dev)
1504{
1505 u32 usbcmd;
1506
5f81f4b0 1507 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1508
1509 /* disable all interrupts */
1510 writel(0, &dev->op_regs->usbintr);
1511
1512 /* set stopped bit */
1513 dev->stopped = 1;
1514
1515 /* set controller to stop state */
1516 usbcmd = readl(&dev->op_regs->usbcmd);
1517 usbcmd &= ~CMD_RUNSTOP;
1518 writel(usbcmd, &dev->op_regs->usbcmd);
1519
5f81f4b0 1520 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1521}
1522
1523
1524/* stop all USB activities */
1525static void stop_activity(struct langwell_udc *dev,
1526 struct usb_gadget_driver *driver)
1527{
1528 struct langwell_ep *ep;
5f81f4b0 1529 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1530
1531 nuke(&dev->ep[0], -ESHUTDOWN);
1532
1533 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
1534 nuke(ep, -ESHUTDOWN);
1535 }
1536
1537 /* report disconnect; the driver is already quiesced */
1538 if (driver) {
1539 spin_unlock(&dev->lock);
1540 driver->disconnect(&dev->gadget);
1541 spin_lock(&dev->lock);
1542 }
1543
5f81f4b0 1544 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1545}
1546
1547
1548/*-------------------------------------------------------------------------*/
1549
1550/* device "function" sysfs attribute file */
1551static ssize_t show_function(struct device *_dev,
1552 struct device_attribute *attr, char *buf)
1553{
1554 struct langwell_udc *dev = the_controller;
1555
1556 if (!dev->driver || !dev->driver->function
1557 || strlen(dev->driver->function) > PAGE_SIZE)
1558 return 0;
1559
1560 return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
1561}
1562static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
1563
1564
56526c0b
RD		 1565static inline enum usb_device_speed lpm_device_speed(u32 reg)
1566{
1567 switch (LPM_PSPD(reg)) {
1568 case LPM_SPEED_HIGH:
1569 return USB_SPEED_HIGH;
1570 case LPM_SPEED_FULL:
1571 return USB_SPEED_FULL;
1572 case LPM_SPEED_LOW:
1573 return USB_SPEED_LOW;
1574 default:
1575 return USB_SPEED_UNKNOWN;
1576 }
1577}
1578
5be19a9d
XS		 1579/* device "langwell_udc" sysfs attribute file */
1580static ssize_t show_langwell_udc(struct device *_dev,
1581 struct device_attribute *attr, char *buf)
1582{
1583 struct langwell_udc *dev = the_controller;
1584 struct langwell_request *req;
1585 struct langwell_ep *ep = NULL;
1586 char *next;
1587 unsigned size;
1588 unsigned t;
1589 unsigned i;
1590 unsigned long flags;
1591 u32 tmp_reg;
1592
1593 next = buf;
1594 size = PAGE_SIZE;
1595 spin_lock_irqsave(&dev->lock, flags);
1596
1597 /* driver basic information */
1598 t = scnprintf(next, size,
1599 DRIVER_DESC "\n"
1600 "%s version: %s\n"
1601 "Gadget driver: %s\n\n",
1602 driver_name, DRIVER_VERSION,
1603 dev->driver ? dev->driver->driver.name : "(none)");
1604 size -= t;
1605 next += t;
1606
1607 /* device registers */
1608 tmp_reg = readl(&dev->op_regs->usbcmd);
1609 t = scnprintf(next, size,
1610 "USBCMD reg:\n"
1611 "SetupTW: %d\n"
1612 "Run/Stop: %s\n\n",
1613 (tmp_reg & CMD_SUTW) ? 1 : 0,
1614 (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
1615 size -= t;
1616 next += t;
1617
1618 tmp_reg = readl(&dev->op_regs->usbsts);
1619 t = scnprintf(next, size,
1620 "USB Status Reg:\n"
1621 "Device Suspend: %d\n"
1622 "Reset Received: %d\n"
1623 "System Error: %s\n"
1624 "USB Error Interrupt: %s\n\n",
1625 (tmp_reg & STS_SLI) ? 1 : 0,
1626 (tmp_reg & STS_URI) ? 1 : 0,
1627 (tmp_reg & STS_SEI) ? "Error" : "No error",
1628 (tmp_reg & STS_UEI) ? "Error detected" : "No error");
1629 size -= t;
1630 next += t;
1631
1632 tmp_reg = readl(&dev->op_regs->usbintr);
1633 t = scnprintf(next, size,
1634 "USB Intrrupt Enable Reg:\n"
1635 "Sleep Enable: %d\n"
1636 "SOF Received Enable: %d\n"
1637 "Reset Enable: %d\n"
1638 "System Error Enable: %d\n"
1639 "Port Change Dectected Enable: %d\n"
1640 "USB Error Intr Enable: %d\n"
1641 "USB Intr Enable: %d\n\n",
1642 (tmp_reg & INTR_SLE) ? 1 : 0,
1643 (tmp_reg & INTR_SRE) ? 1 : 0,
1644 (tmp_reg & INTR_URE) ? 1 : 0,
1645 (tmp_reg & INTR_SEE) ? 1 : 0,
1646 (tmp_reg & INTR_PCE) ? 1 : 0,
1647 (tmp_reg & INTR_UEE) ? 1 : 0,
1648 (tmp_reg & INTR_UE) ? 1 : 0);
1649 size -= t;
1650 next += t;
1651
1652 tmp_reg = readl(&dev->op_regs->frindex);
1653 t = scnprintf(next, size,
1654 "USB Frame Index Reg:\n"
1655 "Frame Number is 0x%08x\n\n",
1656 (tmp_reg & FRINDEX_MASK));
1657 size -= t;
1658 next += t;
1659
1660 tmp_reg = readl(&dev->op_regs->deviceaddr);
1661 t = scnprintf(next, size,
1662 "USB Device Address Reg:\n"
1663 "Device Addr is 0x%x\n\n",
1664 USBADR(tmp_reg));
1665 size -= t;
1666 next += t;
1667
1668 tmp_reg = readl(&dev->op_regs->endpointlistaddr);
1669 t = scnprintf(next, size,
1670 "USB Endpoint List Address Reg:\n"
1671 "Endpoint List Pointer is 0x%x\n\n",
1672 EPBASE(tmp_reg));
1673 size -= t;
1674 next += t;
1675
1676 tmp_reg = readl(&dev->op_regs->portsc1);
1677 t = scnprintf(next, size,
1678 "USB Port Status & Control Reg:\n"
1679 "Port Reset: %s\n"
1680 "Port Suspend Mode: %s\n"
1681 "Over-current Change: %s\n"
1682 "Port Enable/Disable Change: %s\n"
1683 "Port Enabled/Disabled: %s\n"
5f81f4b0
J		 1684 "Current Connect Status: %s\n"
1685 "LPM Suspend Status: %s\n\n",
5be19a9d
XS		 1686 (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
1687 (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
1688 (tmp_reg & PORTS_OCC) ? "Detected" : "No",
1689 (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
1690 (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
5f81f4b0
J		 1691 (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached",
1692 (tmp_reg & PORTS_SLP) ? "LPM L1" : "LPM L0");
5be19a9d
XS		 1693 size -= t;
1694 next += t;
1695
1696 tmp_reg = readl(&dev->op_regs->devlc);
1697 t = scnprintf(next, size,
1698 "Device LPM Control Reg:\n"
1699 "Parallel Transceiver : %d\n"
1700 "Serial Transceiver : %d\n"
1701 "Port Speed: %s\n"
1702 "Port Force Full Speed Connenct: %s\n"
5f81f4b0 1703 "PHY Low Power Suspend Clock: %s\n"
5be19a9d
XS		 1704 "BmAttributes: %d\n\n",
1705 LPM_PTS(tmp_reg),
1706 (tmp_reg & LPM_STS) ? 1 : 0,
e538dfda 1707 usb_speed_string(lpm_device_speed(tmp_reg)),
5be19a9d
XS		 1708 (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
1709 (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
1710 LPM_BA(tmp_reg));
1711 size -= t;
1712 next += t;
1713
1714 tmp_reg = readl(&dev->op_regs->usbmode);
1715 t = scnprintf(next, size,
1716 "USB Mode Reg:\n"
1717 "Controller Mode is : %s\n\n", ({
1718 char *s;
1719 switch (MODE_CM(tmp_reg)) {
1720 case MODE_IDLE:
1721 s = "Idle"; break;
1722 case MODE_DEVICE:
1723 s = "Device Controller"; break;
1724 case MODE_HOST:
1725 s = "Host Controller"; break;
1726 default:
1727 s = "None"; break;
1728 }
1729 s;
1730 }));
1731 size -= t;
1732 next += t;
1733
1734 tmp_reg = readl(&dev->op_regs->endptsetupstat);
1735 t = scnprintf(next, size,
1736 "Endpoint Setup Status Reg:\n"
1737 "SETUP on ep 0x%04x\n\n",
1738 tmp_reg & SETUPSTAT_MASK);
1739 size -= t;
1740 next += t;
1741
1742 for (i = 0; i < dev->ep_max / 2; i++) {
1743 tmp_reg = readl(&dev->op_regs->endptctrl[i]);
1744 t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
1745 i, tmp_reg);
1746 size -= t;
1747 next += t;
1748 }
1749 tmp_reg = readl(&dev->op_regs->endptprime);
1750 t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
1751 size -= t;
1752 next += t;
1753
1754 /* langwell_udc, langwell_ep, langwell_request structure information */
1755 ep = &dev->ep[0];
1756 t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
1757 ep->ep.name, ep->ep.maxpacket, ep->ep_num);
1758 size -= t;
1759 next += t;
1760
1761 if (list_empty(&ep->queue)) {
1762 t = scnprintf(next, size, "its req queue is empty\n\n");
1763 size -= t;
1764 next += t;
1765 } else {
1766 list_for_each_entry(req, &ep->queue, queue) {
1767 t = scnprintf(next, size,
1768 "req %p actual 0x%x length 0x%x buf %p\n",
1769 &req->req, req->req.actual,
1770 req->req.length, req->req.buf);
1771 size -= t;
1772 next += t;
1773 }
1774 }
1775 /* other gadget->eplist ep */
1776 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
1777 if (ep->desc) {
1778 t = scnprintf(next, size,
1779 "\n%s MaxPacketSize: 0x%x, "
1780 "ep_num: %d\n",
1781 ep->ep.name, ep->ep.maxpacket,
1782 ep->ep_num);
1783 size -= t;
1784 next += t;
1785
1786 if (list_empty(&ep->queue)) {
1787 t = scnprintf(next, size,
1788 "its req queue is empty\n\n");
1789 size -= t;
1790 next += t;
1791 } else {
1792 list_for_each_entry(req, &ep->queue, queue) {
1793 t = scnprintf(next, size,
1794 "req %p actual 0x%x length "
1795 "0x%x buf %p\n",
1796 &req->req, req->req.actual,
1797 req->req.length, req->req.buf);
1798 size -= t;
1799 next += t;
1800 }
1801 }
1802 }
1803 }
1804
1805 spin_unlock_irqrestore(&dev->lock, flags);
1806 return PAGE_SIZE - size;
1807}
1808static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
1809
1810
3211cbc2
J		 1811/* device "remote_wakeup" sysfs attribute file */
1812static ssize_t store_remote_wakeup(struct device *_dev,
1813 struct device_attribute *attr, const char *buf, size_t count)
1814{
1815 struct langwell_udc *dev = the_controller;
1816 unsigned long flags;
1817 ssize_t rc = count;
1818
1819 if (count > 2)
1820 return -EINVAL;
1821
1822 if (count > 0 && buf[count-1] == '\n')
1823 ((char *) buf)[count-1] = 0;
1824
1825 if (buf[0] != '1')
1826 return -EINVAL;
1827
1828 /* force remote wakeup enabled in case gadget driver doesn't support */
1829 spin_lock_irqsave(&dev->lock, flags);
1830 dev->remote_wakeup = 1;
1831 dev->dev_status |= (1 << USB_DEVICE_REMOTE_WAKEUP);
1832 spin_unlock_irqrestore(&dev->lock, flags);
1833
1834 langwell_wakeup(&dev->gadget);
1835
1836 return rc;
1837}
1838static DEVICE_ATTR(remote_wakeup, S_IWUSR, NULL, store_remote_wakeup);
1839
1840
5be19a9d
XS		 1841/*-------------------------------------------------------------------------*/
1842
1843/*
1844 * when a driver is successfully registered, it will receive
1845 * control requests including set_configuration(), which enables
1846 * non-control requests. then usb traffic follows until a
1847 * disconnect is reported. then a host may connect again, or
1848 * the driver might get unbound.
1849 */
1850
0f91349b 1851static int langwell_start(struct usb_gadget_driver *driver,
b0fca50f 1852 int (*bind)(struct usb_gadget *))
5be19a9d
XS		 1853{
1854 struct langwell_udc *dev = the_controller;
1855 unsigned long flags;
1856 int retval;
1857
1858 if (!dev)
1859 return -ENODEV;
1860
5f81f4b0 1861 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1862
1863 if (dev->driver)
1864 return -EBUSY;
1865
1866 spin_lock_irqsave(&dev->lock, flags);
1867
1868 /* hook up the driver ... */
1869 driver->driver.bus = NULL;
1870 dev->driver = driver;
1871 dev->gadget.dev.driver = &driver->driver;
1872
1873 spin_unlock_irqrestore(&dev->lock, flags);
1874
b0fca50f 1875 retval = bind(&dev->gadget);
5be19a9d 1876 if (retval) {
5f81f4b0 1877 dev_dbg(&dev->pdev->dev, "bind to driver %s --> %d\n",
5be19a9d
XS		 1878 driver->driver.name, retval);
1879 dev->driver = NULL;
1880 dev->gadget.dev.driver = NULL;
1881 return retval;
1882 }
1883
1884 retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
1885 if (retval)
1886 goto err_unbind;
1887
1888 dev->usb_state = USB_STATE_ATTACHED;
1889 dev->ep0_state = WAIT_FOR_SETUP;
1890 dev->ep0_dir = USB_DIR_OUT;
1891
1892 /* enable interrupt and set controller to run state */
1893 if (dev->got_irq)
1894 langwell_udc_start(dev);
1895
5f81f4b0
J		 1896 dev_vdbg(&dev->pdev->dev,
1897 "After langwell_udc_start(), print all registers:\n");
5be19a9d 1898 print_all_registers(dev);
5be19a9d 1899
5f81f4b0
J		 1900 dev_info(&dev->pdev->dev, "register driver: %s\n",
1901 driver->driver.name);
1902 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1903 return 0;
1904
1905err_unbind:
1906 driver->unbind(&dev->gadget);
1907 dev->gadget.dev.driver = NULL;
1908 dev->driver = NULL;
1909
5f81f4b0 1910 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1911 return retval;
1912}
5be19a9d
XS		 1913
1914/* unregister gadget driver */
0f91349b 1915static int langwell_stop(struct usb_gadget_driver *driver)
5be19a9d
XS		 1916{
1917 struct langwell_udc *dev = the_controller;
1918 unsigned long flags;
1919
1920 if (!dev)
1921 return -ENODEV;
1922
5f81f4b0 1923 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 1924
b0fca50f 1925 if (unlikely(!driver || !driver->unbind))
5be19a9d
XS		 1926 return -EINVAL;
1927
513b91b6
J		 1928 /* exit PHY low power suspend */
1929 if (dev->pdev->device != 0x0829)
1930 langwell_phy_low_power(dev, 0);
1931
5be19a9d
XS		 1932 /* unbind OTG transceiver */
1933 if (dev->transceiver)
1934 (void)otg_set_peripheral(dev->transceiver, 0);
1935
1936 /* disable interrupt and set controller to stop state */
1937 langwell_udc_stop(dev);
1938
1939 dev->usb_state = USB_STATE_ATTACHED;
1940 dev->ep0_state = WAIT_FOR_SETUP;
1941 dev->ep0_dir = USB_DIR_OUT;
1942
1943 spin_lock_irqsave(&dev->lock, flags);
1944
1945 /* stop all usb activities */
1946 dev->gadget.speed = USB_SPEED_UNKNOWN;
1947 stop_activity(dev, driver);
1948 spin_unlock_irqrestore(&dev->lock, flags);
1949
1950 /* unbind gadget driver */
1951 driver->unbind(&dev->gadget);
1952 dev->gadget.dev.driver = NULL;
1953 dev->driver = NULL;
1954
1955 device_remove_file(&dev->pdev->dev, &dev_attr_function);
1956
5f81f4b0
J		 1957 dev_info(&dev->pdev->dev, "unregistered driver '%s'\n",
1958 driver->driver.name);
1959 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 1960 return 0;
1961}
5be19a9d
XS		 1962
1963/*-------------------------------------------------------------------------*/
1964
1965/*
1966 * setup tripwire is used as a semaphore to ensure that the setup data
1967 * payload is extracted from a dQH without being corrupted
1968 */
1969static void setup_tripwire(struct langwell_udc *dev)
1970{
1971 u32 usbcmd,
1972 endptsetupstat;
1973 unsigned long timeout;
1974 struct langwell_dqh *dqh;
1975
5f81f4b0 1976 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 1977
1978 /* ep0 OUT dQH */
1979 dqh = &dev->ep_dqh[EP_DIR_OUT];
1980
1981 /* Write-Clear endptsetupstat */
1982 endptsetupstat = readl(&dev->op_regs->endptsetupstat);
1983 writel(endptsetupstat, &dev->op_regs->endptsetupstat);
1984
1985 /* wait until endptsetupstat is cleared */
1986 timeout = jiffies + SETUPSTAT_TIMEOUT;
1987 while (readl(&dev->op_regs->endptsetupstat)) {
1988 if (time_after(jiffies, timeout)) {
5f81f4b0 1989 dev_err(&dev->pdev->dev, "setup_tripwire timeout\n");
5be19a9d
XS		 1990 break;
1991 }
1992 cpu_relax();
1993 }
1994
1995 /* while a hazard exists when setup packet arrives */
1996 do {
1997 /* set setup tripwire bit */
1998 usbcmd = readl(&dev->op_regs->usbcmd);
1999 writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
2000
2001 /* copy the setup packet to local buffer */
2002 memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
2003 } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
2004
2005 /* Write-Clear setup tripwire bit */
2006 usbcmd = readl(&dev->op_regs->usbcmd);
2007 writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
2008
5f81f4b0 2009 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2010}
2011
2012
2013/* protocol ep0 stall, will automatically be cleared on new transaction */
2014static void ep0_stall(struct langwell_udc *dev)
2015{
2016 u32 endptctrl;
2017
5f81f4b0 2018 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2019
2020 /* set TX and RX to stall */
2021 endptctrl = readl(&dev->op_regs->endptctrl[0]);
2022 endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
2023 writel(endptctrl, &dev->op_regs->endptctrl[0]);
2024
2025 /* update ep0 state */
2026 dev->ep0_state = WAIT_FOR_SETUP;
2027 dev->ep0_dir = USB_DIR_OUT;
2028
5f81f4b0 2029 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2030}
2031
2032
2033/* PRIME a status phase for ep0 */
2034static int prime_status_phase(struct langwell_udc *dev, int dir)
2035{
2036 struct langwell_request *req;
2037 struct langwell_ep *ep;
2038 int status = 0;
2039
5f81f4b0 2040 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2041
2042 if (dir == EP_DIR_IN)
2043 dev->ep0_dir = USB_DIR_IN;
2044 else
2045 dev->ep0_dir = USB_DIR_OUT;
2046
2047 ep = &dev->ep[0];
2048 dev->ep0_state = WAIT_FOR_OUT_STATUS;
2049
2050 req = dev->status_req;
2051
2052 req->ep = ep;
2053 req->req.length = 0;
2054 req->req.status = -EINPROGRESS;
2055 req->req.actual = 0;
2056 req->req.complete = NULL;
2057 req->dtd_count = 0;
2058
2059 if (!req_to_dtd(req))
2060 status = queue_dtd(ep, req);
2061 else
2062 return -ENOMEM;
2063
2064 if (status)
5f81f4b0 2065 dev_err(&dev->pdev->dev, "can't queue ep0 status request\n");
5be19a9d
XS		 2066
2067 list_add_tail(&req->queue, &ep->queue);
2068
5f81f4b0 2069 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2070 return status;
2071}
2072
2073
2074/* SET_ADDRESS request routine */
2075static void set_address(struct langwell_udc *dev, u16 value,
2076 u16 index, u16 length)
2077{
5f81f4b0 2078 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2079
2080 /* save the new address to device struct */
2081 dev->dev_addr = (u8) value;
5f81f4b0 2082 dev_vdbg(&dev->pdev->dev, "dev->dev_addr = %d\n", dev->dev_addr);
5be19a9d
XS		 2083
2084 /* update usb state */
2085 dev->usb_state = USB_STATE_ADDRESS;
2086
2087 /* STATUS phase */
2088 if (prime_status_phase(dev, EP_DIR_IN))
2089 ep0_stall(dev);
2090
5f81f4b0 2091 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2092}
2093
2094
2095/* return endpoint by windex */
2096static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
2097 u16 wIndex)
2098{
2099 struct langwell_ep *ep;
5f81f4b0 2100 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2101
2102 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
2103 return &dev->ep[0];
2104
2105 list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
2106 u8 bEndpointAddress;
2107 if (!ep->desc)
2108 continue;
2109
2110 bEndpointAddress = ep->desc->bEndpointAddress;
2111 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
2112 continue;
2113
2114 if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
2115 == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
2116 return ep;
2117 }
2118
5f81f4b0 2119 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2120 return NULL;
2121}
2122
2123
2124/* return whether endpoint is stalled, 0: not stalled; 1: stalled */
2125static int ep_is_stall(struct langwell_ep *ep)
2126{
2127 struct langwell_udc *dev = ep->dev;
2128 u32 endptctrl;
2129 int retval;
2130
5f81f4b0 2131 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2132
2133 endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
2134 if (is_in(ep))
2135 retval = endptctrl & EPCTRL_TXS ? 1 : 0;
2136 else
2137 retval = endptctrl & EPCTRL_RXS ? 1 : 0;
2138
5f81f4b0 2139 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2140 return retval;
2141}
2142
2143
2144/* GET_STATUS request routine */
2145static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
2146 u16 index, u16 length)
2147{
2148 struct langwell_request *req;
2149 struct langwell_ep *ep;
2150 u16 status_data = 0; /* 16 bits cpu view status data */
2151 int status = 0;
2152
5f81f4b0 2153 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2154
2155 ep = &dev->ep[0];
2156
2157 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
2158 /* get device status */
3211cbc2 2159 status_data = dev->dev_status;
5be19a9d
XS		 2160 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
2161 /* get interface status */
2162 status_data = 0;
2163 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
2164 /* get endpoint status */
2165 struct langwell_ep *epn;
2166 epn = get_ep_by_windex(dev, index);
2167 /* stall if endpoint doesn't exist */
2168 if (!epn)
2169 goto stall;
2170
2171 status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
2172 }
2173
5f81f4b0
J		 2174 dev_dbg(&dev->pdev->dev, "get status data: 0x%04x\n", status_data);
2175
5be19a9d
XS		 2176 dev->ep0_dir = USB_DIR_IN;
2177
2178 /* borrow the per device status_req */
2179 req = dev->status_req;
2180
2181 /* fill in the reqest structure */
2182 *((u16 *) req->req.buf) = cpu_to_le16(status_data);
2183 req->ep = ep;
2184 req->req.length = 2;
2185 req->req.status = -EINPROGRESS;
2186 req->req.actual = 0;
2187 req->req.complete = NULL;
2188 req->dtd_count = 0;
2189
2190 /* prime the data phase */
2191 if (!req_to_dtd(req))
2192 status = queue_dtd(ep, req);
2193 else /* no mem */
2194 goto stall;
2195
2196 if (status) {
5f81f4b0
J		 2197 dev_err(&dev->pdev->dev,
2198 "response error on GET_STATUS request\n");
5be19a9d
XS		 2199 goto stall;
2200 }
2201
2202 list_add_tail(&req->queue, &ep->queue);
2203 dev->ep0_state = DATA_STATE_XMIT;
2204
5f81f4b0 2205 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2206 return;
2207stall:
2208 ep0_stall(dev);
5f81f4b0 2209 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2210}
2211
2212
2213/* setup packet interrupt handler */
2214static void handle_setup_packet(struct langwell_udc *dev,
2215 struct usb_ctrlrequest *setup)
2216{
2217 u16 wValue = le16_to_cpu(setup->wValue);
2218 u16 wIndex = le16_to_cpu(setup->wIndex);
2219 u16 wLength = le16_to_cpu(setup->wLength);
7fc56f0d 2220 u32 portsc1;
5be19a9d 2221
5f81f4b0 2222 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2223
2224 /* ep0 fifo flush */
2225 nuke(&dev->ep[0], -ESHUTDOWN);
2226
5f81f4b0 2227 dev_dbg(&dev->pdev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
5be19a9d
XS		 2228 setup->bRequestType, setup->bRequest,
2229 wValue, wIndex, wLength);
2230
2231 /* RNDIS gadget delegate */
2232 if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
2233 /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
2234 goto delegate;
2235 }
2236
2237 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
2238 if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
2239 /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
2240 goto delegate;
2241 }
2242
2243 /* We process some stardard setup requests here */
2244 switch (setup->bRequest) {
2245 case USB_REQ_GET_STATUS:
5f81f4b0 2246 dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_GET_STATUS\n");
5be19a9d
XS		 2247 /* get status, DATA and STATUS phase */
2248 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
2249 != (USB_DIR_IN | USB_TYPE_STANDARD))
2250 break;
2251 get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
2252 goto end;
2253
2254 case USB_REQ_SET_ADDRESS:
5f81f4b0 2255 dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_SET_ADDRESS\n");
5be19a9d
XS		 2256 /* STATUS phase */
2257 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
2258 | USB_RECIP_DEVICE))
2259 break;
2260 set_address(dev, wValue, wIndex, wLength);
2261 goto end;
2262
2263 case USB_REQ_CLEAR_FEATURE:
2264 case USB_REQ_SET_FEATURE:
2265 /* STATUS phase */
2266 {
2267 int rc = -EOPNOTSUPP;
2268 if (setup->bRequest == USB_REQ_SET_FEATURE)
5f81f4b0
J		 2269 dev_dbg(&dev->pdev->dev,
2270 "SETUP: USB_REQ_SET_FEATURE\n");
5be19a9d 2271 else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
5f81f4b0
J		 2272 dev_dbg(&dev->pdev->dev,
2273 "SETUP: USB_REQ_CLEAR_FEATURE\n");
5be19a9d
XS		 2274
2275 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
2276 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
2277 struct langwell_ep *epn;
2278 epn = get_ep_by_windex(dev, wIndex);
2279 /* stall if endpoint doesn't exist */
2280 if (!epn) {
2281 ep0_stall(dev);
2282 goto end;
2283 }
2284
2285 if (wValue != 0 || wLength != 0
2286 || epn->ep_num > dev->ep_max)
2287 break;
2288
2289 spin_unlock(&dev->lock);
2290 rc = langwell_ep_set_halt(&epn->ep,
5f81f4b0
J		 2291 (setup->bRequest == USB_REQ_SET_FEATURE)
2292 ? 1 : 0);
5be19a9d
XS		 2293 spin_lock(&dev->lock);
2294
2295 } else if ((setup->bRequestType & (USB_RECIP_MASK
2296 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
2297 | USB_TYPE_STANDARD)) {
3211cbc2
J		 2298 rc = 0;
2299 switch (wValue) {
2300 case USB_DEVICE_REMOTE_WAKEUP:
2301 if (setup->bRequest == USB_REQ_SET_FEATURE) {
2302 dev->remote_wakeup = 1;
2303 dev->dev_status |= (1 << wValue);
2304 } else {
2305 dev->remote_wakeup = 0;
2306 dev->dev_status &= ~(1 << wValue);
2307 }
2308 break;
7fc56f0d
LA		 2309 case USB_DEVICE_TEST_MODE:
2310 dev_dbg(&dev->pdev->dev, "SETUP: TEST MODE\n");
2311 if ((wIndex & 0xff) ||
2312 (dev->gadget.speed != USB_SPEED_HIGH))
2313 ep0_stall(dev);
2314
2315 switch (wIndex >> 8) {
2316 case TEST_J:
2317 case TEST_K:
2318 case TEST_SE0_NAK:
2319 case TEST_PACKET:
2320 case TEST_FORCE_EN:
2321 if (prime_status_phase(dev, EP_DIR_IN))
2322 ep0_stall(dev);
2323 portsc1 = readl(&dev->op_regs->portsc1);
2324 portsc1 |= (wIndex & 0xf00) << 8;
2325 writel(portsc1, &dev->op_regs->portsc1);
2326 goto end;
2327 default:
2328 rc = -EOPNOTSUPP;
2329 }
2330 break;
3211cbc2
J		 2331 default:
2332 rc = -EOPNOTSUPP;
2333 break;
2334 }
2335
5be19a9d
XS		 2336 if (!gadget_is_otg(&dev->gadget))
2337 break;
2338 else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) {
2339 dev->gadget.b_hnp_enable = 1;
2340#ifdef OTG_TRANSCEIVER
2341 if (!dev->lotg->otg.default_a)
2342 dev->lotg->hsm.b_hnp_enable = 1;
2343#endif
2344 } else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
2345 dev->gadget.a_hnp_support = 1;
2346 else if (setup->bRequest ==
2347 USB_DEVICE_A_ALT_HNP_SUPPORT)
2348 dev->gadget.a_alt_hnp_support = 1;
2349 else
2350 break;
5be19a9d
XS		 2351 } else
2352 break;
2353
2354 if (rc == 0) {
2355 if (prime_status_phase(dev, EP_DIR_IN))
2356 ep0_stall(dev);
2357 }
2358 goto end;
2359 }
2360
2361 case USB_REQ_GET_DESCRIPTOR:
5f81f4b0
J		 2362 dev_dbg(&dev->pdev->dev,
2363 "SETUP: USB_REQ_GET_DESCRIPTOR\n");
5be19a9d
XS		 2364 goto delegate;
2365
2366 case USB_REQ_SET_DESCRIPTOR:
5f81f4b0
J		 2367 dev_dbg(&dev->pdev->dev,
2368 "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
5be19a9d
XS		 2369 goto delegate;
2370
2371 case USB_REQ_GET_CONFIGURATION:
5f81f4b0
J		 2372 dev_dbg(&dev->pdev->dev,
2373 "SETUP: USB_REQ_GET_CONFIGURATION\n");
5be19a9d
XS		 2374 goto delegate;
2375
2376 case USB_REQ_SET_CONFIGURATION:
5f81f4b0
J		 2377 dev_dbg(&dev->pdev->dev,
2378 "SETUP: USB_REQ_SET_CONFIGURATION\n");
5be19a9d
XS		 2379 goto delegate;
2380
2381 case USB_REQ_GET_INTERFACE:
5f81f4b0
J		 2382 dev_dbg(&dev->pdev->dev,
2383 "SETUP: USB_REQ_GET_INTERFACE\n");
5be19a9d
XS		 2384 goto delegate;
2385
2386 case USB_REQ_SET_INTERFACE:
5f81f4b0
J		 2387 dev_dbg(&dev->pdev->dev,
2388 "SETUP: USB_REQ_SET_INTERFACE\n");
5be19a9d
XS		 2389 goto delegate;
2390
2391 case USB_REQ_SYNCH_FRAME:
5f81f4b0
J		 2392 dev_dbg(&dev->pdev->dev,
2393 "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
5be19a9d
XS		 2394 goto delegate;
2395
2396 default:
2397 /* delegate USB standard requests to the gadget driver */
2398 goto delegate;
2399delegate:
2400 /* USB requests handled by gadget */
2401 if (wLength) {
2402 /* DATA phase from gadget, STATUS phase from udc */
2403 dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
2404 ? USB_DIR_IN : USB_DIR_OUT;
5f81f4b0
J		 2405 dev_vdbg(&dev->pdev->dev,
2406 "dev->ep0_dir = 0x%x, wLength = %d\n",
5be19a9d
XS		 2407 dev->ep0_dir, wLength);
2408 spin_unlock(&dev->lock);
2409 if (dev->driver->setup(&dev->gadget,
2410 &dev->local_setup_buff) < 0)
2411 ep0_stall(dev);
2412 spin_lock(&dev->lock);
2413 dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
2414 ? DATA_STATE_XMIT : DATA_STATE_RECV;
2415 } else {
2416 /* no DATA phase, IN STATUS phase from gadget */
2417 dev->ep0_dir = USB_DIR_IN;
5f81f4b0
J		 2418 dev_vdbg(&dev->pdev->dev,
2419 "dev->ep0_dir = 0x%x, wLength = %d\n",
5be19a9d
XS		 2420 dev->ep0_dir, wLength);
2421 spin_unlock(&dev->lock);
2422 if (dev->driver->setup(&dev->gadget,
2423 &dev->local_setup_buff) < 0)
2424 ep0_stall(dev);
2425 spin_lock(&dev->lock);
2426 dev->ep0_state = WAIT_FOR_OUT_STATUS;
2427 }
2428 break;
2429 }
2430end:
5f81f4b0 2431 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2432}
2433
2434
2435/* transfer completion, process endpoint request and free the completed dTDs
2436 * for this request
2437 */
2438static int process_ep_req(struct langwell_udc *dev, int index,
2439 struct langwell_request *curr_req)
2440{
2441 struct langwell_dtd *curr_dtd;
2442 struct langwell_dqh *curr_dqh;
2443 int td_complete, actual, remaining_length;
2444 int i, dir;
2445 u8 dtd_status = 0;
2446 int retval = 0;
2447
2448 curr_dqh = &dev->ep_dqh[index];
2449 dir = index % 2;
2450
2451 curr_dtd = curr_req->head;
2452 td_complete = 0;
2453 actual = curr_req->req.length;
2454
5f81f4b0 2455 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2456
2457 for (i = 0; i < curr_req->dtd_count; i++) {
5be19a9d
XS		 2458
2459 /* command execution states by dTD */
2460 dtd_status = curr_dtd->dtd_status;
2461
c8458d59
CL		 2462 barrier();
2463 remaining_length = le16_to_cpu(curr_dtd->dtd_total);
2464 actual -= remaining_length;
2465
5be19a9d
XS		 2466 if (!dtd_status) {
2467 /* transfers completed successfully */
2468 if (!remaining_length) {
2469 td_complete++;
5f81f4b0
J		 2470 dev_vdbg(&dev->pdev->dev,
2471 "dTD transmitted successfully\n");
5be19a9d
XS		 2472 } else {
2473 if (dir) {
5f81f4b0
J		 2474 dev_vdbg(&dev->pdev->dev,
2475 "TX dTD remains data\n");
5be19a9d
XS		 2476 retval = -EPROTO;
2477 break;
2478
2479 } else {
2480 td_complete++;
2481 break;
2482 }
2483 }
2484 } else {
2485 /* transfers completed with errors */
2486 if (dtd_status & DTD_STS_ACTIVE) {
5f81f4b0
J		 2487 dev_dbg(&dev->pdev->dev,
2488 "dTD status ACTIVE dQH[%d]\n", index);
5be19a9d
XS		 2489 retval = 1;
2490 return retval;
2491 } else if (dtd_status & DTD_STS_HALTED) {
5f81f4b0
J		 2492 dev_err(&dev->pdev->dev,
2493 "dTD error %08x dQH[%d]\n",
2494 dtd_status, index);
5be19a9d
XS		 2495 /* clear the errors and halt condition */
2496 curr_dqh->dtd_status = 0;
2497 retval = -EPIPE;
2498 break;
2499 } else if (dtd_status & DTD_STS_DBE) {
5f81f4b0
J		 2500 dev_dbg(&dev->pdev->dev,
2501 "data buffer (overflow) error\n");
5be19a9d
XS		 2502 retval = -EPROTO;
2503 break;
2504 } else if (dtd_status & DTD_STS_TRE) {
5f81f4b0
J		 2505 dev_dbg(&dev->pdev->dev,
2506 "transaction(ISO) error\n");
5be19a9d
XS		 2507 retval = -EILSEQ;
2508 break;
2509 } else
5f81f4b0
J		 2510 dev_err(&dev->pdev->dev,
2511 "unknown error (0x%x)!\n",
2512 dtd_status);
5be19a9d
XS		 2513 }
2514
2515 if (i != curr_req->dtd_count - 1)
2516 curr_dtd = (struct langwell_dtd *)
2517 curr_dtd->next_dtd_virt;
2518 }
2519
2520 if (retval)
2521 return retval;
2522
2523 curr_req->req.actual = actual;
2524
5f81f4b0 2525 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2526 return 0;
2527}
2528
2529
2530/* complete DATA or STATUS phase of ep0 prime status phase if needed */
2531static void ep0_req_complete(struct langwell_udc *dev,
2532 struct langwell_ep *ep0, struct langwell_request *req)
2533{
2534 u32 new_addr;
5f81f4b0 2535 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2536
2537 if (dev->usb_state == USB_STATE_ADDRESS) {
2538 /* set the new address */
2539 new_addr = (u32)dev->dev_addr;
2540 writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
2541
2542 new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
5f81f4b0 2543 dev_vdbg(&dev->pdev->dev, "new_addr = %d\n", new_addr);
5be19a9d
XS		 2544 }
2545
2546 done(ep0, req, 0);
2547
2548 switch (dev->ep0_state) {
2549 case DATA_STATE_XMIT:
2550 /* receive status phase */
2551 if (prime_status_phase(dev, EP_DIR_OUT))
2552 ep0_stall(dev);
2553 break;
2554 case DATA_STATE_RECV:
2555 /* send status phase */
2556 if (prime_status_phase(dev, EP_DIR_IN))
2557 ep0_stall(dev);
2558 break;
2559 case WAIT_FOR_OUT_STATUS:
2560 dev->ep0_state = WAIT_FOR_SETUP;
2561 break;
2562 case WAIT_FOR_SETUP:
5f81f4b0 2563 dev_err(&dev->pdev->dev, "unexpect ep0 packets\n");
5be19a9d
XS		 2564 break;
2565 default:
2566 ep0_stall(dev);
2567 break;
2568 }
2569
5f81f4b0 2570 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2571}
2572
2573
2574/* USB transfer completion interrupt */
2575static void handle_trans_complete(struct langwell_udc *dev)
2576{
2577 u32 complete_bits;
2578 int i, ep_num, dir, bit_mask, status;
2579 struct langwell_ep *epn;
2580 struct langwell_request *curr_req, *temp_req;
2581
5f81f4b0 2582 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2583
2584 complete_bits = readl(&dev->op_regs->endptcomplete);
5f81f4b0
J		 2585 dev_vdbg(&dev->pdev->dev, "endptcomplete register: 0x%08x\n",
2586 complete_bits);
5be19a9d
XS		 2587
2588 /* Write-Clear the bits in endptcomplete register */
2589 writel(complete_bits, &dev->op_regs->endptcomplete);
2590
2591 if (!complete_bits) {
5f81f4b0 2592 dev_dbg(&dev->pdev->dev, "complete_bits = 0\n");
5be19a9d
XS		 2593 goto done;
2594 }
2595
2596 for (i = 0; i < dev->ep_max; i++) {
2597 ep_num = i / 2;
2598 dir = i % 2;
2599
2600 bit_mask = 1 << (ep_num + 16 * dir);
2601
2602 if (!(complete_bits & bit_mask))
2603 continue;
2604
2605 /* ep0 */
2606 if (i == 1)
2607 epn = &dev->ep[0];
2608 else
2609 epn = &dev->ep[i];
2610
2611 if (epn->name == NULL) {
5f81f4b0 2612 dev_warn(&dev->pdev->dev, "invalid endpoint\n");
5be19a9d
XS		 2613 continue;
2614 }
2615
2616 if (i < 2)
2617 /* ep0 in and out */
5f81f4b0 2618 dev_dbg(&dev->pdev->dev, "%s-%s transfer completed\n",
5be19a9d
XS		 2619 epn->name,
2620 is_in(epn) ? "in" : "out");
2621 else
5f81f4b0
J		 2622 dev_dbg(&dev->pdev->dev, "%s transfer completed\n",
2623 epn->name);
5be19a9d
XS		 2624
2625 /* process the req queue until an uncomplete request */
2626 list_for_each_entry_safe(curr_req, temp_req,
2627 &epn->queue, queue) {
2628 status = process_ep_req(dev, i, curr_req);
5f81f4b0
J		 2629 dev_vdbg(&dev->pdev->dev, "%s req status: %d\n",
2630 epn->name, status);
5be19a9d
XS		 2631
2632 if (status)
2633 break;
2634
2635 /* write back status to req */
2636 curr_req->req.status = status;
2637
2638 /* ep0 request completion */
2639 if (ep_num == 0) {
2640 ep0_req_complete(dev, epn, curr_req);
2641 break;
2642 } else {
2643 done(epn, curr_req, status);
2644 }
2645 }
2646 }
2647done:
5f81f4b0 2648 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2649}
2650
5be19a9d
XS		 2651/* port change detect interrupt handler */
2652static void handle_port_change(struct langwell_udc *dev)
2653{
2654 u32 portsc1, devlc;
5be19a9d 2655
5f81f4b0 2656 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2657
2658 if (dev->bus_reset)
2659 dev->bus_reset = 0;
2660
2661 portsc1 = readl(&dev->op_regs->portsc1);
2662 devlc = readl(&dev->op_regs->devlc);
5f81f4b0 2663 dev_vdbg(&dev->pdev->dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
5be19a9d
XS		 2664 portsc1, devlc);
2665
2666 /* bus reset is finished */
2667 if (!(portsc1 & PORTS_PR)) {
2668 /* get the speed */
e538dfda
MN		 2669 dev->gadget.speed = lpm_device_speed(devlc);
2670 dev_vdbg(&dev->pdev->dev, "dev->gadget.speed = %d\n",
2671 dev->gadget.speed);
5be19a9d
XS		 2672 }
2673
2674 /* LPM L0 to L1 */
2675 if (dev->lpm && dev->lpm_state == LPM_L0)
2676 if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
5f81f4b0
J		 2677 dev_info(&dev->pdev->dev, "LPM L0 to L1\n");
2678 dev->lpm_state = LPM_L1;
5be19a9d
XS		 2679 }
2680
2681 /* LPM L1 to L0, force resume or remote wakeup finished */
2682 if (dev->lpm && dev->lpm_state == LPM_L1)
2683 if (!(portsc1 & PORTS_SUSP)) {
5f81f4b0 2684 dev_info(&dev->pdev->dev, "LPM L1 to L0\n");
5be19a9d
XS		 2685 dev->lpm_state = LPM_L0;
2686 }
2687
2688 /* update USB state */
2689 if (!dev->resume_state)
2690 dev->usb_state = USB_STATE_DEFAULT;
2691
5f81f4b0 2692 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2693}
2694
2695
2696/* USB reset interrupt handler */
2697static void handle_usb_reset(struct langwell_udc *dev)
2698{
2699 u32 deviceaddr,
2700 endptsetupstat,
2701 endptcomplete;
2702 unsigned long timeout;
2703
5f81f4b0 2704 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2705
2706 /* Write-Clear the device address */
2707 deviceaddr = readl(&dev->op_regs->deviceaddr);
2708 writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
2709
2710 dev->dev_addr = 0;
2711
2712 /* clear usb state */
2713 dev->resume_state = 0;
2714
2715 /* LPM L1 to L0, reset */
2716 if (dev->lpm)
2717 dev->lpm_state = LPM_L0;
2718
2719 dev->ep0_dir = USB_DIR_OUT;
2720 dev->ep0_state = WAIT_FOR_SETUP;
3211cbc2
J		 2721
2722 /* remote wakeup reset to 0 when the device is reset */
2723 dev->remote_wakeup = 0;
2724 dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
5be19a9d
XS		 2725 dev->gadget.b_hnp_enable = 0;
2726 dev->gadget.a_hnp_support = 0;
2727 dev->gadget.a_alt_hnp_support = 0;
2728
2729 /* Write-Clear all the setup token semaphores */
2730 endptsetupstat = readl(&dev->op_regs->endptsetupstat);
2731 writel(endptsetupstat, &dev->op_regs->endptsetupstat);
2732
2733 /* Write-Clear all the endpoint complete status bits */
2734 endptcomplete = readl(&dev->op_regs->endptcomplete);
2735 writel(endptcomplete, &dev->op_regs->endptcomplete);
2736
2737 /* wait until all endptprime bits cleared */
2738 timeout = jiffies + PRIME_TIMEOUT;
2739 while (readl(&dev->op_regs->endptprime)) {
2740 if (time_after(jiffies, timeout)) {
5f81f4b0 2741 dev_err(&dev->pdev->dev, "USB reset timeout\n");
5be19a9d
XS		 2742 break;
2743 }
2744 cpu_relax();
2745 }
2746
2747 /* write 1s to endptflush register to clear any primed buffers */
2748 writel((u32) ~0, &dev->op_regs->endptflush);
2749
2750 if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
5f81f4b0 2751 dev_vdbg(&dev->pdev->dev, "USB bus reset\n");
5be19a9d
XS		 2752 /* bus is reseting */
2753 dev->bus_reset = 1;
2754
2755 /* reset all the queues, stop all USB activities */
2756 stop_activity(dev, dev->driver);
2757 dev->usb_state = USB_STATE_DEFAULT;
2758 } else {
5f81f4b0 2759 dev_vdbg(&dev->pdev->dev, "device controller reset\n");
5be19a9d
XS		 2760 /* controller reset */
2761 langwell_udc_reset(dev);
2762
2763 /* reset all the queues, stop all USB activities */
2764 stop_activity(dev, dev->driver);
2765
2766 /* reset ep0 dQH and endptctrl */
2767 ep0_reset(dev);
2768
2769 /* enable interrupt and set controller to run state */
2770 langwell_udc_start(dev);
2771
2772 dev->usb_state = USB_STATE_ATTACHED;
2773 }
2774
2775#ifdef OTG_TRANSCEIVER
2776 /* refer to USB OTG 6.6.2.3 b_hnp_en is cleared */
2777 if (!dev->lotg->otg.default_a)
2778 dev->lotg->hsm.b_hnp_enable = 0;
2779#endif
2780
5f81f4b0 2781 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2782}
2783
2784
2785/* USB bus suspend/resume interrupt */
2786static void handle_bus_suspend(struct langwell_udc *dev)
2787{
5f81f4b0 2788 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2789
2790 dev->resume_state = dev->usb_state;
2791 dev->usb_state = USB_STATE_SUSPENDED;
2792
2793#ifdef OTG_TRANSCEIVER
2794 if (dev->lotg->otg.default_a) {
2795 if (dev->lotg->hsm.b_bus_suspend_vld == 1) {
2796 dev->lotg->hsm.b_bus_suspend = 1;
2797 /* notify transceiver the state changes */
2798 if (spin_trylock(&dev->lotg->wq_lock)) {
2799 langwell_update_transceiver();
2800 spin_unlock(&dev->lotg->wq_lock);
2801 }
2802 }
2803 dev->lotg->hsm.b_bus_suspend_vld++;
2804 } else {
2805 if (!dev->lotg->hsm.a_bus_suspend) {
2806 dev->lotg->hsm.a_bus_suspend = 1;
2807 /* notify transceiver the state changes */
2808 if (spin_trylock(&dev->lotg->wq_lock)) {
2809 langwell_update_transceiver();
2810 spin_unlock(&dev->lotg->wq_lock);
2811 }
2812 }
2813 }
2814#endif
2815
2816 /* report suspend to the driver */
2817 if (dev->driver) {
2818 if (dev->driver->suspend) {
2819 spin_unlock(&dev->lock);
2820 dev->driver->suspend(&dev->gadget);
2821 spin_lock(&dev->lock);
5f81f4b0
J		 2822 dev_dbg(&dev->pdev->dev, "suspend %s\n",
2823 dev->driver->driver.name);
5be19a9d
XS		 2824 }
2825 }
2826
2827 /* enter PHY low power suspend */
513b91b6
J		 2828 if (dev->pdev->device != 0x0829)
2829 langwell_phy_low_power(dev, 0);
5be19a9d 2830
5f81f4b0 2831 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2832}
2833
2834
2835static void handle_bus_resume(struct langwell_udc *dev)
2836{
5f81f4b0 2837 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2838
2839 dev->usb_state = dev->resume_state;
2840 dev->resume_state = 0;
2841
2842 /* exit PHY low power suspend */
513b91b6
J		 2843 if (dev->pdev->device != 0x0829)
2844 langwell_phy_low_power(dev, 0);
5be19a9d
XS		 2845
2846#ifdef OTG_TRANSCEIVER
2847 if (dev->lotg->otg.default_a == 0)
2848 dev->lotg->hsm.a_bus_suspend = 0;
2849#endif
2850
2851 /* report resume to the driver */
2852 if (dev->driver) {
2853 if (dev->driver->resume) {
2854 spin_unlock(&dev->lock);
2855 dev->driver->resume(&dev->gadget);
2856 spin_lock(&dev->lock);
5f81f4b0
J		 2857 dev_dbg(&dev->pdev->dev, "resume %s\n",
2858 dev->driver->driver.name);
5be19a9d
XS		 2859 }
2860 }
2861
5f81f4b0 2862 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2863}
2864
2865
2866/* USB device controller interrupt handler */
2867static irqreturn_t langwell_irq(int irq, void *_dev)
2868{
2869 struct langwell_udc *dev = _dev;
2870 u32 usbsts,
2871 usbintr,
2872 irq_sts,
2873 portsc1;
2874
5f81f4b0 2875 dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2876
2877 if (dev->stopped) {
5f81f4b0
J		 2878 dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
2879 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2880 return IRQ_NONE;
2881 }
2882
2883 spin_lock(&dev->lock);
2884
2885 /* USB status */
2886 usbsts = readl(&dev->op_regs->usbsts);
2887
2888 /* USB interrupt enable */
2889 usbintr = readl(&dev->op_regs->usbintr);
2890
2891 irq_sts = usbsts & usbintr;
5f81f4b0
J		 2892 dev_vdbg(&dev->pdev->dev,
2893 "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
5be19a9d
XS		 2894 usbsts, usbintr, irq_sts);
2895
2896 if (!irq_sts) {
5f81f4b0
J		 2897 dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
2898 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2899 spin_unlock(&dev->lock);
2900 return IRQ_NONE;
2901 }
2902
2903 /* Write-Clear interrupt status bits */
2904 writel(irq_sts, &dev->op_regs->usbsts);
2905
2906 /* resume from suspend */
2907 portsc1 = readl(&dev->op_regs->portsc1);
2908 if (dev->usb_state == USB_STATE_SUSPENDED)
2909 if (!(portsc1 & PORTS_SUSP))
2910 handle_bus_resume(dev);
2911
2912 /* USB interrupt */
2913 if (irq_sts & STS_UI) {
5f81f4b0 2914 dev_vdbg(&dev->pdev->dev, "USB interrupt\n");
5be19a9d
XS		 2915
2916 /* setup packet received from ep0 */
2917 if (readl(&dev->op_regs->endptsetupstat)
2918 & EP0SETUPSTAT_MASK) {
5f81f4b0
J		 2919 dev_vdbg(&dev->pdev->dev,
2920 "USB SETUP packet received interrupt\n");
5be19a9d
XS		 2921 /* setup tripwire semaphone */
2922 setup_tripwire(dev);
2923 handle_setup_packet(dev, &dev->local_setup_buff);
2924 }
2925
2926 /* USB transfer completion */
2927 if (readl(&dev->op_regs->endptcomplete)) {
5f81f4b0
J		 2928 dev_vdbg(&dev->pdev->dev,
2929 "USB transfer completion interrupt\n");
5be19a9d
XS		 2930 handle_trans_complete(dev);
2931 }
2932 }
2933
2934 /* SOF received interrupt (for ISO transfer) */
2935 if (irq_sts & STS_SRI) {
2936 /* FIXME */
5f81f4b0 2937 /* dev_vdbg(&dev->pdev->dev, "SOF received interrupt\n"); */
5be19a9d
XS		 2938 }
2939
2940 /* port change detect interrupt */
2941 if (irq_sts & STS_PCI) {
5f81f4b0 2942 dev_vdbg(&dev->pdev->dev, "port change detect interrupt\n");
5be19a9d
XS		 2943 handle_port_change(dev);
2944 }
2945
2946 /* suspend interrrupt */
2947 if (irq_sts & STS_SLI) {
5f81f4b0 2948 dev_vdbg(&dev->pdev->dev, "suspend interrupt\n");
5be19a9d
XS		 2949 handle_bus_suspend(dev);
2950 }
2951
2952 /* USB reset interrupt */
2953 if (irq_sts & STS_URI) {
5f81f4b0 2954 dev_vdbg(&dev->pdev->dev, "USB reset interrupt\n");
5be19a9d
XS		 2955 handle_usb_reset(dev);
2956 }
2957
2958 /* USB error or system error interrupt */
2959 if (irq_sts & (STS_UEI | STS_SEI)) {
2960 /* FIXME */
5f81f4b0 2961 dev_warn(&dev->pdev->dev, "error IRQ, irq_sts: %x\n", irq_sts);
5be19a9d
XS		 2962 }
2963
2964 spin_unlock(&dev->lock);
2965
5f81f4b0 2966 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2967 return IRQ_HANDLED;
2968}
2969
2970
2971/*-------------------------------------------------------------------------*/
2972
2973/* release device structure */
2974static void gadget_release(struct device *_dev)
2975{
2976 struct langwell_udc *dev = the_controller;
2977
5f81f4b0 2978 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 2979
2980 complete(dev->done);
2981
5f81f4b0 2982 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 2983 kfree(dev);
2984}
2985
2986
912c93d1
J		 2987/* enable SRAM caching if SRAM detected */
2988static void sram_init(struct langwell_udc *dev)
2989{
2990 struct pci_dev *pdev = dev->pdev;
2991
2992 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
2993
2994 dev->sram_addr = pci_resource_start(pdev, 1);
2995 dev->sram_size = pci_resource_len(pdev, 1);
2996 dev_info(&dev->pdev->dev, "Found private SRAM at %x size:%x\n",
2997 dev->sram_addr, dev->sram_size);
2998 dev->got_sram = 1;
2999
3000 if (pci_request_region(pdev, 1, kobject_name(&pdev->dev.kobj))) {
3001 dev_warn(&dev->pdev->dev, "SRAM request failed\n");
3002 dev->got_sram = 0;
3003 } else if (!dma_declare_coherent_memory(&pdev->dev, dev->sram_addr,
3004 dev->sram_addr, dev->sram_size, DMA_MEMORY_MAP)) {
3005 dev_warn(&dev->pdev->dev, "SRAM DMA declare failed\n");
3006 pci_release_region(pdev, 1);
3007 dev->got_sram = 0;
3008 }
3009
3010 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
3011}
3012
3013
3014/* release SRAM caching */
3015static void sram_deinit(struct langwell_udc *dev)
3016{
3017 struct pci_dev *pdev = dev->pdev;
3018
3019 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
3020
3021 dma_release_declared_memory(&pdev->dev);
3022 pci_release_region(pdev, 1);
3023
3024 dev->got_sram = 0;
3025
3026 dev_info(&dev->pdev->dev, "release SRAM caching\n");
3027 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
3028}
3029
3030
5be19a9d
XS		 3031/* tear down the binding between this driver and the pci device */
3032static void langwell_udc_remove(struct pci_dev *pdev)
3033{
3034 struct langwell_udc *dev = the_controller;
3035
3036 DECLARE_COMPLETION(done);
3037
3038 BUG_ON(dev->driver);
5f81f4b0 3039 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3040
3041 dev->done = &done;
3042
912c93d1
J		 3043#ifndef OTG_TRANSCEIVER
3044 /* free dTD dma_pool and dQH */
5be19a9d
XS		 3045 if (dev->dtd_pool)
3046 dma_pool_destroy(dev->dtd_pool);
3047
912c93d1
J		 3048 if (dev->ep_dqh)
3049 dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
3050 dev->ep_dqh, dev->ep_dqh_dma);
3051
3052 /* release SRAM caching */
3053 if (dev->has_sram && dev->got_sram)
3054 sram_deinit(dev);
3055#endif
3056
5be19a9d
XS		 3057 if (dev->status_req) {
3058 kfree(dev->status_req->req.buf);
3059 kfree(dev->status_req);
3060 }
3061
5be19a9d
XS		 3062 kfree(dev->ep);
3063
48e34d0f 3064 /* disable IRQ handler */
5be19a9d
XS		 3065 if (dev->got_irq)
3066 free_irq(pdev->irq, dev);
3067
3068#ifndef OTG_TRANSCEIVER
3069 if (dev->cap_regs)
3070 iounmap(dev->cap_regs);
3071
3072 if (dev->region)
3073 release_mem_region(pci_resource_start(pdev, 0),
3074 pci_resource_len(pdev, 0));
3075
3076 if (dev->enabled)
3077 pci_disable_device(pdev);
3078#else
3079 if (dev->transceiver) {
3080 otg_put_transceiver(dev->transceiver);
3081 dev->transceiver = NULL;
3082 dev->lotg = NULL;
3083 }
3084#endif
3085
3086 dev->cap_regs = NULL;
3087
5f81f4b0
J		 3088 dev_info(&dev->pdev->dev, "unbind\n");
3089 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3090
3091 device_unregister(&dev->gadget.dev);
3092 device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
3211cbc2 3093 device_remove_file(&pdev->dev, &dev_attr_remote_wakeup);
5be19a9d
XS		 3094
3095#ifndef OTG_TRANSCEIVER
3096 pci_set_drvdata(pdev, NULL);
3097#endif
3098
3099 /* free dev, wait for the release() finished */
3100 wait_for_completion(&done);
3101
3102 the_controller = NULL;
3103}
3104
3105
3106/*
3107 * wrap this driver around the specified device, but
3108 * don't respond over USB until a gadget driver binds to us.
3109 */
3110static int langwell_udc_probe(struct pci_dev *pdev,
3111 const struct pci_device_id *id)
3112{
3113 struct langwell_udc *dev;
3114#ifndef OTG_TRANSCEIVER
3115 unsigned long resource, len;
3116#endif
3117 void __iomem *base = NULL;
3118 size_t size;
3119 int retval;
3120
3121 if (the_controller) {
3122 dev_warn(&pdev->dev, "ignoring\n");
3123 return -EBUSY;
3124 }
3125
3126 /* alloc, and start init */
3127 dev = kzalloc(sizeof *dev, GFP_KERNEL);
3128 if (dev == NULL) {
3129 retval = -ENOMEM;
3130 goto error;
3131 }
3132
3133 /* initialize device spinlock */
3134 spin_lock_init(&dev->lock);
3135
3136 dev->pdev = pdev;
5f81f4b0 3137 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3138
3139#ifdef OTG_TRANSCEIVER
3140 /* PCI device is already enabled by otg_transceiver driver */
3141 dev->enabled = 1;
3142
3143 /* mem region and register base */
3144 dev->region = 1;
3145 dev->transceiver = otg_get_transceiver();
3146 dev->lotg = otg_to_langwell(dev->transceiver);
3147 base = dev->lotg->regs;
3148#else
3149 pci_set_drvdata(pdev, dev);
3150
3151 /* now all the pci goodies ... */
3152 if (pci_enable_device(pdev) < 0) {
3153 retval = -ENODEV;
3154 goto error;
3155 }
3156 dev->enabled = 1;
3157
3158 /* control register: BAR 0 */
3159 resource = pci_resource_start(pdev, 0);
3160 len = pci_resource_len(pdev, 0);
3161 if (!request_mem_region(resource, len, driver_name)) {
5f81f4b0 3162 dev_err(&dev->pdev->dev, "controller already in use\n");
5be19a9d
XS		 3163 retval = -EBUSY;
3164 goto error;
3165 }
3166 dev->region = 1;
3167
3168 base = ioremap_nocache(resource, len);
3169#endif
3170 if (base == NULL) {
5f81f4b0 3171 dev_err(&dev->pdev->dev, "can't map memory\n");
5be19a9d
XS		 3172 retval = -EFAULT;
3173 goto error;
3174 }
3175
3176 dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
5f81f4b0 3177 dev_vdbg(&dev->pdev->dev, "dev->cap_regs: %p\n", dev->cap_regs);
5be19a9d
XS		 3178 dev->op_regs = (struct langwell_op_regs __iomem *)
3179 (base + OP_REG_OFFSET);
5f81f4b0 3180 dev_vdbg(&dev->pdev->dev, "dev->op_regs: %p\n", dev->op_regs);
5be19a9d
XS		 3181
3182 /* irq setup after old hardware is cleaned up */
3183 if (!pdev->irq) {
5f81f4b0 3184 dev_err(&dev->pdev->dev, "No IRQ. Check PCI setup!\n");
5be19a9d
XS		 3185 retval = -ENODEV;
3186 goto error;
3187 }
3188
912c93d1
J		 3189 dev->has_sram = 1;
3190 dev->got_sram = 0;
3191 dev_vdbg(&dev->pdev->dev, "dev->has_sram: %d\n", dev->has_sram);
3192
5be19a9d 3193#ifndef OTG_TRANSCEIVER
912c93d1
J		 3194 /* enable SRAM caching if detected */
3195 if (dev->has_sram && !dev->got_sram)
3196 sram_init(dev);
3197
5f81f4b0
J		 3198 dev_info(&dev->pdev->dev,
3199 "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
5be19a9d
XS		 3200 pdev->irq, resource, len, base);
3201 /* enables bus-mastering for device dev */
3202 pci_set_master(pdev);
3203
3204 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
3205 driver_name, dev) != 0) {
5f81f4b0
J		 3206 dev_err(&dev->pdev->dev,
3207 "request interrupt %d failed\n", pdev->irq);
5be19a9d
XS		 3208 retval = -EBUSY;
3209 goto error;
3210 }
3211 dev->got_irq = 1;
3212#endif
3213
3214 /* set stopped bit */
3215 dev->stopped = 1;
3216
3217 /* capabilities and endpoint number */
3218 dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
3219 dev->dciversion = readw(&dev->cap_regs->dciversion);
3220 dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
5f81f4b0
J		 3221 dev_vdbg(&dev->pdev->dev, "dev->lpm: %d\n", dev->lpm);
3222 dev_vdbg(&dev->pdev->dev, "dev->dciversion: 0x%04x\n",
3223 dev->dciversion);
3224 dev_vdbg(&dev->pdev->dev, "dccparams: 0x%08x\n",
3225 readl(&dev->cap_regs->dccparams));
3226 dev_vdbg(&dev->pdev->dev, "dev->devcap: %d\n", dev->devcap);
5be19a9d 3227 if (!dev->devcap) {
5f81f4b0 3228 dev_err(&dev->pdev->dev, "can't support device mode\n");
5be19a9d
XS		 3229 retval = -ENODEV;
3230 goto error;
3231 }
3232
3233 /* a pair of endpoints (out/in) for each address */
3234 dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
5f81f4b0 3235 dev_vdbg(&dev->pdev->dev, "dev->ep_max: %d\n", dev->ep_max);
5be19a9d
XS		 3236
3237 /* allocate endpoints memory */
3238 dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
3239 GFP_KERNEL);
3240 if (!dev->ep) {
5f81f4b0 3241 dev_err(&dev->pdev->dev, "allocate endpoints memory failed\n");
5be19a9d
XS		 3242 retval = -ENOMEM;
3243 goto error;
3244 }
3245
3246 /* allocate device dQH memory */
3247 size = dev->ep_max * sizeof(struct langwell_dqh);
b9af9ea4 3248 dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
5be19a9d
XS		 3249 if (size < DQH_ALIGNMENT)
3250 size = DQH_ALIGNMENT;
3251 else if ((size % DQH_ALIGNMENT) != 0) {
3252 size += DQH_ALIGNMENT + 1;
3253 size &= ~(DQH_ALIGNMENT - 1);
3254 }
3255 dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
3256 &dev->ep_dqh_dma, GFP_KERNEL);
3257 if (!dev->ep_dqh) {
5f81f4b0 3258 dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
5be19a9d
XS		 3259 retval = -ENOMEM;
3260 goto error;
3261 }
3262 dev->ep_dqh_size = size;
b9af9ea4 3263 dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
5be19a9d
XS		 3264
3265 /* initialize ep0 status request structure */
3266 dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
3267 if (!dev->status_req) {
5f81f4b0
J		 3268 dev_err(&dev->pdev->dev,
3269 "allocate status_req memory failed\n");
5be19a9d
XS		 3270 retval = -ENOMEM;
3271 goto error;
3272 }
3273 INIT_LIST_HEAD(&dev->status_req->queue);
3274
3275 /* allocate a small amount of memory to get valid address */
3276 dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
3277 dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
3278
3279 dev->resume_state = USB_STATE_NOTATTACHED;
3280 dev->usb_state = USB_STATE_POWERED;
3281 dev->ep0_dir = USB_DIR_OUT;
3211cbc2
J		 3282
3283 /* remote wakeup reset to 0 when the device is reset */
3284 dev->remote_wakeup = 0;
3285 dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
5be19a9d
XS		 3286
3287#ifndef OTG_TRANSCEIVER
3288 /* reset device controller */
3289 langwell_udc_reset(dev);
3290#endif
3291
3292 /* initialize gadget structure */
3293 dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
3294 dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
3295 INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
3296 dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
3297 dev->gadget.is_dualspeed = 1; /* support dual speed */
3298#ifdef OTG_TRANSCEIVER
3299 dev->gadget.is_otg = 1; /* support otg mode */
3300#endif
3301
3302 /* the "gadget" abstracts/virtualizes the controller */
3303 dev_set_name(&dev->gadget.dev, "gadget");
3304 dev->gadget.dev.parent = &pdev->dev;
3305 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3306 dev->gadget.dev.release = gadget_release;
3307 dev->gadget.name = driver_name; /* gadget name */
3308
3309 /* controller endpoints reinit */
3310 eps_reinit(dev);
3311
3312#ifndef OTG_TRANSCEIVER
3313 /* reset ep0 dQH and endptctrl */
3314 ep0_reset(dev);
3315#endif
3316
3317 /* create dTD dma_pool resource */
3318 dev->dtd_pool = dma_pool_create("langwell_dtd",
3319 &dev->pdev->dev,
3320 sizeof(struct langwell_dtd),
3321 DTD_ALIGNMENT,
3322 DMA_BOUNDARY);
3323
3324 if (!dev->dtd_pool) {
3325 retval = -ENOMEM;
3326 goto error;
3327 }
3328
3329 /* done */
5f81f4b0
J		 3330 dev_info(&dev->pdev->dev, "%s\n", driver_desc);
3331 dev_info(&dev->pdev->dev, "irq %d, pci mem %p\n", pdev->irq, base);
3332 dev_info(&dev->pdev->dev, "Driver version: " DRIVER_VERSION "\n");
3333 dev_info(&dev->pdev->dev, "Support (max) %d endpoints\n", dev->ep_max);
3334 dev_info(&dev->pdev->dev, "Device interface version: 0x%04x\n",
3335 dev->dciversion);
3336 dev_info(&dev->pdev->dev, "Controller mode: %s\n",
3337 dev->devcap ? "Device" : "Host");
3338 dev_info(&dev->pdev->dev, "Support USB LPM: %s\n",
3339 dev->lpm ? "Yes" : "No");
3340
3341 dev_vdbg(&dev->pdev->dev,
3342 "After langwell_udc_probe(), print all registers:\n");
5be19a9d 3343 print_all_registers(dev);
5be19a9d
XS		 3344
3345 the_controller = dev;
3346
3347 retval = device_register(&dev->gadget.dev);
3348 if (retval)
3349 goto error;
3350
0f91349b
SAS		 3351 retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
3352 if (retval)
3353 goto error;
3354
5be19a9d
XS		 3355 retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
3356 if (retval)
3357 goto error;
3358
3211cbc2
J		 3359 retval = device_create_file(&pdev->dev, &dev_attr_remote_wakeup);
3360 if (retval)
3361 goto error_attr1;
3362
5f81f4b0 3363 dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3364 return 0;
3365
3211cbc2
J		 3366error_attr1:
3367 device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
5be19a9d
XS		 3368error:
3369 if (dev) {
5f81f4b0 3370 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3371 langwell_udc_remove(pdev);
3372 }
3373
3374 return retval;
3375}
3376
3377
3378/* device controller suspend */
3379static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
3380{
3381 struct langwell_udc *dev = the_controller;
5be19a9d 3382
5f81f4b0 3383 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d 3384
0f91349b 3385 usb_del_gadget_udc(&dev->gadget);
5be19a9d
XS		 3386 /* disable interrupt and set controller to stop state */
3387 langwell_udc_stop(dev);
3388
48e34d0f 3389 /* disable IRQ handler */
5be19a9d
XS		 3390 if (dev->got_irq)
3391 free_irq(pdev->irq, dev);
3392 dev->got_irq = 0;
3393
5be19a9d
XS		 3394 /* save PCI state */
3395 pci_save_state(pdev);
3396
cf7d3c8e
PS		 3397 spin_lock_irq(&dev->lock);
3398 /* stop all usb activities */
3399 stop_activity(dev, dev->driver);
3400 spin_unlock_irq(&dev->lock);
3401
912c93d1
J		 3402 /* free dTD dma_pool and dQH */
3403 if (dev->dtd_pool)
3404 dma_pool_destroy(dev->dtd_pool);
3405
3406 if (dev->ep_dqh)
3407 dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
3408 dev->ep_dqh, dev->ep_dqh_dma);
3409
3410 /* release SRAM caching */
3411 if (dev->has_sram && dev->got_sram)
3412 sram_deinit(dev);
3413
5be19a9d
XS		 3414 /* set device power state */
3415 pci_set_power_state(pdev, PCI_D3hot);
3416
3417 /* enter PHY low power suspend */
513b91b6
J		 3418 if (dev->pdev->device != 0x0829)
3419 langwell_phy_low_power(dev, 1);
5be19a9d 3420
5f81f4b0 3421 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3422 return 0;
3423}
3424
3425
3426/* device controller resume */
3427static int langwell_udc_resume(struct pci_dev *pdev)
3428{
3429 struct langwell_udc *dev = the_controller;
912c93d1 3430 size_t size;
5be19a9d 3431
5f81f4b0 3432 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3433
3434 /* exit PHY low power suspend */
513b91b6
J		 3435 if (dev->pdev->device != 0x0829)
3436 langwell_phy_low_power(dev, 0);
5be19a9d
XS		 3437
3438 /* set device D0 power state */
3439 pci_set_power_state(pdev, PCI_D0);
3440
912c93d1
J		 3441 /* enable SRAM caching if detected */
3442 if (dev->has_sram && !dev->got_sram)
3443 sram_init(dev);
3444
3445 /* allocate device dQH memory */
3446 size = dev->ep_max * sizeof(struct langwell_dqh);
b9af9ea4 3447 dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
912c93d1
J		 3448 if (size < DQH_ALIGNMENT)
3449 size = DQH_ALIGNMENT;
3450 else if ((size % DQH_ALIGNMENT) != 0) {
3451 size += DQH_ALIGNMENT + 1;
3452 size &= ~(DQH_ALIGNMENT - 1);
3453 }
3454 dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
3455 &dev->ep_dqh_dma, GFP_KERNEL);
3456 if (!dev->ep_dqh) {
3457 dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
3458 return -ENOMEM;
3459 }
3460 dev->ep_dqh_size = size;
b9af9ea4 3461 dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
912c93d1
J		 3462
3463 /* create dTD dma_pool resource */
3464 dev->dtd_pool = dma_pool_create("langwell_dtd",
3465 &dev->pdev->dev,
3466 sizeof(struct langwell_dtd),
3467 DTD_ALIGNMENT,
3468 DMA_BOUNDARY);
3469
3470 if (!dev->dtd_pool)
3471 return -ENOMEM;
3472
5be19a9d
XS		 3473 /* restore PCI state */
3474 pci_restore_state(pdev);
3475
3476 /* enable IRQ handler */
5f81f4b0
J		 3477 if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
3478 driver_name, dev) != 0) {
3479 dev_err(&dev->pdev->dev, "request interrupt %d failed\n",
3480 pdev->irq);
3481 return -EBUSY;
5be19a9d
XS		 3482 }
3483 dev->got_irq = 1;
3484
3485 /* reset and start controller to run state */
3486 if (dev->stopped) {
3487 /* reset device controller */
3488 langwell_udc_reset(dev);
3489
3490 /* reset ep0 dQH and endptctrl */
3491 ep0_reset(dev);
3492
3493 /* start device if gadget is loaded */
3494 if (dev->driver)
3495 langwell_udc_start(dev);
3496 }
3497
3498 /* reset USB status */
3499 dev->usb_state = USB_STATE_ATTACHED;
3500 dev->ep0_state = WAIT_FOR_SETUP;
3501 dev->ep0_dir = USB_DIR_OUT;
3502
5f81f4b0 3503 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3504 return 0;
3505}
3506
3507
3508/* pci driver shutdown */
3509static void langwell_udc_shutdown(struct pci_dev *pdev)
3510{
3511 struct langwell_udc *dev = the_controller;
3512 u32 usbmode;
3513
5f81f4b0 3514 dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
5be19a9d
XS		 3515
3516 /* reset controller mode to IDLE */
3517 usbmode = readl(&dev->op_regs->usbmode);
5f81f4b0 3518 dev_dbg(&dev->pdev->dev, "usbmode = 0x%08x\n", usbmode);
5be19a9d
XS		 3519 usbmode &= (~3 | MODE_IDLE);
3520 writel(usbmode, &dev->op_regs->usbmode);
3521
5f81f4b0 3522 dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
5be19a9d
XS		 3523}
3524
3525/*-------------------------------------------------------------------------*/
3526
3527static const struct pci_device_id pci_ids[] = { {
3528 .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
3529 .class_mask = ~0,
3530 .vendor = 0x8086,
3531 .device = 0x0811,
3532 .subvendor = PCI_ANY_ID,
3533 .subdevice = PCI_ANY_ID,
3534}, { /* end: all zeroes */ }
3535};
3536
5be19a9d
XS		 3537MODULE_DEVICE_TABLE(pci, pci_ids);
3538
3539
3540static struct pci_driver langwell_pci_driver = {
3541 .name = (char *) driver_name,
3542 .id_table = pci_ids,
3543
3544 .probe = langwell_udc_probe,
3545 .remove = langwell_udc_remove,
3546
3547 /* device controller suspend/resume */
3548 .suspend = langwell_udc_suspend,
3549 .resume = langwell_udc_resume,
3550
3551 .shutdown = langwell_udc_shutdown,
3552};
3553
3554
5be19a9d
XS		 3555static int __init init(void)
3556{
3557#ifdef OTG_TRANSCEIVER
3558 return langwell_register_peripheral(&langwell_pci_driver);
3559#else
3560 return pci_register_driver(&langwell_pci_driver);
3561#endif
3562}
3563module_init(init);
3564
3565
3566static void __exit cleanup(void)
3567{
3568#ifdef OTG_TRANSCEIVER
3569 return langwell_unregister_peripheral(&langwell_pci_driver);
3570#else
3571 pci_unregister_driver(&langwell_pci_driver);
3572#endif
3573}
3574module_exit(cleanup);
3575
5f81f4b0
J		 3576
3577MODULE_DESCRIPTION(DRIVER_DESC);
3578MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
3579MODULE_VERSION(DRIVER_VERSION);
3580MODULE_LICENSE("GPL");
3581
kernel source for telekom puls (alcatel/mediatek)