[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / imx_udc.h

/*
 *	Copyright (C) 2005 Mike Lee(eemike@gmail.com)
 *
 *	This udc driver is now under testing and code is based on pxa2xx_udc.h
 *	Please use it with your own risk!
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 */

#ifndef __LINUX_USB_GADGET_IMX_H
#define __LINUX_USB_GADGET_IMX_H

#include <linux/types.h>

/* Helper macros */
#define EP_NO(ep)	((ep->bEndpointAddress) & ~USB_DIR_IN) /* IN:1, OUT:0 */
#define EP_DIR(ep)	((ep->bEndpointAddress) & USB_DIR_IN ? 1 : 0)
#define IMX_USB_NB_EP	6

/* Driver structures */
struct imx_request {
	struct usb_request			req;
	struct list_head			queue;
	unsigned int				in_use;
};

enum ep0_state {
	EP0_IDLE,
	EP0_IN_DATA_PHASE,
	EP0_OUT_DATA_PHASE,
	EP0_CONFIG,
	EP0_STALL,
};

struct imx_ep_struct {
	struct usb_ep				ep;
	struct imx_udc_struct			*imx_usb;
	struct list_head			queue;
	unsigned char				stopped;
	unsigned char				fifosize;
	unsigned char				bEndpointAddress;
	unsigned char				bmAttributes;
};

struct imx_udc_struct {
	struct usb_gadget			gadget;
	struct usb_gadget_driver		*driver;
	struct device				*dev;
	struct imx_ep_struct			imx_ep[IMX_USB_NB_EP];
	struct clk				*clk;
	struct timer_list			timer;
	enum ep0_state				ep0state;
	struct resource				*res;
	void __iomem				*base;
	unsigned char				set_config;
	int					cfg,
						intf,
						alt,
						usbd_int[7];
};

/* USB registers */
#define  USB_FRAME		(0x00)	/* USB frame */
#define  USB_SPEC		(0x04)	/* USB Spec */
#define  USB_STAT		(0x08)	/* USB Status */
#define  USB_CTRL		(0x0C)	/* USB Control */
#define  USB_DADR		(0x10)	/* USB Desc RAM addr */
#define  USB_DDAT		(0x14)	/* USB Desc RAM/EP buffer data */
#define  USB_INTR		(0x18)	/* USB interrupt */
#define  USB_MASK		(0x1C)	/* USB Mask */
#define  USB_ENAB		(0x24)	/* USB Enable */
#define  USB_EP_STAT(x)		(0x30 + (x*0x30)) /* USB status/control */
#define  USB_EP_INTR(x)		(0x34 + (x*0x30)) /* USB interrupt */
#define  USB_EP_MASK(x)		(0x38 + (x*0x30)) /* USB mask */
#define  USB_EP_FDAT(x)		(0x3C + (x*0x30)) /* USB FIFO data */
#define  USB_EP_FDAT0(x)	(0x3C + (x*0x30)) /* USB FIFO data */
#define  USB_EP_FDAT1(x)	(0x3D + (x*0x30)) /* USB FIFO data */
#define  USB_EP_FDAT2(x)	(0x3E + (x*0x30)) /* USB FIFO data */
#define  USB_EP_FDAT3(x)	(0x3F + (x*0x30)) /* USB FIFO data */
#define  USB_EP_FSTAT(x)	(0x40 + (x*0x30)) /* USB FIFO status */
#define  USB_EP_FCTRL(x)	(0x44 + (x*0x30)) /* USB FIFO control */
#define  USB_EP_LRFP(x)		(0x48 + (x*0x30)) /* USB last rd f. pointer */
#define  USB_EP_LWFP(x)		(0x4C + (x*0x30)) /* USB last wr f. pointer */
#define  USB_EP_FALRM(x)	(0x50 + (x*0x30)) /* USB FIFO alarm */
#define  USB_EP_FRDP(x)		(0x54 + (x*0x30)) /* USB FIFO read pointer */
#define  USB_EP_FWRP(x)		(0x58 + (x*0x30)) /* USB FIFO write pointer */
/* USB Control Register Bit Fields.*/
#define CTRL_CMDOVER		(1<<6)	/* UDC status */
#define CTRL_CMDERROR		(1<<5)	/* UDC status */
#define CTRL_FE_ENA		(1<<3)	/* Enable Font End logic */
#define CTRL_UDC_RST		(1<<2)	/* UDC reset */
#define CTRL_AFE_ENA		(1<<1)	/* Analog Font end enable */
#define CTRL_RESUME		(1<<0)	/* UDC resume */
/* USB Status Register Bit Fields.*/
#define STAT_RST		(1<<8)
#define STAT_SUSP		(1<<7)
#define STAT_CFG		(3<<5)
#define STAT_INTF		(3<<3)
#define STAT_ALTSET		(7<<0)
/* USB Interrupt Status/Mask Registers Bit fields */
#define INTR_WAKEUP		(1<<31)	/* Wake up Interrupt */
#define INTR_MSOF		(1<<7)	/* Missed Start of Frame */
#define INTR_SOF		(1<<6)	/* Start of Frame */
#define INTR_RESET_STOP		(1<<5)	/* Reset Signaling stop */
#define INTR_RESET_START	(1<<4)	/* Reset Signaling start */
#define INTR_RESUME		(1<<3)	/* Suspend to resume */
#define INTR_SUSPEND		(1<<2)	/* Active to suspend */
#define INTR_FRAME_MATCH	(1<<1)	/* Frame matched */
#define INTR_CFG_CHG		(1<<0)	/* Configuration change occurred */
/* USB Enable Register Bit Fields.*/
#define ENAB_RST		(1<<31)	/* Reset USB modules */
#define ENAB_ENAB		(1<<30)	/* Enable USB modules*/
#define ENAB_SUSPEND		(1<<29)	/* Suspend USB modules */
#define ENAB_ENDIAN		(1<<28)	/* Endian of USB modules */
#define ENAB_PWRMD		(1<<0)	/* Power mode of USB modules */
/* USB Descriptor Ram Address Register bit fields */
#define DADR_CFG		(1<<31)	/* Configuration */
#define DADR_BSY		(1<<30)	/* Busy status */
#define DADR_DADR		(0x1FF)	/* Descriptor Ram Address */
/* USB Descriptor RAM/Endpoint Buffer Data Register bit fields */
#define DDAT_DDAT		(0xFF)	/* Descriptor Endpoint Buffer */
/* USB Endpoint Status Register bit fields */
#define EPSTAT_BCOUNT		(0x7F<<16)	/* Endpoint FIFO byte count */
#define EPSTAT_SIP		(1<<8)	/* Endpoint setup in progress */
#define EPSTAT_DIR		(1<<7)	/* Endpoint transfer direction */
#define EPSTAT_MAX		(3<<5)	/* Endpoint Max packet size */
#define EPSTAT_TYP		(3<<3)	/* Endpoint type */
#define EPSTAT_ZLPS		(1<<2)	/* Send zero length packet */
#define EPSTAT_FLUSH		(1<<1)	/* Endpoint FIFO Flush */
#define EPSTAT_STALL		(1<<0)	/* Force stall */
/* USB Endpoint FIFO Status Register bit fields */
#define FSTAT_FRAME_STAT	(0xF<<24)	/* Frame status bit [0-3] */
#define FSTAT_ERR		(1<<22)	/* FIFO error */
#define FSTAT_UF		(1<<21)	/* FIFO underflow */
#define FSTAT_OF		(1<<20)	/* FIFO overflow */
#define FSTAT_FR		(1<<19)	/* FIFO frame ready */
#define FSTAT_FULL		(1<<18)	/* FIFO full */
#define FSTAT_ALRM		(1<<17)	/* FIFO alarm */
#define FSTAT_EMPTY		(1<<16)	/* FIFO empty */
/* USB Endpoint FIFO Control Register bit fields */
#define FCTRL_WFR		(1<<29)	/* Write frame end */
/* USB Endpoint Interrupt Status Regsiter bit fields */
#define EPINTR_FIFO_FULL	(1<<8)	/* fifo full */
#define EPINTR_FIFO_EMPTY	(1<<7)	/* fifo empty */
#define EPINTR_FIFO_ERROR	(1<<6)	/* fifo error */
#define EPINTR_FIFO_HIGH	(1<<5)	/* fifo high */
#define EPINTR_FIFO_LOW		(1<<4)	/* fifo low */
#define EPINTR_MDEVREQ		(1<<3)	/* multi Device request */
#define EPINTR_EOT		(1<<2)	/* fifo end of transfer */
#define EPINTR_DEVREQ		(1<<1)	/* Device request */
#define EPINTR_EOF		(1<<0)	/* fifo end of frame */

/* Debug macros */
#ifdef DEBUG

/* #define DEBUG_REQ */
/* #define DEBUG_TRX */
/* #define DEBUG_INIT */
/* #define DEBUG_EP0 */
/* #define DEBUG_EPX */
/* #define DEBUG_IRQ */
/* #define DEBUG_EPIRQ */
/* #define DEBUG_DUMP */
/* #define DEBUG_ERR */

#ifdef DEBUG_REQ
	#define D_REQ(dev, args...)	dev_dbg(dev, ## args)
#else
	#define D_REQ(dev, args...)	do {} while (0)
#endif /* DEBUG_REQ */

#ifdef DEBUG_TRX
	#define D_TRX(dev, args...)	dev_dbg(dev, ## args)
#else
	#define D_TRX(dev, args...)	do {} while (0)
#endif /* DEBUG_TRX */

#ifdef DEBUG_INIT
	#define D_INI(dev, args...)	dev_dbg(dev, ## args)
#else
	#define D_INI(dev, args...)	do {} while (0)
#endif /* DEBUG_INIT */

#ifdef DEBUG_EP0
	static const char *state_name[] = {
		"EP0_IDLE",
		"EP0_IN_DATA_PHASE",
		"EP0_OUT_DATA_PHASE",
		"EP0_CONFIG",
		"EP0_STALL"
	};
	#define D_EP0(dev, args...)	dev_dbg(dev, ## args)
#else
	#define D_EP0(dev, args...)	do {} while (0)
#endif /* DEBUG_EP0 */

#ifdef DEBUG_EPX
	#define D_EPX(dev, args...)	dev_dbg(dev, ## args)
#else
	#define D_EPX(dev, args...)	do {} while (0)
#endif /* DEBUG_EP0 */

#ifdef DEBUG_IRQ
	static void dump_intr(const char *label, int irqreg, struct device *dev)
	{
		dev_dbg(dev, "<%s> USB_INTR=[%s%s%s%s%s%s%s%s%s]\n", label,
			(irqreg & INTR_WAKEUP) ? " wake" : "",
			(irqreg & INTR_MSOF) ? " msof" : "",
			(irqreg & INTR_SOF) ? " sof" : "",
			(irqreg & INTR_RESUME) ? " resume" : "",
			(irqreg & INTR_SUSPEND) ? " suspend" : "",
			(irqreg & INTR_RESET_STOP) ? " noreset" : "",
			(irqreg & INTR_RESET_START) ? " reset" : "",
			(irqreg & INTR_FRAME_MATCH) ? " fmatch" : "",
			(irqreg & INTR_CFG_CHG) ? " config" : "");
	}
#else
	#define dump_intr(x, y, z)		do {} while (0)
#endif /* DEBUG_IRQ */

#ifdef DEBUG_EPIRQ
	static void dump_ep_intr(const char *label, int nr, int irqreg,
							struct device *dev)
	{
		dev_dbg(dev, "<%s> EP%d_INTR=[%s%s%s%s%s%s%s%s%s]\n", label, nr,
			(irqreg & EPINTR_FIFO_FULL) ? " full" : "",
			(irqreg & EPINTR_FIFO_EMPTY) ? " fempty" : "",
			(irqreg & EPINTR_FIFO_ERROR) ? " ferr" : "",
			(irqreg & EPINTR_FIFO_HIGH) ? " fhigh" : "",
			(irqreg & EPINTR_FIFO_LOW) ? " flow" : "",
			(irqreg & EPINTR_MDEVREQ) ? " mreq" : "",
			(irqreg & EPINTR_EOF) ? " eof" : "",
			(irqreg & EPINTR_DEVREQ) ? " devreq" : "",
			(irqreg & EPINTR_EOT) ? " eot" : "");
	}
#else
	#define dump_ep_intr(x, y, z, i)	do {} while (0)
#endif /* DEBUG_IRQ */

#ifdef DEBUG_DUMP
	static void dump_usb_stat(const char *label,
						struct imx_udc_struct *imx_usb)
	{
		int temp = __raw_readl(imx_usb->base + USB_STAT);

		dev_dbg(imx_usb->dev,
			"<%s> USB_STAT=[%s%s CFG=%d, INTF=%d, ALTR=%d]\n", label,
			(temp & STAT_RST) ? " reset" : "",
			(temp & STAT_SUSP) ? " suspend" : "",
			(temp & STAT_CFG) >> 5,
			(temp & STAT_INTF) >> 3,
			(temp & STAT_ALTSET));
	}

	static void dump_ep_stat(const char *label,
						struct imx_ep_struct *imx_ep)
	{
		int temp = __raw_readl(imx_ep->imx_usb->base
						+ USB_EP_INTR(EP_NO(imx_ep)));

		dev_dbg(imx_ep->imx_usb->dev,
			"<%s> EP%d_INTR=[%s%s%s%s%s%s%s%s%s]\n",
			label, EP_NO(imx_ep),
			(temp & EPINTR_FIFO_FULL) ? " full" : "",
			(temp & EPINTR_FIFO_EMPTY) ? " fempty" : "",
			(temp & EPINTR_FIFO_ERROR) ? " ferr" : "",
			(temp & EPINTR_FIFO_HIGH) ? " fhigh" : "",
			(temp & EPINTR_FIFO_LOW) ? " flow" : "",
			(temp & EPINTR_MDEVREQ) ? " mreq" : "",
			(temp & EPINTR_EOF) ? " eof" : "",
			(temp & EPINTR_DEVREQ) ? " devreq" : "",
			(temp & EPINTR_EOT) ? " eot" : "");

		temp = __raw_readl(imx_ep->imx_usb->base
						+ USB_EP_STAT(EP_NO(imx_ep)));

		dev_dbg(imx_ep->imx_usb->dev,
			"<%s> EP%d_STAT=[%s%s bcount=%d]\n",
			label, EP_NO(imx_ep),
			(temp & EPSTAT_SIP) ? " sip" : "",
			(temp & EPSTAT_STALL) ? " stall" : "",
			(temp & EPSTAT_BCOUNT) >> 16);

		temp = __raw_readl(imx_ep->imx_usb->base
						+ USB_EP_FSTAT(EP_NO(imx_ep)));

		dev_dbg(imx_ep->imx_usb->dev,
			"<%s> EP%d_FSTAT=[%s%s%s%s%s%s%s]\n",
			label, EP_NO(imx_ep),
			(temp & FSTAT_ERR) ? " ferr" : "",
			(temp & FSTAT_UF) ? " funder" : "",
			(temp & FSTAT_OF) ? " fover" : "",
			(temp & FSTAT_FR) ? " fready" : "",
			(temp & FSTAT_FULL) ? " ffull" : "",
			(temp & FSTAT_ALRM) ? " falarm" : "",
			(temp & FSTAT_EMPTY) ? " fempty" : "");
	}

	static void dump_req(const char *label, struct imx_ep_struct *imx_ep,
							struct usb_request *req)
	{
		int i;

		if (!req || !req->buf) {
			dev_dbg(imx_ep->imx_usb->dev,
					"<%s> req or req buf is free\n", label);
			return;
		}

		if ((!EP_NO(imx_ep) && imx_ep->imx_usb->ep0state
			== EP0_IN_DATA_PHASE)
			|| (EP_NO(imx_ep) && EP_DIR(imx_ep))) {

			dev_dbg(imx_ep->imx_usb->dev,
						"<%s> request dump <", label);
			for (i = 0; i < req->length; i++)
				printk("%02x-", *((u8 *)req->buf + i));
			printk(">\n");
		}
	}

#else
	#define dump_ep_stat(x, y)		do {} while (0)
	#define dump_usb_stat(x, y)		do {} while (0)
	#define dump_req(x, y, z)		do {} while (0)
#endif /* DEBUG_DUMP */

#ifdef DEBUG_ERR
	#define D_ERR(dev, args...)	dev_dbg(dev, ## args)
#else
	#define D_ERR(dev, args...)	do {} while (0)
#endif

#else
	#define D_REQ(dev, args...)		do {} while (0)
	#define D_TRX(dev, args...)		do {} while (0)
	#define D_INI(dev, args...)		do {} while (0)
	#define D_EP0(dev, args...)		do {} while (0)
	#define D_EPX(dev, args...)		do {} while (0)
	#define dump_ep_intr(x, y, z, i)	do {} while (0)
	#define dump_intr(x, y, z)		do {} while (0)
	#define dump_ep_stat(x, y)		do {} while (0)
	#define dump_usb_stat(x, y)		do {} while (0)
	#define dump_req(x, y, z)		do {} while (0)
	#define D_ERR(dev, args...)		do {} while (0)
#endif /* DEBUG */

#endif /* __LINUX_USB_GADGET_IMX_H */
Commit	Line	Data
2a4f136f DA	1	/*
	2	* Copyright (C) 2005 Mike Lee(eemike@gmail.com)
	3	*
	4	* This udc driver is now under testing and code is based on pxa2xx_udc.h
	5	* Please use it with your own risk!
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
2a4f136f DA	11	*/
	12
	13	#ifndef __LINUX_USB_GADGET_IMX_H
	14	#define __LINUX_USB_GADGET_IMX_H
	15
	16	#include <linux/types.h>
	17
	18	/* Helper macros */
	19	#define EP_NO(ep) ((ep->bEndpointAddress) & ~USB_DIR_IN) /* IN:1, OUT:0 */
	20	#define EP_DIR(ep) ((ep->bEndpointAddress) & USB_DIR_IN ? 1 : 0)
2a4f136f DA	21	#define IMX_USB_NB_EP 6
	22
	23	/* Driver structures */
	24	struct imx_request {
	25	struct usb_request req;
	26	struct list_head queue;
	27	unsigned int in_use;
	28	};
	29
	30	enum ep0_state {
	31	EP0_IDLE,
	32	EP0_IN_DATA_PHASE,
	33	EP0_OUT_DATA_PHASE,
	34	EP0_CONFIG,
	35	EP0_STALL,
	36	};
	37
	38	struct imx_ep_struct {
	39	struct usb_ep ep;
	40	struct imx_udc_struct *imx_usb;
	41	struct list_head queue;
	42	unsigned char stopped;
	43	unsigned char fifosize;
	44	unsigned char bEndpointAddress;
	45	unsigned char bmAttributes;
	46	};
	47
	48	struct imx_udc_struct {
	49	struct usb_gadget gadget;
	50	struct usb_gadget_driver *driver;
	51	struct device *dev;
	52	struct imx_ep_struct imx_ep[IMX_USB_NB_EP];
	53	struct clk *clk;
b633d28e	54	struct timer_list timer;
2a4f136f DA	55	enum ep0_state ep0state;
	56	struct resource *res;
	57	void __iomem *base;
	58	unsigned char set_config;
	59	int cfg,
	60	intf,
	61	alt,
	62	usbd_int[7];
	63	};
	64
	65	/* USB registers */
	66	#define USB_FRAME (0x00) /* USB frame */
	67	#define USB_SPEC (0x04) /* USB Spec */
	68	#define USB_STAT (0x08) /* USB Status */
	69	#define USB_CTRL (0x0C) /* USB Control */
	70	#define USB_DADR (0x10) /* USB Desc RAM addr */
	71	#define USB_DDAT (0x14) /* USB Desc RAM/EP buffer data */
	72	#define USB_INTR (0x18) /* USB interrupt */
	73	#define USB_MASK (0x1C) /* USB Mask */
	74	#define USB_ENAB (0x24) /* USB Enable */
	75	#define USB_EP_STAT(x) (0x30 + (x0x30)) / USB status/control */
	76	#define USB_EP_INTR(x) (0x34 + (x0x30)) / USB interrupt */
	77	#define USB_EP_MASK(x) (0x38 + (x0x30)) / USB mask */
	78	#define USB_EP_FDAT(x) (0x3C + (x0x30)) / USB FIFO data */
	79	#define USB_EP_FDAT0(x) (0x3C + (x0x30)) / USB FIFO data */
	80	#define USB_EP_FDAT1(x) (0x3D + (x0x30)) / USB FIFO data */
	81	#define USB_EP_FDAT2(x) (0x3E + (x0x30)) / USB FIFO data */
	82	#define USB_EP_FDAT3(x) (0x3F + (x0x30)) / USB FIFO data */
	83	#define USB_EP_FSTAT(x) (0x40 + (x0x30)) / USB FIFO status */
	84	#define USB_EP_FCTRL(x) (0x44 + (x0x30)) / USB FIFO control */
593bef6c DA	85	#define USB_EP_LRFP(x) (0x48 + (x0x30)) / USB last rd f. pointer */
593bef6c DA	86	#define USB_EP_LWFP(x) (0x4C + (x0x30)) / USB last wr f. pointer */
2a4f136f DA	87	#define USB_EP_FALRM(x) (0x50 + (x0x30)) / USB FIFO alarm */
	88	#define USB_EP_FRDP(x) (0x54 + (x0x30)) / USB FIFO read pointer */
	89	#define USB_EP_FWRP(x) (0x58 + (x0x30)) / USB FIFO write pointer */
	90	/* USB Control Register Bit Fields.*/
	91	#define CTRL_CMDOVER (1<<6) /* UDC status */
	92	#define CTRL_CMDERROR (1<<5) /* UDC status */
	93	#define CTRL_FE_ENA (1<<3) /* Enable Font End logic */
	94	#define CTRL_UDC_RST (1<<2) /* UDC reset */
	95	#define CTRL_AFE_ENA (1<<1) /* Analog Font end enable */
	96	#define CTRL_RESUME (1<<0) /* UDC resume */
	97	/* USB Status Register Bit Fields.*/
	98	#define STAT_RST (1<<8)
	99	#define STAT_SUSP (1<<7)
	100	#define STAT_CFG (3<<5)
	101	#define STAT_INTF (3<<3)
	102	#define STAT_ALTSET (7<<0)
	103	/* USB Interrupt Status/Mask Registers Bit fields */
	104	#define INTR_WAKEUP (1<<31) /* Wake up Interrupt */
	105	#define INTR_MSOF (1<<7) /* Missed Start of Frame */
	106	#define INTR_SOF (1<<6) /* Start of Frame */
	107	#define INTR_RESET_STOP (1<<5) /* Reset Signaling stop */
	108	#define INTR_RESET_START (1<<4) /* Reset Signaling start */
	109	#define INTR_RESUME (1<<3) /* Suspend to resume */
	110	#define INTR_SUSPEND (1<<2) /* Active to suspend */
	111	#define INTR_FRAME_MATCH (1<<1) /* Frame matched */
	112	#define INTR_CFG_CHG (1<<0) /* Configuration change occurred */
	113	/* USB Enable Register Bit Fields.*/
	114	#define ENAB_RST (1<<31) /* Reset USB modules */
	115	#define ENAB_ENAB (1<<30) /* Enable USB modules*/
	116	#define ENAB_SUSPEND (1<<29) /* Suspend USB modules */
	117	#define ENAB_ENDIAN (1<<28) /* Endian of USB modules */
	118	#define ENAB_PWRMD (1<<0) /* Power mode of USB modules */
	119	/* USB Descriptor Ram Address Register bit fields */
	120	#define DADR_CFG (1<<31) /* Configuration */
	121	#define DADR_BSY (1<<30) /* Busy status */
	122	#define DADR_DADR (0x1FF) /* Descriptor Ram Address */
	123	/* USB Descriptor RAM/Endpoint Buffer Data Register bit fields */
	124	#define DDAT_DDAT (0xFF) /* Descriptor Endpoint Buffer */
	125	/* USB Endpoint Status Register bit fields */
	126	#define EPSTAT_BCOUNT (0x7F<<16) /* Endpoint FIFO byte count */
	127	#define EPSTAT_SIP (1<<8) /* Endpoint setup in progress */
	128	#define EPSTAT_DIR (1<<7) /* Endpoint transfer direction */
	129	#define EPSTAT_MAX (3<<5) /* Endpoint Max packet size */
	130	#define EPSTAT_TYP (3<<3) /* Endpoint type */
	131	#define EPSTAT_ZLPS (1<<2) /* Send zero length packet */
	132	#define EPSTAT_FLUSH (1<<1) /* Endpoint FIFO Flush */
	133	#define EPSTAT_STALL (1<<0) /* Force stall */
	134	/* USB Endpoint FIFO Status Register bit fields */
	135	#define FSTAT_FRAME_STAT (0xF<<24) /* Frame status bit [0-3] */
	136	#define FSTAT_ERR (1<<22) /* FIFO error */
	137	#define FSTAT_UF (1<<21) /* FIFO underflow */
	138	#define FSTAT_OF (1<<20) /* FIFO overflow */
	139	#define FSTAT_FR (1<<19) /* FIFO frame ready */
	140	#define FSTAT_FULL (1<<18) /* FIFO full */
	141	#define FSTAT_ALRM (1<<17) /* FIFO alarm */
	142	#define FSTAT_EMPTY (1<<16) /* FIFO empty */
	143	/* USB Endpoint FIFO Control Register bit fields */
	144	#define FCTRL_WFR (1<<29) /* Write frame end */
	145	/* USB Endpoint Interrupt Status Regsiter bit fields */
	146	#define EPINTR_FIFO_FULL (1<<8) /* fifo full */
	147	#define EPINTR_FIFO_EMPTY (1<<7) /* fifo empty */
	148	#define EPINTR_FIFO_ERROR (1<<6) /* fifo error */
	149	#define EPINTR_FIFO_HIGH (1<<5) /* fifo high */
	150	#define EPINTR_FIFO_LOW (1<<4) /* fifo low */
151	#define EPINTR_MDEVREQ (1<<3) /* multi Device request */
152	#define EPINTR_EOT (1<<2) /* fifo end of transfer */
153	#define EPINTR_DEVREQ (1<<1) /* Device request */
154	#define EPINTR_EOF (1<<0) /* fifo end of frame */
155
156	/* Debug macros */
157	#ifdef DEBUG
158
159	/* #define DEBUG_REQ */
160	/* #define DEBUG_TRX */
161	/* #define DEBUG_INIT */
162	/* #define DEBUG_EP0 */
163	/* #define DEBUG_EPX */
164	/* #define DEBUG_IRQ */
165	/* #define DEBUG_EPIRQ */
166	/* #define DEBUG_DUMP */
8f182e5d	167	/* #define DEBUG_ERR */
2a4f136f DA	168
	169	#ifdef DEBUG_REQ
	170	#define D_REQ(dev, args...) dev_dbg(dev, ## args)
	171	#else
	172	#define D_REQ(dev, args...) do {} while (0)
	173	#endif /* DEBUG_REQ */
	174
	175	#ifdef DEBUG_TRX
	176	#define D_TRX(dev, args...) dev_dbg(dev, ## args)
	177	#else
	178	#define D_TRX(dev, args...) do {} while (0)
	179	#endif /* DEBUG_TRX */
	180
	181	#ifdef DEBUG_INIT
	182	#define D_INI(dev, args...) dev_dbg(dev, ## args)
	183	#else
	184	#define D_INI(dev, args...) do {} while (0)
	185	#endif /* DEBUG_INIT */
	186
	187	#ifdef DEBUG_EP0
	188	static const char *state_name[] = {
	189	"EP0_IDLE",
	190	"EP0_IN_DATA_PHASE",
	191	"EP0_OUT_DATA_PHASE",
	192	"EP0_CONFIG",
	193	"EP0_STALL"
	194	};
	195	#define D_EP0(dev, args...) dev_dbg(dev, ## args)
	196	#else
	197	#define D_EP0(dev, args...) do {} while (0)
	198	#endif /* DEBUG_EP0 */
	199
	200	#ifdef DEBUG_EPX
	201	#define D_EPX(dev, args...) dev_dbg(dev, ## args)
	202	#else
	203	#define D_EPX(dev, args...) do {} while (0)
	204	#endif /* DEBUG_EP0 */
	205
	206	#ifdef DEBUG_IRQ
	207	static void dump_intr(const char label, int irqreg, struct device dev)
	208	{
	209	dev_dbg(dev, "<%s> USB_INTR=[%s%s%s%s%s%s%s%s%s]\n", label,
	210	(irqreg & INTR_WAKEUP) ? " wake" : "",
	211	(irqreg & INTR_MSOF) ? " msof" : "",
	212	(irqreg & INTR_SOF) ? " sof" : "",
	213	(irqreg & INTR_RESUME) ? " resume" : "",
	214	(irqreg & INTR_SUSPEND) ? " suspend" : "",
	215	(irqreg & INTR_RESET_STOP) ? " noreset" : "",
	216	(irqreg & INTR_RESET_START) ? " reset" : "",
	217	(irqreg & INTR_FRAME_MATCH) ? " fmatch" : "",
	218	(irqreg & INTR_CFG_CHG) ? " config" : "");
	219	}
	220	#else
	221	#define dump_intr(x, y, z) do {} while (0)
	222	#endif /* DEBUG_IRQ */
	223
	224	#ifdef DEBUG_EPIRQ
593bef6c DA	225	static void dump_ep_intr(const char *label, int nr, int irqreg,
593bef6c DA	226	struct device *dev)
2a4f136f DA	227	{
	228	dev_dbg(dev, "<%s> EP%d_INTR=[%s%s%s%s%s%s%s%s%s]\n", label, nr,
	229	(irqreg & EPINTR_FIFO_FULL) ? " full" : "",
	230	(irqreg & EPINTR_FIFO_EMPTY) ? " fempty" : "",
	231	(irqreg & EPINTR_FIFO_ERROR) ? " ferr" : "",
	232	(irqreg & EPINTR_FIFO_HIGH) ? " fhigh" : "",
	233	(irqreg & EPINTR_FIFO_LOW) ? " flow" : "",
	234	(irqreg & EPINTR_MDEVREQ) ? " mreq" : "",
	235	(irqreg & EPINTR_EOF) ? " eof" : "",
	236	(irqreg & EPINTR_DEVREQ) ? " devreq" : "",
	237	(irqreg & EPINTR_EOT) ? " eot" : "");
	238	}
	239	#else
	240	#define dump_ep_intr(x, y, z, i) do {} while (0)
	241	#endif /* DEBUG_IRQ */
	242
	243	#ifdef DEBUG_DUMP
593bef6c DA	244	static void dump_usb_stat(const char *label,
593bef6c DA	245	struct imx_udc_struct *imx_usb)
2a4f136f DA	246	{
	247	int temp = __raw_readl(imx_usb->base + USB_STAT);
	248
	249	dev_dbg(imx_usb->dev,
	250	"<%s> USB_STAT=[%s%s CFG=%d, INTF=%d, ALTR=%d]\n", label,
	251	(temp & STAT_RST) ? " reset" : "",
	252	(temp & STAT_SUSP) ? " suspend" : "",
	253	(temp & STAT_CFG) >> 5,
	254	(temp & STAT_INTF) >> 3,
	255	(temp & STAT_ALTSET));
	256	}
	257
593bef6c DA	258	static void dump_ep_stat(const char *label,
593bef6c DA	259	struct imx_ep_struct *imx_ep)
2a4f136f	260	{
593bef6c DA	261	int temp = __raw_readl(imx_ep->imx_usb->base
593bef6c DA	262	+ USB_EP_INTR(EP_NO(imx_ep)));
2a4f136f DA	263
2a4f136f DA	264	dev_dbg(imx_ep->imx_usb->dev,
593bef6c DA	265	"<%s> EP%d_INTR=[%s%s%s%s%s%s%s%s%s]\n",
593bef6c DA	266	label, EP_NO(imx_ep),
2a4f136f DA	267	(temp & EPINTR_FIFO_FULL) ? " full" : "",
	268	(temp & EPINTR_FIFO_EMPTY) ? " fempty" : "",
	269	(temp & EPINTR_FIFO_ERROR) ? " ferr" : "",
	270	(temp & EPINTR_FIFO_HIGH) ? " fhigh" : "",
	271	(temp & EPINTR_FIFO_LOW) ? " flow" : "",
	272	(temp & EPINTR_MDEVREQ) ? " mreq" : "",
	273	(temp & EPINTR_EOF) ? " eof" : "",
	274	(temp & EPINTR_DEVREQ) ? " devreq" : "",
	275	(temp & EPINTR_EOT) ? " eot" : "");
	276
593bef6c DA	277	temp = __raw_readl(imx_ep->imx_usb->base
593bef6c DA	278	+ USB_EP_STAT(EP_NO(imx_ep)));
2a4f136f DA	279
2a4f136f DA	280	dev_dbg(imx_ep->imx_usb->dev,
593bef6c DA	281	"<%s> EP%d_STAT=[%s%s bcount=%d]\n",
593bef6c DA	282	label, EP_NO(imx_ep),
2a4f136f DA	283	(temp & EPSTAT_SIP) ? " sip" : "",
	284	(temp & EPSTAT_STALL) ? " stall" : "",
	285	(temp & EPSTAT_BCOUNT) >> 16);
	286
593bef6c DA	287	temp = __raw_readl(imx_ep->imx_usb->base
593bef6c DA	288	+ USB_EP_FSTAT(EP_NO(imx_ep)));
2a4f136f DA	289
2a4f136f DA	290	dev_dbg(imx_ep->imx_usb->dev,
593bef6c DA	291	"<%s> EP%d_FSTAT=[%s%s%s%s%s%s%s]\n",
593bef6c DA	292	label, EP_NO(imx_ep),
2a4f136f DA	293	(temp & FSTAT_ERR) ? " ferr" : "",
	294	(temp & FSTAT_UF) ? " funder" : "",
	295	(temp & FSTAT_OF) ? " fover" : "",
	296	(temp & FSTAT_FR) ? " fready" : "",
	297	(temp & FSTAT_FULL) ? " ffull" : "",
	298	(temp & FSTAT_ALRM) ? " falarm" : "",
	299	(temp & FSTAT_EMPTY) ? " fempty" : "");
	300	}
	301
593bef6c DA	302	static void dump_req(const char label, struct imx_ep_struct imx_ep,
593bef6c DA	303	struct usb_request *req)
2a4f136f DA	304	{
	305	int i;
	306
	307	if (!req \|\| !req->buf) {
593bef6c DA	308	dev_dbg(imx_ep->imx_usb->dev,
593bef6c DA	309	"<%s> req or req buf is free\n", label);
2a4f136f DA	310	return;
	311	}
	312
593bef6c DA	313	if ((!EP_NO(imx_ep) && imx_ep->imx_usb->ep0state
593bef6c DA	314	== EP0_IN_DATA_PHASE)
2a4f136f DA	315	\|\| (EP_NO(imx_ep) && EP_DIR(imx_ep))) {
2a4f136f DA	316
593bef6c DA	317	dev_dbg(imx_ep->imx_usb->dev,
593bef6c DA	318	"<%s> request dump <", label);
2a4f136f DA	319	for (i = 0; i < req->length; i++)
	320	printk("%02x-", ((u8 )req->buf + i));
	321	printk(">\n");
	322	}
	323	}
	324
	325	#else
	326	#define dump_ep_stat(x, y) do {} while (0)
	327	#define dump_usb_stat(x, y) do {} while (0)
	328	#define dump_req(x, y, z) do {} while (0)
	329	#endif /* DEBUG_DUMP */
	330
	331	#ifdef DEBUG_ERR
	332	#define D_ERR(dev, args...) dev_dbg(dev, ## args)
	333	#else
	334	#define D_ERR(dev, args...) do {} while (0)
	335	#endif
	336
	337	#else
	338	#define D_REQ(dev, args...) do {} while (0)
	339	#define D_TRX(dev, args...) do {} while (0)
	340	#define D_INI(dev, args...) do {} while (0)
	341	#define D_EP0(dev, args...) do {} while (0)
	342	#define D_EPX(dev, args...) do {} while (0)
	343	#define dump_ep_intr(x, y, z, i) do {} while (0)
	344	#define dump_intr(x, y, z) do {} while (0)
	345	#define dump_ep_stat(x, y) do {} while (0)
	346	#define dump_usb_stat(x, y) do {} while (0)
	347	#define dump_req(x, y, z) do {} while (0)
	348	#define D_ERR(dev, args...) do {} while (0)
	349	#endif /* DEBUG */
	350
	351	#endif /* __LINUX_USB_GADGET_IMX_H */