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USB: fsl_usb2_udc: replace deprecated irq flag
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / fsl_usb2_udc.h
CommitLineData
b504882d
LY		 1/*
2 * Freescale USB device/endpoint management registers
3 */
4#ifndef __FSL_USB2_UDC_H
5#define __FSL_USB2_UDC_H
6
7/* ### define USB registers here
8 */
9#define USB_MAX_CTRL_PAYLOAD 64
10#define USB_DR_SYS_OFFSET 0x400
11
12 /* USB DR device mode registers (Little Endian) */
13struct usb_dr_device {
14 /* Capability register */
15 u8 res1[256];
16 u16 caplength; /* Capability Register Length */
17 u16 hciversion; /* Host Controller Interface Version */
18 u32 hcsparams; /* Host Controller Structual Parameters */
19 u32 hccparams; /* Host Controller Capability Parameters */
20 u8 res2[20];
21 u32 dciversion; /* Device Controller Interface Version */
22 u32 dccparams; /* Device Controller Capability Parameters */
23 u8 res3[24];
24 /* Operation register */
25 u32 usbcmd; /* USB Command Register */
26 u32 usbsts; /* USB Status Register */
27 u32 usbintr; /* USB Interrupt Enable Register */
28 u32 frindex; /* Frame Index Register */
29 u8 res4[4];
30 u32 deviceaddr; /* Device Address */
31 u32 endpointlistaddr; /* Endpoint List Address Register */
32 u8 res5[4];
33 u32 burstsize; /* Master Interface Data Burst Size Register */
34 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
35 u8 res6[24];
36 u32 configflag; /* Configure Flag Register */
37 u32 portsc1; /* Port 1 Status and Control Register */
38 u8 res7[28];
39 u32 otgsc; /* On-The-Go Status and Control */
40 u32 usbmode; /* USB Mode Register */
41 u32 endptsetupstat; /* Endpoint Setup Status Register */
42 u32 endpointprime; /* Endpoint Initialization Register */
43 u32 endptflush; /* Endpoint Flush Register */
44 u32 endptstatus; /* Endpoint Status Register */
45 u32 endptcomplete; /* Endpoint Complete Register */
46 u32 endptctrl[6]; /* Endpoint Control Registers */
47};
48
49 /* USB DR host mode registers (Little Endian) */
50struct usb_dr_host {
51 /* Capability register */
52 u8 res1[256];
53 u16 caplength; /* Capability Register Length */
54 u16 hciversion; /* Host Controller Interface Version */
55 u32 hcsparams; /* Host Controller Structual Parameters */
56 u32 hccparams; /* Host Controller Capability Parameters */
57 u8 res2[20];
58 u32 dciversion; /* Device Controller Interface Version */
59 u32 dccparams; /* Device Controller Capability Parameters */
60 u8 res3[24];
61 /* Operation register */
62 u32 usbcmd; /* USB Command Register */
63 u32 usbsts; /* USB Status Register */
64 u32 usbintr; /* USB Interrupt Enable Register */
65 u32 frindex; /* Frame Index Register */
66 u8 res4[4];
67 u32 periodiclistbase; /* Periodic Frame List Base Address Register */
68 u32 asynclistaddr; /* Current Asynchronous List Address Register */
69 u8 res5[4];
70 u32 burstsize; /* Master Interface Data Burst Size Register */
71 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
72 u8 res6[24];
73 u32 configflag; /* Configure Flag Register */
74 u32 portsc1; /* Port 1 Status and Control Register */
75 u8 res7[28];
76 u32 otgsc; /* On-The-Go Status and Control */
77 u32 usbmode; /* USB Mode Register */
78 u32 endptsetupstat; /* Endpoint Setup Status Register */
79 u32 endpointprime; /* Endpoint Initialization Register */
80 u32 endptflush; /* Endpoint Flush Register */
81 u32 endptstatus; /* Endpoint Status Register */
82 u32 endptcomplete; /* Endpoint Complete Register */
83 u32 endptctrl[6]; /* Endpoint Control Registers */
84};
85
86 /* non-EHCI USB system interface registers (Big Endian) */
87struct usb_sys_interface {
88 u32 snoop1;
89 u32 snoop2;
90 u32 age_cnt_thresh; /* Age Count Threshold Register */
91 u32 pri_ctrl; /* Priority Control Register */
92 u32 si_ctrl; /* System Interface Control Register */
93 u8 res[236];
94 u32 control; /* General Purpose Control Register */
95};
96
97/* ep0 transfer state */
98#define WAIT_FOR_SETUP 0
99#define DATA_STATE_XMIT 1
100#define DATA_STATE_NEED_ZLP 2
101#define WAIT_FOR_OUT_STATUS 3
102#define DATA_STATE_RECV 4
103
104/* Frame Index Register Bit Masks */
105#define USB_FRINDEX_MASKS 0x3fff
106/* USB CMD Register Bit Masks */
107#define USB_CMD_RUN_STOP 0x00000001
108#define USB_CMD_CTRL_RESET 0x00000002
109#define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010
110#define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020
111#define USB_CMD_INT_AA_DOORBELL 0x00000040
112#define USB_CMD_ASP 0x00000300
113#define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800
114#define USB_CMD_SUTW 0x00002000
115#define USB_CMD_ATDTW 0x00004000
116#define USB_CMD_ITC 0x00FF0000
117
118/* bit 15,3,2 are frame list size */
119#define USB_CMD_FRAME_SIZE_1024 0x00000000
120#define USB_CMD_FRAME_SIZE_512 0x00000004
121#define USB_CMD_FRAME_SIZE_256 0x00000008
122#define USB_CMD_FRAME_SIZE_128 0x0000000C
123#define USB_CMD_FRAME_SIZE_64 0x00008000
124#define USB_CMD_FRAME_SIZE_32 0x00008004
125#define USB_CMD_FRAME_SIZE_16 0x00008008
126#define USB_CMD_FRAME_SIZE_8 0x0000800C
127
128/* bit 9-8 are async schedule park mode count */
129#define USB_CMD_ASP_00 0x00000000
130#define USB_CMD_ASP_01 0x00000100
131#define USB_CMD_ASP_10 0x00000200
132#define USB_CMD_ASP_11 0x00000300
133#define USB_CMD_ASP_BIT_POS 8
134
135/* bit 23-16 are interrupt threshold control */
136#define USB_CMD_ITC_NO_THRESHOLD 0x00000000
137#define USB_CMD_ITC_1_MICRO_FRM 0x00010000
138#define USB_CMD_ITC_2_MICRO_FRM 0x00020000
139#define USB_CMD_ITC_4_MICRO_FRM 0x00040000
140#define USB_CMD_ITC_8_MICRO_FRM 0x00080000
141#define USB_CMD_ITC_16_MICRO_FRM 0x00100000
142#define USB_CMD_ITC_32_MICRO_FRM 0x00200000
143#define USB_CMD_ITC_64_MICRO_FRM 0x00400000
144#define USB_CMD_ITC_BIT_POS 16
145
146/* USB STS Register Bit Masks */
147#define USB_STS_INT 0x00000001
148#define USB_STS_ERR 0x00000002
149#define USB_STS_PORT_CHANGE 0x00000004
150#define USB_STS_FRM_LST_ROLL 0x00000008
151#define USB_STS_SYS_ERR 0x00000010
152#define USB_STS_IAA 0x00000020
153#define USB_STS_RESET 0x00000040
154#define USB_STS_SOF 0x00000080
155#define USB_STS_SUSPEND 0x00000100
156#define USB_STS_HC_HALTED 0x00001000
157#define USB_STS_RCL 0x00002000
158#define USB_STS_PERIODIC_SCHEDULE 0x00004000
159#define USB_STS_ASYNC_SCHEDULE 0x00008000
160
161/* USB INTR Register Bit Masks */
162#define USB_INTR_INT_EN 0x00000001
163#define USB_INTR_ERR_INT_EN 0x00000002
164#define USB_INTR_PTC_DETECT_EN 0x00000004
165#define USB_INTR_FRM_LST_ROLL_EN 0x00000008
166#define USB_INTR_SYS_ERR_EN 0x00000010
167#define USB_INTR_ASYN_ADV_EN 0x00000020
168#define USB_INTR_RESET_EN 0x00000040
169#define USB_INTR_SOF_EN 0x00000080
170#define USB_INTR_DEVICE_SUSPEND 0x00000100
171
172/* Device Address bit masks */
173#define USB_DEVICE_ADDRESS_MASK 0xFE000000
174#define USB_DEVICE_ADDRESS_BIT_POS 25
175
176/* endpoint list address bit masks */
177#define USB_EP_LIST_ADDRESS_MASK 0xfffff800
178
179/* PORTSCX Register Bit Masks */
180#define PORTSCX_CURRENT_CONNECT_STATUS 0x00000001
181#define PORTSCX_CONNECT_STATUS_CHANGE 0x00000002
182#define PORTSCX_PORT_ENABLE 0x00000004
183#define PORTSCX_PORT_EN_DIS_CHANGE 0x00000008
184#define PORTSCX_OVER_CURRENT_ACT 0x00000010
185#define PORTSCX_OVER_CURRENT_CHG 0x00000020
186#define PORTSCX_PORT_FORCE_RESUME 0x00000040
187#define PORTSCX_PORT_SUSPEND 0x00000080
188#define PORTSCX_PORT_RESET 0x00000100
189#define PORTSCX_LINE_STATUS_BITS 0x00000C00
190#define PORTSCX_PORT_POWER 0x00001000
191#define PORTSCX_PORT_INDICTOR_CTRL 0x0000C000
192#define PORTSCX_PORT_TEST_CTRL 0x000F0000
193#define PORTSCX_WAKE_ON_CONNECT_EN 0x00100000
194#define PORTSCX_WAKE_ON_CONNECT_DIS 0x00200000
195#define PORTSCX_WAKE_ON_OVER_CURRENT 0x00400000
196#define PORTSCX_PHY_LOW_POWER_SPD 0x00800000
197#define PORTSCX_PORT_FORCE_FULL_SPEED 0x01000000
198#define PORTSCX_PORT_SPEED_MASK 0x0C000000
199#define PORTSCX_PORT_WIDTH 0x10000000
200#define PORTSCX_PHY_TYPE_SEL 0xC0000000
201
202/* bit 11-10 are line status */
203#define PORTSCX_LINE_STATUS_SE0 0x00000000
204#define PORTSCX_LINE_STATUS_JSTATE 0x00000400
205#define PORTSCX_LINE_STATUS_KSTATE 0x00000800
206#define PORTSCX_LINE_STATUS_UNDEF 0x00000C00
207#define PORTSCX_LINE_STATUS_BIT_POS 10
208
209/* bit 15-14 are port indicator control */
210#define PORTSCX_PIC_OFF 0x00000000
211#define PORTSCX_PIC_AMBER 0x00004000
212#define PORTSCX_PIC_GREEN 0x00008000
213#define PORTSCX_PIC_UNDEF 0x0000C000
214#define PORTSCX_PIC_BIT_POS 14
215
216/* bit 19-16 are port test control */
217#define PORTSCX_PTC_DISABLE 0x00000000
218#define PORTSCX_PTC_JSTATE 0x00010000
219#define PORTSCX_PTC_KSTATE 0x00020000
220#define PORTSCX_PTC_SEQNAK 0x00030000
221#define PORTSCX_PTC_PACKET 0x00040000
222#define PORTSCX_PTC_FORCE_EN 0x00050000
223#define PORTSCX_PTC_BIT_POS 16
224
225/* bit 27-26 are port speed */
226#define PORTSCX_PORT_SPEED_FULL 0x00000000
227#define PORTSCX_PORT_SPEED_LOW 0x04000000
228#define PORTSCX_PORT_SPEED_HIGH 0x08000000
229#define PORTSCX_PORT_SPEED_UNDEF 0x0C000000
230#define PORTSCX_SPEED_BIT_POS 26
231
232/* bit 28 is parallel transceiver width for UTMI interface */
233#define PORTSCX_PTW 0x10000000
234#define PORTSCX_PTW_8BIT 0x00000000
235#define PORTSCX_PTW_16BIT 0x10000000
236
237/* bit 31-30 are port transceiver select */
238#define PORTSCX_PTS_UTMI 0x00000000
239#define PORTSCX_PTS_ULPI 0x80000000
240#define PORTSCX_PTS_FSLS 0xC0000000
241#define PORTSCX_PTS_BIT_POS 30
242
243/* otgsc Register Bit Masks */
244#define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001
245#define OTGSC_CTRL_VUSB_CHARGE 0x00000002
246#define OTGSC_CTRL_OTG_TERM 0x00000008
247#define OTGSC_CTRL_DATA_PULSING 0x00000010
248#define OTGSC_STS_USB_ID 0x00000100
249#define OTGSC_STS_A_VBUS_VALID 0x00000200
250#define OTGSC_STS_A_SESSION_VALID 0x00000400
251#define OTGSC_STS_B_SESSION_VALID 0x00000800
252#define OTGSC_STS_B_SESSION_END 0x00001000
253#define OTGSC_STS_1MS_TOGGLE 0x00002000
254#define OTGSC_STS_DATA_PULSING 0x00004000
255#define OTGSC_INTSTS_USB_ID 0x00010000
256#define OTGSC_INTSTS_A_VBUS_VALID 0x00020000
257#define OTGSC_INTSTS_A_SESSION_VALID 0x00040000
258#define OTGSC_INTSTS_B_SESSION_VALID 0x00080000
259#define OTGSC_INTSTS_B_SESSION_END 0x00100000
260#define OTGSC_INTSTS_1MS 0x00200000
261#define OTGSC_INTSTS_DATA_PULSING 0x00400000
262#define OTGSC_INTR_USB_ID 0x01000000
263#define OTGSC_INTR_A_VBUS_VALID 0x02000000
264#define OTGSC_INTR_A_SESSION_VALID 0x04000000
265#define OTGSC_INTR_B_SESSION_VALID 0x08000000
266#define OTGSC_INTR_B_SESSION_END 0x10000000
267#define OTGSC_INTR_1MS_TIMER 0x20000000
268#define OTGSC_INTR_DATA_PULSING 0x40000000
269
270/* USB MODE Register Bit Masks */
271#define USB_MODE_CTRL_MODE_IDLE 0x00000000
272#define USB_MODE_CTRL_MODE_DEVICE 0x00000002
273#define USB_MODE_CTRL_MODE_HOST 0x00000003
274#define USB_MODE_CTRL_MODE_RSV 0x00000001
275#define USB_MODE_SETUP_LOCK_OFF 0x00000008
276#define USB_MODE_STREAM_DISABLE 0x00000010
277/* Endpoint Flush Register */
278#define EPFLUSH_TX_OFFSET 0x00010000
279#define EPFLUSH_RX_OFFSET 0x00000000
280
281/* Endpoint Setup Status bit masks */
282#define EP_SETUP_STATUS_MASK 0x0000003F
283#define EP_SETUP_STATUS_EP0 0x00000001
284
285/* ENDPOINTCTRLx Register Bit Masks */
286#define EPCTRL_TX_ENABLE 0x00800000
287#define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */
288#define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */
289#define EPCTRL_TX_TYPE 0x000C0000
290#define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */
291#define EPCTRL_TX_EP_STALL 0x00010000
292#define EPCTRL_RX_ENABLE 0x00000080
293#define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */
294#define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */
295#define EPCTRL_RX_TYPE 0x0000000C
296#define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */
297#define EPCTRL_RX_EP_STALL 0x00000001
298
299/* bit 19-18 and 3-2 are endpoint type */
300#define EPCTRL_EP_TYPE_CONTROL 0
301#define EPCTRL_EP_TYPE_ISO 1
302#define EPCTRL_EP_TYPE_BULK 2
303#define EPCTRL_EP_TYPE_INTERRUPT 3
304#define EPCTRL_TX_EP_TYPE_SHIFT 18
305#define EPCTRL_RX_EP_TYPE_SHIFT 2
306
307/* SNOOPn Register Bit Masks */
308#define SNOOP_ADDRESS_MASK 0xFFFFF000
309#define SNOOP_SIZE_ZERO 0x00 /* snooping disable */
310#define SNOOP_SIZE_4KB 0x0B /* 4KB snoop size */
311#define SNOOP_SIZE_8KB 0x0C
312#define SNOOP_SIZE_16KB 0x0D
313#define SNOOP_SIZE_32KB 0x0E
314#define SNOOP_SIZE_64KB 0x0F
315#define SNOOP_SIZE_128KB 0x10
316#define SNOOP_SIZE_256KB 0x11
317#define SNOOP_SIZE_512KB 0x12
318#define SNOOP_SIZE_1MB 0x13
319#define SNOOP_SIZE_2MB 0x14
320#define SNOOP_SIZE_4MB 0x15
321#define SNOOP_SIZE_8MB 0x16
322#define SNOOP_SIZE_16MB 0x17
323#define SNOOP_SIZE_32MB 0x18
324#define SNOOP_SIZE_64MB 0x19
325#define SNOOP_SIZE_128MB 0x1A
326#define SNOOP_SIZE_256MB 0x1B
327#define SNOOP_SIZE_512MB 0x1C
328#define SNOOP_SIZE_1GB 0x1D
329#define SNOOP_SIZE_2GB 0x1E /* 2GB snoop size */
330
331/* pri_ctrl Register Bit Masks */
332#define PRI_CTRL_PRI_LVL1 0x0000000C
333#define PRI_CTRL_PRI_LVL0 0x00000003
334
335/* si_ctrl Register Bit Masks */
336#define SI_CTRL_ERR_DISABLE 0x00000010
337#define SI_CTRL_IDRC_DISABLE 0x00000008
338#define SI_CTRL_RD_SAFE_EN 0x00000004
339#define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002
340#define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001
341
342/* control Register Bit Masks */
343#define USB_CTRL_IOENB 0x00000004
344#define USB_CTRL_ULPI_INT0EN 0x00000001
345
346/* Endpoint Queue Head data struct
347 * Rem: all the variables of qh are LittleEndian Mode
348 * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr
349 */
350struct ep_queue_head {
351 u32 max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len
352 and IOS(15) */
353 u32 curr_dtd_ptr; /* Current dTD Pointer(31-5) */
354 u32 next_dtd_ptr; /* Next dTD Pointer(31-5), T(0) */
355 u32 size_ioc_int_sts; /* Total bytes (30-16), IOC (15),
356 MultO(11-10), STS (7-0) */
357 u32 buff_ptr0; /* Buffer pointer Page 0 (31-12) */
358 u32 buff_ptr1; /* Buffer pointer Page 1 (31-12) */
359 u32 buff_ptr2; /* Buffer pointer Page 2 (31-12) */
360 u32 buff_ptr3; /* Buffer pointer Page 3 (31-12) */
361 u32 buff_ptr4; /* Buffer pointer Page 4 (31-12) */
362 u32 res1;
363 u8 setup_buffer[8]; /* Setup data 8 bytes */
364 u32 res2[4];
365};
366
367/* Endpoint Queue Head Bit Masks */
368#define EP_QUEUE_HEAD_MULT_POS 30
369#define EP_QUEUE_HEAD_ZLT_SEL 0x20000000
370#define EP_QUEUE_HEAD_MAX_PKT_LEN_POS 16
371#define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff)
372#define EP_QUEUE_HEAD_IOS 0x00008000
373#define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001
374#define EP_QUEUE_HEAD_IOC 0x00008000
375#define EP_QUEUE_HEAD_MULTO 0x00000C00
376#define EP_QUEUE_HEAD_STATUS_HALT 0x00000040
377#define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080
378#define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF
379#define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0
380#define EP_QUEUE_FRINDEX_MASK 0x000007FF
381#define EP_MAX_LENGTH_TRANSFER 0x4000
382
383/* Endpoint Transfer Descriptor data struct */
384/* Rem: all the variables of td are LittleEndian Mode */
385struct ep_td_struct {
386 u32 next_td_ptr; /* Next TD pointer(31-5), T(0) set
387 indicate invalid */
388 u32 size_ioc_sts; /* Total bytes (30-16), IOC (15),
389 MultO(11-10), STS (7-0) */
390 u32 buff_ptr0; /* Buffer pointer Page 0 */
391 u32 buff_ptr1; /* Buffer pointer Page 1 */
392 u32 buff_ptr2; /* Buffer pointer Page 2 */
393 u32 buff_ptr3; /* Buffer pointer Page 3 */
394 u32 buff_ptr4; /* Buffer pointer Page 4 */
395 u32 res;
396 /* 32 bytes */
397 dma_addr_t td_dma; /* dma address for this td */
398 /* virtual address of next td specified in next_td_ptr */
399 struct ep_td_struct *next_td_virt;
400};
401
402/* Endpoint Transfer Descriptor bit Masks */
403#define DTD_NEXT_TERMINATE 0x00000001
404#define DTD_IOC 0x00008000
405#define DTD_STATUS_ACTIVE 0x00000080
406#define DTD_STATUS_HALTED 0x00000040
407#define DTD_STATUS_DATA_BUFF_ERR 0x00000020
408#define DTD_STATUS_TRANSACTION_ERR 0x00000008
409#define DTD_RESERVED_FIELDS 0x80007300
410#define DTD_ADDR_MASK 0xFFFFFFE0
411#define DTD_PACKET_SIZE 0x7FFF0000
412#define DTD_LENGTH_BIT_POS 16
413#define DTD_ERROR_MASK (DTD_STATUS_HALTED | \
414 DTD_STATUS_DATA_BUFF_ERR | \
415 DTD_STATUS_TRANSACTION_ERR)
416/* Alignment requirements; must be a power of two */
417#define DTD_ALIGNMENT 0x20
418#define QH_ALIGNMENT 2048
419
420/* Controller dma boundary */
421#define UDC_DMA_BOUNDARY 0x1000
422
423/* -----------------------------------------------------------------------*/
424/* ##### enum data
425*/
426typedef enum {
427 e_ULPI,
428 e_UTMI_8BIT,
429 e_UTMI_16BIT,
430 e_SERIAL
431} e_PhyInterface;
432
433/*-------------------------------------------------------------------------*/
434
435/* ### driver private data
436 */
437struct fsl_req {
438 struct usb_request req;
439 struct list_head queue;
440 /* ep_queue() func will add
441 a request->queue into a udc_ep->queue 'd tail */
442 struct fsl_ep *ep;
443 unsigned mapped:1;
444
445 struct ep_td_struct *head, *tail; /* For dTD List
446 cpu endian Virtual addr */
447 unsigned int dtd_count;
448};
449
450#define REQ_UNCOMPLETE 1
451
452struct fsl_ep {
453 struct usb_ep ep;
454 struct list_head queue;
455 struct fsl_udc *udc;
456 struct ep_queue_head *qh;
457 const struct usb_endpoint_descriptor *desc;
458 struct usb_gadget *gadget;
459
460 char name[14];
461 unsigned stopped:1;
462};
463
464#define EP_DIR_IN 1
465#define EP_DIR_OUT 0
466
467struct fsl_udc {
468
469 struct usb_gadget gadget;
470 struct usb_gadget_driver *driver;
471 struct fsl_ep *eps;
472 unsigned int max_ep;
473 unsigned int irq;
474
475 struct usb_ctrlrequest local_setup_buff;
476 spinlock_t lock;
477 struct otg_transceiver *transceiver;
478 unsigned softconnect:1;
479 unsigned vbus_active:1;
480 unsigned stopped:1;
481 unsigned remote_wakeup:1;
482
483 struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */
484 struct fsl_req *status_req; /* ep0 status request */
485 struct dma_pool *td_pool; /* dma pool for DTD */
486 enum fsl_usb2_phy_modes phy_mode;
487
488 size_t ep_qh_size; /* size after alignment adjustment*/
489 dma_addr_t ep_qh_dma; /* dma address of QH */
490
491 u32 max_pipes; /* Device max pipes */
492 u32 max_use_endpts; /* Max endpointes to be used */
493 u32 bus_reset; /* Device is bus reseting */
494 u32 resume_state; /* USB state to resume */
495 u32 usb_state; /* USB current state */
496 u32 usb_next_state; /* USB next state */
497 u32 ep0_state; /* Endpoint zero state */
498 u32 ep0_dir; /* Endpoint zero direction: can be
499 USB_DIR_IN or USB_DIR_OUT */
500 u32 usb_sof_count; /* SOF count */
501 u32 errors; /* USB ERRORs count */
502 u8 device_address; /* Device USB address */
503
504 struct completion *done; /* to make sure release() is done */
505};
506
507/*-------------------------------------------------------------------------*/
508
509#ifdef DEBUG
510#define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt "\n", \
511 __FUNCTION__, ## args)
512#else
513#define DBG(fmt, args...) do{}while(0)
514#endif
515
516#if 0
517static void dump_msg(const char *label, const u8 * buf, unsigned int length)
518{
519 unsigned int start, num, i;
520 char line[52], *p;
521
522 if (length >= 512)
523 return;
524 DBG("%s, length %u:\n", label, length);
525 start = 0;
526 while (length > 0) {
527 num = min(length, 16u);
528 p = line;
529 for (i = 0; i < num; ++i) {
530 if (i == 8)
531 *p++ = ' ';
532 sprintf(p, " %02x", buf[i]);
533 p += 3;
534 }
535 *p = 0;
536 printk(KERN_DEBUG "%6x: %s\n", start, line);
537 buf += num;
538 start += num;
539 length -= num;
540 }
541}
542#endif
543
544#ifdef VERBOSE
545#define VDBG DBG
546#else
547#define VDBG(stuff...) do{}while(0)
548#endif
549
550#define ERR(stuff...) printk(KERN_ERR "udc: " stuff)
551#define WARN(stuff...) printk(KERN_WARNING "udc: " stuff)
552#define INFO(stuff...) printk(KERN_INFO "udc: " stuff)
553
554/*-------------------------------------------------------------------------*/
555
556/* ### Add board specific defines here
557 */
558
559/*
560 * ### pipe direction macro from device view
561 */
562#define USB_RECV 0 /* OUT EP */
563#define USB_SEND 1 /* IN EP */
564
565/*
566 * ### internal used help routines.
567 */
568#define ep_index(EP) ((EP)->desc->bEndpointAddress&0xF)
569#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
570#define ep_is_in(EP) ( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \
571 USB_DIR_IN ):((EP)->desc->bEndpointAddress \
572 & USB_DIR_IN)==USB_DIR_IN)
573#define get_ep_by_pipe(udc, pipe) ((pipe == 1)? &udc->eps[0]: \
574 &udc->eps[pipe])
575#define get_pipe_by_windex(windex) ((windex & USB_ENDPOINT_NUMBER_MASK) \
576 * 2 + ((windex & USB_DIR_IN) ? 1 : 0))
577#define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP))
578
579#endif
kernel source for telekom puls (alcatel/mediatek)