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Merge branch 'timer/cleanup' into late/mvebu2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / fsl_udc_core.c
CommitLineData
b504882d 1/*
58c559e6 2 * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
ea437f39 3 * All rights reserved.
b504882d
LY		 4 *
5 * Author: Li Yang <leoli@freescale.com>
6 * Jiang Bo <tanya.jiang@freescale.com>
7 *
8 * Description:
9 * Freescale high-speed USB SOC DR module device controller driver.
2ea6698d 10 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
b504882d
LY		 11 * The driver is previously named as mpc_udc. Based on bare board
12 * code from Dave Liu and Shlomi Gridish.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20#undef VERBOSE
21
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/ioport.h>
25#include <linux/types.h>
26#include <linux/errno.h>
ded017ee 27#include <linux/err.h>
b504882d
LY		 28#include <linux/slab.h>
29#include <linux/init.h>
b504882d
LY		 30#include <linux/list.h>
31#include <linux/interrupt.h>
32#include <linux/proc_fs.h>
33#include <linux/mm.h>
34#include <linux/moduleparam.h>
35#include <linux/device.h>
36#include <linux/usb/ch9.h>
9454a57a 37#include <linux/usb/gadget.h>
b504882d
LY		 38#include <linux/usb/otg.h>
39#include <linux/dma-mapping.h>
40#include <linux/platform_device.h>
41#include <linux/fsl_devices.h>
42#include <linux/dmapool.h>
54e4026b 43#include <linux/delay.h>
f0ea8834 44#include <linux/of_device.h>
b504882d
LY		 45
46#include <asm/byteorder.h>
47#include <asm/io.h>
b504882d
LY		 48#include <asm/unaligned.h>
49#include <asm/dma.h>
b504882d
LY		 50
51#include "fsl_usb2_udc.h"
52
53#define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
54#define DRIVER_AUTHOR "Li Yang/Jiang Bo"
55#define DRIVER_VERSION "Apr 20, 2007"
56
57#define DMA_ADDR_INVALID (~(dma_addr_t)0)
58
59static const char driver_name[] = "fsl-usb2-udc";
60static const char driver_desc[] = DRIVER_DESC;
61
7483cff8 62static struct usb_dr_device *dr_regs;
58c559e6 63
7483cff8 64static struct usb_sys_interface *usb_sys_regs;
b504882d
LY		 65
66/* it is initialized in probe() */
67static struct fsl_udc *udc_controller = NULL;
68
69static const struct usb_endpoint_descriptor
70fsl_ep0_desc = {
71 .bLength = USB_DT_ENDPOINT_SIZE,
72 .bDescriptorType = USB_DT_ENDPOINT,
73 .bEndpointAddress = 0,
74 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
75 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
76};
77
b504882d
LY		 78static void fsl_ep_fifo_flush(struct usb_ep *_ep);
79
80#ifdef CONFIG_PPC32
09ba0def
AG		 81/*
82 * On some SoCs, the USB controller registers can be big or little endian,
83 * depending on the version of the chip. In order to be able to run the
84 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
85 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
86 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
87 * call through those pointers. Platform code for SoCs that have BE USB
88 * registers should set pdata->big_endian_mmio flag.
89 *
90 * This also applies to controller-to-cpu accessors for the USB descriptors,
91 * since their endianness is also SoC dependant. Platform code for SoCs that
92 * have BE USB descriptors should set pdata->big_endian_desc flag.
93 */
94static u32 _fsl_readl_be(const unsigned __iomem *p)
95{
96 return in_be32(p);
97}
98
99static u32 _fsl_readl_le(const unsigned __iomem *p)
100{
101 return in_le32(p);
102}
103
104static void _fsl_writel_be(u32 v, unsigned __iomem *p)
105{
106 out_be32(p, v);
107}
108
109static void _fsl_writel_le(u32 v, unsigned __iomem *p)
110{
111 out_le32(p, v);
112}
113
114static u32 (*_fsl_readl)(const unsigned __iomem *p);
115static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
116
117#define fsl_readl(p) (*_fsl_readl)((p))
118#define fsl_writel(v, p) (*_fsl_writel)((v), (p))
119
3140d5b2
AG		 120static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
121{
122 if (pdata->big_endian_mmio) {
123 _fsl_readl = _fsl_readl_be;
124 _fsl_writel = _fsl_writel_be;
125 } else {
126 _fsl_readl = _fsl_readl_le;
127 _fsl_writel = _fsl_writel_le;
128 }
129}
130
09ba0def
AG		 131static inline u32 cpu_to_hc32(const u32 x)
132{
133 return udc_controller->pdata->big_endian_desc
134 ? (__force u32)cpu_to_be32(x)
135 : (__force u32)cpu_to_le32(x);
136}
137
138static inline u32 hc32_to_cpu(const u32 x)
139{
140 return udc_controller->pdata->big_endian_desc
141 ? be32_to_cpu((__force __be32)x)
142 : le32_to_cpu((__force __le32)x);
143}
144#else /* !CONFIG_PPC32 */
3140d5b2
AG		 145static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
146
b504882d 147#define fsl_readl(addr) readl(addr)
c93eebbe 148#define fsl_writel(val32, addr) writel(val32, addr)
09ba0def
AG		 149#define cpu_to_hc32(x) cpu_to_le32(x)
150#define hc32_to_cpu(x) le32_to_cpu(x)
151#endif /* CONFIG_PPC32 */
b504882d
LY		 152
153/********************************************************************
154 * Internal Used Function
155********************************************************************/
156/*-----------------------------------------------------------------
157 * done() - retire a request; caller blocked irqs
158 * @status : request status to be set, only works when
159 * request is still in progress.
160 *--------------------------------------------------------------*/
161static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
162{
163 struct fsl_udc *udc = NULL;
164 unsigned char stopped = ep->stopped;
165 struct ep_td_struct *curr_td, *next_td;
166 int j;
167
168 udc = (struct fsl_udc *)ep->udc;
169 /* Removed the req from fsl_ep->queue */
170 list_del_init(&req->queue);
171
172 /* req.status should be set as -EINPROGRESS in ep_queue() */
173 if (req->req.status == -EINPROGRESS)
174 req->req.status = status;
175 else
176 status = req->req.status;
177
178 /* Free dtd for the request */
179 next_td = req->head;
180 for (j = 0; j < req->dtd_count; j++) {
181 curr_td = next_td;
182 if (j != req->dtd_count - 1) {
183 next_td = curr_td->next_td_virt;
184 }
185 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
186 }
187
188 if (req->mapped) {
189 dma_unmap_single(ep->udc->gadget.dev.parent,
190 req->req.dma, req->req.length,
191 ep_is_in(ep)
192 ? DMA_TO_DEVICE
193 : DMA_FROM_DEVICE);
194 req->req.dma = DMA_ADDR_INVALID;
195 req->mapped = 0;
196 } else
197 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
198 req->req.dma, req->req.length,
199 ep_is_in(ep)
200 ? DMA_TO_DEVICE
201 : DMA_FROM_DEVICE);
202
203 if (status && (status != -ESHUTDOWN))
204 VDBG("complete %s req %p stat %d len %u/%u",
205 ep->ep.name, &req->req, status,
206 req->req.actual, req->req.length);
207
208 ep->stopped = 1;
209
210 spin_unlock(&ep->udc->lock);
211 /* complete() is from gadget layer,
212 * eg fsg->bulk_in_complete() */
213 if (req->req.complete)
214 req->req.complete(&ep->ep, &req->req);
215
216 spin_lock(&ep->udc->lock);
217 ep->stopped = stopped;
218}
219
220/*-----------------------------------------------------------------
221 * nuke(): delete all requests related to this ep
222 * called with spinlock held
223 *--------------------------------------------------------------*/
224static void nuke(struct fsl_ep *ep, int status)
225{
226 ep->stopped = 1;
227
228 /* Flush fifo */
229 fsl_ep_fifo_flush(&ep->ep);
230
231 /* Whether this eq has request linked */
232 while (!list_empty(&ep->queue)) {
233 struct fsl_req *req = NULL;
234
235 req = list_entry(ep->queue.next, struct fsl_req, queue);
236 done(ep, req, status);
237 }
238}
239
240/*------------------------------------------------------------------
241 Internal Hardware related function
242 ------------------------------------------------------------------*/
243
244static int dr_controller_setup(struct fsl_udc *udc)
245{
ea437f39
RM		 246 unsigned int tmp, portctrl, ep_num;
247 unsigned int max_no_of_ep;
54e4026b 248 unsigned int ctrl;
b504882d 249 unsigned long timeout;
58c559e6 250
b504882d
LY		 251#define FSL_UDC_RESET_TIMEOUT 1000
252
54e4026b
GL		 253 /* Config PHY interface */
254 portctrl = fsl_readl(&dr_regs->portsc1);
255 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
256 switch (udc->phy_mode) {
257 case FSL_USB2_PHY_ULPI:
58c559e6
RM		 258 if (udc->pdata->have_sysif_regs) {
259 if (udc->pdata->controller_ver) {
260 /* controller version 1.6 or above */
261 ctrl = __raw_readl(&usb_sys_regs->control);
262 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
263 ctrl |= USB_CTRL_USB_EN;
264 __raw_writel(ctrl, &usb_sys_regs->control);
265 }
266 }
54e4026b
GL		 267 portctrl |= PORTSCX_PTS_ULPI;
268 break;
269 case FSL_USB2_PHY_UTMI_WIDE:
270 portctrl |= PORTSCX_PTW_16BIT;
271 /* fall through */
272 case FSL_USB2_PHY_UTMI:
58c559e6
RM		 273 if (udc->pdata->have_sysif_regs) {
274 if (udc->pdata->controller_ver) {
275 /* controller version 1.6 or above */
276 ctrl = __raw_readl(&usb_sys_regs->control);
277 ctrl |= (USB_CTRL_UTMI_PHY_EN |
278 USB_CTRL_USB_EN);
279 __raw_writel(ctrl, &usb_sys_regs->control);
280 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
281 PHY CLK to become stable - 10ms*/
282 }
283 }
54e4026b
GL		 284 portctrl |= PORTSCX_PTS_UTMI;
285 break;
286 case FSL_USB2_PHY_SERIAL:
287 portctrl |= PORTSCX_PTS_FSLS;
288 break;
289 default:
290 return -EINVAL;
291 }
292 fsl_writel(portctrl, &dr_regs->portsc1);
293
b504882d
LY		 294 /* Stop and reset the usb controller */
295 tmp = fsl_readl(&dr_regs->usbcmd);
296 tmp &= ~USB_CMD_RUN_STOP;
297 fsl_writel(tmp, &dr_regs->usbcmd);
298
299 tmp = fsl_readl(&dr_regs->usbcmd);
300 tmp |= USB_CMD_CTRL_RESET;
301 fsl_writel(tmp, &dr_regs->usbcmd);
302
303 /* Wait for reset to complete */
304 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
305 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
306 if (time_after(jiffies, timeout)) {
bf7409a2 307 ERR("udc reset timeout!\n");
b504882d
LY		 308 return -ETIMEDOUT;
309 }
310 cpu_relax();
311 }
312
313 /* Set the controller as device mode */
314 tmp = fsl_readl(&dr_regs->usbmode);
2ea6698d 315 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
b504882d
LY		 316 tmp |= USB_MODE_CTRL_MODE_DEVICE;
317 /* Disable Setup Lockout */
318 tmp |= USB_MODE_SETUP_LOCK_OFF;
2ea6698d
AG		 319 if (udc->pdata->es)
320 tmp |= USB_MODE_ES;
b504882d
LY		 321 fsl_writel(tmp, &dr_regs->usbmode);
322
323 /* Clear the setup status */
324 fsl_writel(0, &dr_regs->usbsts);
325
326 tmp = udc->ep_qh_dma;
327 tmp &= USB_EP_LIST_ADDRESS_MASK;
328 fsl_writel(tmp, &dr_regs->endpointlistaddr);
329
330 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
6ef65a7f 331 udc->ep_qh, (int)tmp,
b504882d
LY		 332 fsl_readl(&dr_regs->endpointlistaddr));
333
ea437f39
RM		 334 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
335 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
336 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
337 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
338 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
339 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
340 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
341 }
b504882d 342 /* Config control enable i/o output, cpu endian register */
54e4026b 343#ifndef CONFIG_ARCH_MXC
2ea6698d
AG		 344 if (udc->pdata->have_sysif_regs) {
345 ctrl = __raw_readl(&usb_sys_regs->control);
346 ctrl |= USB_CTRL_IOENB;
347 __raw_writel(ctrl, &usb_sys_regs->control);
348 }
54e4026b 349#endif
b504882d
LY		 350
351#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
352 /* Turn on cache snooping hardware, since some PowerPC platforms
353 * wholly rely on hardware to deal with cache coherent. */
354
2ea6698d
AG		 355 if (udc->pdata->have_sysif_regs) {
356 /* Setup Snooping for all the 4GB space */
357 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
358 __raw_writel(tmp, &usb_sys_regs->snoop1);
359 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
360 __raw_writel(tmp, &usb_sys_regs->snoop2);
361 }
b504882d
LY		 362#endif
363
364 return 0;
365}
366
367/* Enable DR irq and set controller to run state */
368static void dr_controller_run(struct fsl_udc *udc)
369{
370 u32 temp;
371
372 /* Enable DR irq reg */
373 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
374 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
375 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
376
377 fsl_writel(temp, &dr_regs->usbintr);
378
379 /* Clear stopped bit */
380 udc->stopped = 0;
381
382 /* Set the controller as device mode */
383 temp = fsl_readl(&dr_regs->usbmode);
384 temp |= USB_MODE_CTRL_MODE_DEVICE;
385 fsl_writel(temp, &dr_regs->usbmode);
386
387 /* Set controller to Run */
388 temp = fsl_readl(&dr_regs->usbcmd);
389 temp |= USB_CMD_RUN_STOP;
390 fsl_writel(temp, &dr_regs->usbcmd);
b504882d
LY		 391}
392
393static void dr_controller_stop(struct fsl_udc *udc)
394{
395 unsigned int tmp;
396
83722bc9
AG		 397 pr_debug("%s\n", __func__);
398
399 /* if we're in OTG mode, and the Host is currently using the port,
400 * stop now and don't rip the controller out from under the
401 * ehci driver
402 */
403 if (udc->gadget.is_otg) {
404 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
405 pr_debug("udc: Leaving early\n");
406 return;
407 }
408 }
409
b504882d
LY		 410 /* disable all INTR */
411 fsl_writel(0, &dr_regs->usbintr);
412
413 /* Set stopped bit for isr */
414 udc->stopped = 1;
415
416 /* disable IO output */
417/* usb_sys_regs->control = 0; */
418
419 /* set controller to Stop */
420 tmp = fsl_readl(&dr_regs->usbcmd);
421 tmp &= ~USB_CMD_RUN_STOP;
422 fsl_writel(tmp, &dr_regs->usbcmd);
b504882d
LY		 423}
424
9c94155e
WN		 425static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
426 unsigned char ep_type)
b504882d
LY		 427{
428 unsigned int tmp_epctrl = 0;
429
430 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
431 if (dir) {
432 if (ep_num)
433 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
434 tmp_epctrl |= EPCTRL_TX_ENABLE;
ea437f39 435 tmp_epctrl &= ~EPCTRL_TX_TYPE;
b504882d
LY		 436 tmp_epctrl |= ((unsigned int)(ep_type)
437 << EPCTRL_TX_EP_TYPE_SHIFT);
438 } else {
439 if (ep_num)
440 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
441 tmp_epctrl |= EPCTRL_RX_ENABLE;
ea437f39 442 tmp_epctrl &= ~EPCTRL_RX_TYPE;
b504882d
LY		 443 tmp_epctrl |= ((unsigned int)(ep_type)
444 << EPCTRL_RX_EP_TYPE_SHIFT);
445 }
446
447 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
448}
449
450static void
451dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
452{
453 u32 tmp_epctrl = 0;
454
455 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
456
457 if (value) {
458 /* set the stall bit */
459 if (dir)
460 tmp_epctrl |= EPCTRL_TX_EP_STALL;
461 else
462 tmp_epctrl |= EPCTRL_RX_EP_STALL;
463 } else {
464 /* clear the stall bit and reset data toggle */
465 if (dir) {
466 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
467 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
468 } else {
469 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
470 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
471 }
472 }
473 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
474}
475
476/* Get stall status of a specific ep
477 Return: 0: not stalled; 1:stalled */
478static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
479{
480 u32 epctrl;
481
482 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
483 if (dir)
484 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
485 else
486 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
487}
488
489/********************************************************************
490 Internal Structure Build up functions
491********************************************************************/
492
493/*------------------------------------------------------------------
494* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
495 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
496 * @mult: Mult field
497 ------------------------------------------------------------------*/
498static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
499 unsigned char dir, unsigned char ep_type,
500 unsigned int max_pkt_len,
501 unsigned int zlt, unsigned char mult)
502{
503 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
504 unsigned int tmp = 0;
505
506 /* set the Endpoint Capabilites in QH */
507 switch (ep_type) {
508 case USB_ENDPOINT_XFER_CONTROL:
509 /* Interrupt On Setup (IOS). for control ep */
510 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
511 | EP_QUEUE_HEAD_IOS;
512 break;
513 case USB_ENDPOINT_XFER_ISOC:
514 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
515 | (mult << EP_QUEUE_HEAD_MULT_POS);
516 break;
517 case USB_ENDPOINT_XFER_BULK:
518 case USB_ENDPOINT_XFER_INT:
519 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
520 break;
521 default:
522 VDBG("error ep type is %d", ep_type);
523 return;
524 }
525 if (zlt)
526 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
9a6e184c 527
09ba0def 528 p_QH->max_pkt_length = cpu_to_hc32(tmp);
9a6e184c
LY		 529 p_QH->next_dtd_ptr = 1;
530 p_QH->size_ioc_int_sts = 0;
b504882d
LY		 531}
532
533/* Setup qh structure and ep register for ep0. */
534static void ep0_setup(struct fsl_udc *udc)
535{
536 /* the intialization of an ep includes: fields in QH, Regs,
537 * fsl_ep struct */
538 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
539 USB_MAX_CTRL_PAYLOAD, 0, 0);
540 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
541 USB_MAX_CTRL_PAYLOAD, 0, 0);
542 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
543 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
544
545 return;
546
547}
548
549/***********************************************************************
550 Endpoint Management Functions
551***********************************************************************/
552
553/*-------------------------------------------------------------------------
554 * when configurations are set, or when interface settings change
555 * for example the do_set_interface() in gadget layer,
556 * the driver will enable or disable the relevant endpoints
557 * ep0 doesn't use this routine. It is always enabled.
558-------------------------------------------------------------------------*/
559static int fsl_ep_enable(struct usb_ep *_ep,
560 const struct usb_endpoint_descriptor *desc)
561{
562 struct fsl_udc *udc = NULL;
563 struct fsl_ep *ep = NULL;
564 unsigned short max = 0;
565 unsigned char mult = 0, zlt;
566 int retval = -EINVAL;
567 unsigned long flags = 0;
568
569 ep = container_of(_ep, struct fsl_ep, ep);
570
571 /* catch various bogus parameters */
1fa75972 572 if (!_ep || !desc
b504882d
LY		 573 || (desc->bDescriptorType != USB_DT_ENDPOINT))
574 return -EINVAL;
575
576 udc = ep->udc;
577
578 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
579 return -ESHUTDOWN;
580
29cc8897 581 max = usb_endpoint_maxp(desc);
b504882d 582
25985edc 583 /* Disable automatic zlp generation. Driver is responsible to indicate
b504882d
LY		 584 * explicitly through req->req.zero. This is needed to enable multi-td
585 * request. */
586 zlt = 1;
587
588 /* Assume the max packet size from gadget is always correct */
589 switch (desc->bmAttributes & 0x03) {
590 case USB_ENDPOINT_XFER_CONTROL:
591 case USB_ENDPOINT_XFER_BULK:
592 case USB_ENDPOINT_XFER_INT:
593 /* mult = 0. Execute N Transactions as demonstrated by
594 * the USB variable length packet protocol where N is
595 * computed using the Maximum Packet Length (dQH) and
596 * the Total Bytes field (dTD) */
597 mult = 0;
598 break;
599 case USB_ENDPOINT_XFER_ISOC:
600 /* Calculate transactions needed for high bandwidth iso */
601 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
88e3b59b 602 max = max & 0x7ff; /* bit 0~10 */
b504882d
LY		 603 /* 3 transactions at most */
604 if (mult > 3)
605 goto en_done;
606 break;
607 default:
608 goto en_done;
609 }
610
611 spin_lock_irqsave(&udc->lock, flags);
612 ep->ep.maxpacket = max;
79149b8b 613 ep->ep.desc = desc;
b504882d
LY		 614 ep->stopped = 0;
615
616 /* Controller related setup */
617 /* Init EPx Queue Head (Ep Capabilites field in QH
618 * according to max, zlt, mult) */
619 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
620 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
621 ? USB_SEND : USB_RECV),
622 (unsigned char) (desc->bmAttributes
623 & USB_ENDPOINT_XFERTYPE_MASK),
624 max, zlt, mult);
625
626 /* Init endpoint ctrl register */
627 dr_ep_setup((unsigned char) ep_index(ep),
628 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
629 ? USB_SEND : USB_RECV),
630 (unsigned char) (desc->bmAttributes
631 & USB_ENDPOINT_XFERTYPE_MASK));
632
633 spin_unlock_irqrestore(&udc->lock, flags);
634 retval = 0;
635
636 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
79149b8b 637 ep->ep.desc->bEndpointAddress & 0x0f,
b504882d
LY		 638 (desc->bEndpointAddress & USB_DIR_IN)
639 ? "in" : "out", max);
640en_done:
641 return retval;
642}
643
644/*---------------------------------------------------------------------
645 * @ep : the ep being unconfigured. May not be ep0
646 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
647*---------------------------------------------------------------------*/
648static int fsl_ep_disable(struct usb_ep *_ep)
649{
650 struct fsl_udc *udc = NULL;
651 struct fsl_ep *ep = NULL;
652 unsigned long flags = 0;
653 u32 epctrl;
654 int ep_num;
655
656 ep = container_of(_ep, struct fsl_ep, ep);
79149b8b 657 if (!_ep || !ep->ep.desc) {
b504882d
LY		 658 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
659 return -EINVAL;
660 }
661
662 /* disable ep on controller */
663 ep_num = ep_index(ep);
664 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
ea437f39
RM		 665 if (ep_is_in(ep)) {
666 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
667 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
668 } else {
669 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
670 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
671 }
b504882d
LY		 672 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
673
674 udc = (struct fsl_udc *)ep->udc;
675 spin_lock_irqsave(&udc->lock, flags);
676
677 /* nuke all pending requests (does flush) */
678 nuke(ep, -ESHUTDOWN);
679
f9c56cdd 680 ep->ep.desc = NULL;
b504882d
LY		 681 ep->stopped = 1;
682 spin_unlock_irqrestore(&udc->lock, flags);
683
684 VDBG("disabled %s OK", _ep->name);
685 return 0;
686}
687
688/*---------------------------------------------------------------------
689 * allocate a request object used by this endpoint
690 * the main operation is to insert the req->queue to the eq->queue
691 * Returns the request, or null if one could not be allocated
692*---------------------------------------------------------------------*/
693static struct usb_request *
694fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
695{
696 struct fsl_req *req = NULL;
697
698 req = kzalloc(sizeof *req, gfp_flags);
699 if (!req)
700 return NULL;
701
702 req->req.dma = DMA_ADDR_INVALID;
703 INIT_LIST_HEAD(&req->queue);
704
705 return &req->req;
706}
707
708static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
709{
710 struct fsl_req *req = NULL;
711
712 req = container_of(_req, struct fsl_req, req);
713
714 if (_req)
715 kfree(req);
716}
717
6414e94c
LY		 718/* Actually add a dTD chain to an empty dQH and let go */
719static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
720{
721 struct ep_queue_head *qh = get_qh_by_ep(ep);
722
723 /* Write dQH next pointer and terminate bit to 0 */
724 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
725 & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
726
727 /* Clear active and halt bit */
728 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
729 | EP_QUEUE_HEAD_STATUS_HALT));
730
731 /* Ensure that updates to the QH will occur before priming. */
732 wmb();
733
734 /* Prime endpoint by writing correct bit to ENDPTPRIME */
735 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
736 : (1 << (ep_index(ep))), &dr_regs->endpointprime);
737}
738
739/* Add dTD chain to the dQH of an EP */
224b5039 740static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
b504882d 741{
b504882d 742 u32 temp, bitmask, tmp_stat;
b504882d
LY		 743
744 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
745 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
746
747 bitmask = ep_is_in(ep)
748 ? (1 << (ep_index(ep) + 16))
749 : (1 << (ep_index(ep)));
750
751 /* check if the pipe is empty */
f79a60b8 752 if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
b504882d
LY		 753 /* Add td to the end */
754 struct fsl_req *lastreq;
755 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
756 lastreq->tail->next_td_ptr =
09ba0def 757 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
4d0947de
PC		 758 /* Ensure dTD's next dtd pointer to be updated */
759 wmb();
b504882d
LY		 760 /* Read prime bit, if 1 goto done */
761 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
6414e94c 762 return;
b504882d
LY		 763
764 do {
765 /* Set ATDTW bit in USBCMD */
766 temp = fsl_readl(&dr_regs->usbcmd);
767 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
768
769 /* Read correct status bit */
770 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
771
772 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
773
774 /* Write ATDTW bit to 0 */
775 temp = fsl_readl(&dr_regs->usbcmd);
776 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
777
778 if (tmp_stat)
6414e94c 779 return;
b504882d
LY		 780 }
781
6414e94c 782 fsl_prime_ep(ep, req->head);
b504882d
LY		 783}
784
785/* Fill in the dTD structure
786 * @req: request that the transfer belongs to
787 * @length: return actually data length of the dTD
788 * @dma: return dma address of the dTD
789 * @is_last: return flag if it is the last dTD of the request
790 * return: pointer to the built dTD */
791static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
c5cc5ed8 792 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
b504882d
LY		 793{
794 u32 swap_temp;
795 struct ep_td_struct *dtd;
796
797 /* how big will this transfer be? */
798 *length = min(req->req.length - req->req.actual,
799 (unsigned)EP_MAX_LENGTH_TRANSFER);
800
c5cc5ed8 801 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
b504882d
LY		 802 if (dtd == NULL)
803 return dtd;
804
805 dtd->td_dma = *dma;
806 /* Clear reserved field */
09ba0def 807 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
b504882d 808 swap_temp &= ~DTD_RESERVED_FIELDS;
09ba0def 809 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
b504882d
LY		 810
811 /* Init all of buffer page pointers */
812 swap_temp = (u32) (req->req.dma + req->req.actual);
09ba0def
AG		 813 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
814 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
815 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
816 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
817 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
b504882d
LY		 818
819 req->req.actual += *length;
820
821 /* zlp is needed if req->req.zero is set */
822 if (req->req.zero) {
823 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
824 *is_last = 1;
825 else
826 *is_last = 0;
827 } else if (req->req.length == req->req.actual)
828 *is_last = 1;
829 else
830 *is_last = 0;
831
832 if ((*is_last) == 0)
bf7409a2 833 VDBG("multi-dtd request!");
b504882d
LY		 834 /* Fill in the transfer size; set active bit */
835 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
836
837 /* Enable interrupt for the last dtd of a request */
838 if (*is_last && !req->req.no_interrupt)
839 swap_temp |= DTD_IOC;
840
09ba0def 841 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
b504882d
LY		 842
843 mb();
844
845 VDBG("length = %d address= 0x%x", *length, (int)*dma);
846
847 return dtd;
848}
849
850/* Generate dtd chain for a request */
c5cc5ed8 851static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
b504882d
LY		 852{
853 unsigned count;
854 int is_last;
855 int is_first =1;
856 struct ep_td_struct *last_dtd = NULL, *dtd;
857 dma_addr_t dma;
858
859 do {
c5cc5ed8 860 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
b504882d
LY		 861 if (dtd == NULL)
862 return -ENOMEM;
863
864 if (is_first) {
865 is_first = 0;
866 req->head = dtd;
867 } else {
09ba0def 868 last_dtd->next_td_ptr = cpu_to_hc32(dma);
b504882d
LY		 869 last_dtd->next_td_virt = dtd;
870 }
871 last_dtd = dtd;
872
873 req->dtd_count++;
874 } while (!is_last);
875
09ba0def 876 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
b504882d
LY		 877
878 req->tail = dtd;
879
880 return 0;
881}
882
883/* queues (submits) an I/O request to an endpoint */
884static int
885fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
886{
887 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
888 struct fsl_req *req = container_of(_req, struct fsl_req, req);
889 struct fsl_udc *udc;
890 unsigned long flags;
b504882d
LY		 891
892 /* catch various bogus parameters */
893 if (!_req || !req->req.complete || !req->req.buf
894 || !list_empty(&req->queue)) {
bf7409a2 895 VDBG("%s, bad params", __func__);
b504882d
LY		 896 return -EINVAL;
897 }
79149b8b 898 if (unlikely(!_ep || !ep->ep.desc)) {
bf7409a2 899 VDBG("%s, bad ep", __func__);
b504882d
LY		 900 return -EINVAL;
901 }
79149b8b 902 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
b504882d
LY		 903 if (req->req.length > ep->ep.maxpacket)
904 return -EMSGSIZE;
b504882d
LY		 905 }
906
907 udc = ep->udc;
908 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
909 return -ESHUTDOWN;
910
911 req->ep = ep;
912
913 /* map virtual address to hardware */
914 if (req->req.dma == DMA_ADDR_INVALID) {
915 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
916 req->req.buf,
917 req->req.length, ep_is_in(ep)
918 ? DMA_TO_DEVICE
919 : DMA_FROM_DEVICE);
920 req->mapped = 1;
921 } else {
922 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
923 req->req.dma, req->req.length,
924 ep_is_in(ep)
925 ? DMA_TO_DEVICE
926 : DMA_FROM_DEVICE);
927 req->mapped = 0;
928 }
929
930 req->req.status = -EINPROGRESS;
931 req->req.actual = 0;
932 req->dtd_count = 0;
933
b504882d 934 /* build dtds and push them to device queue */
c5cc5ed8
PC		 935 if (!fsl_req_to_dtd(req, gfp_flags)) {
936 spin_lock_irqsave(&udc->lock, flags);
b504882d
LY		 937 fsl_queue_td(ep, req);
938 } else {
b504882d
LY		 939 return -ENOMEM;
940 }
941
b504882d
LY		 942 /* irq handler advances the queue */
943 if (req != NULL)
944 list_add_tail(&req->queue, &ep->queue);
945 spin_unlock_irqrestore(&udc->lock, flags);
946
947 return 0;
948}
949
950/* dequeues (cancels, unlinks) an I/O request from an endpoint */
951static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
952{
953 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
954 struct fsl_req *req;
955 unsigned long flags;
956 int ep_num, stopped, ret = 0;
957 u32 epctrl;
958
959 if (!_ep || !_req)
960 return -EINVAL;
961
962 spin_lock_irqsave(&ep->udc->lock, flags);
963 stopped = ep->stopped;
964
965 /* Stop the ep before we deal with the queue */
966 ep->stopped = 1;
967 ep_num = ep_index(ep);
968 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
969 if (ep_is_in(ep))
970 epctrl &= ~EPCTRL_TX_ENABLE;
971 else
972 epctrl &= ~EPCTRL_RX_ENABLE;
973 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
974
975 /* make sure it's actually queued on this endpoint */
976 list_for_each_entry(req, &ep->queue, queue) {
977 if (&req->req == _req)
978 break;
979 }
980 if (&req->req != _req) {
981 ret = -EINVAL;
982 goto out;
983 }
984
985 /* The request is in progress, or completed but not dequeued */
986 if (ep->queue.next == &req->queue) {
987 _req->status = -ECONNRESET;
988 fsl_ep_fifo_flush(_ep); /* flush current transfer */
989
990 /* The request isn't the last request in this ep queue */
991 if (req->queue.next != &ep->queue) {
b504882d
LY		 992 struct fsl_req *next_req;
993
b504882d
LY		 994 next_req = list_entry(req->queue.next, struct fsl_req,
995 queue);
996
6414e94c
LY		 997 /* prime with dTD of next request */
998 fsl_prime_ep(ep, next_req->head);
b504882d 999 }
6414e94c 1000 /* The request hasn't been processed, patch up the TD chain */
b504882d
LY		 1001 } else {
1002 struct fsl_req *prev_req;
1003
1004 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
6414e94c 1005 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
b504882d
LY		 1006 }
1007
1008 done(ep, req, -ECONNRESET);
1009
1010 /* Enable EP */
1011out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1012 if (ep_is_in(ep))
1013 epctrl |= EPCTRL_TX_ENABLE;
1014 else
1015 epctrl |= EPCTRL_RX_ENABLE;
1016 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1017 ep->stopped = stopped;
1018
1019 spin_unlock_irqrestore(&ep->udc->lock, flags);
1020 return ret;
1021}
1022
1023/*-------------------------------------------------------------------------*/
1024
1025/*-----------------------------------------------------------------
1026 * modify the endpoint halt feature
1027 * @ep: the non-isochronous endpoint being stalled
1028 * @value: 1--set halt 0--clear halt
1029 * Returns zero, or a negative error code.
1030*----------------------------------------------------------------*/
1031static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1032{
1033 struct fsl_ep *ep = NULL;
1034 unsigned long flags = 0;
1035 int status = -EOPNOTSUPP; /* operation not supported */
1036 unsigned char ep_dir = 0, ep_num = 0;
1037 struct fsl_udc *udc = NULL;
1038
1039 ep = container_of(_ep, struct fsl_ep, ep);
1040 udc = ep->udc;
79149b8b 1041 if (!_ep || !ep->ep.desc) {
b504882d
LY		 1042 status = -EINVAL;
1043 goto out;
1044 }
1045
79149b8b 1046 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
b504882d
LY		 1047 status = -EOPNOTSUPP;
1048 goto out;
1049 }
1050
1051 /* Attempt to halt IN ep will fail if any transfer requests
1052 * are still queue */
1053 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1054 status = -EAGAIN;
1055 goto out;
1056 }
1057
1058 status = 0;
1059 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1060 ep_num = (unsigned char)(ep_index(ep));
1061 spin_lock_irqsave(&ep->udc->lock, flags);
1062 dr_ep_change_stall(ep_num, ep_dir, value);
1063 spin_unlock_irqrestore(&ep->udc->lock, flags);
1064
1065 if (ep_index(ep) == 0) {
1066 udc->ep0_state = WAIT_FOR_SETUP;
1067 udc->ep0_dir = 0;
1068 }
1069out:
1070 VDBG(" %s %s halt stat %d", ep->ep.name,
1071 value ? "set" : "clear", status);
1072
1073 return status;
1074}
1075
2ea6698d
AG		 1076static int fsl_ep_fifo_status(struct usb_ep *_ep)
1077{
1078 struct fsl_ep *ep;
1079 struct fsl_udc *udc;
1080 int size = 0;
1081 u32 bitmask;
6414e94c 1082 struct ep_queue_head *qh;
2ea6698d
AG		 1083
1084 ep = container_of(_ep, struct fsl_ep, ep);
79149b8b 1085 if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
2ea6698d
AG		 1086 return -ENODEV;
1087
1088 udc = (struct fsl_udc *)ep->udc;
1089
1090 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1091 return -ESHUTDOWN;
1092
6414e94c 1093 qh = get_qh_by_ep(ep);
2ea6698d
AG		 1094
1095 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1096 (1 << (ep_index(ep)));
1097
1098 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
6414e94c 1099 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
2ea6698d
AG		 1100 >> DTD_LENGTH_BIT_POS;
1101
1102 pr_debug("%s %u\n", __func__, size);
1103 return size;
1104}
1105
b504882d
LY		 1106static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1107{
1108 struct fsl_ep *ep;
1109 int ep_num, ep_dir;
1110 u32 bits;
1111 unsigned long timeout;
1112#define FSL_UDC_FLUSH_TIMEOUT 1000
1113
1114 if (!_ep) {
1115 return;
1116 } else {
1117 ep = container_of(_ep, struct fsl_ep, ep);
79149b8b 1118 if (!ep->ep.desc)
b504882d
LY		 1119 return;
1120 }
1121 ep_num = ep_index(ep);
1122 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1123
1124 if (ep_num == 0)
1125 bits = (1 << 16) | 1;
1126 else if (ep_dir == USB_SEND)
1127 bits = 1 << (16 + ep_num);
1128 else
1129 bits = 1 << ep_num;
1130
1131 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1132 do {
1133 fsl_writel(bits, &dr_regs->endptflush);
1134
1135 /* Wait until flush complete */
1136 while (fsl_readl(&dr_regs->endptflush)) {
1137 if (time_after(jiffies, timeout)) {
1138 ERR("ep flush timeout\n");
1139 return;
1140 }
1141 cpu_relax();
1142 }
1143 /* See if we need to flush again */
1144 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1145}
1146
1147static struct usb_ep_ops fsl_ep_ops = {
1148 .enable = fsl_ep_enable,
1149 .disable = fsl_ep_disable,
1150
1151 .alloc_request = fsl_alloc_request,
1152 .free_request = fsl_free_request,
1153
b504882d
LY		 1154 .queue = fsl_ep_queue,
1155 .dequeue = fsl_ep_dequeue,
1156
1157 .set_halt = fsl_ep_set_halt,
2ea6698d 1158 .fifo_status = fsl_ep_fifo_status,
b504882d
LY		 1159 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1160};
1161
1162/*-------------------------------------------------------------------------
1163 Gadget Driver Layer Operations
1164-------------------------------------------------------------------------*/
1165
1166/*----------------------------------------------------------------------
1167 * Get the current frame number (from DR frame_index Reg )
1168 *----------------------------------------------------------------------*/
1169static int fsl_get_frame(struct usb_gadget *gadget)
1170{
1171 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1172}
1173
1174/*-----------------------------------------------------------------------
1175 * Tries to wake up the host connected to this gadget
1176 -----------------------------------------------------------------------*/
1177static int fsl_wakeup(struct usb_gadget *gadget)
1178{
1179 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1180 u32 portsc;
1181
1182 /* Remote wakeup feature not enabled by host */
1183 if (!udc->remote_wakeup)
1184 return -ENOTSUPP;
1185
1186 portsc = fsl_readl(&dr_regs->portsc1);
1187 /* not suspended? */
1188 if (!(portsc & PORTSCX_PORT_SUSPEND))
1189 return 0;
1190 /* trigger force resume */
1191 portsc |= PORTSCX_PORT_FORCE_RESUME;
1192 fsl_writel(portsc, &dr_regs->portsc1);
1193 return 0;
1194}
1195
1196static int can_pullup(struct fsl_udc *udc)
1197{
1198 return udc->driver && udc->softconnect && udc->vbus_active;
1199}
1200
1201/* Notify controller that VBUS is powered, Called by whatever
1202 detects VBUS sessions */
1203static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1204{
1205 struct fsl_udc *udc;
1206 unsigned long flags;
1207
1208 udc = container_of(gadget, struct fsl_udc, gadget);
1209 spin_lock_irqsave(&udc->lock, flags);
bf7409a2 1210 VDBG("VBUS %s", is_active ? "on" : "off");
b504882d
LY		 1211 udc->vbus_active = (is_active != 0);
1212 if (can_pullup(udc))
1213 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1214 &dr_regs->usbcmd);
1215 else
1216 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1217 &dr_regs->usbcmd);
1218 spin_unlock_irqrestore(&udc->lock, flags);
1219 return 0;
1220}
1221
1222/* constrain controller's VBUS power usage
1223 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1224 * reporting how much power the device may consume. For example, this
1225 * could affect how quickly batteries are recharged.
1226 *
1227 * Returns zero on success, else negative errno.
1228 */
1229static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1230{
b504882d
LY		 1231 struct fsl_udc *udc;
1232
1233 udc = container_of(gadget, struct fsl_udc, gadget);
ded017ee 1234 if (!IS_ERR_OR_NULL(udc->transceiver))
b96d3b08 1235 return usb_phy_set_power(udc->transceiver, mA);
b504882d
LY		 1236 return -ENOTSUPP;
1237}
1238
1239/* Change Data+ pullup status
1240 * this func is used by usb_gadget_connect/disconnet
1241 */
1242static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1243{
1244 struct fsl_udc *udc;
1245
1246 udc = container_of(gadget, struct fsl_udc, gadget);
1247 udc->softconnect = (is_on != 0);
1248 if (can_pullup(udc))
1249 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1250 &dr_regs->usbcmd);
1251 else
1252 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1253 &dr_regs->usbcmd);
1254
1255 return 0;
1256}
1257
0f91349b 1258static int fsl_start(struct usb_gadget_driver *driver,
ffe0b335 1259 int (*bind)(struct usb_gadget *, struct usb_gadget_driver *));
0f91349b 1260static int fsl_stop(struct usb_gadget_driver *driver);
9454a57a 1261/* defined in gadget.h */
b504882d
LY		 1262static struct usb_gadget_ops fsl_gadget_ops = {
1263 .get_frame = fsl_get_frame,
1264 .wakeup = fsl_wakeup,
1265/* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1266 .vbus_session = fsl_vbus_session,
1267 .vbus_draw = fsl_vbus_draw,
1268 .pullup = fsl_pullup,
0f91349b
SAS		 1269 .start = fsl_start,
1270 .stop = fsl_stop,
b504882d
LY		 1271};
1272
1273/* Set protocol stall on ep0, protocol stall will automatically be cleared
1274 on new transaction */
1275static void ep0stall(struct fsl_udc *udc)
1276{
1277 u32 tmp;
1278
1279 /* must set tx and rx to stall at the same time */
1280 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1281 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1282 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1283 udc->ep0_state = WAIT_FOR_SETUP;
1284 udc->ep0_dir = 0;
1285}
1286
1287/* Prime a status phase for ep0 */
1288static int ep0_prime_status(struct fsl_udc *udc, int direction)
1289{
1290 struct fsl_req *req = udc->status_req;
1291 struct fsl_ep *ep;
b504882d
LY		 1292
1293 if (direction == EP_DIR_IN)
1294 udc->ep0_dir = USB_DIR_IN;
1295 else
1296 udc->ep0_dir = USB_DIR_OUT;
1297
1298 ep = &udc->eps[0];
f79a60b8
PC		 1299 if (udc->ep0_state != DATA_STATE_XMIT)
1300 udc->ep0_state = WAIT_FOR_OUT_STATUS;
b504882d
LY		 1301
1302 req->ep = ep;
1303 req->req.length = 0;
1304 req->req.status = -EINPROGRESS;
1305 req->req.actual = 0;
1306 req->req.complete = NULL;
1307 req->dtd_count = 0;
1308
3140d5b2
AG		 1309 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1310 req->req.buf, req->req.length,
1311 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1312 req->mapped = 1;
1313
c5cc5ed8 1314 if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
224b5039 1315 fsl_queue_td(ep, req);
b504882d
LY		 1316 else
1317 return -ENOMEM;
1318
b504882d
LY		 1319 list_add_tail(&req->queue, &ep->queue);
1320
224b5039 1321 return 0;
b504882d
LY		 1322}
1323
825bee3a 1324static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
b504882d
LY		 1325{
1326 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1327
825bee3a
WN		 1328 if (ep->name)
1329 nuke(ep, -ESHUTDOWN);
b504882d
LY		 1330}
1331
1332/*
1333 * ch9 Set address
1334 */
1335static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1336{
1337 /* Save the new address to device struct */
1338 udc->device_address = (u8) value;
1339 /* Update usb state */
1340 udc->usb_state = USB_STATE_ADDRESS;
1341 /* Status phase */
1342 if (ep0_prime_status(udc, EP_DIR_IN))
1343 ep0stall(udc);
1344}
1345
1346/*
1347 * ch9 Get status
1348 */
1349static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1350 u16 index, u16 length)
1351{
1352 u16 tmp = 0; /* Status, cpu endian */
b504882d
LY		 1353 struct fsl_req *req;
1354 struct fsl_ep *ep;
b504882d
LY		 1355
1356 ep = &udc->eps[0];
1357
1358 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1359 /* Get device status */
1360 tmp = 1 << USB_DEVICE_SELF_POWERED;
1361 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1362 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1363 /* Get interface status */
1364 /* We don't have interface information in udc driver */
1365 tmp = 0;
1366 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1367 /* Get endpoint status */
1368 struct fsl_ep *target_ep;
1369
1370 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1371
1372 /* stall if endpoint doesn't exist */
79149b8b 1373 if (!target_ep->ep.desc)
b504882d
LY		 1374 goto stall;
1375 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1376 << USB_ENDPOINT_HALT;
1377 }
1378
1379 udc->ep0_dir = USB_DIR_IN;
1380 /* Borrow the per device status_req */
1381 req = udc->status_req;
1382 /* Fill in the reqest structure */
1383 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
2ea6698d 1384
b504882d
LY		 1385 req->ep = ep;
1386 req->req.length = 2;
1387 req->req.status = -EINPROGRESS;
1388 req->req.actual = 0;
1389 req->req.complete = NULL;
1390 req->dtd_count = 0;
1391
3140d5b2
AG		 1392 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1393 req->req.buf, req->req.length,
1394 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1395 req->mapped = 1;
1396
b504882d 1397 /* prime the data phase */
c5cc5ed8 1398 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
224b5039 1399 fsl_queue_td(ep, req);
b504882d
LY		 1400 else /* no mem */
1401 goto stall;
1402
b504882d
LY		 1403 list_add_tail(&req->queue, &ep->queue);
1404 udc->ep0_state = DATA_STATE_XMIT;
f79a60b8
PC		 1405 if (ep0_prime_status(udc, EP_DIR_OUT))
1406 ep0stall(udc);
1407
b504882d
LY		 1408 return;
1409stall:
1410 ep0stall(udc);
1411}
1412
1413static void setup_received_irq(struct fsl_udc *udc,
1414 struct usb_ctrlrequest *setup)
1415{
1416 u16 wValue = le16_to_cpu(setup->wValue);
1417 u16 wIndex = le16_to_cpu(setup->wIndex);
1418 u16 wLength = le16_to_cpu(setup->wLength);
1419
1420 udc_reset_ep_queue(udc, 0);
1421
39d1f8c9 1422 /* We process some stardard setup requests here */
b504882d 1423 switch (setup->bRequest) {
b504882d 1424 case USB_REQ_GET_STATUS:
39d1f8c9
LY		 1425 /* Data+Status phase from udc */
1426 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
b504882d
LY		 1427 != (USB_DIR_IN | USB_TYPE_STANDARD))
1428 break;
1429 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
39d1f8c9 1430 return;
b504882d 1431
b504882d 1432 case USB_REQ_SET_ADDRESS:
39d1f8c9 1433 /* Status phase from udc */
b504882d
LY		 1434 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1435 | USB_RECIP_DEVICE))
1436 break;
1437 ch9setaddress(udc, wValue, wIndex, wLength);
39d1f8c9 1438 return;
b504882d 1439
b504882d
LY		 1440 case USB_REQ_CLEAR_FEATURE:
1441 case USB_REQ_SET_FEATURE:
39d1f8c9
LY		 1442 /* Status phase from udc */
1443 {
b504882d 1444 int rc = -EOPNOTSUPP;
2ea6698d 1445 u16 ptc = 0;
b504882d 1446
39d1f8c9
LY		 1447 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1448 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
b504882d
LY		 1449 int pipe = get_pipe_by_windex(wIndex);
1450 struct fsl_ep *ep;
1451
118d63f7 1452 if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
b504882d
LY		 1453 break;
1454 ep = get_ep_by_pipe(udc, pipe);
1455
1456 spin_unlock(&udc->lock);
1457 rc = fsl_ep_set_halt(&ep->ep,
1458 (setup->bRequest == USB_REQ_SET_FEATURE)
1459 ? 1 : 0);
1460 spin_lock(&udc->lock);
1461
39d1f8c9
LY		 1462 } else if ((setup->bRequestType & (USB_RECIP_MASK
1463 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1464 | USB_TYPE_STANDARD)) {
b504882d
LY		 1465 /* Note: The driver has not include OTG support yet.
1466 * This will be set when OTG support is added */
2ea6698d
AG		 1467 if (wValue == USB_DEVICE_TEST_MODE)
1468 ptc = wIndex >> 8;
1469 else if (gadget_is_otg(&udc->gadget)) {
1470 if (setup->bRequest ==
1471 USB_DEVICE_B_HNP_ENABLE)
1472 udc->gadget.b_hnp_enable = 1;
1473 else if (setup->bRequest ==
1474 USB_DEVICE_A_HNP_SUPPORT)
1475 udc->gadget.a_hnp_support = 1;
1476 else if (setup->bRequest ==
1477 USB_DEVICE_A_ALT_HNP_SUPPORT)
1478 udc->gadget.a_alt_hnp_support = 1;
1479 }
b504882d 1480 rc = 0;
39d1f8c9
LY		 1481 } else
1482 break;
1483
b504882d
LY		 1484 if (rc == 0) {
1485 if (ep0_prime_status(udc, EP_DIR_IN))
1486 ep0stall(udc);
1487 }
2ea6698d
AG		 1488 if (ptc) {
1489 u32 tmp;
1490
1491 mdelay(10);
1492 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1493 fsl_writel(tmp, &dr_regs->portsc1);
1494 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1495 }
1496
39d1f8c9 1497 return;
b504882d 1498 }
b504882d 1499
39d1f8c9 1500 default:
b504882d
LY		 1501 break;
1502 }
39d1f8c9
LY		 1503
1504 /* Requests handled by gadget */
1505 if (wLength) {
1506 /* Data phase from gadget, status phase from udc */
1507 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1508 ? USB_DIR_IN : USB_DIR_OUT;
1509 spin_unlock(&udc->lock);
1510 if (udc->driver->setup(&udc->gadget,
1511 &udc->local_setup_buff) < 0)
1512 ep0stall(udc);
1513 spin_lock(&udc->lock);
1514 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1515 ? DATA_STATE_XMIT : DATA_STATE_RECV;
f79a60b8
PC		 1516 /*
1517 * If the data stage is IN, send status prime immediately.
1518 * See 2.0 Spec chapter 8.5.3.3 for detail.
1519 */
1520 if (udc->ep0_state == DATA_STATE_XMIT)
1521 if (ep0_prime_status(udc, EP_DIR_OUT))
1522 ep0stall(udc);
1523
39d1f8c9
LY		 1524 } else {
1525 /* No data phase, IN status from gadget */
1526 udc->ep0_dir = USB_DIR_IN;
1527 spin_unlock(&udc->lock);
1528 if (udc->driver->setup(&udc->gadget,
1529 &udc->local_setup_buff) < 0)
1530 ep0stall(udc);
1531 spin_lock(&udc->lock);
1532 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1533 }
b504882d
LY		 1534}
1535
1536/* Process request for Data or Status phase of ep0
1537 * prime status phase if needed */
1538static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1539 struct fsl_req *req)
1540{
1541 if (udc->usb_state == USB_STATE_ADDRESS) {
1542 /* Set the new address */
1543 u32 new_address = (u32) udc->device_address;
1544 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1545 &dr_regs->deviceaddr);
1546 }
1547
1548 done(ep0, req, 0);
1549
1550 switch (udc->ep0_state) {
1551 case DATA_STATE_XMIT:
f79a60b8
PC		 1552 /* already primed at setup_received_irq */
1553 udc->ep0_state = WAIT_FOR_OUT_STATUS;
b504882d
LY		 1554 break;
1555 case DATA_STATE_RECV:
1556 /* send status phase */
1557 if (ep0_prime_status(udc, EP_DIR_IN))
1558 ep0stall(udc);
1559 break;
1560 case WAIT_FOR_OUT_STATUS:
1561 udc->ep0_state = WAIT_FOR_SETUP;
1562 break;
1563 case WAIT_FOR_SETUP:
bf7409a2 1564 ERR("Unexpect ep0 packets\n");
b504882d
LY		 1565 break;
1566 default:
1567 ep0stall(udc);
1568 break;
1569 }
1570}
1571
1572/* Tripwire mechanism to ensure a setup packet payload is extracted without
1573 * being corrupted by another incoming setup packet */
1574static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1575{
1576 u32 temp;
1577 struct ep_queue_head *qh;
09ba0def 1578 struct fsl_usb2_platform_data *pdata = udc->pdata;
b504882d
LY		 1579
1580 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1581
1582 /* Clear bit in ENDPTSETUPSTAT */
1583 temp = fsl_readl(&dr_regs->endptsetupstat);
1584 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1585
1586 /* while a hazard exists when setup package arrives */
1587 do {
1588 /* Set Setup Tripwire */
1589 temp = fsl_readl(&dr_regs->usbcmd);
1590 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1591
1592 /* Copy the setup packet to local buffer */
09ba0def
AG		 1593 if (pdata->le_setup_buf) {
1594 u32 *p = (u32 *)buffer_ptr;
1595 u32 *s = (u32 *)qh->setup_buffer;
1596
1597 /* Convert little endian setup buffer to CPU endian */
1598 *p++ = le32_to_cpu(*s++);
1599 *p = le32_to_cpu(*s);
1600 } else {
1601 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1602 }
b504882d
LY		 1603 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1604
1605 /* Clear Setup Tripwire */
1606 temp = fsl_readl(&dr_regs->usbcmd);
1607 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1608}
1609
1610/* process-ep_req(): free the completed Tds for this req */
1611static int process_ep_req(struct fsl_udc *udc, int pipe,
1612 struct fsl_req *curr_req)
1613{
1614 struct ep_td_struct *curr_td;
1615 int td_complete, actual, remaining_length, j, tmp;
1616 int status = 0;
1617 int errors = 0;
1618 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1619 int direction = pipe % 2;
1620
1621 curr_td = curr_req->head;
1622 td_complete = 0;
1623 actual = curr_req->req.length;
1624
1625 for (j = 0; j < curr_req->dtd_count; j++) {
09ba0def 1626 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
b504882d
LY		 1627 & DTD_PACKET_SIZE)
1628 >> DTD_LENGTH_BIT_POS;
1629 actual -= remaining_length;
1630
09ba0def
AG		 1631 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1632 if (errors & DTD_ERROR_MASK) {
b504882d
LY		 1633 if (errors & DTD_STATUS_HALTED) {
1634 ERR("dTD error %08x QH=%d\n", errors, pipe);
1635 /* Clear the errors and Halt condition */
09ba0def 1636 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
b504882d 1637 tmp &= ~errors;
09ba0def 1638 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
b504882d
LY		 1639 status = -EPIPE;
1640 /* FIXME: continue with next queued TD? */
1641
1642 break;
1643 }
1644 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1645 VDBG("Transfer overflow");
1646 status = -EPROTO;
1647 break;
1648 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1649 VDBG("ISO error");
1650 status = -EILSEQ;
1651 break;
1652 } else
25985edc 1653 ERR("Unknown error has occurred (0x%x)!\n",
b504882d
LY		 1654 errors);
1655
09ba0def 1656 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
b504882d
LY		 1657 & DTD_STATUS_ACTIVE) {
1658 VDBG("Request not complete");
1659 status = REQ_UNCOMPLETE;
1660 return status;
1661 } else if (remaining_length) {
1662 if (direction) {
1663 VDBG("Transmit dTD remaining length not zero");
1664 status = -EPROTO;
1665 break;
1666 } else {
1667 td_complete++;
1668 break;
1669 }
1670 } else {
1671 td_complete++;
bf7409a2 1672 VDBG("dTD transmitted successful");
b504882d
LY		 1673 }
1674
1675 if (j != curr_req->dtd_count - 1)
1676 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1677 }
1678
1679 if (status)
1680 return status;
1681
1682 curr_req->req.actual = actual;
1683
1684 return 0;
1685}
1686
1687/* Process a DTD completion interrupt */
1688static void dtd_complete_irq(struct fsl_udc *udc)
1689{
1690 u32 bit_pos;
1691 int i, ep_num, direction, bit_mask, status;
1692 struct fsl_ep *curr_ep;
1693 struct fsl_req *curr_req, *temp_req;
1694
1695 /* Clear the bits in the register */
1696 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1697 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1698
1699 if (!bit_pos)
1700 return;
1701
118d63f7 1702 for (i = 0; i < udc->max_ep; i++) {
b504882d
LY		 1703 ep_num = i >> 1;
1704 direction = i % 2;
1705
1706 bit_mask = 1 << (ep_num + 16 * direction);
1707
1708 if (!(bit_pos & bit_mask))
1709 continue;
1710
1711 curr_ep = get_ep_by_pipe(udc, i);
1712
1713 /* If the ep is configured */
1714 if (curr_ep->name == NULL) {
b6c63937 1715 WARNING("Invalid EP?");
b504882d
LY		 1716 continue;
1717 }
1718
1719 /* process the req queue until an uncomplete request */
1720 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1721 queue) {
1722 status = process_ep_req(udc, i, curr_req);
1723
1724 VDBG("status of process_ep_req= %d, ep = %d",
1725 status, ep_num);
1726 if (status == REQ_UNCOMPLETE)
1727 break;
1728 /* write back status to req */
1729 curr_req->req.status = status;
1730
1731 if (ep_num == 0) {
1732 ep0_req_complete(udc, curr_ep, curr_req);
1733 break;
1734 } else
1735 done(curr_ep, curr_req, status);
1736 }
1737 }
1738}
1739
e538dfda
MN		 1740static inline enum usb_device_speed portscx_device_speed(u32 reg)
1741{
0e042be3 1742 switch (reg & PORTSCX_PORT_SPEED_MASK) {
e538dfda
MN		 1743 case PORTSCX_PORT_SPEED_HIGH:
1744 return USB_SPEED_HIGH;
1745 case PORTSCX_PORT_SPEED_FULL:
1746 return USB_SPEED_FULL;
1747 case PORTSCX_PORT_SPEED_LOW:
1748 return USB_SPEED_LOW;
1749 default:
1750 return USB_SPEED_UNKNOWN;
1751 }
1752}
1753
b504882d
LY		 1754/* Process a port change interrupt */
1755static void port_change_irq(struct fsl_udc *udc)
1756{
83722bc9
AG		 1757 if (udc->bus_reset)
1758 udc->bus_reset = 0;
1759
b504882d 1760 /* Bus resetting is finished */
e538dfda 1761 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
b504882d 1762 /* Get the speed */
e538dfda
MN		 1763 udc->gadget.speed =
1764 portscx_device_speed(fsl_readl(&dr_regs->portsc1));
b504882d
LY		 1765
1766 /* Update USB state */
1767 if (!udc->resume_state)
1768 udc->usb_state = USB_STATE_DEFAULT;
1769}
1770
1771/* Process suspend interrupt */
1772static void suspend_irq(struct fsl_udc *udc)
1773{
1774 udc->resume_state = udc->usb_state;
1775 udc->usb_state = USB_STATE_SUSPENDED;
1776
1777 /* report suspend to the driver, serial.c does not support this */
1778 if (udc->driver->suspend)
1779 udc->driver->suspend(&udc->gadget);
1780}
1781
1782static void bus_resume(struct fsl_udc *udc)
1783{
1784 udc->usb_state = udc->resume_state;
1785 udc->resume_state = 0;
1786
1787 /* report resume to the driver, serial.c does not support this */
1788 if (udc->driver->resume)
1789 udc->driver->resume(&udc->gadget);
1790}
1791
1792/* Clear up all ep queues */
1793static int reset_queues(struct fsl_udc *udc)
1794{
1795 u8 pipe;
1796
1797 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1798 udc_reset_ep_queue(udc, pipe);
1799
1800 /* report disconnect; the driver is already quiesced */
185e3dea 1801 spin_unlock(&udc->lock);
b504882d 1802 udc->driver->disconnect(&udc->gadget);
185e3dea 1803 spin_lock(&udc->lock);
b504882d
LY		 1804
1805 return 0;
1806}
1807
1808/* Process reset interrupt */
1809static void reset_irq(struct fsl_udc *udc)
1810{
1811 u32 temp;
1812 unsigned long timeout;
1813
1814 /* Clear the device address */
1815 temp = fsl_readl(&dr_regs->deviceaddr);
1816 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1817
1818 udc->device_address = 0;
1819
1820 /* Clear usb state */
1821 udc->resume_state = 0;
1822 udc->ep0_dir = 0;
1823 udc->ep0_state = WAIT_FOR_SETUP;
1824 udc->remote_wakeup = 0; /* default to 0 on reset */
1825 udc->gadget.b_hnp_enable = 0;
1826 udc->gadget.a_hnp_support = 0;
1827 udc->gadget.a_alt_hnp_support = 0;
1828
1829 /* Clear all the setup token semaphores */
1830 temp = fsl_readl(&dr_regs->endptsetupstat);
1831 fsl_writel(temp, &dr_regs->endptsetupstat);
1832
1833 /* Clear all the endpoint complete status bits */
1834 temp = fsl_readl(&dr_regs->endptcomplete);
1835 fsl_writel(temp, &dr_regs->endptcomplete);
1836
1837 timeout = jiffies + 100;
1838 while (fsl_readl(&dr_regs->endpointprime)) {
1839 /* Wait until all endptprime bits cleared */
1840 if (time_after(jiffies, timeout)) {
1841 ERR("Timeout for reset\n");
1842 break;
1843 }
1844 cpu_relax();
1845 }
1846
1847 /* Write 1s to the flush register */
1848 fsl_writel(0xffffffff, &dr_regs->endptflush);
1849
1850 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1851 VDBG("Bus reset");
83722bc9
AG		 1852 /* Bus is reseting */
1853 udc->bus_reset = 1;
b504882d
LY		 1854 /* Reset all the queues, include XD, dTD, EP queue
1855 * head and TR Queue */
1856 reset_queues(udc);
1857 udc->usb_state = USB_STATE_DEFAULT;
1858 } else {
1859 VDBG("Controller reset");
1860 /* initialize usb hw reg except for regs for EP, not
1861 * touch usbintr reg */
1862 dr_controller_setup(udc);
1863
1864 /* Reset all internal used Queues */
1865 reset_queues(udc);
1866
1867 ep0_setup(udc);
1868
1869 /* Enable DR IRQ reg, Set Run bit, change udc state */
1870 dr_controller_run(udc);
1871 udc->usb_state = USB_STATE_ATTACHED;
1872 }
1873}
1874
1875/*
1876 * USB device controller interrupt handler
1877 */
1878static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1879{
1880 struct fsl_udc *udc = _udc;
1881 u32 irq_src;
1882 irqreturn_t status = IRQ_NONE;
1883 unsigned long flags;
1884
1885 /* Disable ISR for OTG host mode */
1886 if (udc->stopped)
1887 return IRQ_NONE;
1888 spin_lock_irqsave(&udc->lock, flags);
1889 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1890 /* Clear notification bits */
1891 fsl_writel(irq_src, &dr_regs->usbsts);
1892
1893 /* VDBG("irq_src [0x%8x]", irq_src); */
1894
1895 /* Need to resume? */
1896 if (udc->usb_state == USB_STATE_SUSPENDED)
1897 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1898 bus_resume(udc);
1899
1900 /* USB Interrupt */
1901 if (irq_src & USB_STS_INT) {
1902 VDBG("Packet int");
1903 /* Setup package, we only support ep0 as control ep */
1904 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1905 tripwire_handler(udc, 0,
1906 (u8 *) (&udc->local_setup_buff));
1907 setup_received_irq(udc, &udc->local_setup_buff);
1908 status = IRQ_HANDLED;
1909 }
1910
1911 /* completion of dtd */
1912 if (fsl_readl(&dr_regs->endptcomplete)) {
1913 dtd_complete_irq(udc);
1914 status = IRQ_HANDLED;
1915 }
1916 }
1917
1918 /* SOF (for ISO transfer) */
1919 if (irq_src & USB_STS_SOF) {
1920 status = IRQ_HANDLED;
1921 }
1922
1923 /* Port Change */
1924 if (irq_src & USB_STS_PORT_CHANGE) {
1925 port_change_irq(udc);
1926 status = IRQ_HANDLED;
1927 }
1928
1929 /* Reset Received */
1930 if (irq_src & USB_STS_RESET) {
83722bc9 1931 VDBG("reset int");
b504882d
LY		 1932 reset_irq(udc);
1933 status = IRQ_HANDLED;
1934 }
1935
1936 /* Sleep Enable (Suspend) */
1937 if (irq_src & USB_STS_SUSPEND) {
1938 suspend_irq(udc);
1939 status = IRQ_HANDLED;
1940 }
1941
1942 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
bf7409a2 1943 VDBG("Error IRQ %x", irq_src);
b504882d
LY		 1944 }
1945
1946 spin_unlock_irqrestore(&udc->lock, flags);
1947 return status;
1948}
1949
1950/*----------------------------------------------------------------*
1951 * Hook to gadget drivers
1952 * Called by initialization code of gadget drivers
1953*----------------------------------------------------------------*/
0f91349b 1954static int fsl_start(struct usb_gadget_driver *driver,
ffe0b335 1955 int (*bind)(struct usb_gadget *, struct usb_gadget_driver *))
b504882d
LY		 1956{
1957 int retval = -ENODEV;
1958 unsigned long flags = 0;
1959
1960 if (!udc_controller)
1961 return -ENODEV;
1962
7177aed4 1963 if (!driver || driver->max_speed < USB_SPEED_FULL
b0fca50f 1964 || !bind || !driver->disconnect || !driver->setup)
b504882d
LY		 1965 return -EINVAL;
1966
1967 if (udc_controller->driver)
1968 return -EBUSY;
1969
1970 /* lock is needed but whether should use this lock or another */
1971 spin_lock_irqsave(&udc_controller->lock, flags);
1972
7483cff8 1973 driver->driver.bus = NULL;
b504882d
LY		 1974 /* hook up the driver */
1975 udc_controller->driver = driver;
1976 udc_controller->gadget.dev.driver = &driver->driver;
1977 spin_unlock_irqrestore(&udc_controller->lock, flags);
1978
1979 /* bind udc driver to gadget driver */
ffe0b335 1980 retval = bind(&udc_controller->gadget, driver);
b504882d
LY		 1981 if (retval) {
1982 VDBG("bind to %s --> %d", driver->driver.name, retval);
7483cff8
WN		 1983 udc_controller->gadget.dev.driver = NULL;
1984 udc_controller->driver = NULL;
b504882d
LY		 1985 goto out;
1986 }
1987
ded017ee 1988 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
83722bc9
AG		 1989 /* Suspend the controller until OTG enable it */
1990 udc_controller->stopped = 1;
1991 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1992
1993 /* connect to bus through transceiver */
ded017ee 1994 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
6e13c650
HK		 1995 retval = otg_set_peripheral(
1996 udc_controller->transceiver->otg,
83722bc9
AG		 1997 &udc_controller->gadget);
1998 if (retval < 0) {
1999 ERR("can't bind to transceiver\n");
2000 driver->unbind(&udc_controller->gadget);
2001 udc_controller->gadget.dev.driver = 0;
2002 udc_controller->driver = 0;
2003 return retval;
2004 }
2005 }
2006 } else {
2007 /* Enable DR IRQ reg and set USBCMD reg Run bit */
2008 dr_controller_run(udc_controller);
2009 udc_controller->usb_state = USB_STATE_ATTACHED;
2010 udc_controller->ep0_state = WAIT_FOR_SETUP;
2011 udc_controller->ep0_dir = 0;
2012 }
bf7409a2 2013 printk(KERN_INFO "%s: bind to driver %s\n",
b504882d
LY		 2014 udc_controller->gadget.name, driver->driver.name);
2015
2016out:
2017 if (retval)
6f8aa65b
FS		 2018 printk(KERN_WARNING "gadget driver register failed %d\n",
2019 retval);
b504882d
LY		 2020 return retval;
2021}
b504882d
LY		 2022
2023/* Disconnect from gadget driver */
0f91349b 2024static int fsl_stop(struct usb_gadget_driver *driver)
b504882d
LY		 2025{
2026 struct fsl_ep *loop_ep;
2027 unsigned long flags;
2028
2029 if (!udc_controller)
2030 return -ENODEV;
2031
2032 if (!driver || driver != udc_controller->driver || !driver->unbind)
2033 return -EINVAL;
2034
ded017ee 2035 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
6e13c650 2036 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
b504882d
LY		 2037
2038 /* stop DR, disable intr */
2039 dr_controller_stop(udc_controller);
2040
2041 /* in fact, no needed */
2042 udc_controller->usb_state = USB_STATE_ATTACHED;
2043 udc_controller->ep0_state = WAIT_FOR_SETUP;
2044 udc_controller->ep0_dir = 0;
2045
2046 /* stand operation */
2047 spin_lock_irqsave(&udc_controller->lock, flags);
2048 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2049 nuke(&udc_controller->eps[0], -ESHUTDOWN);
2050 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2051 ep.ep_list)
2052 nuke(loop_ep, -ESHUTDOWN);
2053 spin_unlock_irqrestore(&udc_controller->lock, flags);
2054
1f15a506
AV		 2055 /* report disconnect; the controller is already quiesced */
2056 driver->disconnect(&udc_controller->gadget);
2057
b504882d
LY		 2058 /* unbind gadget and unhook driver. */
2059 driver->unbind(&udc_controller->gadget);
7483cff8
WN		 2060 udc_controller->gadget.dev.driver = NULL;
2061 udc_controller->driver = NULL;
b504882d 2062
6f8aa65b
FS		 2063 printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2064 driver->driver.name);
b504882d
LY		 2065 return 0;
2066}
b504882d
LY		 2067
2068/*-------------------------------------------------------------------------
2069 PROC File System Support
2070-------------------------------------------------------------------------*/
2071#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2072
2073#include <linux/seq_file.h>
2074
2075static const char proc_filename[] = "driver/fsl_usb2_udc";
2076
2077static int fsl_proc_read(char *page, char **start, off_t off, int count,
2078 int *eof, void *_dev)
2079{
2080 char *buf = page;
2081 char *next = buf;
2082 unsigned size = count;
2083 unsigned long flags;
2084 int t, i;
2085 u32 tmp_reg;
2086 struct fsl_ep *ep = NULL;
2087 struct fsl_req *req;
2088
2089 struct fsl_udc *udc = udc_controller;
2090 if (off != 0)
2091 return 0;
2092
2093 spin_lock_irqsave(&udc->lock, flags);
2094
dc0d5c1e 2095 /* ------basic driver information ---- */
b504882d
LY		 2096 t = scnprintf(next, size,
2097 DRIVER_DESC "\n"
2098 "%s version: %s\n"
2099 "Gadget driver: %s\n\n",
2100 driver_name, DRIVER_VERSION,
2101 udc->driver ? udc->driver->driver.name : "(none)");
2102 size -= t;
2103 next += t;
2104
2105 /* ------ DR Registers ----- */
2106 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2107 t = scnprintf(next, size,
2108 "USBCMD reg:\n"
2109 "SetupTW: %d\n"
2110 "Run/Stop: %s\n\n",
2111 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2112 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2113 size -= t;
2114 next += t;
2115
2116 tmp_reg = fsl_readl(&dr_regs->usbsts);
2117 t = scnprintf(next, size,
2118 "USB Status Reg:\n"
9d9d88c8 2119 "Dr Suspend: %d Reset Received: %d System Error: %s "
b504882d
LY		 2120 "USB Error Interrupt: %s\n\n",
2121 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2122 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2123 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2124 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2125 size -= t;
2126 next += t;
2127
2128 tmp_reg = fsl_readl(&dr_regs->usbintr);
2129 t = scnprintf(next, size,
984e833c 2130 "USB Interrupt Enable Reg:\n"
9d9d88c8 2131 "Sleep Enable: %d SOF Received Enable: %d "
b504882d 2132 "Reset Enable: %d\n"
9d9d88c8 2133 "System Error Enable: %d "
b504882d 2134 "Port Change Dectected Enable: %d\n"
9d9d88c8 2135 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
b504882d
LY		 2136 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2137 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2138 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2139 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2140 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2141 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2142 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2143 size -= t;
2144 next += t;
2145
2146 tmp_reg = fsl_readl(&dr_regs->frindex);
2147 t = scnprintf(next, size,
9d9d88c8 2148 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
b504882d
LY		 2149 (tmp_reg & USB_FRINDEX_MASKS));
2150 size -= t;
2151 next += t;
2152
2153 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2154 t = scnprintf(next, size,
9d9d88c8 2155 "USB Device Address Reg: Device Addr is 0x%x\n\n",
b504882d
LY		 2156 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2157 size -= t;
2158 next += t;
2159
2160 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2161 t = scnprintf(next, size,
9d9d88c8 2162 "USB Endpoint List Address Reg: "
b504882d
LY		 2163 "Device Addr is 0x%x\n\n",
2164 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2165 size -= t;
2166 next += t;
2167
2168 tmp_reg = fsl_readl(&dr_regs->portsc1);
2169 t = scnprintf(next, size,
2170 "USB Port Status&Control Reg:\n"
9d9d88c8
WN		 2171 "Port Transceiver Type : %s Port Speed: %s\n"
2172 "PHY Low Power Suspend: %s Port Reset: %s "
2173 "Port Suspend Mode: %s\n"
2174 "Over-current Change: %s "
b504882d 2175 "Port Enable/Disable Change: %s\n"
9d9d88c8 2176 "Port Enabled/Disabled: %s "
b504882d
LY		 2177 "Current Connect Status: %s\n\n", ( {
2178 char *s;
2179 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2180 case PORTSCX_PTS_UTMI:
2181 s = "UTMI"; break;
2182 case PORTSCX_PTS_ULPI:
2183 s = "ULPI "; break;
2184 case PORTSCX_PTS_FSLS:
2185 s = "FS/LS Serial"; break;
2186 default:
2187 s = "None"; break;
2188 }
e538dfda
MN		 2189 s;} ),
2190 usb_speed_string(portscx_device_speed(tmp_reg)),
b504882d
LY		 2191 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2192 "Normal PHY mode" : "Low power mode",
2193 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2194 "Not in Reset",
2195 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2196 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2197 "No",
2198 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2199 "Not change",
2200 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2201 "Not correct",
2202 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2203 "Attached" : "Not-Att");
2204 size -= t;
2205 next += t;
2206
2207 tmp_reg = fsl_readl(&dr_regs->usbmode);
2208 t = scnprintf(next, size,
9d9d88c8 2209 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
b504882d
LY		 2210 char *s;
2211 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2212 case USB_MODE_CTRL_MODE_IDLE:
2213 s = "Idle"; break;
2214 case USB_MODE_CTRL_MODE_DEVICE:
2215 s = "Device Controller"; break;
2216 case USB_MODE_CTRL_MODE_HOST:
2217 s = "Host Controller"; break;
2218 default:
2219 s = "None"; break;
2220 }
2221 s;
2222 } ));
2223 size -= t;
2224 next += t;
2225
2226 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2227 t = scnprintf(next, size,
9d9d88c8 2228 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
b504882d
LY		 2229 (tmp_reg & EP_SETUP_STATUS_MASK));
2230 size -= t;
2231 next += t;
2232
2233 for (i = 0; i < udc->max_ep / 2; i++) {
2234 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2235 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2236 i, tmp_reg);
2237 size -= t;
2238 next += t;
2239 }
2240 tmp_reg = fsl_readl(&dr_regs->endpointprime);
9d9d88c8 2241 t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
b504882d
LY		 2242 size -= t;
2243 next += t;
2244
54e4026b 2245#ifndef CONFIG_ARCH_MXC
2ea6698d
AG		 2246 if (udc->pdata->have_sysif_regs) {
2247 tmp_reg = usb_sys_regs->snoop1;
2248 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2249 size -= t;
2250 next += t;
b504882d 2251
2ea6698d
AG		 2252 tmp_reg = usb_sys_regs->control;
2253 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2254 tmp_reg);
2255 size -= t;
2256 next += t;
2257 }
54e4026b 2258#endif
b504882d
LY		 2259
2260 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2261 ep = &udc->eps[0];
2262 t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2263 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2264 size -= t;
2265 next += t;
2266
2267 if (list_empty(&ep->queue)) {
2268 t = scnprintf(next, size, "its req queue is empty\n\n");
2269 size -= t;
2270 next += t;
2271 } else {
2272 list_for_each_entry(req, &ep->queue, queue) {
2273 t = scnprintf(next, size,
9d9d88c8 2274 "req %p actual 0x%x length 0x%x buf %p\n",
b504882d
LY		 2275 &req->req, req->req.actual,
2276 req->req.length, req->req.buf);
2277 size -= t;
2278 next += t;
2279 }
2280 }
2281 /* other gadget->eplist ep */
2282 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
79149b8b 2283 if (ep->ep.desc) {
b504882d
LY		 2284 t = scnprintf(next, size,
2285 "\nFor %s Maxpkt is 0x%x "
2286 "index is 0x%x\n",
2287 ep->ep.name, ep_maxpacket(ep),
2288 ep_index(ep));
2289 size -= t;
2290 next += t;
2291
2292 if (list_empty(&ep->queue)) {
2293 t = scnprintf(next, size,
2294 "its req queue is empty\n\n");
2295 size -= t;
2296 next += t;
2297 } else {
2298 list_for_each_entry(req, &ep->queue, queue) {
2299 t = scnprintf(next, size,
9d9d88c8 2300 "req %p actual 0x%x length "
b504882d
LY		 2301 "0x%x buf %p\n",
2302 &req->req, req->req.actual,
2303 req->req.length, req->req.buf);
2304 size -= t;
2305 next += t;
2306 } /* end for each_entry of ep req */
2307 } /* end for else */
2308 } /* end for if(ep->queue) */
2309 } /* end (ep->desc) */
2310
2311 spin_unlock_irqrestore(&udc->lock, flags);
2312
2313 *eof = 1;
2314 return count - size;
2315}
2316
2317#define create_proc_file() create_proc_read_entry(proc_filename, \
2318 0, NULL, fsl_proc_read, NULL)
2319
2320#define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2321
2322#else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2323
2324#define create_proc_file() do {} while (0)
2325#define remove_proc_file() do {} while (0)
2326
2327#endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2328
2329/*-------------------------------------------------------------------------*/
2330
2331/* Release udc structures */
2332static void fsl_udc_release(struct device *dev)
2333{
2334 complete(udc_controller->done);
37c4fd8c 2335 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
b504882d
LY		 2336 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2337 kfree(udc_controller);
2338}
2339
2340/******************************************************************
2341 Internal structure setup functions
2342*******************************************************************/
2343/*------------------------------------------------------------------
2344 * init resource for globle controller
2345 * Return the udc handle on success or NULL on failure
2346 ------------------------------------------------------------------*/
4365831d
LY		 2347static int __init struct_udc_setup(struct fsl_udc *udc,
2348 struct platform_device *pdev)
b504882d 2349{
b504882d
LY		 2350 struct fsl_usb2_platform_data *pdata;
2351 size_t size;
2352
b504882d
LY		 2353 pdata = pdev->dev.platform_data;
2354 udc->phy_mode = pdata->phy_mode;
b504882d
LY		 2355
2356 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2357 if (!udc->eps) {
2358 ERR("malloc fsl_ep failed\n");
4365831d 2359 return -1;
b504882d
LY		 2360 }
2361
2362 /* initialized QHs, take care of alignment */
2363 size = udc->max_ep * sizeof(struct ep_queue_head);
2364 if (size < QH_ALIGNMENT)
2365 size = QH_ALIGNMENT;
2366 else if ((size % QH_ALIGNMENT) != 0) {
2367 size += QH_ALIGNMENT + 1;
2368 size &= ~(QH_ALIGNMENT - 1);
2369 }
2370 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2371 &udc->ep_qh_dma, GFP_KERNEL);
2372 if (!udc->ep_qh) {
2373 ERR("malloc QHs for udc failed\n");
2374 kfree(udc->eps);
4365831d 2375 return -1;
b504882d
LY		 2376 }
2377
2378 udc->ep_qh_size = size;
2379
2380 /* Initialize ep0 status request structure */
2381 /* FIXME: fsl_alloc_request() ignores ep argument */
2382 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2383 struct fsl_req, req);
2384 /* allocate a small amount of memory to get valid address */
2385 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
b504882d
LY		 2386
2387 udc->resume_state = USB_STATE_NOTATTACHED;
2388 udc->usb_state = USB_STATE_POWERED;
2389 udc->ep0_dir = 0;
2390 udc->remote_wakeup = 0; /* default to 0 on reset */
b504882d 2391
4365831d 2392 return 0;
b504882d
LY		 2393}
2394
2395/*----------------------------------------------------------------
2396 * Setup the fsl_ep struct for eps
2397 * Link fsl_ep->ep to gadget->ep_list
2398 * ep0out is not used so do nothing here
2399 * ep0in should be taken care
2400 *--------------------------------------------------------------*/
2401static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2402 char *name, int link)
2403{
2404 struct fsl_ep *ep = &udc->eps[index];
2405
2406 ep->udc = udc;
2407 strcpy(ep->name, name);
2408 ep->ep.name = ep->name;
2409
2410 ep->ep.ops = &fsl_ep_ops;
2411 ep->stopped = 0;
2412
2413 /* for ep0: maxP defined in desc
2414 * for other eps, maxP is set by epautoconfig() called by gadget layer
2415 */
2416 ep->ep.maxpacket = (unsigned short) ~0;
2417
2418 /* the queue lists any req for this ep */
2419 INIT_LIST_HEAD(&ep->queue);
2420
2421 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2422 if (link)
2423 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2424 ep->gadget = &udc->gadget;
2425 ep->qh = &udc->ep_qh[index];
2426
2427 return 0;
2428}
2429
2430/* Driver probe function
4365831d
LY		 2431 * all intialization operations implemented here except enabling usb_intr reg
2432 * board setup should have been done in the platform code
b504882d
LY		 2433 */
2434static int __init fsl_udc_probe(struct platform_device *pdev)
2435{
09ba0def 2436 struct fsl_usb2_platform_data *pdata;
b504882d
LY		 2437 struct resource *res;
2438 int ret = -ENODEV;
2439 unsigned int i;
4365831d 2440 u32 dccparams;
b504882d 2441
4365831d
LY		 2442 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2443 if (udc_controller == NULL) {
2444 ERR("malloc udc failed\n");
b504882d
LY		 2445 return -ENOMEM;
2446 }
2447
09ba0def
AG		 2448 pdata = pdev->dev.platform_data;
2449 udc_controller->pdata = pdata;
e06da9a8
WN		 2450 spin_lock_init(&udc_controller->lock);
2451 udc_controller->stopped = 1;
2452
83722bc9
AG		 2453#ifdef CONFIG_USB_OTG
2454 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
662dca54 2455 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
ded017ee 2456 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
83722bc9
AG		 2457 ERR("Can't find OTG driver!\n");
2458 ret = -ENODEV;
2459 goto err_kfree;
2460 }
2461 }
2462#endif
2463
b504882d 2464 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4365831d 2465 if (!res) {
23d7cd04
WN		 2466 ret = -ENXIO;
2467 goto err_kfree;
4365831d 2468 }
b504882d 2469
83722bc9 2470 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
28f65c11 2471 if (!request_mem_region(res->start, resource_size(res),
83722bc9
AG		 2472 driver_name)) {
2473 ERR("request mem region for %s failed\n", pdev->name);
2474 ret = -EBUSY;
2475 goto err_kfree;
2476 }
b504882d
LY		 2477 }
2478
54e4026b 2479 dr_regs = ioremap(res->start, resource_size(res));
b504882d
LY		 2480 if (!dr_regs) {
2481 ret = -ENOMEM;
23d7cd04 2482 goto err_release_mem_region;
b504882d
LY		 2483 }
2484
2ea6698d
AG		 2485 pdata->regs = (void *)dr_regs;
2486
2487 /*
2488 * do platform specific init: check the clock, grab/config pins, etc.
2489 */
2490 if (pdata->init && pdata->init(pdev)) {
2491 ret = -ENODEV;
2492 goto err_iounmap_noclk;
2493 }
2494
2495 /* Set accessors only after pdata->init() ! */
3140d5b2 2496 fsl_set_accessors(pdata);
09ba0def 2497
54e4026b 2498#ifndef CONFIG_ARCH_MXC
2ea6698d 2499 if (pdata->have_sysif_regs)
8981d76a 2500 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
54e4026b
GL		 2501#endif
2502
2503 /* Initialize USB clocks */
2504 ret = fsl_udc_clk_init(pdev);
2505 if (ret < 0)
2506 goto err_iounmap_noclk;
b504882d 2507
4365831d
LY		 2508 /* Read Device Controller Capability Parameters register */
2509 dccparams = fsl_readl(&dr_regs->dccparams);
2510 if (!(dccparams & DCCPARAMS_DC)) {
2511 ERR("This SOC doesn't support device role\n");
2512 ret = -ENODEV;
23d7cd04 2513 goto err_iounmap;
4365831d
LY		 2514 }
2515 /* Get max device endpoints */
2516 /* DEN is bidirectional ep number, max_ep doubles the number */
2517 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2518
b504882d
LY		 2519 udc_controller->irq = platform_get_irq(pdev, 0);
2520 if (!udc_controller->irq) {
2521 ret = -ENODEV;
23d7cd04 2522 goto err_iounmap;
b504882d
LY		 2523 }
2524
37b5453d 2525 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
b504882d
LY		 2526 driver_name, udc_controller);
2527 if (ret != 0) {
bf7409a2 2528 ERR("cannot request irq %d err %d\n",
b504882d 2529 udc_controller->irq, ret);
23d7cd04 2530 goto err_iounmap;
b504882d
LY		 2531 }
2532
4365831d
LY		 2533 /* Initialize the udc structure including QH member and other member */
2534 if (struct_udc_setup(udc_controller, pdev)) {
2535 ERR("Can't initialize udc data structure\n");
2536 ret = -ENOMEM;
23d7cd04 2537 goto err_free_irq;
4365831d
LY		 2538 }
2539
ded017ee 2540 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
83722bc9
AG		 2541 /* initialize usb hw reg except for regs for EP,
2542 * leave usbintr reg untouched */
2543 dr_controller_setup(udc_controller);
2544 }
b504882d 2545
c2c9caa9
PC		 2546 ret = fsl_udc_clk_finalize(pdev);
2547 if (ret)
2548 goto err_free_irq;
54e4026b 2549
b504882d
LY		 2550 /* Setup gadget structure */
2551 udc_controller->gadget.ops = &fsl_gadget_ops;
d327ab5b 2552 udc_controller->gadget.max_speed = USB_SPEED_HIGH;
b504882d
LY		 2553 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2554 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2555 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2556 udc_controller->gadget.name = driver_name;
2557
2558 /* Setup gadget.dev and register with kernel */
0031a06e 2559 dev_set_name(&udc_controller->gadget.dev, "gadget");
b504882d
LY		 2560 udc_controller->gadget.dev.release = fsl_udc_release;
2561 udc_controller->gadget.dev.parent = &pdev->dev;
cb4baf10 2562 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
b504882d
LY		 2563 ret = device_register(&udc_controller->gadget.dev);
2564 if (ret < 0)
23d7cd04 2565 goto err_free_irq;
b504882d 2566
ded017ee 2567 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
83722bc9
AG		 2568 udc_controller->gadget.is_otg = 1;
2569
b504882d
LY		 2570 /* setup QH and epctrl for ep0 */
2571 ep0_setup(udc_controller);
2572
2573 /* setup udc->eps[] for ep0 */
2574 struct_ep_setup(udc_controller, 0, "ep0", 0);
2575 /* for ep0: the desc defined here;
2576 * for other eps, gadget layer called ep_enable with defined desc
2577 */
80e91fd5 2578 udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
b504882d
LY		 2579 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2580
2581 /* setup the udc->eps[] for non-control endpoints and link
2582 * to gadget.ep_list */
2583 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2584 char name[14];
2585
2586 sprintf(name, "ep%dout", i);
2587 struct_ep_setup(udc_controller, i * 2, name, 1);
2588 sprintf(name, "ep%din", i);
2589 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2590 }
2591
2592 /* use dma_pool for TD management */
2593 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2594 sizeof(struct ep_td_struct),
2595 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2596 if (udc_controller->td_pool == NULL) {
2597 ret = -ENOMEM;
23d7cd04 2598 goto err_unregister;
b504882d 2599 }
0f91349b
SAS		 2600
2601 ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
2602 if (ret)
2603 goto err_del_udc;
2604
b504882d
LY		 2605 create_proc_file();
2606 return 0;
2607
0f91349b
SAS		 2608err_del_udc:
2609 dma_pool_destroy(udc_controller->td_pool);
23d7cd04 2610err_unregister:
b504882d 2611 device_unregister(&udc_controller->gadget.dev);
23d7cd04 2612err_free_irq:
b504882d 2613 free_irq(udc_controller->irq, udc_controller);
23d7cd04 2614err_iounmap:
2ea6698d
AG		 2615 if (pdata->exit)
2616 pdata->exit(pdev);
54e4026b
GL		 2617 fsl_udc_clk_release();
2618err_iounmap_noclk:
b504882d 2619 iounmap(dr_regs);
23d7cd04 2620err_release_mem_region:
83722bc9 2621 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
28f65c11 2622 release_mem_region(res->start, resource_size(res));
23d7cd04 2623err_kfree:
4365831d 2624 kfree(udc_controller);
23d7cd04 2625 udc_controller = NULL;
b504882d
LY		 2626 return ret;
2627}
2628
2629/* Driver removal function
2630 * Free resources and finish pending transactions
2631 */
2632static int __exit fsl_udc_remove(struct platform_device *pdev)
2633{
2634 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2ea6698d 2635 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
b504882d
LY		 2636
2637 DECLARE_COMPLETION(done);
2638
2639 if (!udc_controller)
2640 return -ENODEV;
0f91349b
SAS		 2641
2642 usb_del_gadget_udc(&udc_controller->gadget);
b504882d
LY		 2643 udc_controller->done = &done;
2644
54e4026b
GL		 2645 fsl_udc_clk_release();
2646
b504882d
LY		 2647 /* DR has been stopped in usb_gadget_unregister_driver() */
2648 remove_proc_file();
2649
2650 /* Free allocated memory */
2651 kfree(udc_controller->status_req->req.buf);
2652 kfree(udc_controller->status_req);
2653 kfree(udc_controller->eps);
2654
2655 dma_pool_destroy(udc_controller->td_pool);
2656 free_irq(udc_controller->irq, udc_controller);
2657 iounmap(dr_regs);
83722bc9 2658 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
28f65c11 2659 release_mem_region(res->start, resource_size(res));
b504882d
LY		 2660
2661 device_unregister(&udc_controller->gadget.dev);
2662 /* free udc --wait for the release() finished */
2663 wait_for_completion(&done);
2664
2ea6698d
AG		 2665 /*
2666 * do platform specific un-initialization:
2667 * release iomux pins, etc.
2668 */
2669 if (pdata->exit)
2670 pdata->exit(pdev);
2671
b504882d
LY		 2672 return 0;
2673}
2674
2675/*-----------------------------------------------------------------
2676 * Modify Power management attributes
2677 * Used by OTG statemachine to disable gadget temporarily
2678 -----------------------------------------------------------------*/
2679static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2680{
2681 dr_controller_stop(udc_controller);
2682 return 0;
2683}
2684
2685/*-----------------------------------------------------------------
2686 * Invoked on USB resume. May be called in_interrupt.
2687 * Here we start the DR controller and enable the irq
2688 *-----------------------------------------------------------------*/
2689static int fsl_udc_resume(struct platform_device *pdev)
2690{
2691 /* Enable DR irq reg and set controller Run */
2692 if (udc_controller->stopped) {
2693 dr_controller_setup(udc_controller);
2694 dr_controller_run(udc_controller);
2695 }
2696 udc_controller->usb_state = USB_STATE_ATTACHED;
2697 udc_controller->ep0_state = WAIT_FOR_SETUP;
2698 udc_controller->ep0_dir = 0;
2699 return 0;
2700}
2701
83722bc9
AG		 2702static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2703{
2704 struct fsl_udc *udc = udc_controller;
2705 u32 mode, usbcmd;
2706
2707 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2708
2709 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2710
2711 /*
2712 * If the controller is already stopped, then this must be a
2713 * PM suspend. Remember this fact, so that we will leave the
2714 * controller stopped at PM resume time.
2715 */
2716 if (udc->stopped) {
2717 pr_debug("gadget already stopped, leaving early\n");
2718 udc->already_stopped = 1;
2719 return 0;
2720 }
2721
2722 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2723 pr_debug("gadget not in device mode, leaving early\n");
2724 return 0;
2725 }
2726
2727 /* stop the controller */
2728 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2729 fsl_writel(usbcmd, &dr_regs->usbcmd);
2730
2731 udc->stopped = 1;
2732
2733 pr_info("USB Gadget suspended\n");
2734
2735 return 0;
2736}
2737
2738static int fsl_udc_otg_resume(struct device *dev)
2739{
2740 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2741 udc_controller->stopped, udc_controller->already_stopped);
2742
2743 /*
2744 * If the controller was stopped at suspend time, then
2745 * don't resume it now.
2746 */
2747 if (udc_controller->already_stopped) {
2748 udc_controller->already_stopped = 0;
2749 pr_debug("gadget was already stopped, leaving early\n");
2750 return 0;
2751 }
2752
2753 pr_info("USB Gadget resume\n");
2754
2755 return fsl_udc_resume(NULL);
2756}
b504882d
LY		 2757/*-------------------------------------------------------------------------
2758 Register entry point for the peripheral controller driver
2759--------------------------------------------------------------------------*/
f0ea8834
PC		 2760static const struct platform_device_id fsl_udc_devtype[] = {
2761 {
2762 .name = "imx-udc-mx27",
2763 }, {
2764 .name = "imx-udc-mx51",
2765 }, {
2766 /* sentinel */
2767 }
2768};
2769MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
b504882d 2770static struct platform_driver udc_driver = {
f0ea8834
PC		 2771 .remove = __exit_p(fsl_udc_remove),
2772 /* Just for FSL i.mx SoC currently */
2773 .id_table = fsl_udc_devtype,
b504882d 2774 /* these suspend and resume are not usb suspend and resume */
f0ea8834
PC		 2775 .suspend = fsl_udc_suspend,
2776 .resume = fsl_udc_resume,
2777 .driver = {
2778 .name = (char *)driver_name,
2779 .owner = THIS_MODULE,
2780 /* udc suspend/resume called from OTG driver */
2781 .suspend = fsl_udc_otg_suspend,
2782 .resume = fsl_udc_otg_resume,
b504882d
LY		 2783 },
2784};
2785
2786static int __init udc_init(void)
2787{
2788 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2789 return platform_driver_probe(&udc_driver, fsl_udc_probe);
2790}
2791
2792module_init(udc_init);
2793
2794static void __exit udc_exit(void)
2795{
2796 platform_driver_unregister(&udc_driver);
6f8aa65b 2797 printk(KERN_WARNING "%s unregistered\n", driver_desc);
b504882d
LY		 2798}
2799
2800module_exit(udc_exit);
2801
2802MODULE_DESCRIPTION(DRIVER_DESC);
2803MODULE_AUTHOR(DRIVER_AUTHOR);
2804MODULE_LICENSE("GPL");
f34c32f1 2805MODULE_ALIAS("platform:fsl-usb2-udc");
kernel source for telekom puls (alcatel/mediatek)