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USB: Unusual Device support for Gold MP3 Player Energy
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / ci13xxx_udc.c
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aa69a809
DL		 1/*
2 * ci13xxx_udc.c - MIPS USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 * Description: MIPS USB IP core family device controller
15 * Currently it only supports IP part number CI13412
16 *
17 * This driver is composed of several blocks:
18 * - HW: hardware interface
19 * - DBG: debug facilities (optional)
20 * - UTIL: utilities
21 * - ISR: interrupts handling
22 * - ENDPT: endpoint operations (Gadget API)
23 * - GADGET: gadget operations (Gadget API)
24 * - BUS: bus glue code, bus abstraction layer
25 * - PCI: PCI core interface and PCI resources (interrupts, memory...)
26 *
27 * Compile Options
28 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
29 * - STALL_IN: non-empty bulk-in pipes cannot be halted
30 * if defined mass storage compliance succeeds but with warnings
31 * => case 4: Hi > Dn
32 * => case 5: Hi > Di
33 * => case 8: Hi <> Do
34 * if undefined usbtest 13 fails
35 * - TRACE: enable function tracing (depends on DEBUG)
36 *
37 * Main Features
38 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
39 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
40 * - Normal & LPM support
41 *
42 * USBTEST Report
43 * - OK: 0-12, 13 (STALL_IN defined) & 14
44 * - Not Supported: 15 & 16 (ISO)
45 *
46 * TODO List
47 * - OTG
48 * - Isochronous & Interrupt Traffic
49 * - Handle requests which spawns into several TDs
50 * - GET_STATUS(device) - always reports 0
51 * - Gadget API (majority of optional features)
52 * - Suspend & Remote Wakeup
53 */
54#include <linux/device.h>
55#include <linux/dmapool.h>
56#include <linux/dma-mapping.h>
57#include <linux/init.h>
58#include <linux/interrupt.h>
aa69a809
DL		 59#include <linux/io.h>
60#include <linux/irq.h>
61#include <linux/kernel.h>
62#include <linux/module.h>
63#include <linux/pci.h>
64#include <linux/usb/ch9.h>
65#include <linux/usb/gadget.h>
66
67#include "ci13xxx_udc.h"
68
69
70/******************************************************************************
71 * DEFINE
72 *****************************************************************************/
73/* ctrl register bank access */
74static DEFINE_SPINLOCK(udc_lock);
75
76/* driver name */
77#define UDC_DRIVER_NAME "ci13xxx_udc"
78
79/* control endpoint description */
80static const struct usb_endpoint_descriptor
81ctrl_endpt_desc = {
82 .bLength = USB_DT_ENDPOINT_SIZE,
83 .bDescriptorType = USB_DT_ENDPOINT,
84
85 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
86 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
87};
88
89/* UDC descriptor */
90static struct ci13xxx *_udc;
91
92/* Interrupt statistics */
93#define ISR_MASK 0x1F
94static struct {
95 u32 test;
96 u32 ui;
97 u32 uei;
98 u32 pci;
99 u32 uri;
100 u32 sli;
101 u32 none;
102 struct {
103 u32 cnt;
104 u32 buf[ISR_MASK+1];
105 u32 idx;
106 } hndl;
107} isr_statistics;
108
109/**
110 * ffs_nr: find first (least significant) bit set
111 * @x: the word to search
112 *
113 * This function returns bit number (instead of position)
114 */
115static int ffs_nr(u32 x)
116{
117 int n = ffs(x);
118
119 return n ? n-1 : 32;
120}
121
122/******************************************************************************
123 * HW block
124 *****************************************************************************/
125/* register bank descriptor */
126static struct {
127 unsigned lpm; /* is LPM? */
128 void __iomem *abs; /* bus map offset */
129 void __iomem *cap; /* bus map offset + CAP offset + CAP data */
130 size_t size; /* bank size */
131} hw_bank;
132
133/* UDC register map */
134#define ABS_CAPLENGTH (0x100UL)
135#define ABS_HCCPARAMS (0x108UL)
136#define ABS_DCCPARAMS (0x124UL)
137#define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
138/* offset to CAPLENTGH (addr + data) */
139#define CAP_USBCMD (0x000UL)
140#define CAP_USBSTS (0x004UL)
141#define CAP_USBINTR (0x008UL)
142#define CAP_DEVICEADDR (0x014UL)
143#define CAP_ENDPTLISTADDR (0x018UL)
144#define CAP_PORTSC (0x044UL)
145#define CAP_DEVLC (0x0B4UL)
146#define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
147#define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
148#define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
149#define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
150#define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
151#define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
152#define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
153#define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
154
155/* maximum number of enpoints: valid only after hw_device_reset() */
156static unsigned hw_ep_max;
157
158/**
159 * hw_ep_bit: calculates the bit number
160 * @num: endpoint number
161 * @dir: endpoint direction
162 *
163 * This function returns bit number
164 */
165static inline int hw_ep_bit(int num, int dir)
166{
167 return num + (dir ? 16 : 0);
168}
169
170/**
171 * hw_aread: reads from register bitfield
172 * @addr: address relative to bus map
173 * @mask: bitfield mask
174 *
175 * This function returns register bitfield data
176 */
177static u32 hw_aread(u32 addr, u32 mask)
178{
179 return ioread32(addr + hw_bank.abs) & mask;
180}
181
182/**
183 * hw_awrite: writes to register bitfield
184 * @addr: address relative to bus map
185 * @mask: bitfield mask
186 * @data: new data
187 */
188static void hw_awrite(u32 addr, u32 mask, u32 data)
189{
190 iowrite32(hw_aread(addr, ~mask) | (data & mask),
191 addr + hw_bank.abs);
192}
193
194/**
195 * hw_cread: reads from register bitfield
196 * @addr: address relative to CAP offset plus content
197 * @mask: bitfield mask
198 *
199 * This function returns register bitfield data
200 */
201static u32 hw_cread(u32 addr, u32 mask)
202{
203 return ioread32(addr + hw_bank.cap) & mask;
204}
205
206/**
207 * hw_cwrite: writes to register bitfield
208 * @addr: address relative to CAP offset plus content
209 * @mask: bitfield mask
210 * @data: new data
211 */
212static void hw_cwrite(u32 addr, u32 mask, u32 data)
213{
214 iowrite32(hw_cread(addr, ~mask) | (data & mask),
215 addr + hw_bank.cap);
216}
217
218/**
219 * hw_ctest_and_clear: tests & clears register bitfield
220 * @addr: address relative to CAP offset plus content
221 * @mask: bitfield mask
222 *
223 * This function returns register bitfield data
224 */
225static u32 hw_ctest_and_clear(u32 addr, u32 mask)
226{
227 u32 reg = hw_cread(addr, mask);
228
229 iowrite32(reg, addr + hw_bank.cap);
230 return reg;
231}
232
233/**
234 * hw_ctest_and_write: tests & writes register bitfield
235 * @addr: address relative to CAP offset plus content
236 * @mask: bitfield mask
237 * @data: new data
238 *
239 * This function returns register bitfield data
240 */
241static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
242{
243 u32 reg = hw_cread(addr, ~0);
244
245 iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
246 return (reg & mask) >> ffs_nr(mask);
247}
248
249/**
250 * hw_device_reset: resets chip (execute without interruption)
251 * @base: register base address
252 *
253 * This function returns an error code
254 */
255static int hw_device_reset(void __iomem *base)
256{
257 u32 reg;
258
259 /* bank is a module variable */
260 hw_bank.abs = base;
261
262 hw_bank.cap = hw_bank.abs;
263 hw_bank.cap += ABS_CAPLENGTH;
264 hw_bank.cap += ioread8(hw_bank.cap);
265
266 reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
267 hw_bank.lpm = reg;
268 hw_bank.size = hw_bank.cap - hw_bank.abs;
269 hw_bank.size += CAP_LAST;
270 hw_bank.size /= sizeof(u32);
271
272 /* should flush & stop before reset */
273 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
274 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
275
276 hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
277 while (hw_cread(CAP_USBCMD, USBCMD_RST))
278 udelay(10); /* not RTOS friendly */
279
280 /* USBMODE should be configured step by step */
281 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
282 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
283 hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
284
285 if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
286 pr_err("cannot enter in device mode");
287 pr_err("lpm = %i", hw_bank.lpm);
288 return -ENODEV;
289 }
290
291 reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
292 if (reg == 0 || reg > ENDPT_MAX)
293 return -ENODEV;
294
295 hw_ep_max = reg; /* cache hw ENDPT_MAX */
296
297 /* setup lock mode ? */
298
299 /* ENDPTSETUPSTAT is '0' by default */
300
301 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
302
303 return 0;
304}
305
306/**
307 * hw_device_state: enables/disables interrupts & starts/stops device (execute
308 * without interruption)
309 * @dma: 0 => disable, !0 => enable and set dma engine
310 *
311 * This function returns an error code
312 */
313static int hw_device_state(u32 dma)
314{
315 if (dma) {
316 hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
317 /* interrupt, error, port change, reset, sleep/suspend */
318 hw_cwrite(CAP_USBINTR, ~0,
319 USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
320 hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
321 } else {
322 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
323 hw_cwrite(CAP_USBINTR, ~0, 0);
324 }
325 return 0;
326}
327
328/**
329 * hw_ep_flush: flush endpoint fifo (execute without interruption)
330 * @num: endpoint number
331 * @dir: endpoint direction
332 *
333 * This function returns an error code
334 */
335static int hw_ep_flush(int num, int dir)
336{
337 int n = hw_ep_bit(num, dir);
338
339 do {
340 /* flush any pending transfer */
341 hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
342 while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
343 cpu_relax();
344 } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
345
346 return 0;
347}
348
349/**
350 * hw_ep_disable: disables endpoint (execute without interruption)
351 * @num: endpoint number
352 * @dir: endpoint direction
353 *
354 * This function returns an error code
355 */
356static int hw_ep_disable(int num, int dir)
357{
358 hw_ep_flush(num, dir);
359 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
360 dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
361 return 0;
362}
363
364/**
365 * hw_ep_enable: enables endpoint (execute without interruption)
366 * @num: endpoint number
367 * @dir: endpoint direction
368 * @type: endpoint type
369 *
370 * This function returns an error code
371 */
372static int hw_ep_enable(int num, int dir, int type)
373{
374 u32 mask, data;
375
376 if (dir) {
377 mask = ENDPTCTRL_TXT; /* type */
378 data = type << ffs_nr(mask);
379
380 mask |= ENDPTCTRL_TXS; /* unstall */
381 mask |= ENDPTCTRL_TXR; /* reset data toggle */
382 data |= ENDPTCTRL_TXR;
383 mask |= ENDPTCTRL_TXE; /* enable */
384 data |= ENDPTCTRL_TXE;
385 } else {
386 mask = ENDPTCTRL_RXT; /* type */
387 data = type << ffs_nr(mask);
388
389 mask |= ENDPTCTRL_RXS; /* unstall */
390 mask |= ENDPTCTRL_RXR; /* reset data toggle */
391 data |= ENDPTCTRL_RXR;
392 mask |= ENDPTCTRL_RXE; /* enable */
393 data |= ENDPTCTRL_RXE;
394 }
395 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
396 return 0;
397}
398
399/**
400 * hw_ep_get_halt: return endpoint halt status
401 * @num: endpoint number
402 * @dir: endpoint direction
403 *
404 * This function returns 1 if endpoint halted
405 */
406static int hw_ep_get_halt(int num, int dir)
407{
408 u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
409
410 return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
411}
412
413/**
414 * hw_ep_is_primed: test if endpoint is primed (execute without interruption)
415 * @num: endpoint number
416 * @dir: endpoint direction
417 *
418 * This function returns true if endpoint primed
419 */
420static int hw_ep_is_primed(int num, int dir)
421{
422 u32 reg = hw_cread(CAP_ENDPTPRIME, ~0) | hw_cread(CAP_ENDPTSTAT, ~0);
423
424 return test_bit(hw_ep_bit(num, dir), (void *)&reg);
425}
426
427/**
428 * hw_test_and_clear_setup_status: test & clear setup status (execute without
429 * interruption)
430 * @n: bit number (endpoint)
431 *
432 * This function returns setup status
433 */
434static int hw_test_and_clear_setup_status(int n)
435{
436 return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
437}
438
439/**
440 * hw_ep_prime: primes endpoint (execute without interruption)
441 * @num: endpoint number
442 * @dir: endpoint direction
443 * @is_ctrl: true if control endpoint
444 *
445 * This function returns an error code
446 */
447static int hw_ep_prime(int num, int dir, int is_ctrl)
448{
449 int n = hw_ep_bit(num, dir);
450
451 /* the caller should flush first */
452 if (hw_ep_is_primed(num, dir))
453 return -EBUSY;
454
455 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
456 return -EAGAIN;
457
458 hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
459
460 while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
461 cpu_relax();
462 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
463 return -EAGAIN;
464
465 /* status shoult be tested according with manual but it doesn't work */
466 return 0;
467}
468
469/**
470 * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
471 * without interruption)
472 * @num: endpoint number
473 * @dir: endpoint direction
474 * @value: true => stall, false => unstall
475 *
476 * This function returns an error code
477 */
478static int hw_ep_set_halt(int num, int dir, int value)
479{
480 if (value != 0 && value != 1)
481 return -EINVAL;
482
483 do {
484 u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
485 u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
486 u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
487
488 /* data toggle - reserved for EP0 but it's in ESS */
489 hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
490
491 } while (value != hw_ep_get_halt(num, dir));
492
493 return 0;
494}
495
496/**
497 * hw_intr_clear: disables interrupt & clears interrupt status (execute without
498 * interruption)
499 * @n: interrupt bit
500 *
501 * This function returns an error code
502 */
503static int hw_intr_clear(int n)
504{
505 if (n >= REG_BITS)
506 return -EINVAL;
507
508 hw_cwrite(CAP_USBINTR, BIT(n), 0);
509 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
510 return 0;
511}
512
513/**
514 * hw_intr_force: enables interrupt & forces interrupt status (execute without
515 * interruption)
516 * @n: interrupt bit
517 *
518 * This function returns an error code
519 */
520static int hw_intr_force(int n)
521{
522 if (n >= REG_BITS)
523 return -EINVAL;
524
525 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
526 hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
527 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
528 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
529 return 0;
530}
531
532/**
533 * hw_is_port_high_speed: test if port is high speed
534 *
535 * This function returns true if high speed port
536 */
537static int hw_port_is_high_speed(void)
538{
539 return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
540 hw_cread(CAP_PORTSC, PORTSC_HSP);
541}
542
543/**
544 * hw_port_test_get: reads port test mode value
545 *
546 * This function returns port test mode value
547 */
548static u8 hw_port_test_get(void)
549{
550 return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
551}
552
553/**
554 * hw_port_test_set: writes port test mode (execute without interruption)
555 * @mode: new value
556 *
557 * This function returns an error code
558 */
559static int hw_port_test_set(u8 mode)
560{
561 const u8 TEST_MODE_MAX = 7;
562
563 if (mode > TEST_MODE_MAX)
564 return -EINVAL;
565
566 hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
567 return 0;
568}
569
570/**
571 * hw_read_intr_enable: returns interrupt enable register
572 *
573 * This function returns register data
574 */
575static u32 hw_read_intr_enable(void)
576{
577 return hw_cread(CAP_USBINTR, ~0);
578}
579
580/**
581 * hw_read_intr_status: returns interrupt status register
582 *
583 * This function returns register data
584 */
585static u32 hw_read_intr_status(void)
586{
587 return hw_cread(CAP_USBSTS, ~0);
588}
589
590/**
591 * hw_register_read: reads all device registers (execute without interruption)
592 * @buf: destination buffer
593 * @size: buffer size
594 *
595 * This function returns number of registers read
596 */
597static size_t hw_register_read(u32 *buf, size_t size)
598{
599 unsigned i;
600
601 if (size > hw_bank.size)
602 size = hw_bank.size;
603
604 for (i = 0; i < size; i++)
605 buf[i] = hw_aread(i * sizeof(u32), ~0);
606
607 return size;
608}
609
610/**
611 * hw_register_write: writes to register
612 * @addr: register address
613 * @data: register value
614 *
615 * This function returns an error code
616 */
617static int hw_register_write(u16 addr, u32 data)
618{
619 /* align */
620 addr /= sizeof(u32);
621
622 if (addr >= hw_bank.size)
623 return -EINVAL;
624
625 /* align */
626 addr *= sizeof(u32);
627
628 hw_awrite(addr, ~0, data);
629 return 0;
630}
631
632/**
633 * hw_test_and_clear_complete: test & clear complete status (execute without
634 * interruption)
635 * @n: bit number (endpoint)
636 *
637 * This function returns complete status
638 */
639static int hw_test_and_clear_complete(int n)
640{
641 return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
642}
643
644/**
645 * hw_test_and_clear_intr_active: test & clear active interrupts (execute
646 * without interruption)
647 *
648 * This function returns active interrutps
649 */
650static u32 hw_test_and_clear_intr_active(void)
651{
652 u32 reg = hw_read_intr_status() & hw_read_intr_enable();
653
654 hw_cwrite(CAP_USBSTS, ~0, reg);
655 return reg;
656}
657
658/**
659 * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
660 * interruption)
661 *
662 * This function returns guard value
663 */
664static int hw_test_and_clear_setup_guard(void)
665{
666 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
667}
668
669/**
670 * hw_test_and_set_setup_guard: test & set setup guard (execute without
671 * interruption)
672 *
673 * This function returns guard value
674 */
675static int hw_test_and_set_setup_guard(void)
676{
677 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
678}
679
680/**
681 * hw_usb_set_address: configures USB address (execute without interruption)
682 * @value: new USB address
683 *
684 * This function returns an error code
685 */
686static int hw_usb_set_address(u8 value)
687{
688 /* advance */
689 hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
690 value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
691 return 0;
692}
693
694/**
695 * hw_usb_reset: restart device after a bus reset (execute without
696 * interruption)
697 *
698 * This function returns an error code
699 */
700static int hw_usb_reset(void)
701{
702 hw_usb_set_address(0);
703
704 /* ESS flushes only at end?!? */
705 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
706
707 /* clear setup token semaphores */
708 hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
709
710 /* clear complete status */
711 hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
712
713 /* wait until all bits cleared */
714 while (hw_cread(CAP_ENDPTPRIME, ~0))
715 udelay(10); /* not RTOS friendly */
716
717 /* reset all endpoints ? */
718
719 /* reset internal status and wait for further instructions
720 no need to verify the port reset status (ESS does it) */
721
722 return 0;
723}
724
725/******************************************************************************
726 * DBG block
727 *****************************************************************************/
728/**
729 * show_device: prints information about device capabilities and status
730 *
731 * Check "device.h" for details
732 */
733static ssize_t show_device(struct device *dev, struct device_attribute *attr,
734 char *buf)
735{
736 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
737 struct usb_gadget *gadget = &udc->gadget;
738 int n = 0;
739
740 dbg_trace("[%s] %p\n", __func__, buf);
741 if (attr == NULL || buf == NULL) {
742 dev_err(dev, "[%s] EINVAL\n", __func__);
743 return 0;
744 }
745
746 n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
747 gadget->speed);
748 n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
749 gadget->is_dualspeed);
750 n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
751 gadget->is_otg);
752 n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
753 gadget->is_a_peripheral);
754 n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
755 gadget->b_hnp_enable);
756 n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
757 gadget->a_hnp_support);
758 n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
759 gadget->a_alt_hnp_support);
760 n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
761 (gadget->name ? gadget->name : ""));
762
763 return n;
764}
765static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
766
767/**
768 * show_driver: prints information about attached gadget (if any)
769 *
770 * Check "device.h" for details
771 */
772static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
773 char *buf)
774{
775 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
776 struct usb_gadget_driver *driver = udc->driver;
777 int n = 0;
778
779 dbg_trace("[%s] %p\n", __func__, buf);
780 if (attr == NULL || buf == NULL) {
781 dev_err(dev, "[%s] EINVAL\n", __func__);
782 return 0;
783 }
784
785 if (driver == NULL)
786 return scnprintf(buf, PAGE_SIZE,
787 "There is no gadget attached!\n");
788
789 n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
790 (driver->function ? driver->function : ""));
791 n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
792 driver->speed);
793
794 return n;
795}
796static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
797
798/* Maximum event message length */
799#define DBG_DATA_MSG 64UL
800
801/* Maximum event messages */
802#define DBG_DATA_MAX 128UL
803
804/* Event buffer descriptor */
805static struct {
806 char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
807 unsigned idx; /* index */
808 unsigned tty; /* print to console? */
809 rwlock_t lck; /* lock */
810} dbg_data = {
811 .idx = 0,
812 .tty = 0,
813 .lck = __RW_LOCK_UNLOCKED(lck)
814};
815
816/**
817 * dbg_dec: decrements debug event index
818 * @idx: buffer index
819 */
820static void dbg_dec(unsigned *idx)
821{
822 *idx = (*idx - 1) & (DBG_DATA_MAX-1);
823}
824
825/**
826 * dbg_inc: increments debug event index
827 * @idx: buffer index
828 */
829static void dbg_inc(unsigned *idx)
830{
831 *idx = (*idx + 1) & (DBG_DATA_MAX-1);
832}
833
834/**
835 * dbg_print: prints the common part of the event
836 * @addr: endpoint address
837 * @name: event name
838 * @status: status
839 * @extra: extra information
840 */
841static void dbg_print(u8 addr, const char *name, int status, const char *extra)
842{
843 struct timeval tval;
844 unsigned int stamp;
845 unsigned long flags;
846
847 write_lock_irqsave(&dbg_data.lck, flags);
848
849 do_gettimeofday(&tval);
850 stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
851 stamp = stamp * 1000000 + tval.tv_usec;
852
853 scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
854