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USB: gadget: Separate out PCI bus code from ci13xxx_udc
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / ci13xxx_udc.c
CommitLineData
aa69a809
DL		 1/*
2 * ci13xxx_udc.c - MIPS USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 * Description: MIPS USB IP core family device controller
15 * Currently it only supports IP part number CI13412
16 *
17 * This driver is composed of several blocks:
18 * - HW: hardware interface
19 * - DBG: debug facilities (optional)
20 * - UTIL: utilities
21 * - ISR: interrupts handling
22 * - ENDPT: endpoint operations (Gadget API)
23 * - GADGET: gadget operations (Gadget API)
24 * - BUS: bus glue code, bus abstraction layer
aa69a809
DL		 25 *
26 * Compile Options
27 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
28 * - STALL_IN: non-empty bulk-in pipes cannot be halted
29 * if defined mass storage compliance succeeds but with warnings
30 * => case 4: Hi > Dn
31 * => case 5: Hi > Di
32 * => case 8: Hi <> Do
33 * if undefined usbtest 13 fails
34 * - TRACE: enable function tracing (depends on DEBUG)
35 *
36 * Main Features
37 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
38 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
39 * - Normal & LPM support
40 *
41 * USBTEST Report
42 * - OK: 0-12, 13 (STALL_IN defined) & 14
43 * - Not Supported: 15 & 16 (ISO)
44 *
45 * TODO List
46 * - OTG
47 * - Isochronous & Interrupt Traffic
48 * - Handle requests which spawns into several TDs
49 * - GET_STATUS(device) - always reports 0
50 * - Gadget API (majority of optional features)
51 * - Suspend & Remote Wakeup
52 */
36825a2d 53#include <linux/delay.h>
aa69a809
DL		 54#include <linux/device.h>
55#include <linux/dmapool.h>
56#include <linux/dma-mapping.h>
57#include <linux/init.h>
58#include <linux/interrupt.h>
aa69a809
DL		 59#include <linux/io.h>
60#include <linux/irq.h>
61#include <linux/kernel.h>
5a0e3ad6 62#include <linux/slab.h>
aa69a809
DL		 63#include <linux/usb/ch9.h>
64#include <linux/usb/gadget.h>
65
66#include "ci13xxx_udc.h"
67
68
69/******************************************************************************
70 * DEFINE
71 *****************************************************************************/
72/* ctrl register bank access */
73static DEFINE_SPINLOCK(udc_lock);
74
aa69a809
DL		 75/* control endpoint description */
76static const struct usb_endpoint_descriptor
77ctrl_endpt_desc = {
78 .bLength = USB_DT_ENDPOINT_SIZE,
79 .bDescriptorType = USB_DT_ENDPOINT,
80
81 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
82 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
83};
84
85/* UDC descriptor */
86static struct ci13xxx *_udc;
87
88/* Interrupt statistics */
89#define ISR_MASK 0x1F
90static struct {
91 u32 test;
92 u32 ui;
93 u32 uei;
94 u32 pci;
95 u32 uri;
96 u32 sli;
97 u32 none;
98 struct {
99 u32 cnt;
100 u32 buf[ISR_MASK+1];
101 u32 idx;
102 } hndl;
103} isr_statistics;
104
105/**
106 * ffs_nr: find first (least significant) bit set
107 * @x: the word to search
108 *
109 * This function returns bit number (instead of position)
110 */
111static int ffs_nr(u32 x)
112{
113 int n = ffs(x);
114
115 return n ? n-1 : 32;
116}
117
118/******************************************************************************
119 * HW block
120 *****************************************************************************/
121/* register bank descriptor */
122static struct {
123 unsigned lpm; /* is LPM? */
124 void __iomem *abs; /* bus map offset */
125 void __iomem *cap; /* bus map offset + CAP offset + CAP data */
126 size_t size; /* bank size */
127} hw_bank;
128
129/* UDC register map */
130#define ABS_CAPLENGTH (0x100UL)
131#define ABS_HCCPARAMS (0x108UL)
132#define ABS_DCCPARAMS (0x124UL)
133#define ABS_TESTMODE (hw_bank.lpm ? 0x0FCUL : 0x138UL)
134/* offset to CAPLENTGH (addr + data) */
135#define CAP_USBCMD (0x000UL)
136#define CAP_USBSTS (0x004UL)
137#define CAP_USBINTR (0x008UL)
138#define CAP_DEVICEADDR (0x014UL)
139#define CAP_ENDPTLISTADDR (0x018UL)
140#define CAP_PORTSC (0x044UL)
f23e649b 141#define CAP_DEVLC (0x084UL)
aa69a809
DL		 142#define CAP_USBMODE (hw_bank.lpm ? 0x0C8UL : 0x068UL)
143#define CAP_ENDPTSETUPSTAT (hw_bank.lpm ? 0x0D8UL : 0x06CUL)
144#define CAP_ENDPTPRIME (hw_bank.lpm ? 0x0DCUL : 0x070UL)
145#define CAP_ENDPTFLUSH (hw_bank.lpm ? 0x0E0UL : 0x074UL)
146#define CAP_ENDPTSTAT (hw_bank.lpm ? 0x0E4UL : 0x078UL)
147#define CAP_ENDPTCOMPLETE (hw_bank.lpm ? 0x0E8UL : 0x07CUL)
148#define CAP_ENDPTCTRL (hw_bank.lpm ? 0x0ECUL : 0x080UL)
149#define CAP_LAST (hw_bank.lpm ? 0x12CUL : 0x0C0UL)
150
151/* maximum number of enpoints: valid only after hw_device_reset() */
152static unsigned hw_ep_max;
153
154/**
155 * hw_ep_bit: calculates the bit number
156 * @num: endpoint number
157 * @dir: endpoint direction
158 *
159 * This function returns bit number
160 */
161static inline int hw_ep_bit(int num, int dir)
162{
163 return num + (dir ? 16 : 0);
164}
165
166/**
167 * hw_aread: reads from register bitfield
168 * @addr: address relative to bus map
169 * @mask: bitfield mask
170 *
171 * This function returns register bitfield data
172 */
173static u32 hw_aread(u32 addr, u32 mask)
174{
175 return ioread32(addr + hw_bank.abs) & mask;
176}
177
178/**
179 * hw_awrite: writes to register bitfield
180 * @addr: address relative to bus map
181 * @mask: bitfield mask
182 * @data: new data
183 */
184static void hw_awrite(u32 addr, u32 mask, u32 data)
185{
186 iowrite32(hw_aread(addr, ~mask) | (data & mask),
187 addr + hw_bank.abs);
188}
189
190/**
191 * hw_cread: reads from register bitfield
192 * @addr: address relative to CAP offset plus content
193 * @mask: bitfield mask
194 *
195 * This function returns register bitfield data
196 */
197static u32 hw_cread(u32 addr, u32 mask)
198{
199 return ioread32(addr + hw_bank.cap) & mask;
200}
201
202/**
203 * hw_cwrite: writes to register bitfield
204 * @addr: address relative to CAP offset plus content
205 * @mask: bitfield mask
206 * @data: new data
207 */
208static void hw_cwrite(u32 addr, u32 mask, u32 data)
209{
210 iowrite32(hw_cread(addr, ~mask) | (data & mask),
211 addr + hw_bank.cap);
212}
213
214/**
215 * hw_ctest_and_clear: tests & clears register bitfield
216 * @addr: address relative to CAP offset plus content
217 * @mask: bitfield mask
218 *
219 * This function returns register bitfield data
220 */
221static u32 hw_ctest_and_clear(u32 addr, u32 mask)
222{
223 u32 reg = hw_cread(addr, mask);
224
225 iowrite32(reg, addr + hw_bank.cap);
226 return reg;
227}
228
229/**
230 * hw_ctest_and_write: tests & writes register bitfield
231 * @addr: address relative to CAP offset plus content
232 * @mask: bitfield mask
233 * @data: new data
234 *
235 * This function returns register bitfield data
236 */
237static u32 hw_ctest_and_write(u32 addr, u32 mask, u32 data)
238{
239 u32 reg = hw_cread(addr, ~0);
240
241 iowrite32((reg & ~mask) | (data & mask), addr + hw_bank.cap);
242 return (reg & mask) >> ffs_nr(mask);
243}
244
245/**
246 * hw_device_reset: resets chip (execute without interruption)
247 * @base: register base address
248 *
249 * This function returns an error code
250 */
251static int hw_device_reset(void __iomem *base)
252{
253 u32 reg;
254
255 /* bank is a module variable */
256 hw_bank.abs = base;
257
258 hw_bank.cap = hw_bank.abs;
259 hw_bank.cap += ABS_CAPLENGTH;
260 hw_bank.cap += ioread8(hw_bank.cap);
261
262 reg = hw_aread(ABS_HCCPARAMS, HCCPARAMS_LEN) >> ffs_nr(HCCPARAMS_LEN);
263 hw_bank.lpm = reg;
264 hw_bank.size = hw_bank.cap - hw_bank.abs;
265 hw_bank.size += CAP_LAST;
266 hw_bank.size /= sizeof(u32);
267
268 /* should flush & stop before reset */
269 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0);
270 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
271
272 hw_cwrite(CAP_USBCMD, USBCMD_RST, USBCMD_RST);
273 while (hw_cread(CAP_USBCMD, USBCMD_RST))
274 udelay(10); /* not RTOS friendly */
275
276 /* USBMODE should be configured step by step */
277 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
278 hw_cwrite(CAP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
279 hw_cwrite(CAP_USBMODE, USBMODE_SLOM, USBMODE_SLOM); /* HW >= 2.3 */
280
281 if (hw_cread(CAP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
282 pr_err("cannot enter in device mode");
283 pr_err("lpm = %i", hw_bank.lpm);
284 return -ENODEV;
285 }
286
287 reg = hw_aread(ABS_DCCPARAMS, DCCPARAMS_DEN) >> ffs_nr(DCCPARAMS_DEN);
288 if (reg == 0 || reg > ENDPT_MAX)
289 return -ENODEV;
290
291 hw_ep_max = reg; /* cache hw ENDPT_MAX */
292
293 /* setup lock mode ? */
294
295 /* ENDPTSETUPSTAT is '0' by default */
296
297 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
298
299 return 0;
300}
301
302/**
303 * hw_device_state: enables/disables interrupts & starts/stops device (execute
304 * without interruption)
305 * @dma: 0 => disable, !0 => enable and set dma engine
306 *
307 * This function returns an error code
308 */
309static int hw_device_state(u32 dma)
310{
311 if (dma) {
312 hw_cwrite(CAP_ENDPTLISTADDR, ~0, dma);
313 /* interrupt, error, port change, reset, sleep/suspend */
314 hw_cwrite(CAP_USBINTR, ~0,
315 USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
316 hw_cwrite(CAP_USBCMD, USBCMD_RS, USBCMD_RS);
317 } else {
318 hw_cwrite(CAP_USBCMD, USBCMD_RS, 0);
319 hw_cwrite(CAP_USBINTR, ~0, 0);
320 }
321 return 0;
322}
323
324/**
325 * hw_ep_flush: flush endpoint fifo (execute without interruption)
326 * @num: endpoint number
327 * @dir: endpoint direction
328 *
329 * This function returns an error code
330 */
331static int hw_ep_flush(int num, int dir)
332{
333 int n = hw_ep_bit(num, dir);
334
335 do {
336 /* flush any pending transfer */
337 hw_cwrite(CAP_ENDPTFLUSH, BIT(n), BIT(n));
338 while (hw_cread(CAP_ENDPTFLUSH, BIT(n)))
339 cpu_relax();
340 } while (hw_cread(CAP_ENDPTSTAT, BIT(n)));
341
342 return 0;
343}
344
345/**
346 * hw_ep_disable: disables endpoint (execute without interruption)
347 * @num: endpoint number
348 * @dir: endpoint direction
349 *
350 * This function returns an error code
351 */
352static int hw_ep_disable(int num, int dir)
353{
354 hw_ep_flush(num, dir);
355 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32),
356 dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
357 return 0;
358}
359
360/**
361 * hw_ep_enable: enables endpoint (execute without interruption)
362 * @num: endpoint number
363 * @dir: endpoint direction
364 * @type: endpoint type
365 *
366 * This function returns an error code
367 */
368static int hw_ep_enable(int num, int dir, int type)
369{
370 u32 mask, data;
371
372 if (dir) {
373 mask = ENDPTCTRL_TXT; /* type */
374 data = type << ffs_nr(mask);
375
376 mask |= ENDPTCTRL_TXS; /* unstall */
377 mask |= ENDPTCTRL_TXR; /* reset data toggle */
378 data |= ENDPTCTRL_TXR;
379 mask |= ENDPTCTRL_TXE; /* enable */
380 data |= ENDPTCTRL_TXE;
381 } else {
382 mask = ENDPTCTRL_RXT; /* type */
383 data = type << ffs_nr(mask);
384
385 mask |= ENDPTCTRL_RXS; /* unstall */
386 mask |= ENDPTCTRL_RXR; /* reset data toggle */
387 data |= ENDPTCTRL_RXR;
388 mask |= ENDPTCTRL_RXE; /* enable */
389 data |= ENDPTCTRL_RXE;
390 }
391 hw_cwrite(CAP_ENDPTCTRL + num * sizeof(u32), mask, data);
392 return 0;
393}
394
395/**
396 * hw_ep_get_halt: return endpoint halt status
397 * @num: endpoint number
398 * @dir: endpoint direction
399 *
400 * This function returns 1 if endpoint halted
401 */
402static int hw_ep_get_halt(int num, int dir)
403{
404 u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
405
406 return hw_cread(CAP_ENDPTCTRL + num * sizeof(u32), mask) ? 1 : 0;
407}
408
409/**
410 * hw_ep_is_primed: test if endpoint is primed (execute without interruption)
411 * @num: endpoint number
412 * @dir: endpoint direction
413 *
414 * This function returns true if endpoint primed
415 */
416static int hw_ep_is_primed(int num, int dir)
417{
418 u32 reg = hw_cread(CAP_ENDPTPRIME, ~0) | hw_cread(CAP_ENDPTSTAT, ~0);
419
420 return test_bit(hw_ep_bit(num, dir), (void *)&reg);
421}
422
423/**
424 * hw_test_and_clear_setup_status: test & clear setup status (execute without
425 * interruption)
426 * @n: bit number (endpoint)
427 *
428 * This function returns setup status
429 */
430static int hw_test_and_clear_setup_status(int n)
431{
432 return hw_ctest_and_clear(CAP_ENDPTSETUPSTAT, BIT(n));
433}
434
435/**
436 * hw_ep_prime: primes endpoint (execute without interruption)
437 * @num: endpoint number
438 * @dir: endpoint direction
439 * @is_ctrl: true if control endpoint
440 *
441 * This function returns an error code
442 */
443static int hw_ep_prime(int num, int dir, int is_ctrl)
444{
445 int n = hw_ep_bit(num, dir);
446
447 /* the caller should flush first */
448 if (hw_ep_is_primed(num, dir))
449 return -EBUSY;
450
451 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
452 return -EAGAIN;
453
454 hw_cwrite(CAP_ENDPTPRIME, BIT(n), BIT(n));
455
456 while (hw_cread(CAP_ENDPTPRIME, BIT(n)))
457 cpu_relax();
458 if (is_ctrl && dir == RX && hw_cread(CAP_ENDPTSETUPSTAT, BIT(num)))
459 return -EAGAIN;
460
461 /* status shoult be tested according with manual but it doesn't work */
462 return 0;
463}
464
465/**
466 * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
467 * without interruption)
468 * @num: endpoint number
469 * @dir: endpoint direction
470 * @value: true => stall, false => unstall
471 *
472 * This function returns an error code
473 */
474static int hw_ep_set_halt(int num, int dir, int value)
475{
476 if (value != 0 && value != 1)
477 return -EINVAL;
478
479 do {
480 u32 addr = CAP_ENDPTCTRL + num * sizeof(u32);
481 u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
482 u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
483
484 /* data toggle - reserved for EP0 but it's in ESS */
485 hw_cwrite(addr, mask_xs|mask_xr, value ? mask_xs : mask_xr);
486
487 } while (value != hw_ep_get_halt(num, dir));
488
489 return 0;
490}
491
492/**
493 * hw_intr_clear: disables interrupt & clears interrupt status (execute without
494 * interruption)
495 * @n: interrupt bit
496 *
497 * This function returns an error code
498 */
499static int hw_intr_clear(int n)
500{
501 if (n >= REG_BITS)
502 return -EINVAL;
503
504 hw_cwrite(CAP_USBINTR, BIT(n), 0);
505 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
506 return 0;
507}
508
509/**
510 * hw_intr_force: enables interrupt & forces interrupt status (execute without
511 * interruption)
512 * @n: interrupt bit
513 *
514 * This function returns an error code
515 */
516static int hw_intr_force(int n)
517{
518 if (n >= REG_BITS)
519 return -EINVAL;
520
521 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
522 hw_cwrite(CAP_USBINTR, BIT(n), BIT(n));
523 hw_cwrite(CAP_USBSTS, BIT(n), BIT(n));
524 hw_awrite(ABS_TESTMODE, TESTMODE_FORCE, 0);
525 return 0;
526}
527
528/**
529 * hw_is_port_high_speed: test if port is high speed
530 *
531 * This function returns true if high speed port
532 */
533static int hw_port_is_high_speed(void)
534{
535 return hw_bank.lpm ? hw_cread(CAP_DEVLC, DEVLC_PSPD) :
536 hw_cread(CAP_PORTSC, PORTSC_HSP);
537}
538
539/**
540 * hw_port_test_get: reads port test mode value
541 *
542 * This function returns port test mode value
543 */
544static u8 hw_port_test_get(void)
545{
546 return hw_cread(CAP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
547}
548
549/**
550 * hw_port_test_set: writes port test mode (execute without interruption)
551 * @mode: new value
552 *
553 * This function returns an error code
554 */
555static int hw_port_test_set(u8 mode)
556{
557 const u8 TEST_MODE_MAX = 7;
558
559 if (mode > TEST_MODE_MAX)
560 return -EINVAL;
561
562 hw_cwrite(CAP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
563 return 0;
564}
565
566/**
567 * hw_read_intr_enable: returns interrupt enable register
568 *
569 * This function returns register data
570 */
571static u32 hw_read_intr_enable(void)
572{
573 return hw_cread(CAP_USBINTR, ~0);
574}
575
576/**
577 * hw_read_intr_status: returns interrupt status register
578 *
579 * This function returns register data
580 */
581static u32 hw_read_intr_status(void)
582{
583 return hw_cread(CAP_USBSTS, ~0);
584}
585
586/**
587 * hw_register_read: reads all device registers (execute without interruption)
588 * @buf: destination buffer
589 * @size: buffer size
590 *
591 * This function returns number of registers read
592 */
593static size_t hw_register_read(u32 *buf, size_t size)
594{
595 unsigned i;
596
597 if (size > hw_bank.size)
598 size = hw_bank.size;
599
600 for (i = 0; i < size; i++)
601 buf[i] = hw_aread(i * sizeof(u32), ~0);
602
603 return size;
604}
605
606/**
607 * hw_register_write: writes to register
608 * @addr: register address
609 * @data: register value
610 *
611 * This function returns an error code
612 */
613static int hw_register_write(u16 addr, u32 data)
614{
615 /* align */
616 addr /= sizeof(u32);
617
618 if (addr >= hw_bank.size)
619 return -EINVAL;
620
621 /* align */
622 addr *= sizeof(u32);
623
624 hw_awrite(addr, ~0, data);
625 return 0;
626}
627
628/**
629 * hw_test_and_clear_complete: test & clear complete status (execute without
630 * interruption)
631 * @n: bit number (endpoint)
632 *
633 * This function returns complete status
634 */
635static int hw_test_and_clear_complete(int n)
636{
637 return hw_ctest_and_clear(CAP_ENDPTCOMPLETE, BIT(n));
638}
639
640/**
641 * hw_test_and_clear_intr_active: test & clear active interrupts (execute
642 * without interruption)
643 *
644 * This function returns active interrutps
645 */
646static u32 hw_test_and_clear_intr_active(void)
647{
648 u32 reg = hw_read_intr_status() & hw_read_intr_enable();
649
650 hw_cwrite(CAP_USBSTS, ~0, reg);
651 return reg;
652}
653
654/**
655 * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
656 * interruption)
657 *
658 * This function returns guard value
659 */
660static int hw_test_and_clear_setup_guard(void)
661{
662 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, 0);
663}
664
665/**
666 * hw_test_and_set_setup_guard: test & set setup guard (execute without
667 * interruption)
668 *
669 * This function returns guard value
670 */
671static int hw_test_and_set_setup_guard(void)
672{
673 return hw_ctest_and_write(CAP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
674}
675
676/**
677 * hw_usb_set_address: configures USB address (execute without interruption)
678 * @value: new USB address
679 *
680 * This function returns an error code
681 */
682static int hw_usb_set_address(u8 value)
683{
684 /* advance */
685 hw_cwrite(CAP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
686 value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
687 return 0;
688}
689
690/**
691 * hw_usb_reset: restart device after a bus reset (execute without
692 * interruption)
693 *
694 * This function returns an error code
695 */
696static int hw_usb_reset(void)
697{
698 hw_usb_set_address(0);
699
700 /* ESS flushes only at end?!? */
701 hw_cwrite(CAP_ENDPTFLUSH, ~0, ~0); /* flush all EPs */
702
703 /* clear setup token semaphores */
704 hw_cwrite(CAP_ENDPTSETUPSTAT, 0, 0); /* writes its content */
705
706 /* clear complete status */
707 hw_cwrite(CAP_ENDPTCOMPLETE, 0, 0); /* writes its content */
708
709 /* wait until all bits cleared */
710 while (hw_cread(CAP_ENDPTPRIME, ~0))
711 udelay(10); /* not RTOS friendly */
712
713 /* reset all endpoints ? */
714
715 /* reset internal status and wait for further instructions
716 no need to verify the port reset status (ESS does it) */
717
718 return 0;
719}
720
721/******************************************************************************
722 * DBG block
723 *****************************************************************************/
724/**
725 * show_device: prints information about device capabilities and status
726 *
727 * Check "device.h" for details
728 */
729static ssize_t show_device(struct device *dev, struct device_attribute *attr,
730 char *buf)
731{
732 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
733 struct usb_gadget *gadget = &udc->gadget;
734 int n = 0;
735
736 dbg_trace("[%s] %p\n", __func__, buf);
737 if (attr == NULL || buf == NULL) {
738 dev_err(dev, "[%s] EINVAL\n", __func__);
739 return 0;
740 }
741
742 n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
743 gadget->speed);
744 n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
745 gadget->is_dualspeed);
746 n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
747 gadget->is_otg);
748 n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
749 gadget->is_a_peripheral);
750 n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
751 gadget->b_hnp_enable);
752 n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
753 gadget->a_hnp_support);
754 n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
755 gadget->a_alt_hnp_support);
756 n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
757 (gadget->name ? gadget->name : ""));
758
759 return n;
760}
761static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
762
763/**
764 * show_driver: prints information about attached gadget (if any)
765 *
766 * Check "device.h" for details
767 */
768static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
769 char *buf)
770{
771 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
772 struct usb_gadget_driver *driver = udc->driver;
773 int n = 0;
774
775 dbg_trace("[%s] %p\n", __func__, buf);
776 if (attr == NULL || buf == NULL) {
777 dev_err(dev, "[%s] EINVAL\n", __func__);
778 return 0;
779 }
780
781 if (driver == NULL)
782 return scnprintf(buf, PAGE_SIZE,
783 "There is no gadget attached!\n");
784
785 n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
786 (driver->function ? driver->function : ""));
787 n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
788 driver->speed);
789
790 return n;
791}
792static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
793
794/* Maximum event message length */
795#define DBG_DATA_MSG 64UL
796
797/* Maximum event messages */
798#define DBG_DATA_MAX 128UL
799
800/* Event buffer descriptor */
801static struct {
802 char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
803 unsigned idx; /* index */
804 unsigned tty; /* print to console? */
805 rwlock_t lck; /* lock */
806} dbg_data = {
807 .idx = 0,
808 .tty = 0,
809 .lck = __RW_LOCK_UNLOCKED(lck)
810};
811
812/**
813 * dbg_dec: decrements debug event index
814 * @idx: buffer index
815 */
816static void dbg_dec(unsigned *idx)
817{
818 *idx = (*idx - 1) & (DBG_DATA_MAX-1);
819}
820
821/**
822 * dbg_inc: increments debug event index
823 * @idx: buffer index
824 */
825static void dbg_inc(unsigned *idx)
826{
827 *idx = (*idx + 1) & (DBG_DATA_MAX-1);
828}
829
830/**
831 * dbg_print: prints the common part of the event
832 * @addr: endpoint address
833 * @name: event name
834 * @status: status
835 * @extra: extra information
836 */
837static void dbg_print(u8 addr, const char *name, int status, const char *extra)
838{
839 struct timeval tval;
840 unsigned int stamp;
841 unsigned long flags;
842
843 write_lock_irqsave(&dbg_data.lck, flags);
844
845 do_gettimeofday(&tval);
846 stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
847 stamp = stamp * 1000000 + tval.tv_usec;
848
849 scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
850