[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / atmel_usba_udc.h

/*
 * Driver for the Atmel USBA high speed USB device controller
 *
 * Copyright (C) 2005-2007 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __LINUX_USB_GADGET_USBA_UDC_H__
#define __LINUX_USB_GADGET_USBA_UDC_H__

/* USB register offsets */
#define USBA_CTRL				0x0000
#define USBA_FNUM				0x0004
#define USBA_INT_ENB				0x0010
#define USBA_INT_STA				0x0014
#define USBA_INT_CLR				0x0018
#define USBA_EPT_RST				0x001c
#define USBA_TST				0x00e0

/* USB endpoint register offsets */
#define USBA_EPT_CFG				0x0000
#define USBA_EPT_CTL_ENB			0x0004
#define USBA_EPT_CTL_DIS			0x0008
#define USBA_EPT_CTL				0x000c
#define USBA_EPT_SET_STA			0x0014
#define USBA_EPT_CLR_STA			0x0018
#define USBA_EPT_STA				0x001c

/* USB DMA register offsets */
#define USBA_DMA_NXT_DSC			0x0000
#define USBA_DMA_ADDRESS			0x0004
#define USBA_DMA_CONTROL			0x0008
#define USBA_DMA_STATUS				0x000c

/* Bitfields in CTRL */
#define USBA_DEV_ADDR_OFFSET			0
#define USBA_DEV_ADDR_SIZE			7
#define USBA_FADDR_EN				(1 <<  7)
#define USBA_EN_USBA				(1 <<  8)
#define USBA_DETACH				(1 <<  9)
#define USBA_REMOTE_WAKE_UP			(1 << 10)

/* Bitfields in FNUM */
#define USBA_MICRO_FRAME_NUM_OFFSET		0
#define USBA_MICRO_FRAME_NUM_SIZE		3
#define USBA_FRAME_NUMBER_OFFSET		3
#define USBA_FRAME_NUMBER_SIZE			11
#define USBA_FRAME_NUM_ERROR			(1 << 31)

/* Bitfields in INT_ENB/INT_STA/INT_CLR */
#define USBA_HIGH_SPEED				(1 <<  0)
#define USBA_DET_SUSPEND			(1 <<  1)
#define USBA_MICRO_SOF				(1 <<  2)
#define USBA_SOF				(1 <<  3)
#define USBA_END_OF_RESET			(1 <<  4)
#define USBA_WAKE_UP				(1 <<  5)
#define USBA_END_OF_RESUME			(1 <<  6)
#define USBA_UPSTREAM_RESUME			(1 <<  7)
#define USBA_EPT_INT_OFFSET			8
#define USBA_EPT_INT_SIZE			16
#define USBA_DMA_INT_OFFSET			24
#define USBA_DMA_INT_SIZE			8

/* Bitfields in EPT_RST */
#define USBA_RST_OFFSET				0
#define USBA_RST_SIZE				16

/* Bitfields in USBA_TST */
#define USBA_SPEED_CFG_OFFSET			0
#define USBA_SPEED_CFG_SIZE			2
#define USBA_TST_J_MODE				(1 <<  2)
#define USBA_TST_K_MODE				(1 <<  3)
#define USBA_TST_PKT_MODE			(1 <<  4)
#define USBA_OPMODE2				(1 <<  5)

/* Bitfields in EPT_CFG */
#define USBA_EPT_SIZE_OFFSET			0
#define USBA_EPT_SIZE_SIZE			3
#define USBA_EPT_DIR_IN				(1 <<  3)
#define USBA_EPT_TYPE_OFFSET			4
#define USBA_EPT_TYPE_SIZE			2
#define USBA_BK_NUMBER_OFFSET			6
#define USBA_BK_NUMBER_SIZE			2
#define USBA_NB_TRANS_OFFSET			8
#define USBA_NB_TRANS_SIZE			2
#define USBA_EPT_MAPPED				(1 << 31)

/* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
#define USBA_EPT_ENABLE				(1 <<  0)
#define USBA_AUTO_VALID				(1 <<  1)
#define USBA_INTDIS_DMA				(1 <<  3)
#define USBA_NYET_DIS				(1 <<  4)
#define USBA_DATAX_RX				(1 <<  6)
#define USBA_MDATA_RX				(1 <<  7)
/* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
#define USBA_BUSY_BANK_IE			(1 << 18)

/* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
#define USBA_FORCE_STALL			(1 <<  5)
#define USBA_TOGGLE_CLR				(1 <<  6)
#define USBA_TOGGLE_SEQ_OFFSET			6
#define USBA_TOGGLE_SEQ_SIZE			2
#define USBA_ERR_OVFLW				(1 <<  8)
#define USBA_RX_BK_RDY				(1 <<  9)
#define USBA_KILL_BANK				(1 <<  9)
#define USBA_TX_COMPLETE			(1 << 10)
#define USBA_TX_PK_RDY				(1 << 11)
#define USBA_ISO_ERR_TRANS			(1 << 11)
#define USBA_RX_SETUP				(1 << 12)
#define USBA_ISO_ERR_FLOW			(1 << 12)
#define USBA_STALL_SENT				(1 << 13)
#define USBA_ISO_ERR_CRC			(1 << 13)
#define USBA_ISO_ERR_NBTRANS			(1 << 13)
#define USBA_NAK_IN				(1 << 14)
#define USBA_ISO_ERR_FLUSH			(1 << 14)
#define USBA_NAK_OUT				(1 << 15)
#define USBA_CURRENT_BANK_OFFSET		16
#define USBA_CURRENT_BANK_SIZE			2
#define USBA_BUSY_BANKS_OFFSET			18
#define USBA_BUSY_BANKS_SIZE			2
#define USBA_BYTE_COUNT_OFFSET			20
#define USBA_BYTE_COUNT_SIZE			11
#define USBA_SHORT_PACKET			(1 << 31)

/* Bitfields in DMA_CONTROL */
#define USBA_DMA_CH_EN				(1 <<  0)
#define USBA_DMA_LINK				(1 <<  1)
#define USBA_DMA_END_TR_EN			(1 <<  2)
#define USBA_DMA_END_BUF_EN			(1 <<  3)
#define USBA_DMA_END_TR_IE			(1 <<  4)
#define USBA_DMA_END_BUF_IE			(1 <<  5)
#define USBA_DMA_DESC_LOAD_IE			(1 <<  6)
#define USBA_DMA_BURST_LOCK			(1 <<  7)
#define USBA_DMA_BUF_LEN_OFFSET			16
#define USBA_DMA_BUF_LEN_SIZE			16

/* Bitfields in DMA_STATUS */
#define USBA_DMA_CH_ACTIVE			(1 <<  1)
#define USBA_DMA_END_TR_ST			(1 <<  4)
#define USBA_DMA_END_BUF_ST			(1 <<  5)
#define USBA_DMA_DESC_LOAD_ST			(1 <<  6)

/* Constants for SPEED_CFG */
#define USBA_SPEED_CFG_NORMAL			0
#define USBA_SPEED_CFG_FORCE_HIGH		2
#define USBA_SPEED_CFG_FORCE_FULL		3

/* Constants for EPT_SIZE */
#define USBA_EPT_SIZE_8				0
#define USBA_EPT_SIZE_16			1
#define USBA_EPT_SIZE_32			2
#define USBA_EPT_SIZE_64			3
#define USBA_EPT_SIZE_128			4
#define USBA_EPT_SIZE_256			5
#define USBA_EPT_SIZE_512			6
#define USBA_EPT_SIZE_1024			7

/* Constants for EPT_TYPE */
#define USBA_EPT_TYPE_CONTROL			0
#define USBA_EPT_TYPE_ISO			1
#define USBA_EPT_TYPE_BULK			2
#define USBA_EPT_TYPE_INT			3

/* Constants for BK_NUMBER */
#define USBA_BK_NUMBER_ZERO			0
#define USBA_BK_NUMBER_ONE			1
#define USBA_BK_NUMBER_DOUBLE			2
#define USBA_BK_NUMBER_TRIPLE			3

/* Bit manipulation macros */
#define USBA_BF(name, value)					\
	(((value) & ((1 << USBA_##name##_SIZE) - 1))		\
	 << USBA_##name##_OFFSET)
#define USBA_BFEXT(name, value)					\
	(((value) >> USBA_##name##_OFFSET)			\
	 & ((1 << USBA_##name##_SIZE) - 1))
#define USBA_BFINS(name, value, old)				\
	(((old) & ~(((1 << USBA_##name##_SIZE) - 1)		\
		    << USBA_##name##_OFFSET))			\
	 | USBA_BF(name, value))

/* Register access macros */
#define usba_readl(udc, reg)					\
	__raw_readl((udc)->regs + USBA_##reg)
#define usba_writel(udc, reg, value)				\
	__raw_writel((value), (udc)->regs + USBA_##reg)
#define usba_ep_readl(ep, reg)					\
	__raw_readl((ep)->ep_regs + USBA_EPT_##reg)
#define usba_ep_writel(ep, reg, value)				\
	__raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
#define usba_dma_readl(ep, reg)					\
	__raw_readl((ep)->dma_regs + USBA_DMA_##reg)
#define usba_dma_writel(ep, reg, value)				\
	__raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg)

/* Calculate base address for a given endpoint or DMA controller */
#define USBA_EPT_BASE(x)	(0x100 + (x) * 0x20)
#define USBA_DMA_BASE(x)	(0x300 + (x) * 0x10)
#define USBA_FIFO_BASE(x)	((x) << 16)

/* Synth parameters */
#define USBA_NR_ENDPOINTS	7

#define EP0_FIFO_SIZE		64
#define EP0_EPT_SIZE		USBA_EPT_SIZE_64
#define EP0_NR_BANKS		1

/*
 * REVISIT: Try to eliminate this value. Can we rely on req->mapped to
 * provide this information?
 */
#define DMA_ADDR_INVALID (~(dma_addr_t)0)

#define FIFO_IOMEM_ID	0
#define CTRL_IOMEM_ID	1

#ifdef DEBUG
#define DBG_ERR		0x0001	/* report all error returns */
#define DBG_HW		0x0002	/* debug hardware initialization */
#define DBG_GADGET	0x0004	/* calls to/from gadget driver */
#define DBG_INT		0x0008	/* interrupts */
#define DBG_BUS		0x0010	/* report changes in bus state */
#define DBG_QUEUE	0x0020  /* debug request queue processing */
#define DBG_FIFO	0x0040  /* debug FIFO contents */
#define DBG_DMA		0x0080  /* debug DMA handling */
#define DBG_REQ		0x0100	/* print out queued request length */
#define DBG_ALL		0xffff
#define DBG_NONE	0x0000

#define DEBUG_LEVEL	(DBG_ERR)
#define DBG(level, fmt, ...)					\
	do {							\
		if ((level) & DEBUG_LEVEL)			\
			printk(KERN_DEBUG "udc: " fmt, ## __VA_ARGS__);	\
	} while (0)
#else
#define DBG(level, fmt...)
#endif

enum usba_ctrl_state {
	WAIT_FOR_SETUP,
	DATA_STAGE_IN,
	DATA_STAGE_OUT,
	STATUS_STAGE_IN,
	STATUS_STAGE_OUT,
	STATUS_STAGE_ADDR,
	STATUS_STAGE_TEST,
};
/*
  EP_STATE_IDLE,
  EP_STATE_SETUP,
  EP_STATE_IN_DATA,
  EP_STATE_OUT_DATA,
  EP_STATE_SET_ADDR_STATUS,
  EP_STATE_RX_STATUS,
  EP_STATE_TX_STATUS,
  EP_STATE_HALT,
*/

struct usba_dma_desc {
	dma_addr_t next;
	dma_addr_t addr;
	u32 ctrl;
};

struct usba_ep {
	int					state;
	void __iomem				*ep_regs;
	void __iomem				*dma_regs;
	void __iomem				*fifo;
	struct usb_ep				ep;
	struct usba_udc				*udc;

	struct list_head			queue;
	const struct usb_endpoint_descriptor	*desc;

	u16					fifo_size;
	u8					nr_banks;
	u8					index;
	unsigned int				can_dma:1;
	unsigned int				can_isoc:1;
	unsigned int				is_isoc:1;
	unsigned int				is_in:1;

#ifdef CONFIG_USB_GADGET_DEBUG_FS
	u32					last_dma_status;
	struct dentry				*debugfs_dir;
	struct dentry				*debugfs_queue;
	struct dentry				*debugfs_dma_status;
	struct dentry				*debugfs_state;
#endif
};

struct usba_request {
	struct usb_request			req;
	struct list_head			queue;

	u32					ctrl;

	unsigned int				submitted:1;
	unsigned int				last_transaction:1;
	unsigned int				using_dma:1;
	unsigned int				mapped:1;
};

struct usba_udc {
	/* Protect hw registers from concurrent modifications */
	spinlock_t lock;

	void __iomem *regs;
	void __iomem *fifo;

	struct usb_gadget gadget;
	struct usb_gadget_driver *driver;
	struct platform_device *pdev;
	int irq;
	int vbus_pin;
	struct clk *pclk;
	struct clk *hclk;

	u16 devstatus;

	u16 test_mode;
	int vbus_prev;

#ifdef CONFIG_USB_GADGET_DEBUG_FS
	struct dentry *debugfs_root;
	struct dentry *debugfs_regs;
#endif
};

static inline struct usba_ep *to_usba_ep(struct usb_ep *ep)
{
	return container_of(ep, struct usba_ep, ep);
}

static inline struct usba_request *to_usba_req(struct usb_request *req)
{
	return container_of(req, struct usba_request, req);
}

static inline struct usba_udc *to_usba_udc(struct usb_gadget *gadget)
{
	return container_of(gadget, struct usba_udc, gadget);
}

#define ep_is_control(ep)	((ep)->index == 0)
#define ep_is_idle(ep)		((ep)->state == EP_STATE_IDLE)

#endif /* __LINUX_USB_GADGET_USBA_UDC_H */
Commit	Line	Data
914a3f3b HS	1	/*
	2	* Driver for the Atmel USBA high speed USB device controller
	3	*
	4	* Copyright (C) 2005-2007 Atmel Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef __LINUX_USB_GADGET_USBA_UDC_H__
	11	#define __LINUX_USB_GADGET_USBA_UDC_H__
	12
	13	/* USB register offsets */
	14	#define USBA_CTRL 0x0000
	15	#define USBA_FNUM 0x0004
	16	#define USBA_INT_ENB 0x0010
	17	#define USBA_INT_STA 0x0014
	18	#define USBA_INT_CLR 0x0018
	19	#define USBA_EPT_RST 0x001c
	20	#define USBA_TST 0x00e0
	21
	22	/* USB endpoint register offsets */
	23	#define USBA_EPT_CFG 0x0000
	24	#define USBA_EPT_CTL_ENB 0x0004
	25	#define USBA_EPT_CTL_DIS 0x0008
	26	#define USBA_EPT_CTL 0x000c
	27	#define USBA_EPT_SET_STA 0x0014
	28	#define USBA_EPT_CLR_STA 0x0018
	29	#define USBA_EPT_STA 0x001c
	30
	31	/* USB DMA register offsets */
	32	#define USBA_DMA_NXT_DSC 0x0000
	33	#define USBA_DMA_ADDRESS 0x0004
	34	#define USBA_DMA_CONTROL 0x0008
	35	#define USBA_DMA_STATUS 0x000c
	36
	37	/* Bitfields in CTRL */
	38	#define USBA_DEV_ADDR_OFFSET 0
	39	#define USBA_DEV_ADDR_SIZE 7
	40	#define USBA_FADDR_EN (1 << 7)
	41	#define USBA_EN_USBA (1 << 8)
	42	#define USBA_DETACH (1 << 9)
	43	#define USBA_REMOTE_WAKE_UP (1 << 10)
	44
	45	/* Bitfields in FNUM */
	46	#define USBA_MICRO_FRAME_NUM_OFFSET 0
	47	#define USBA_MICRO_FRAME_NUM_SIZE 3
	48	#define USBA_FRAME_NUMBER_OFFSET 3
	49	#define USBA_FRAME_NUMBER_SIZE 11
	50	#define USBA_FRAME_NUM_ERROR (1 << 31)
	51
	52	/* Bitfields in INT_ENB/INT_STA/INT_CLR */
	53	#define USBA_HIGH_SPEED (1 << 0)
	54	#define USBA_DET_SUSPEND (1 << 1)
	55	#define USBA_MICRO_SOF (1 << 2)
	56	#define USBA_SOF (1 << 3)
	57	#define USBA_END_OF_RESET (1 << 4)
	58	#define USBA_WAKE_UP (1 << 5)
	59	#define USBA_END_OF_RESUME (1 << 6)
	60	#define USBA_UPSTREAM_RESUME (1 << 7)
	61	#define USBA_EPT_INT_OFFSET 8
	62	#define USBA_EPT_INT_SIZE 16
	63	#define USBA_DMA_INT_OFFSET 24
	64	#define USBA_DMA_INT_SIZE 8
65
66	/* Bitfields in EPT_RST */
67	#define USBA_RST_OFFSET 0
68	#define USBA_RST_SIZE 16
69
70	/* Bitfields in USBA_TST */
71	#define USBA_SPEED_CFG_OFFSET 0
72	#define USBA_SPEED_CFG_SIZE 2
73	#define USBA_TST_J_MODE (1 << 2)
74	#define USBA_TST_K_MODE (1 << 3)
75	#define USBA_TST_PKT_MODE (1 << 4)
76	#define USBA_OPMODE2 (1 << 5)
77
78	/* Bitfields in EPT_CFG */
79	#define USBA_EPT_SIZE_OFFSET 0
80	#define USBA_EPT_SIZE_SIZE 3
81	#define USBA_EPT_DIR_IN (1 << 3)
82	#define USBA_EPT_TYPE_OFFSET 4
83	#define USBA_EPT_TYPE_SIZE 2
84	#define USBA_BK_NUMBER_OFFSET 6
85	#define USBA_BK_NUMBER_SIZE 2
86	#define USBA_NB_TRANS_OFFSET 8
87	#define USBA_NB_TRANS_SIZE 2
88	#define USBA_EPT_MAPPED (1 << 31)
89
90	/* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
91	#define USBA_EPT_ENABLE (1 << 0)
92	#define USBA_AUTO_VALID (1 << 1)
93	#define USBA_INTDIS_DMA (1 << 3)
94	#define USBA_NYET_DIS (1 << 4)
95	#define USBA_DATAX_RX (1 << 6)
96	#define USBA_MDATA_RX (1 << 7)
97	/* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
98	#define USBA_BUSY_BANK_IE (1 << 18)
99
100	/* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
101	#define USBA_FORCE_STALL (1 << 5)
102	#define USBA_TOGGLE_CLR (1 << 6)
103	#define USBA_TOGGLE_SEQ_OFFSET 6
104	#define USBA_TOGGLE_SEQ_SIZE 2
105	#define USBA_ERR_OVFLW (1 << 8)
106	#define USBA_RX_BK_RDY (1 << 9)
107	#define USBA_KILL_BANK (1 << 9)
108	#define USBA_TX_COMPLETE (1 << 10)
109	#define USBA_TX_PK_RDY (1 << 11)
110	#define USBA_ISO_ERR_TRANS (1 << 11)
111	#define USBA_RX_SETUP (1 << 12)
112	#define USBA_ISO_ERR_FLOW (1 << 12)
113	#define USBA_STALL_SENT (1 << 13)
114	#define USBA_ISO_ERR_CRC (1 << 13)
115	#define USBA_ISO_ERR_NBTRANS (1 << 13)
116	#define USBA_NAK_IN (1 << 14)
117	#define USBA_ISO_ERR_FLUSH (1 << 14)
118	#define USBA_NAK_OUT (1 << 15)
119	#define USBA_CURRENT_BANK_OFFSET 16
120	#define USBA_CURRENT_BANK_SIZE 2
121	#define USBA_BUSY_BANKS_OFFSET 18
122	#define USBA_BUSY_BANKS_SIZE 2
123	#define USBA_BYTE_COUNT_OFFSET 20
124	#define USBA_BYTE_COUNT_SIZE 11
125	#define USBA_SHORT_PACKET (1 << 31)
126
127	/* Bitfields in DMA_CONTROL */
128	#define USBA_DMA_CH_EN (1 << 0)
129	#define USBA_DMA_LINK (1 << 1)
130	#define USBA_DMA_END_TR_EN (1 << 2)
131	#define USBA_DMA_END_BUF_EN (1 << 3)
132	#define USBA_DMA_END_TR_IE (1 << 4)
133	#define USBA_DMA_END_BUF_IE (1 << 5)
134	#define USBA_DMA_DESC_LOAD_IE (1 << 6)
135	#define USBA_DMA_BURST_LOCK (1 << 7)
136	#define USBA_DMA_BUF_LEN_OFFSET 16
137	#define USBA_DMA_BUF_LEN_SIZE 16
138
139	/* Bitfields in DMA_STATUS */
140	#define USBA_DMA_CH_ACTIVE (1 << 1)
141	#define USBA_DMA_END_TR_ST (1 << 4)
142	#define USBA_DMA_END_BUF_ST (1 << 5)
143	#define USBA_DMA_DESC_LOAD_ST (1 << 6)
144
145	/* Constants for SPEED_CFG */
146	#define USBA_SPEED_CFG_NORMAL 0
147	#define USBA_SPEED_CFG_FORCE_HIGH 2
148	#define USBA_SPEED_CFG_FORCE_FULL 3
149
150	/* Constants for EPT_SIZE */
151	#define USBA_EPT_SIZE_8 0
152	#define USBA_EPT_SIZE_16 1
153	#define USBA_EPT_SIZE_32 2
154	#define USBA_EPT_SIZE_64 3
155	#define USBA_EPT_SIZE_128 4
156	#define USBA_EPT_SIZE_256 5
157	#define USBA_EPT_SIZE_512 6
158	#define USBA_EPT_SIZE_1024 7
159
160	/* Constants for EPT_TYPE */
161	#define USBA_EPT_TYPE_CONTROL 0
162	#define USBA_EPT_TYPE_ISO 1
163	#define USBA_EPT_TYPE_BULK 2
164	#define USBA_EPT_TYPE_INT 3
165
166	/* Constants for BK_NUMBER */
167	#define USBA_BK_NUMBER_ZERO 0
168	#define USBA_BK_NUMBER_ONE 1
169	#define USBA_BK_NUMBER_DOUBLE 2
170	#define USBA_BK_NUMBER_TRIPLE 3
171
172	/* Bit manipulation macros */
173	#define USBA_BF(name, value) \
174	(((value) & ((1 << USBA_##name##_SIZE) - 1)) \
175	<< USBA_##name##_OFFSET)
176	#define USBA_BFEXT(name, value) \
177	(((value) >> USBA_##name##_OFFSET) \
178	& ((1 << USBA_##name##_SIZE) - 1))
179	#define USBA_BFINS(name, value, old) \
180	(((old) & ~(((1 << USBA_##name##_SIZE) - 1) \
181	<< USBA_##name##_OFFSET)) \
182	\| USBA_BF(name, value))
183
184	/* Register access macros */
185	#define usba_readl(udc, reg) \
186	__raw_readl((udc)->regs + USBA_##reg)
187	#define usba_writel(udc, reg, value) \
188	__raw_writel((value), (udc)->regs + USBA_##reg)
189	#define usba_ep_readl(ep, reg) \
190	__raw_readl((ep)->ep_regs + USBA_EPT_##reg)
191	#define usba_ep_writel(ep, reg, value) \
192	__raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
193	#define usba_dma_readl(ep, reg) \
194	__raw_readl((ep)->dma_regs + USBA_DMA_##reg)
195	#define usba_dma_writel(ep, reg, value) \
196	__raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
197
198	/* Calculate base address for a given endpoint or DMA controller */
199	#define USBA_EPT_BASE(x) (0x100 + (x) * 0x20)
200	#define USBA_DMA_BASE(x) (0x300 + (x) * 0x10)
201	#define USBA_FIFO_BASE(x) ((x) << 16)
202
203	/* Synth parameters */
204	#define USBA_NR_ENDPOINTS 7
205
206	#define EP0_FIFO_SIZE 64
207	#define EP0_EPT_SIZE USBA_EPT_SIZE_64
208	#define EP0_NR_BANKS 1
209
210	/*
211	* REVISIT: Try to eliminate this value. Can we rely on req->mapped to
212	* provide this information?
213	*/
214	#define DMA_ADDR_INVALID (~(dma_addr_t)0)
215
216	#define FIFO_IOMEM_ID 0
217	#define CTRL_IOMEM_ID 1
218
219	#ifdef DEBUG
220	#define DBG_ERR 0x0001 /* report all error returns */
221	#define DBG_HW 0x0002 /* debug hardware initialization */
222	#define DBG_GADGET 0x0004 /* calls to/from gadget driver */
223	#define DBG_INT 0x0008 /* interrupts */
224	#define DBG_BUS 0x0010 /* report changes in bus state */
225	#define DBG_QUEUE 0x0020 /* debug request queue processing */
226	#define DBG_FIFO 0x0040 /* debug FIFO contents */
227	#define DBG_DMA 0x0080 /* debug DMA handling */
228	#define DBG_REQ 0x0100 /* print out queued request length */
229	#define DBG_ALL 0xffff
230	#define DBG_NONE 0x0000
231
232	#define DEBUG_LEVEL (DBG_ERR)
233	#define DBG(level, fmt, ...) \
234	do { \
235	if ((level) & DEBUG_LEVEL) \
236	printk(KERN_DEBUG "udc: " fmt, ## __VA_ARGS__); \
237	} while (0)
238	#else
239	#define DBG(level, fmt...)
240	#endif
241
242	enum usba_ctrl_state {
243	WAIT_FOR_SETUP,
244	DATA_STAGE_IN,
245	DATA_STAGE_OUT,
246	STATUS_STAGE_IN,
247	STATUS_STAGE_OUT,
248	STATUS_STAGE_ADDR,
249	STATUS_STAGE_TEST,
250	};
251	/*
252	EP_STATE_IDLE,
253	EP_STATE_SETUP,
254	EP_STATE_IN_DATA,
255	EP_STATE_OUT_DATA,
256	EP_STATE_SET_ADDR_STATUS,
257	EP_STATE_RX_STATUS,
258	EP_STATE_TX_STATUS,
259	EP_STATE_HALT,
260	*/
261
262	struct usba_dma_desc {
263	dma_addr_t next;
264	dma_addr_t addr;
265	u32 ctrl;
266	};
267
268	struct usba_ep {
269	int state;
270	void __iomem *ep_regs;
271	void __iomem *dma_regs;
272	void __iomem *fifo;
273	struct usb_ep ep;
274	struct usba_udc *udc;
275
276	struct list_head queue;
277	const struct usb_endpoint_descriptor *desc;
278
279	u16 fifo_size;
280	u8 nr_banks;
281	u8 index;
282	unsigned int can_dma:1;
283	unsigned int can_isoc:1;
284	unsigned int is_isoc:1;
285	unsigned int is_in:1;
286
287	#ifdef CONFIG_USB_GADGET_DEBUG_FS
288	u32 last_dma_status;
289	struct dentry *debugfs_dir;
290	struct dentry *debugfs_queue;
291	struct dentry *debugfs_dma_status;
292	struct dentry *debugfs_state;
293	#endif
294	};
295
296	struct usba_request {
297	struct usb_request req;
298	struct list_head queue;
299
300	u32 ctrl;
301
302	unsigned int submitted:1;
303	unsigned int last_transaction:1;
304	unsigned int using_dma:1;
305	unsigned int mapped:1;
306	};
307
308	struct usba_udc {
309	/* Protect hw registers from concurrent modifications */
310	spinlock_t lock;
311
312	void __iomem *regs;
313	void __iomem *fifo;
314
315	struct usb_gadget gadget;
316	struct usb_gadget_driver *driver;
317	struct platform_device *pdev;
318	int irq;
319	int vbus_pin;
320	struct clk *pclk;
321	struct clk *hclk;
322
58ed7b94 HS	323	u16 devstatus;
	324
	325	u16 test_mode;
914a3f3b HS	326	int vbus_prev;
	327
	328	#ifdef CONFIG_USB_GADGET_DEBUG_FS
	329	struct dentry *debugfs_root;
	330	struct dentry *debugfs_regs;
	331	#endif
	332	};
	333
	334	static inline struct usba_ep to_usba_ep(struct usb_ep ep)
	335	{
	336	return container_of(ep, struct usba_ep, ep);
	337	}
	338
	339	static inline struct usba_request to_usba_req(struct usb_request req)
	340	{
	341	return container_of(req, struct usba_request, req);
	342	}
	343
	344	static inline struct usba_udc to_usba_udc(struct usb_gadget gadget)
	345	{
	346	return container_of(gadget, struct usba_udc, gadget);
	347	}
	348
	349	#define ep_is_control(ep) ((ep)->index == 0)
	350	#define ep_is_idle(ep) ((ep)->state == EP_STATE_IDLE)
	351
	352	#endif /* __LINUX_USB_GADGET_USBA_UDC_H */