usb: chipidea: add power_budget limit for ehci to platform data
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / chipidea / udc.c
CommitLineData
aa69a809 1/*
eb70e5ab 2 * udc.c - ChipIdea UDC driver
aa69a809
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3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
36825a2d 13#include <linux/delay.h>
aa69a809
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14#include <linux/device.h>
15#include <linux/dmapool.h>
16#include <linux/dma-mapping.h>
17#include <linux/init.h>
62bb84ed
AS
18#include <linux/platform_device.h>
19#include <linux/module.h>
aa69a809 20#include <linux/interrupt.h>
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21#include <linux/io.h>
22#include <linux/irq.h>
23#include <linux/kernel.h>
5a0e3ad6 24#include <linux/slab.h>
c036019e 25#include <linux/pm_runtime.h>
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26#include <linux/usb/ch9.h>
27#include <linux/usb/gadget.h>
f01ef574 28#include <linux/usb/otg.h>
e443b333 29#include <linux/usb/chipidea.h>
aa69a809 30
e443b333
AS
31#include "ci.h"
32#include "udc.h"
33#include "bits.h"
34#include "debug.h"
954aad8c 35
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36/* control endpoint description */
37static const struct usb_endpoint_descriptor
ca9cfea0 38ctrl_endpt_out_desc = {
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39 .bLength = USB_DT_ENDPOINT_SIZE,
40 .bDescriptorType = USB_DT_ENDPOINT,
41
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42 .bEndpointAddress = USB_DIR_OUT,
43 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
44 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
45};
46
47static const struct usb_endpoint_descriptor
48ctrl_endpt_in_desc = {
49 .bLength = USB_DT_ENDPOINT_SIZE,
50 .bDescriptorType = USB_DT_ENDPOINT,
51
52 .bEndpointAddress = USB_DIR_IN,
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53 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
54 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
55};
56
aa69a809
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57/**
58 * hw_ep_bit: calculates the bit number
59 * @num: endpoint number
60 * @dir: endpoint direction
61 *
62 * This function returns bit number
63 */
64static inline int hw_ep_bit(int num, int dir)
65{
66 return num + (dir ? 16 : 0);
67}
68
e443b333 69static inline int ep_to_bit(struct ci13xxx *udc, int n)
dd39c358 70{
d3595d13 71 int fill = 16 - udc->hw_ep_max / 2;
dd39c358 72
d3595d13 73 if (n >= udc->hw_ep_max / 2)
dd39c358
MKB
74 n += fill;
75
76 return n;
77}
78
aa69a809
DL
79/**
80 * hw_device_state: enables/disables interrupts & starts/stops device (execute
81 * without interruption)
82 * @dma: 0 => disable, !0 => enable and set dma engine
83 *
84 * This function returns an error code
85 */
d3595d13 86static int hw_device_state(struct ci13xxx *udc, u32 dma)
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DL
87{
88 if (dma) {
262c1632 89 hw_write(udc, OP_ENDPTLISTADDR, ~0, dma);
aa69a809 90 /* interrupt, error, port change, reset, sleep/suspend */
262c1632 91 hw_write(udc, OP_USBINTR, ~0,
aa69a809 92 USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
262c1632 93 hw_write(udc, OP_USBCMD, USBCMD_RS, USBCMD_RS);
aa69a809 94 } else {
262c1632
AS
95 hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
96 hw_write(udc, OP_USBINTR, ~0, 0);
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97 }
98 return 0;
99}
100
101/**
102 * hw_ep_flush: flush endpoint fifo (execute without interruption)
103 * @num: endpoint number
104 * @dir: endpoint direction
105 *
106 * This function returns an error code
107 */
d3595d13 108static int hw_ep_flush(struct ci13xxx *udc, int num, int dir)
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109{
110 int n = hw_ep_bit(num, dir);
111
112 do {
113 /* flush any pending transfer */
262c1632
AS
114 hw_write(udc, OP_ENDPTFLUSH, BIT(n), BIT(n));
115 while (hw_read(udc, OP_ENDPTFLUSH, BIT(n)))
aa69a809 116 cpu_relax();
262c1632 117 } while (hw_read(udc, OP_ENDPTSTAT, BIT(n)));
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118
119 return 0;
120}
121
122/**
123 * hw_ep_disable: disables endpoint (execute without interruption)
124 * @num: endpoint number
125 * @dir: endpoint direction
126 *
127 * This function returns an error code
128 */
d3595d13 129static int hw_ep_disable(struct ci13xxx *udc, int num, int dir)
aa69a809 130{
d3595d13 131 hw_ep_flush(udc, num, dir);
262c1632 132 hw_write(udc, OP_ENDPTCTRL + num,
d3595d13 133 dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
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134 return 0;
135}
136
137/**
138 * hw_ep_enable: enables endpoint (execute without interruption)
139 * @num: endpoint number
140 * @dir: endpoint direction
141 * @type: endpoint type
142 *
143 * This function returns an error code
144 */
d3595d13 145static int hw_ep_enable(struct ci13xxx *udc, int num, int dir, int type)
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DL
146{
147 u32 mask, data;
148
149 if (dir) {
150 mask = ENDPTCTRL_TXT; /* type */
151 data = type << ffs_nr(mask);
152
153 mask |= ENDPTCTRL_TXS; /* unstall */
154 mask |= ENDPTCTRL_TXR; /* reset data toggle */
155 data |= ENDPTCTRL_TXR;
156 mask |= ENDPTCTRL_TXE; /* enable */
157 data |= ENDPTCTRL_TXE;
158 } else {
159 mask = ENDPTCTRL_RXT; /* type */
160 data = type << ffs_nr(mask);
161
162 mask |= ENDPTCTRL_RXS; /* unstall */
163 mask |= ENDPTCTRL_RXR; /* reset data toggle */
164 data |= ENDPTCTRL_RXR;
165 mask |= ENDPTCTRL_RXE; /* enable */
166 data |= ENDPTCTRL_RXE;
167 }
262c1632 168 hw_write(udc, OP_ENDPTCTRL + num, mask, data);
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169 return 0;
170}
171
172/**
173 * hw_ep_get_halt: return endpoint halt status
174 * @num: endpoint number
175 * @dir: endpoint direction
176 *
177 * This function returns 1 if endpoint halted
178 */
d3595d13 179static int hw_ep_get_halt(struct ci13xxx *udc, int num, int dir)
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180{
181 u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
182
262c1632 183 return hw_read(udc, OP_ENDPTCTRL + num, mask) ? 1 : 0;
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184}
185
aa69a809
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186/**
187 * hw_test_and_clear_setup_status: test & clear setup status (execute without
188 * interruption)
dd39c358 189 * @n: endpoint number
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190 *
191 * This function returns setup status
192 */
d3595d13 193static int hw_test_and_clear_setup_status(struct ci13xxx *udc, int n)
aa69a809 194{
d3595d13 195 n = ep_to_bit(udc, n);
262c1632 196 return hw_test_and_clear(udc, OP_ENDPTSETUPSTAT, BIT(n));
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197}
198
199/**
200 * hw_ep_prime: primes endpoint (execute without interruption)
201 * @num: endpoint number
202 * @dir: endpoint direction
203 * @is_ctrl: true if control endpoint
204 *
205 * This function returns an error code
206 */
d3595d13 207static int hw_ep_prime(struct ci13xxx *udc, int num, int dir, int is_ctrl)
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208{
209 int n = hw_ep_bit(num, dir);
210
262c1632 211 if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
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212 return -EAGAIN;
213
262c1632 214 hw_write(udc, OP_ENDPTPRIME, BIT(n), BIT(n));
aa69a809 215
262c1632 216 while (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
aa69a809 217 cpu_relax();
262c1632 218 if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
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219 return -EAGAIN;
220
221 /* status shoult be tested according with manual but it doesn't work */
222 return 0;
223}
224
225/**
226 * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
227 * without interruption)
228 * @num: endpoint number
229 * @dir: endpoint direction
230 * @value: true => stall, false => unstall
231 *
232 * This function returns an error code
233 */
d3595d13 234static int hw_ep_set_halt(struct ci13xxx *udc, int num, int dir, int value)
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235{
236 if (value != 0 && value != 1)
237 return -EINVAL;
238
239 do {
262c1632 240 enum ci13xxx_regs reg = OP_ENDPTCTRL + num;
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241 u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
242 u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
243
244 /* data toggle - reserved for EP0 but it's in ESS */
262c1632
AS
245 hw_write(udc, reg, mask_xs|mask_xr,
246 value ? mask_xs : mask_xr);
d3595d13 247 } while (value != hw_ep_get_halt(udc, num, dir));
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248
249 return 0;
250}
251
aa69a809
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252/**
253 * hw_is_port_high_speed: test if port is high speed
254 *
255 * This function returns true if high speed port
256 */
d3595d13 257static int hw_port_is_high_speed(struct ci13xxx *udc)
aa69a809 258{
262c1632
AS
259 return udc->hw_bank.lpm ? hw_read(udc, OP_DEVLC, DEVLC_PSPD) :
260 hw_read(udc, OP_PORTSC, PORTSC_HSP);
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261}
262
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263/**
264 * hw_read_intr_enable: returns interrupt enable register
265 *
266 * This function returns register data
267 */
d3595d13 268static u32 hw_read_intr_enable(struct ci13xxx *udc)
aa69a809 269{
262c1632 270 return hw_read(udc, OP_USBINTR, ~0);
aa69a809
DL
271}
272
273/**
274 * hw_read_intr_status: returns interrupt status register
275 *
276 * This function returns register data
277 */
d3595d13 278static u32 hw_read_intr_status(struct ci13xxx *udc)
aa69a809 279{
262c1632 280 return hw_read(udc, OP_USBSTS, ~0);
aa69a809
DL
281}
282
aa69a809
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283/**
284 * hw_test_and_clear_complete: test & clear complete status (execute without
285 * interruption)
dd39c358 286 * @n: endpoint number
aa69a809
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287 *
288 * This function returns complete status
289 */
d3595d13 290static int hw_test_and_clear_complete(struct ci13xxx *udc, int n)
aa69a809 291{
d3595d13 292 n = ep_to_bit(udc, n);
262c1632 293 return hw_test_and_clear(udc, OP_ENDPTCOMPLETE, BIT(n));
aa69a809
DL
294}
295
296/**
297 * hw_test_and_clear_intr_active: test & clear active interrupts (execute
298 * without interruption)
299 *
300 * This function returns active interrutps
301 */
d3595d13 302static u32 hw_test_and_clear_intr_active(struct ci13xxx *udc)
aa69a809 303{
d3595d13 304 u32 reg = hw_read_intr_status(udc) & hw_read_intr_enable(udc);
aa69a809 305
262c1632 306 hw_write(udc, OP_USBSTS, ~0, reg);
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DL
307 return reg;
308}
309
310/**
311 * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
312 * interruption)
313 *
314 * This function returns guard value
315 */
d3595d13 316static int hw_test_and_clear_setup_guard(struct ci13xxx *udc)
aa69a809 317{
262c1632 318 return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, 0);
aa69a809
DL
319}
320
321/**
322 * hw_test_and_set_setup_guard: test & set setup guard (execute without
323 * interruption)
324 *
325 * This function returns guard value
326 */
d3595d13 327static int hw_test_and_set_setup_guard(struct ci13xxx *udc)
aa69a809 328{
262c1632 329 return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
aa69a809
DL
330}
331
332/**
333 * hw_usb_set_address: configures USB address (execute without interruption)
334 * @value: new USB address
335 *
ef15e549
AS
336 * This function explicitly sets the address, without the "USBADRA" (advance)
337 * feature, which is not supported by older versions of the controller.
aa69a809 338 */
ef15e549 339static void hw_usb_set_address(struct ci13xxx *udc, u8 value)
aa69a809 340{
ef15e549
AS
341 hw_write(udc, OP_DEVICEADDR, DEVICEADDR_USBADR,
342 value << ffs_nr(DEVICEADDR_USBADR));
aa69a809
DL
343}
344
345/**
346 * hw_usb_reset: restart device after a bus reset (execute without
347 * interruption)
348 *
349 * This function returns an error code
350 */
d3595d13 351static int hw_usb_reset(struct ci13xxx *udc)
aa69a809 352{
d3595d13 353 hw_usb_set_address(udc, 0);
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354
355 /* ESS flushes only at end?!? */
262c1632 356 hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
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357
358 /* clear setup token semaphores */
262c1632 359 hw_write(udc, OP_ENDPTSETUPSTAT, 0, 0);
aa69a809
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360
361 /* clear complete status */
262c1632 362 hw_write(udc, OP_ENDPTCOMPLETE, 0, 0);
aa69a809
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363
364 /* wait until all bits cleared */
262c1632 365 while (hw_read(udc, OP_ENDPTPRIME, ~0))
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366 udelay(10); /* not RTOS friendly */
367
368 /* reset all endpoints ? */
369
370 /* reset internal status and wait for further instructions
371 no need to verify the port reset status (ESS does it) */
372
373 return 0;
374}
375
aa69a809
DL
376/******************************************************************************
377 * UTIL block
378 *****************************************************************************/
379/**
380 * _usb_addr: calculates endpoint address from direction & number
381 * @ep: endpoint
382 */
383static inline u8 _usb_addr(struct ci13xxx_ep *ep)
384{
385 return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
386}
387
388/**
389 * _hardware_queue: configures a request at hardware level
390 * @gadget: gadget
391 * @mEp: endpoint
392 *
393 * This function returns an error code
394 */
395static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
396{
d3595d13 397 struct ci13xxx *udc = mEp->udc;
aa69a809 398 unsigned i;
0e6ca199
PK
399 int ret = 0;
400 unsigned length = mReq->req.length;
aa69a809 401
aa69a809
DL
402 /* don't queue twice */
403 if (mReq->req.status == -EALREADY)
404 return -EALREADY;
405
aa69a809 406 mReq->req.status = -EALREADY;
954aad8c 407 if (length && mReq->req.dma == DMA_ADDR_INVALID) {
aa69a809
DL
408 mReq->req.dma = \
409 dma_map_single(mEp->device, mReq->req.buf,
0e6ca199
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410 length, mEp->dir ? DMA_TO_DEVICE :
411 DMA_FROM_DEVICE);
aa69a809
DL
412 if (mReq->req.dma == 0)
413 return -ENOMEM;
414
415 mReq->map = 1;
416 }
417
0e6ca199
PK
418 if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
419 mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
420 &mReq->zdma);
421 if (mReq->zptr == NULL) {
422 if (mReq->map) {
423 dma_unmap_single(mEp->device, mReq->req.dma,
424 length, mEp->dir ? DMA_TO_DEVICE :
425 DMA_FROM_DEVICE);
954aad8c 426 mReq->req.dma = DMA_ADDR_INVALID;
0e6ca199
PK
427 mReq->map = 0;
428 }
429 return -ENOMEM;
430 }
431 memset(mReq->zptr, 0, sizeof(*mReq->zptr));
432 mReq->zptr->next = TD_TERMINATE;
433 mReq->zptr->token = TD_STATUS_ACTIVE;
434 if (!mReq->req.no_interrupt)
435 mReq->zptr->token |= TD_IOC;
436 }
aa69a809
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437 /*
438 * TD configuration
439 * TODO - handle requests which spawns into several TDs
440 */
441 memset(mReq->ptr, 0, sizeof(*mReq->ptr));
0e6ca199 442 mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
aa69a809 443 mReq->ptr->token &= TD_TOTAL_BYTES;
aa69a809 444 mReq->ptr->token |= TD_STATUS_ACTIVE;
0e6ca199
PK
445 if (mReq->zptr) {
446 mReq->ptr->next = mReq->zdma;
447 } else {
448 mReq->ptr->next = TD_TERMINATE;
449 if (!mReq->req.no_interrupt)
450 mReq->ptr->token |= TD_IOC;
451 }
aa69a809
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452 mReq->ptr->page[0] = mReq->req.dma;
453 for (i = 1; i < 5; i++)
454 mReq->ptr->page[i] =
0a313c4d 455 (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
aa69a809 456
0e6ca199
PK
457 if (!list_empty(&mEp->qh.queue)) {
458 struct ci13xxx_req *mReqPrev;
459 int n = hw_ep_bit(mEp->num, mEp->dir);
460 int tmp_stat;
461
462 mReqPrev = list_entry(mEp->qh.queue.prev,
463 struct ci13xxx_req, queue);
464 if (mReqPrev->zptr)
465 mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
466 else
467 mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
468 wmb();
262c1632 469 if (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
0e6ca199
PK
470 goto done;
471 do {
262c1632
AS
472 hw_write(udc, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
473 tmp_stat = hw_read(udc, OP_ENDPTSTAT, BIT(n));
474 } while (!hw_read(udc, OP_USBCMD, USBCMD_ATDTW));
475 hw_write(udc, OP_USBCMD, USBCMD_ATDTW, 0);
0e6ca199
PK
476 if (tmp_stat)
477 goto done;
478 }
479
480 /* QH configuration */
ca9cfea0
PK
481 mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
482 mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
0e6ca199 483 mEp->qh.ptr->cap |= QH_ZLT;
aa69a809
DL
484
485 wmb(); /* synchronize before ep prime */
486
d3595d13 487 ret = hw_ep_prime(udc, mEp->num, mEp->dir,
aa69a809 488 mEp->type == USB_ENDPOINT_XFER_CONTROL);
0e6ca199
PK
489done:
490 return ret;
aa69a809
DL
491}
492
493/**
494 * _hardware_dequeue: handles a request at hardware level
495 * @gadget: gadget
496 * @mEp: endpoint
497 *
498 * This function returns an error code
499 */
500static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
501{
aa69a809
DL
502 if (mReq->req.status != -EALREADY)
503 return -EINVAL;
504
0e6ca199
PK
505 if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
506 return -EBUSY;
507
508 if (mReq->zptr) {
509 if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
510 return -EBUSY;
511 dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
512 mReq->zptr = NULL;
513 }
aa69a809
DL
514
515 mReq->req.status = 0;
516
517 if (mReq->map) {
518 dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
519 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
954aad8c 520 mReq->req.dma = DMA_ADDR_INVALID;
aa69a809
DL
521 mReq->map = 0;
522 }
523
524 mReq->req.status = mReq->ptr->token & TD_STATUS;
0e6ca199 525 if ((TD_STATUS_HALTED & mReq->req.status) != 0)
aa69a809
DL
526 mReq->req.status = -1;
527 else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
528 mReq->req.status = -1;
529 else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
530 mReq->req.status = -1;
531
532 mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
533 mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
534 mReq->req.actual = mReq->req.length - mReq->req.actual;
535 mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
536
537 return mReq->req.actual;
538}
539
540/**
541 * _ep_nuke: dequeues all endpoint requests
542 * @mEp: endpoint
543 *
544 * This function returns an error code
545 * Caller must hold lock
546 */
547static int _ep_nuke(struct ci13xxx_ep *mEp)
548__releases(mEp->lock)
549__acquires(mEp->lock)
550{
aa69a809
DL
551 if (mEp == NULL)
552 return -EINVAL;
553
d3595d13 554 hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
aa69a809 555
ca9cfea0 556 while (!list_empty(&mEp->qh.queue)) {
aa69a809
DL
557
558 /* pop oldest request */
559 struct ci13xxx_req *mReq = \
ca9cfea0 560 list_entry(mEp->qh.queue.next,
aa69a809
DL
561 struct ci13xxx_req, queue);
562 list_del_init(&mReq->queue);
563 mReq->req.status = -ESHUTDOWN;
564
7c25a826 565 if (mReq->req.complete != NULL) {
aa69a809
DL
566 spin_unlock(mEp->lock);
567 mReq->req.complete(&mEp->ep, &mReq->req);
568 spin_lock(mEp->lock);
569 }
570 }
571 return 0;
572}
573
574/**
575 * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
576 * @gadget: gadget
577 *
578 * This function returns an error code
aa69a809
DL
579 */
580static int _gadget_stop_activity(struct usb_gadget *gadget)
aa69a809
DL
581{
582 struct usb_ep *ep;
583 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
e2b61c1d 584 unsigned long flags;
aa69a809 585
d3595d13 586 spin_lock_irqsave(&udc->lock, flags);
e2b61c1d
PK
587 udc->gadget.speed = USB_SPEED_UNKNOWN;
588 udc->remote_wakeup = 0;
589 udc->suspended = 0;
d3595d13 590 spin_unlock_irqrestore(&udc->lock, flags);
e2b61c1d 591
aa69a809
DL
592 /* flush all endpoints */
593 gadget_for_each_ep(ep, gadget) {
594 usb_ep_fifo_flush(ep);
595 }
d36ade60
AS
596 usb_ep_fifo_flush(&udc->ep0out->ep);
597 usb_ep_fifo_flush(&udc->ep0in->ep);
aa69a809 598
1f339d84
AS
599 if (udc->driver)
600 udc->driver->disconnect(gadget);
aa69a809
DL
601
602 /* make sure to disable all endpoints */
603 gadget_for_each_ep(ep, gadget) {
604 usb_ep_disable(ep);
605 }
aa69a809 606
ca9cfea0 607 if (udc->status != NULL) {
d36ade60 608 usb_ep_free_request(&udc->ep0in->ep, udc->status);
ca9cfea0 609 udc->status = NULL;
aa69a809
DL
610 }
611
aa69a809
DL
612 return 0;
613}
614
615/******************************************************************************
616 * ISR block
617 *****************************************************************************/
618/**
619 * isr_reset_handler: USB reset interrupt handler
620 * @udc: UDC device
621 *
622 * This function resets USB engine after a bus reset occurred
623 */
624static void isr_reset_handler(struct ci13xxx *udc)
625__releases(udc->lock)
626__acquires(udc->lock)
627{
aa69a809
DL
628 int retval;
629
aa69a809
DL
630 dbg_event(0xFF, "BUS RST", 0);
631
d3595d13 632 spin_unlock(&udc->lock);
aa69a809
DL
633 retval = _gadget_stop_activity(&udc->gadget);
634 if (retval)
635 goto done;
636
d3595d13 637 retval = hw_usb_reset(udc);
aa69a809
DL
638 if (retval)
639 goto done;
640
d36ade60 641 udc->status = usb_ep_alloc_request(&udc->ep0in->ep, GFP_ATOMIC);
ac1aa6a2
A
642 if (udc->status == NULL)
643 retval = -ENOMEM;
ca9cfea0 644
b9322252 645done:
d3595d13 646 spin_lock(&udc->lock);
aa69a809 647
aa69a809 648 if (retval)
0f089094 649 dev_err(udc->dev, "error: %i\n", retval);
aa69a809
DL
650}
651
652/**
653 * isr_get_status_complete: get_status request complete function
654 * @ep: endpoint
655 * @req: request handled
656 *
657 * Caller must release lock
658 */
659static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
660{
0f089094 661 if (ep == NULL || req == NULL)
aa69a809 662 return;
aa69a809
DL
663
664 kfree(req->buf);
665 usb_ep_free_request(ep, req);
666}
667
668/**
669 * isr_get_status_response: get_status request response
ca9cfea0 670 * @udc: udc struct
aa69a809
DL
671 * @setup: setup request packet
672 *
673 * This function returns an error code
674 */
ca9cfea0 675static int isr_get_status_response(struct ci13xxx *udc,
aa69a809
DL
676 struct usb_ctrlrequest *setup)
677__releases(mEp->lock)
678__acquires(mEp->lock)
679{
d36ade60 680 struct ci13xxx_ep *mEp = udc->ep0in;
aa69a809
DL
681 struct usb_request *req = NULL;
682 gfp_t gfp_flags = GFP_ATOMIC;
683 int dir, num, retval;
684
aa69a809
DL
685 if (mEp == NULL || setup == NULL)
686 return -EINVAL;
687
688 spin_unlock(mEp->lock);
689 req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
690 spin_lock(mEp->lock);
691 if (req == NULL)
692 return -ENOMEM;
693
694 req->complete = isr_get_status_complete;
695 req->length = 2;
696 req->buf = kzalloc(req->length, gfp_flags);
697 if (req->buf == NULL) {
698 retval = -ENOMEM;
699 goto err_free_req;
700 }
701
702 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
e2b61c1d 703 /* Assume that device is bus powered for now. */
1f339d84 704 *(u16 *)req->buf = udc->remote_wakeup << 1;
aa69a809
DL
705 retval = 0;
706 } else if ((setup->bRequestType & USB_RECIP_MASK) \
707 == USB_RECIP_ENDPOINT) {
708 dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
709 TX : RX;
710 num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
d3595d13 711 *(u16 *)req->buf = hw_ep_get_halt(udc, num, dir);
aa69a809
DL
712 }
713 /* else do nothing; reserved for future use */
714
715 spin_unlock(mEp->lock);
716 retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
717 spin_lock(mEp->lock);
718 if (retval)
719 goto err_free_buf;
720
721 return 0;
722
723 err_free_buf:
724 kfree(req->buf);
725 err_free_req:
726 spin_unlock(mEp->lock);
727 usb_ep_free_request(&mEp->ep, req);
728 spin_lock(mEp->lock);
729 return retval;
730}
731
541cace8
PK
732/**
733 * isr_setup_status_complete: setup_status request complete function
734 * @ep: endpoint
735 * @req: request handled
736 *
737 * Caller must release lock. Put the port in test mode if test mode
738 * feature is selected.
739 */
740static void
741isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
742{
743 struct ci13xxx *udc = req->context;
744 unsigned long flags;
745
ef15e549
AS
746 if (udc->setaddr) {
747 hw_usb_set_address(udc, udc->address);
748 udc->setaddr = false;
749 }
750
d3595d13 751 spin_lock_irqsave(&udc->lock, flags);
541cace8 752 if (udc->test_mode)
d3595d13
AS
753 hw_port_test_set(udc, udc->test_mode);
754 spin_unlock_irqrestore(&udc->lock, flags);
541cace8
PK
755}
756
aa69a809
DL
757/**
758 * isr_setup_status_phase: queues the status phase of a setup transation
ca9cfea0 759 * @udc: udc struct
aa69a809
DL
760 *
761 * This function returns an error code
762 */
ca9cfea0 763static int isr_setup_status_phase(struct ci13xxx *udc)
aa69a809
DL
764__releases(mEp->lock)
765__acquires(mEp->lock)
766{
767 int retval;
ca9cfea0 768 struct ci13xxx_ep *mEp;
aa69a809 769
d36ade60 770 mEp = (udc->ep0_dir == TX) ? udc->ep0out : udc->ep0in;
541cace8
PK
771 udc->status->context = udc;
772 udc->status->complete = isr_setup_status_complete;
aa69a809
DL
773
774 spin_unlock(mEp->lock);
ca9cfea0 775 retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
aa69a809
DL
776 spin_lock(mEp->lock);
777
778 return retval;
779}
780
781/**
782 * isr_tr_complete_low: transaction complete low level handler
783 * @mEp: endpoint
784 *
785 * This function returns an error code
786 * Caller must hold lock
787 */
788static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
789__releases(mEp->lock)
790__acquires(mEp->lock)
791{
0e6ca199 792 struct ci13xxx_req *mReq, *mReqTemp;
76cd9cfb 793 struct ci13xxx_ep *mEpTemp = mEp;
986b11b8 794 int uninitialized_var(retval);
aa69a809 795
ca9cfea0 796 if (list_empty(&mEp->qh.queue))
aa69a809
DL
797 return -EINVAL;
798
0e6ca199
PK
799 list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
800 queue) {
801 retval = _hardware_dequeue(mEp, mReq);
802 if (retval < 0)
803 break;
804 list_del_init(&mReq->queue);
805 dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
806 if (mReq->req.complete != NULL) {
807 spin_unlock(mEp->lock);
76cd9cfb
PK
808 if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
809 mReq->req.length)
1f339d84 810 mEpTemp = mEp->udc->ep0in;
76cd9cfb 811 mReq->req.complete(&mEpTemp->ep, &mReq->req);
0e6ca199
PK
812 spin_lock(mEp->lock);
813 }
d9bb9c18
AL
814 }
815
ef907482 816 if (retval == -EBUSY)
0e6ca199
PK
817 retval = 0;
818 if (retval < 0)
819 dbg_event(_usb_addr(mEp), "DONE", retval);
aa69a809 820
aa69a809
DL
821 return retval;
822}
823
824/**
825 * isr_tr_complete_handler: transaction complete interrupt handler
826 * @udc: UDC descriptor
827 *
828 * This function handles traffic events
829 */
830static void isr_tr_complete_handler(struct ci13xxx *udc)
831__releases(udc->lock)
832__acquires(udc->lock)
833{
834 unsigned i;
541cace8 835 u8 tmode = 0;
aa69a809 836
d3595d13 837 for (i = 0; i < udc->hw_ep_max; i++) {
aa69a809 838 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
4c5212b7 839 int type, num, dir, err = -EINVAL;
aa69a809
DL
840 struct usb_ctrlrequest req;
841
31fb6014 842 if (mEp->ep.desc == NULL)
aa69a809
DL
843 continue; /* not configured */
844
d3595d13 845 if (hw_test_and_clear_complete(udc, i)) {
aa69a809
DL
846 err = isr_tr_complete_low(mEp);
847 if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
848 if (err > 0) /* needs status phase */
ca9cfea0 849 err = isr_setup_status_phase(udc);
aa69a809
DL
850 if (err < 0) {
851 dbg_event(_usb_addr(mEp),
852 "ERROR", err);
d3595d13 853 spin_unlock(&udc->lock);
aa69a809 854 if (usb_ep_set_halt(&mEp->ep))
0f089094 855 dev_err(udc->dev,
0917ba84 856 "error: ep_set_halt\n");
d3595d13 857 spin_lock(&udc->lock);
aa69a809
DL
858 }
859 }
860 }
861
862 if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
d3595d13 863 !hw_test_and_clear_setup_status(udc, i))
aa69a809
DL
864 continue;
865
866 if (i != 0) {
0f089094 867 dev_warn(udc->dev, "ctrl traffic at endpoint %d\n", i);
aa69a809
DL
868 continue;
869 }
870
ca9cfea0
PK
871 /*
872 * Flush data and handshake transactions of previous
873 * setup packet.
874 */
d36ade60
AS
875 _ep_nuke(udc->ep0out);
876 _ep_nuke(udc->ep0in);
ca9cfea0 877
aa69a809
DL
878 /* read_setup_packet */
879 do {
d3595d13 880 hw_test_and_set_setup_guard(udc);
ca9cfea0 881 memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
d3595d13 882 } while (!hw_test_and_clear_setup_guard(udc));
aa69a809
DL
883
884 type = req.bRequestType;
885
ca9cfea0 886 udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
aa69a809
DL
887
888 dbg_setup(_usb_addr(mEp), &req);
889
890 switch (req.bRequest) {
891 case USB_REQ_CLEAR_FEATURE:
e2b61c1d
PK
892 if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
893 le16_to_cpu(req.wValue) ==
894 USB_ENDPOINT_HALT) {
895 if (req.wLength != 0)
896 break;
897 num = le16_to_cpu(req.wIndex);
4c5212b7 898 dir = num & USB_ENDPOINT_DIR_MASK;
e2b61c1d 899 num &= USB_ENDPOINT_NUMBER_MASK;
4c5212b7 900 if (dir) /* TX */
d3595d13 901 num += udc->hw_ep_max/2;
e2b61c1d 902 if (!udc->ci13xxx_ep[num].wedge) {
d3595d13 903 spin_unlock(&udc->lock);
e2b61c1d
PK
904 err = usb_ep_clear_halt(
905 &udc->ci13xxx_ep[num].ep);
d3595d13 906 spin_lock(&udc->lock);
e2b61c1d
PK
907 if (err)
908 break;
909 }
910 err = isr_setup_status_phase(udc);
911 } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
912 le16_to_cpu(req.wValue) ==
913 USB_DEVICE_REMOTE_WAKEUP) {
914 if (req.wLength != 0)
aa69a809 915 break;
e2b61c1d
PK
916 udc->remote_wakeup = 0;
917 err = isr_setup_status_phase(udc);
918 } else {
919 goto delegate;
aa69a809 920 }
aa69a809
DL
921 break;
922 case USB_REQ_GET_STATUS:
923 if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
924 type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
925 type != (USB_DIR_IN|USB_RECIP_INTERFACE))
926 goto delegate;
927 if (le16_to_cpu(req.wLength) != 2 ||
928 le16_to_cpu(req.wValue) != 0)
929 break;
ca9cfea0 930 err = isr_get_status_response(udc, &req);
aa69a809
DL
931 break;
932 case USB_REQ_SET_ADDRESS:
933 if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
934 goto delegate;
935 if (le16_to_cpu(req.wLength) != 0 ||
936 le16_to_cpu(req.wIndex) != 0)
937 break;
ef15e549
AS
938 udc->address = (u8)le16_to_cpu(req.wValue);
939 udc->setaddr = true;
ca9cfea0 940 err = isr_setup_status_phase(udc);
aa69a809
DL
941 break;
942 case USB_REQ_SET_FEATURE:
e2b61c1d
PK
943 if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
944 le16_to_cpu(req.wValue) ==
945 USB_ENDPOINT_HALT) {
946 if (req.wLength != 0)
947 break;
948 num = le16_to_cpu(req.wIndex);
4c5212b7 949 dir = num & USB_ENDPOINT_DIR_MASK;
e2b61c1d 950 num &= USB_ENDPOINT_NUMBER_MASK;
4c5212b7 951 if (dir) /* TX */
d3595d13 952 num += udc->hw_ep_max/2;
aa69a809 953
d3595d13 954 spin_unlock(&udc->lock);
e2b61c1d 955 err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
d3595d13 956 spin_lock(&udc->lock);
e2b61c1d 957 if (!err)
541cace8
PK
958 isr_setup_status_phase(udc);
959 } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
e2b61c1d
PK
960 if (req.wLength != 0)
961 break;
541cace8
PK
962 switch (le16_to_cpu(req.wValue)) {
963 case USB_DEVICE_REMOTE_WAKEUP:
964 udc->remote_wakeup = 1;
965 err = isr_setup_status_phase(udc);
966 break;
967 case USB_DEVICE_TEST_MODE:
968 tmode = le16_to_cpu(req.wIndex) >> 8;
969 switch (tmode) {
970 case TEST_J:
971 case TEST_K:
972 case TEST_SE0_NAK:
973 case TEST_PACKET:
974 case TEST_FORCE_EN:
975 udc->test_mode = tmode;
976 err = isr_setup_status_phase(
977 udc);
978 break;
979 default:
980 break;
981 }
982 default:
983 goto delegate;
984 }
e2b61c1d
PK
985 } else {
986 goto delegate;
987 }
aa69a809
DL
988 break;
989 default:
990delegate:
991 if (req.wLength == 0) /* no data phase */
ca9cfea0 992 udc->ep0_dir = TX;
aa69a809 993
d3595d13 994 spin_unlock(&udc->lock);
aa69a809 995 err = udc->driver->setup(&udc->gadget, &req);
d3595d13 996 spin_lock(&udc->lock);
aa69a809
DL
997 break;
998 }
999
1000 if (err < 0) {
1001 dbg_event(_usb_addr(mEp), "ERROR", err);
1002
d3595d13 1003 spin_unlock(&udc->lock);
aa69a809 1004 if (usb_ep_set_halt(&mEp->ep))
0f089094 1005 dev_err(udc->dev, "error: ep_set_halt\n");
d3595d13 1006 spin_lock(&udc->lock);
aa69a809
DL
1007 }
1008 }
1009}
1010
1011/******************************************************************************
1012 * ENDPT block
1013 *****************************************************************************/
1014/**
1015 * ep_enable: configure endpoint, making it usable
1016 *
1017 * Check usb_ep_enable() at "usb_gadget.h" for details
1018 */
1019static int ep_enable(struct usb_ep *ep,
1020 const struct usb_endpoint_descriptor *desc)
1021{
1022 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
ca9cfea0 1023 int retval = 0;
aa69a809
DL
1024 unsigned long flags;
1025
aa69a809
DL
1026 if (ep == NULL || desc == NULL)
1027 return -EINVAL;
1028
1029 spin_lock_irqsave(mEp->lock, flags);
1030
1031 /* only internal SW should enable ctrl endpts */
1032
31fb6014 1033 mEp->ep.desc = desc;
aa69a809 1034
ca9cfea0 1035 if (!list_empty(&mEp->qh.queue))
0f089094 1036 dev_warn(mEp->udc->dev, "enabling a non-empty endpoint!\n");
aa69a809 1037
15739bb5
MK
1038 mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
1039 mEp->num = usb_endpoint_num(desc);
1040 mEp->type = usb_endpoint_type(desc);
aa69a809 1041
29cc8897 1042 mEp->ep.maxpacket = usb_endpoint_maxp(desc);
aa69a809 1043
ca9cfea0 1044 dbg_event(_usb_addr(mEp), "ENABLE", 0);
aa69a809 1045
ca9cfea0 1046 mEp->qh.ptr->cap = 0;
aa69a809 1047
ca9cfea0
PK
1048 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
1049 mEp->qh.ptr->cap |= QH_IOS;
1050 else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
1051 mEp->qh.ptr->cap &= ~QH_MULT;
1052 else
1053 mEp->qh.ptr->cap &= ~QH_ZLT;
aa69a809 1054
ca9cfea0
PK
1055 mEp->qh.ptr->cap |=
1056 (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
1057 mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
aa69a809 1058
ac1aa6a2
A
1059 /*
1060 * Enable endpoints in the HW other than ep0 as ep0
1061 * is always enabled
1062 */
1063 if (mEp->num)
d3595d13 1064 retval |= hw_ep_enable(mEp->udc, mEp->num, mEp->dir, mEp->type);
aa69a809
DL
1065
1066 spin_unlock_irqrestore(mEp->lock, flags);
1067 return retval;
1068}
1069
1070/**
1071 * ep_disable: endpoint is no longer usable
1072 *
1073 * Check usb_ep_disable() at "usb_gadget.h" for details
1074 */
1075static int ep_disable(struct usb_ep *ep)
1076{
1077 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1078 int direction, retval = 0;
1079 unsigned long flags;
1080
aa69a809
DL
1081 if (ep == NULL)
1082 return -EINVAL;
31fb6014 1083 else if (mEp->ep.desc == NULL)
aa69a809
DL
1084 return -EBUSY;
1085
1086 spin_lock_irqsave(mEp->lock, flags);
1087
1088 /* only internal SW should disable ctrl endpts */
1089
1090 direction = mEp->dir;
1091 do {
1092 dbg_event(_usb_addr(mEp), "DISABLE", 0);
1093
1094 retval |= _ep_nuke(mEp);
d3595d13 1095 retval |= hw_ep_disable(mEp->udc, mEp->num, mEp->dir);
aa69a809
DL
1096
1097 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
1098 mEp->dir = (mEp->dir == TX) ? RX : TX;
1099
1100 } while (mEp->dir != direction);
1101
f9c56cdd 1102 mEp->ep.desc = NULL;
aa69a809
DL
1103
1104 spin_unlock_irqrestore(mEp->lock, flags);
1105 return retval;
1106}
1107
1108/**
1109 * ep_alloc_request: allocate a request object to use with this endpoint
1110 *
1111 * Check usb_ep_alloc_request() at "usb_gadget.h" for details
1112 */
1113static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1114{
1115 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1116 struct ci13xxx_req *mReq = NULL;
aa69a809 1117
0f089094 1118 if (ep == NULL)
aa69a809 1119 return NULL;
aa69a809 1120
aa69a809
DL
1121 mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
1122 if (mReq != NULL) {
1123 INIT_LIST_HEAD(&mReq->queue);
954aad8c 1124 mReq->req.dma = DMA_ADDR_INVALID;
aa69a809
DL
1125
1126 mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
1127 &mReq->dma);
1128 if (mReq->ptr == NULL) {
1129 kfree(mReq);
1130 mReq = NULL;
1131 }
1132 }
1133
1134 dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
1135
aa69a809
DL
1136 return (mReq == NULL) ? NULL : &mReq->req;
1137}
1138
1139/**
1140 * ep_free_request: frees a request object
1141 *
1142 * Check usb_ep_free_request() at "usb_gadget.h" for details
1143 */
1144static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
1145{
1146 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1147 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
1148 unsigned long flags;
1149
aa69a809 1150 if (ep == NULL || req == NULL) {
aa69a809
DL
1151 return;
1152 } else if (!list_empty(&mReq->queue)) {
0f089094 1153 dev_err(mEp->udc->dev, "freeing queued request\n");
aa69a809
DL
1154 return;
1155 }
1156
1157 spin_lock_irqsave(mEp->lock, flags);
1158
1159 if (mReq->ptr)
1160 dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
1161 kfree(mReq);
1162
1163 dbg_event(_usb_addr(mEp), "FREE", 0);
1164
1165 spin_unlock_irqrestore(mEp->lock, flags);
1166}
1167
1168/**
1169 * ep_queue: queues (submits) an I/O request to an endpoint
1170 *
1171 * Check usb_ep_queue()* at usb_gadget.h" for details
1172 */
1173static int ep_queue(struct usb_ep *ep, struct usb_request *req,
1174 gfp_t __maybe_unused gfp_flags)
1175{
1176 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1177 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
1f339d84 1178 struct ci13xxx *udc = mEp->udc;
aa69a809
DL
1179 int retval = 0;
1180 unsigned long flags;
1181
31fb6014 1182 if (ep == NULL || req == NULL || mEp->ep.desc == NULL)
aa69a809
DL
1183 return -EINVAL;
1184
1185 spin_lock_irqsave(mEp->lock, flags);
1186
76cd9cfb
PK
1187 if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
1188 if (req->length)
1f339d84
AS
1189 mEp = (udc->ep0_dir == RX) ?
1190 udc->ep0out : udc->ep0in;
76cd9cfb
PK
1191 if (!list_empty(&mEp->qh.queue)) {
1192 _ep_nuke(mEp);
1193 retval = -EOVERFLOW;
0f089094
AS
1194 dev_warn(mEp->udc->dev, "endpoint ctrl %X nuked\n",
1195 _usb_addr(mEp));
76cd9cfb 1196 }
aa69a809
DL
1197 }
1198
1199 /* first nuke then test link, e.g. previous status has not sent */
1200 if (!list_empty(&mReq->queue)) {
1201 retval = -EBUSY;
0f089094 1202 dev_err(mEp->udc->dev, "request already in queue\n");
aa69a809
DL
1203 goto done;
1204 }
1205
1155a7b8
AS
1206 if (req->length > 4 * CI13XXX_PAGE_SIZE) {
1207 req->length = 4 * CI13XXX_PAGE_SIZE;
aa69a809 1208 retval = -EMSGSIZE;
0f089094 1209 dev_warn(mEp->udc->dev, "request length truncated\n");
aa69a809
DL
1210 }
1211
1212 dbg_queue(_usb_addr(mEp), req, retval);
1213
1214 /* push request */
1215 mReq->req.status = -EINPROGRESS;
1216 mReq->req.actual = 0;
aa69a809 1217
0e6ca199 1218 retval = _hardware_enqueue(mEp, mReq);
d9bb9c18
AL
1219
1220 if (retval == -EALREADY) {
aa69a809
DL
1221 dbg_event(_usb_addr(mEp), "QUEUE", retval);
1222 retval = 0;
1223 }
0e6ca199
PK
1224 if (!retval)
1225 list_add_tail(&mReq->queue, &mEp->qh.queue);
aa69a809
DL
1226
1227 done:
1228 spin_unlock_irqrestore(mEp->lock, flags);
1229 return retval;
1230}
1231
1232/**
1233 * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
1234 *
1235 * Check usb_ep_dequeue() at "usb_gadget.h" for details
1236 */
1237static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
1238{
1239 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1240 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
1241 unsigned long flags;
1242
0e6ca199 1243 if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
31fb6014 1244 mEp->ep.desc == NULL || list_empty(&mReq->queue) ||
0e6ca199 1245 list_empty(&mEp->qh.queue))
aa69a809
DL
1246 return -EINVAL;
1247
1248 spin_lock_irqsave(mEp->lock, flags);
1249
1250 dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
1251
d3595d13 1252 hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
aa69a809
DL
1253
1254 /* pop request */
1255 list_del_init(&mReq->queue);
0e6ca199
PK
1256 if (mReq->map) {
1257 dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
1258 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
954aad8c 1259 mReq->req.dma = DMA_ADDR_INVALID;
0e6ca199
PK
1260 mReq->map = 0;
1261 }
aa69a809
DL
1262 req->status = -ECONNRESET;
1263
7c25a826 1264 if (mReq->req.complete != NULL) {
aa69a809
DL
1265 spin_unlock(mEp->lock);
1266 mReq->req.complete(&mEp->ep, &mReq->req);
1267 spin_lock(mEp->lock);
1268 }
1269
1270 spin_unlock_irqrestore(mEp->lock, flags);
1271 return 0;
1272}
1273
1274/**
1275 * ep_set_halt: sets the endpoint halt feature
1276 *
1277 * Check usb_ep_set_halt() at "usb_gadget.h" for details
1278 */
1279static int ep_set_halt(struct usb_ep *ep, int value)
1280{
1281 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1282 int direction, retval = 0;
1283 unsigned long flags;
1284
31fb6014 1285 if (ep == NULL || mEp->ep.desc == NULL)
aa69a809
DL
1286 return -EINVAL;
1287
1288 spin_lock_irqsave(mEp->lock, flags);
1289
1290#ifndef STALL_IN
1291 /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
1292 if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
ca9cfea0 1293 !list_empty(&mEp->qh.queue)) {
aa69a809
DL
1294 spin_unlock_irqrestore(mEp->lock, flags);
1295 return -EAGAIN;
1296 }
1297#endif
1298
1299 direction = mEp->dir;
1300 do {
1301 dbg_event(_usb_addr(mEp), "HALT", value);
d3595d13 1302 retval |= hw_ep_set_halt(mEp->udc, mEp->num, mEp->dir, value);
aa69a809
DL
1303
1304 if (!value)
1305 mEp->wedge = 0;
1306
1307 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
1308 mEp->dir = (mEp->dir == TX) ? RX : TX;
1309
1310 } while (mEp->dir != direction);
1311
1312 spin_unlock_irqrestore(mEp->lock, flags);
1313 return retval;
1314}
1315
1316/**
1317 * ep_set_wedge: sets the halt feature and ignores clear requests
1318 *
1319 * Check usb_ep_set_wedge() at "usb_gadget.h" for details
1320 */
1321static int ep_set_wedge(struct usb_ep *ep)
1322{
1323 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1324 unsigned long flags;
1325
31fb6014 1326 if (ep == NULL || mEp->ep.desc == NULL)
aa69a809
DL
1327 return -EINVAL;
1328
1329 spin_lock_irqsave(mEp->lock, flags);
1330
1331 dbg_event(_usb_addr(mEp), "WEDGE", 0);
1332 mEp->wedge = 1;
1333
1334 spin_unlock_irqrestore(mEp->lock, flags);
1335
1336 return usb_ep_set_halt(ep);
1337}
1338
1339/**
1340 * ep_fifo_flush: flushes contents of a fifo
1341 *
1342 * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
1343 */
1344static void ep_fifo_flush(struct usb_ep *ep)
1345{
1346 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
1347 unsigned long flags;
1348
aa69a809 1349 if (ep == NULL) {
0f089094 1350 dev_err(mEp->udc->dev, "%02X: -EINVAL\n", _usb_addr(mEp));
aa69a809
DL
1351 return;
1352 }
1353
1354 spin_lock_irqsave(mEp->lock, flags);
1355
1356 dbg_event(_usb_addr(mEp), "FFLUSH", 0);
d3595d13 1357 hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
aa69a809
DL
1358
1359 spin_unlock_irqrestore(mEp->lock, flags);
1360}
1361
1362/**
1363 * Endpoint-specific part of the API to the USB controller hardware
1364 * Check "usb_gadget.h" for details
1365 */
1366static const struct usb_ep_ops usb_ep_ops = {
1367 .enable = ep_enable,
1368 .disable = ep_disable,
1369 .alloc_request = ep_alloc_request,
1370 .free_request = ep_free_request,
1371 .queue = ep_queue,
1372 .dequeue = ep_dequeue,
1373 .set_halt = ep_set_halt,
1374 .set_wedge = ep_set_wedge,
1375 .fifo_flush = ep_fifo_flush,
1376};
1377
1378/******************************************************************************
1379 * GADGET block
1380 *****************************************************************************/
f01ef574
PK
1381static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
1382{
1383 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
1384 unsigned long flags;
1385 int gadget_ready = 0;
1386
1387 if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
1388 return -EOPNOTSUPP;
1389
d3595d13 1390 spin_lock_irqsave(&udc->lock, flags);
f01ef574
PK
1391 udc->vbus_active = is_active;
1392 if (udc->driver)
1393 gadget_ready = 1;
d3595d13 1394 spin_unlock_irqrestore(&udc->lock, flags);
f01ef574
PK
1395
1396 if (gadget_ready) {
1397 if (is_active) {
c036019e 1398 pm_runtime_get_sync(&_gadget->dev);
eb70e5ab 1399 hw_device_reset(udc, USBMODE_CM_DC);
d3595d13 1400 hw_device_state(udc, udc->ep0out->qh.dma);
f01ef574 1401 } else {
d3595d13 1402 hw_device_state(udc, 0);
f01ef574
PK
1403 if (udc->udc_driver->notify_event)
1404 udc->udc_driver->notify_event(udc,
1405 CI13XXX_CONTROLLER_STOPPED_EVENT);
1406 _gadget_stop_activity(&udc->gadget);
c036019e 1407 pm_runtime_put_sync(&_gadget->dev);
f01ef574
PK
1408 }
1409 }
1410
1411 return 0;
1412}
1413
e2b61c1d
PK
1414static int ci13xxx_wakeup(struct usb_gadget *_gadget)
1415{
1416 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
1417 unsigned long flags;
1418 int ret = 0;
1419
d3595d13 1420 spin_lock_irqsave(&udc->lock, flags);
e2b61c1d
PK
1421 if (!udc->remote_wakeup) {
1422 ret = -EOPNOTSUPP;
e2b61c1d
PK
1423 goto out;
1424 }
262c1632 1425 if (!hw_read(udc, OP_PORTSC, PORTSC_SUSP)) {
e2b61c1d 1426 ret = -EINVAL;
e2b61c1d
PK
1427 goto out;
1428 }
262c1632 1429 hw_write(udc, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
e2b61c1d 1430out:
d3595d13 1431 spin_unlock_irqrestore(&udc->lock, flags);
e2b61c1d
PK
1432 return ret;
1433}
1434
d860852e
PK
1435static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1436{
1437 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
1438
1439 if (udc->transceiver)
b96d3b08 1440 return usb_phy_set_power(udc->transceiver, mA);
d860852e
PK
1441 return -ENOTSUPP;
1442}
1443
1f339d84
AS
1444static int ci13xxx_start(struct usb_gadget *gadget,
1445 struct usb_gadget_driver *driver);
1446static int ci13xxx_stop(struct usb_gadget *gadget,
1447 struct usb_gadget_driver *driver);
aa69a809
DL
1448/**
1449 * Device operations part of the API to the USB controller hardware,
1450 * which don't involve endpoints (or i/o)
1451 * Check "usb_gadget.h" for details
1452 */
f01ef574
PK
1453static const struct usb_gadget_ops usb_gadget_ops = {
1454 .vbus_session = ci13xxx_vbus_session,
e2b61c1d 1455 .wakeup = ci13xxx_wakeup,
d860852e 1456 .vbus_draw = ci13xxx_vbus_draw,
1f339d84
AS
1457 .udc_start = ci13xxx_start,
1458 .udc_stop = ci13xxx_stop,
f01ef574 1459};
aa69a809 1460
790c2d52 1461static int init_eps(struct ci13xxx *udc)
aa69a809 1462{
790c2d52 1463 int retval = 0, i, j;
aa69a809 1464
790c2d52 1465 for (i = 0; i < udc->hw_ep_max/2; i++)
ca9cfea0 1466 for (j = RX; j <= TX; j++) {
d3595d13 1467 int k = i + j * udc->hw_ep_max/2;
ca9cfea0 1468 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
aa69a809 1469
ca9cfea0
PK
1470 scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
1471 (j == TX) ? "in" : "out");
aa69a809 1472
d3595d13
AS
1473 mEp->udc = udc;
1474 mEp->lock = &udc->lock;
ca9cfea0
PK
1475 mEp->device = &udc->gadget.dev;
1476 mEp->td_pool = udc->td_pool;
aa69a809 1477
ca9cfea0
PK
1478 mEp->ep.name = mEp->name;
1479 mEp->ep.ops = &usb_ep_ops;
1480 mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
aa69a809 1481
ca9cfea0 1482 INIT_LIST_HEAD(&mEp->qh.queue);
ca9cfea0 1483 mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
790c2d52 1484 &mEp->qh.dma);
ca9cfea0 1485 if (mEp->qh.ptr == NULL)
aa69a809
DL
1486 retval = -ENOMEM;
1487 else
ca9cfea0
PK
1488 memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
1489
d36ade60
AS
1490 /*
1491 * set up shorthands for ep0 out and in endpoints,
1492 * don't add to gadget's ep_list
1493 */
1494 if (i == 0) {
1495 if (j == RX)
1496 udc->ep0out = mEp;
1497 else
1498 udc->ep0in = mEp;
1499
ca9cfea0 1500 continue;
d36ade60 1501 }
ca9cfea0 1502
aa69a809 1503 list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
ca9cfea0 1504 }
790c2d52
AS
1505
1506 return retval;
1507}
1508
1509/**
1510 * ci13xxx_start: register a gadget driver
1f339d84 1511 * @gadget: our gadget
790c2d52 1512 * @driver: the driver being registered
790c2d52 1513 *
790c2d52
AS
1514 * Interrupts are enabled here.
1515 */
1f339d84
AS
1516static int ci13xxx_start(struct usb_gadget *gadget,
1517 struct usb_gadget_driver *driver)
790c2d52 1518{
1f339d84 1519 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
790c2d52 1520 unsigned long flags;
790c2d52
AS
1521 int retval = -ENOMEM;
1522
1f339d84 1523 if (driver->disconnect == NULL)
790c2d52 1524 return -EINVAL;
790c2d52 1525
790c2d52 1526
d36ade60
AS
1527 udc->ep0out->ep.desc = &ctrl_endpt_out_desc;
1528 retval = usb_ep_enable(&udc->ep0out->ep);
ac1aa6a2
A
1529 if (retval)
1530 return retval;
877c1f54 1531
d36ade60
AS
1532 udc->ep0in->ep.desc = &ctrl_endpt_in_desc;
1533 retval = usb_ep_enable(&udc->ep0in->ep);
ac1aa6a2
A
1534 if (retval)
1535 return retval;
d3595d13 1536 spin_lock_irqsave(&udc->lock, flags);
aa69a809 1537
49d3df53 1538 udc->driver = driver;
c036019e 1539 pm_runtime_get_sync(&udc->gadget.dev);
f01ef574
PK
1540 if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
1541 if (udc->vbus_active) {
1542 if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
eb70e5ab 1543 hw_device_reset(udc, USBMODE_CM_DC);
f01ef574 1544 } else {
c036019e 1545 pm_runtime_put_sync(&udc->gadget.dev);
f01ef574
PK
1546 goto done;
1547 }
1548 }
1549
d3595d13 1550 retval = hw_device_state(udc, udc->ep0out->qh.dma);
c036019e
PK
1551 if (retval)
1552 pm_runtime_put_sync(&udc->gadget.dev);
aa69a809
DL
1553
1554 done:
d3595d13 1555 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809
DL
1556 return retval;
1557}
aa69a809
DL
1558
1559/**
0f91349b 1560 * ci13xxx_stop: unregister a gadget driver
aa69a809 1561 */
1f339d84
AS
1562static int ci13xxx_stop(struct usb_gadget *gadget,
1563 struct usb_gadget_driver *driver)
aa69a809 1564{
1f339d84
AS
1565 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
1566 unsigned long flags;
aa69a809 1567
d3595d13 1568 spin_lock_irqsave(&udc->lock, flags);
aa69a809 1569
f01ef574
PK
1570 if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
1571 udc->vbus_active) {
d3595d13 1572 hw_device_state(udc, 0);
f01ef574
PK
1573 if (udc->udc_driver->notify_event)
1574 udc->udc_driver->notify_event(udc,
1575 CI13XXX_CONTROLLER_STOPPED_EVENT);
1f339d84 1576 udc->driver = NULL;
d3595d13 1577 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809 1578 _gadget_stop_activity(&udc->gadget);
d3595d13 1579 spin_lock_irqsave(&udc->lock, flags);
c036019e 1580 pm_runtime_put(&udc->gadget.dev);
f01ef574 1581 }
aa69a809 1582
d3595d13 1583 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809 1584
aa69a809
DL
1585 return 0;
1586}
aa69a809
DL
1587
1588/******************************************************************************
1589 * BUS block
1590 *****************************************************************************/
1591/**
5f36e231 1592 * udc_irq: udc interrupt handler
aa69a809
DL
1593 *
1594 * This function returns IRQ_HANDLED if the IRQ has been handled
1595 * It locks access to registers
1596 */
5f36e231 1597static irqreturn_t udc_irq(struct ci13xxx *udc)
aa69a809 1598{
aa69a809
DL
1599 irqreturn_t retval;
1600 u32 intr;
1601
f639554b 1602 if (udc == NULL)
aa69a809 1603 return IRQ_HANDLED;
aa69a809 1604
d3595d13 1605 spin_lock(&udc->lock);
f01ef574
PK
1606
1607 if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
262c1632 1608 if (hw_read(udc, OP_USBMODE, USBMODE_CM) !=
758fc986 1609 USBMODE_CM_DC) {
d3595d13 1610 spin_unlock(&udc->lock);
f01ef574
PK
1611 return IRQ_NONE;
1612 }
1613 }
d3595d13 1614 intr = hw_test_and_clear_intr_active(udc);
e443b333 1615 dbg_interrupt(intr);
aa69a809 1616
e443b333 1617 if (intr) {
aa69a809 1618 /* order defines priority - do NOT change it */
e443b333 1619 if (USBi_URI & intr)
aa69a809 1620 isr_reset_handler(udc);
e443b333 1621
aa69a809 1622 if (USBi_PCI & intr) {
d3595d13 1623 udc->gadget.speed = hw_port_is_high_speed(udc) ?
aa69a809 1624 USB_SPEED_HIGH : USB_SPEED_FULL;
7bb4fdc6 1625 if (udc->suspended && udc->driver->resume) {
d3595d13 1626 spin_unlock(&udc->lock);
e2b61c1d 1627 udc->driver->resume(&udc->gadget);
d3595d13 1628 spin_lock(&udc->lock);
e2b61c1d
PK
1629 udc->suspended = 0;
1630 }
aa69a809 1631 }
e443b333
AS
1632
1633 if (USBi_UI & intr)
aa69a809 1634 isr_tr_complete_handler(udc);
e443b333 1635
e2b61c1d 1636 if (USBi_SLI & intr) {
7bb4fdc6
MKB
1637 if (udc->gadget.speed != USB_SPEED_UNKNOWN &&
1638 udc->driver->suspend) {
e2b61c1d 1639 udc->suspended = 1;
d3595d13 1640 spin_unlock(&udc->lock);
e2b61c1d 1641 udc->driver->suspend(&udc->gadget);
d3595d13 1642 spin_lock(&udc->lock);
e2b61c1d 1643 }
e2b61c1d 1644 }
aa69a809
DL
1645 retval = IRQ_HANDLED;
1646 } else {
aa69a809
DL
1647 retval = IRQ_NONE;
1648 }
d3595d13 1649 spin_unlock(&udc->lock);
aa69a809
DL
1650
1651 return retval;
1652}
1653
1654/**
1655 * udc_release: driver release function
1656 * @dev: device
1657 *
1658 * Currently does nothing
1659 */
1660static void udc_release(struct device *dev)
1661{
aa69a809
DL
1662}
1663
1664/**
5f36e231
AS
1665 * udc_start: initialize gadget role
1666 * @udc: chipidea controller
aa69a809 1667 */
5f36e231 1668static int udc_start(struct ci13xxx *udc)
aa69a809 1669{
5f36e231 1670 struct device *dev = udc->dev;
aa69a809
DL
1671 int retval = 0;
1672
5f36e231 1673 if (!udc)
aa69a809
DL
1674 return -EINVAL;
1675
d3595d13 1676 spin_lock_init(&udc->lock);
aa69a809 1677
f01ef574 1678 udc->gadget.ops = &usb_gadget_ops;
aa69a809 1679 udc->gadget.speed = USB_SPEED_UNKNOWN;
d327ab5b 1680 udc->gadget.max_speed = USB_SPEED_HIGH;
aa69a809 1681 udc->gadget.is_otg = 0;
5f36e231 1682 udc->gadget.name = udc->udc_driver->name;
aa69a809
DL
1683
1684 INIT_LIST_HEAD(&udc->gadget.ep_list);
aa69a809 1685
5df58524 1686 dev_set_name(&udc->gadget.dev, "gadget");
aa69a809 1687 udc->gadget.dev.dma_mask = dev->dma_mask;
61948ee4 1688 udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
aa69a809
DL
1689 udc->gadget.dev.parent = dev;
1690 udc->gadget.dev.release = udc_release;
1691
790c2d52
AS
1692 /* alloc resources */
1693 udc->qh_pool = dma_pool_create("ci13xxx_qh", dev,
1694 sizeof(struct ci13xxx_qh),
1695 64, CI13XXX_PAGE_SIZE);
5f36e231
AS
1696 if (udc->qh_pool == NULL)
1697 return -ENOMEM;
790c2d52
AS
1698
1699 udc->td_pool = dma_pool_create("ci13xxx_td", dev,
1700 sizeof(struct ci13xxx_td),
1701 64, CI13XXX_PAGE_SIZE);
1702 if (udc->td_pool == NULL) {
1703 retval = -ENOMEM;
1704 goto free_qh_pool;
1705 }
1706
790c2d52
AS
1707 retval = init_eps(udc);
1708 if (retval)
1709 goto free_pools;
1710
1711 udc->gadget.ep0 = &udc->ep0in->ep;
f01ef574 1712
b96d3b08 1713 udc->transceiver = usb_get_transceiver();
f01ef574
PK
1714
1715 if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
1716 if (udc->transceiver == NULL) {
1717 retval = -ENODEV;
790c2d52 1718 goto free_pools;
f01ef574
PK
1719 }
1720 }
1721
1722 if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
eb70e5ab 1723 retval = hw_device_reset(udc, USBMODE_CM_DC);
f01ef574
PK
1724 if (retval)
1725 goto put_transceiver;
1726 }
1727
aa69a809 1728 retval = device_register(&udc->gadget.dev);
f01ef574
PK
1729 if (retval) {
1730 put_device(&udc->gadget.dev);
1731 goto put_transceiver;
1732 }
aa69a809 1733
aa69a809 1734 retval = dbg_create_files(&udc->gadget.dev);
f01ef574
PK
1735 if (retval)
1736 goto unreg_device;
1737
1738 if (udc->transceiver) {
6e13c650
HK
1739 retval = otg_set_peripheral(udc->transceiver->otg,
1740 &udc->gadget);
f01ef574
PK
1741 if (retval)
1742 goto remove_dbg;
aa69a809 1743 }
0f91349b
SAS
1744
1745 retval = usb_add_gadget_udc(dev, &udc->gadget);
1746 if (retval)
1747 goto remove_trans;
1748
c036019e
PK
1749 pm_runtime_no_callbacks(&udc->gadget.dev);
1750 pm_runtime_enable(&udc->gadget.dev);
aa69a809 1751
aa69a809
DL
1752 return retval;
1753
0f91349b
SAS
1754remove_trans:
1755 if (udc->transceiver) {
6e13c650 1756 otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
b96d3b08 1757 usb_put_transceiver(udc->transceiver);
0f91349b
SAS
1758 }
1759
0917ba84 1760 dev_err(dev, "error = %i\n", retval);
f01ef574 1761remove_dbg:
f01ef574 1762 dbg_remove_files(&udc->gadget.dev);
f01ef574
PK
1763unreg_device:
1764 device_unregister(&udc->gadget.dev);
1765put_transceiver:
1766 if (udc->transceiver)
b96d3b08 1767 usb_put_transceiver(udc->transceiver);
790c2d52
AS
1768free_pools:
1769 dma_pool_destroy(udc->td_pool);
1770free_qh_pool:
1771 dma_pool_destroy(udc->qh_pool);
aa69a809
DL
1772 return retval;
1773}
1774
1775/**
1776 * udc_remove: parent remove must call this to remove UDC
1777 *
1778 * No interrupts active, the IRQ has been released
1779 */
5f36e231 1780static void udc_stop(struct ci13xxx *udc)
aa69a809 1781{
790c2d52 1782 int i;
aa69a809 1783
0f089094 1784 if (udc == NULL)
aa69a809 1785 return;
0f089094 1786
0f91349b 1787 usb_del_gadget_udc(&udc->gadget);
aa69a809 1788
790c2d52
AS
1789 for (i = 0; i < udc->hw_ep_max; i++) {
1790 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
1791
1792 dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
1793 }
1794
1795 dma_pool_destroy(udc->td_pool);
1796 dma_pool_destroy(udc->qh_pool);
1797
f01ef574 1798 if (udc->transceiver) {
5f36e231 1799 otg_set_peripheral(udc->transceiver->otg, NULL);
b96d3b08 1800 usb_put_transceiver(udc->transceiver);
f01ef574 1801 }
aa69a809 1802 dbg_remove_files(&udc->gadget.dev);
aa69a809 1803 device_unregister(&udc->gadget.dev);
5f36e231
AS
1804 /* my kobject is dynamic, I swear! */
1805 memset(&udc->gadget, 0, sizeof(udc->gadget));
1806}
1807
1808/**
1809 * ci_hdrc_gadget_init - initialize device related bits
1810 * ci: the controller
1811 *
1812 * This function enables the gadget role, if the device is "device capable".
1813 */
1814int ci_hdrc_gadget_init(struct ci13xxx *ci)
1815{
1816 struct ci_role_driver *rdrv;
1817
1818 if (!hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DC))
1819 return -ENXIO;
1820
1821 rdrv = devm_kzalloc(ci->dev, sizeof(struct ci_role_driver), GFP_KERNEL);
1822 if (!rdrv)
1823 return -ENOMEM;
1824
1825 rdrv->start = udc_start;
1826 rdrv->stop = udc_stop;
1827 rdrv->irq = udc_irq;
1828 rdrv->name = "gadget";
1829 ci->roles[CI_ROLE_GADGET] = rdrv;
aa69a809 1830
5f36e231 1831 return 0;
aa69a809 1832}