[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / usb / chipidea / core.c

/*
 * core.c - ChipIdea USB IP core family device controller
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * Description: ChipIdea USB IP core family device controller
 *
 * This driver is composed of several blocks:
 * - HW:     hardware interface
 * - DBG:    debug facilities (optional)
 * - UTIL:   utilities
 * - ISR:    interrupts handling
 * - ENDPT:  endpoint operations (Gadget API)
 * - GADGET: gadget operations (Gadget API)
 * - BUS:    bus glue code, bus abstraction layer
 *
 * Compile Options
 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
 * - STALL_IN:  non-empty bulk-in pipes cannot be halted
 *              if defined mass storage compliance succeeds but with warnings
 *              => case 4: Hi >  Dn
 *              => case 5: Hi >  Di
 *              => case 8: Hi <> Do
 *              if undefined usbtest 13 fails
 * - TRACE:     enable function tracing (depends on DEBUG)
 *
 * Main Features
 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
 * - Normal & LPM support
 *
 * USBTEST Report
 * - OK: 0-12, 13 (STALL_IN defined) & 14
 * - Not Supported: 15 & 16 (ISO)
 *
 * TODO List
 * - OTG
 * - Interrupt Traffic
 * - GET_STATUS(device) - always reports 0
 * - Gadget API (majority of optional features)
 * - Suspend & Remote Wakeup
 */
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/idr.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg.h>
#include <linux/usb/chipidea.h>
#include <linux/usb/of.h>
#include <linux/phy.h>
#include <linux/regulator/consumer.h>

#include "ci.h"
#include "udc.h"
#include "bits.h"
#include "host.h"
#include "debug.h"
#include "otg.h"

/* Controller register map */
static uintptr_t ci_regs_nolpm[] = {
	[CAP_CAPLENGTH]		= 0x000UL,
	[CAP_HCCPARAMS]		= 0x008UL,
	[CAP_DCCPARAMS]		= 0x024UL,
	[CAP_TESTMODE]		= 0x038UL,
	[OP_USBCMD]		= 0x000UL,
	[OP_USBSTS]		= 0x004UL,
	[OP_USBINTR]		= 0x008UL,
	[OP_DEVICEADDR]		= 0x014UL,
	[OP_ENDPTLISTADDR]	= 0x018UL,
	[OP_PORTSC]		= 0x044UL,
	[OP_DEVLC]		= 0x084UL,
	[OP_OTGSC]		= 0x064UL,
	[OP_USBMODE]		= 0x068UL,
	[OP_ENDPTSETUPSTAT]	= 0x06CUL,
	[OP_ENDPTPRIME]		= 0x070UL,
	[OP_ENDPTFLUSH]		= 0x074UL,
	[OP_ENDPTSTAT]		= 0x078UL,
	[OP_ENDPTCOMPLETE]	= 0x07CUL,
	[OP_ENDPTCTRL]		= 0x080UL,
};

static uintptr_t ci_regs_lpm[] = {
	[CAP_CAPLENGTH]		= 0x000UL,
	[CAP_HCCPARAMS]		= 0x008UL,
	[CAP_DCCPARAMS]		= 0x024UL,
	[CAP_TESTMODE]		= 0x0FCUL,
	[OP_USBCMD]		= 0x000UL,
	[OP_USBSTS]		= 0x004UL,
	[OP_USBINTR]		= 0x008UL,
	[OP_DEVICEADDR]		= 0x014UL,
	[OP_ENDPTLISTADDR]	= 0x018UL,
	[OP_PORTSC]		= 0x044UL,
	[OP_DEVLC]		= 0x084UL,
	[OP_OTGSC]		= 0x0C4UL,
	[OP_USBMODE]		= 0x0C8UL,
	[OP_ENDPTSETUPSTAT]	= 0x0D8UL,
	[OP_ENDPTPRIME]		= 0x0DCUL,
	[OP_ENDPTFLUSH]		= 0x0E0UL,
	[OP_ENDPTSTAT]		= 0x0E4UL,
	[OP_ENDPTCOMPLETE]	= 0x0E8UL,
	[OP_ENDPTCTRL]		= 0x0ECUL,
};

static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
{
	int i;

	kfree(ci->hw_bank.regmap);

	ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
				     GFP_KERNEL);
	if (!ci->hw_bank.regmap)
		return -ENOMEM;

	for (i = 0; i < OP_ENDPTCTRL; i++)
		ci->hw_bank.regmap[i] =
			(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
			(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);

	for (; i <= OP_LAST; i++)
		ci->hw_bank.regmap[i] = ci->hw_bank.op +
			4 * (i - OP_ENDPTCTRL) +
			(is_lpm
			 ? ci_regs_lpm[OP_ENDPTCTRL]
			 : ci_regs_nolpm[OP_ENDPTCTRL]);

	return 0;
}

/**
 * hw_port_test_set: writes port test mode (execute without interruption)
 * @mode: new value
 *
 * This function returns an error code
 */
int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
{
	const u8 TEST_MODE_MAX = 7;

	if (mode > TEST_MODE_MAX)
		return -EINVAL;

	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
	return 0;
}

/**
 * hw_port_test_get: reads port test mode value
 *
 * This function returns port test mode value
 */
u8 hw_port_test_get(struct ci_hdrc *ci)
{
	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
}

static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
{
	u32 reg;

	/* bank is a module variable */
	ci->hw_bank.abs = base;

	ci->hw_bank.cap = ci->hw_bank.abs;
	ci->hw_bank.cap += ci->platdata->capoffset;
	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);

	hw_alloc_regmap(ci, false);
	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
		__ffs(HCCPARAMS_LEN);
	ci->hw_bank.lpm  = reg;
	hw_alloc_regmap(ci, !!reg);
	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	ci->hw_bank.size += OP_LAST;
	ci->hw_bank.size /= sizeof(u32);

	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
		__ffs(DCCPARAMS_DEN);
	ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */

	if (ci->hw_ep_max > ENDPT_MAX)
		return -ENODEV;

	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
		ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);

	/* setup lock mode ? */

	/* ENDPTSETUPSTAT is '0' by default */

	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */

	return 0;
}

static void hw_phymode_configure(struct ci_hdrc *ci)
{
	u32 portsc, lpm, sts;

	switch (ci->platdata->phy_mode) {
	case USBPHY_INTERFACE_MODE_UTMI:
		portsc = PORTSC_PTS(PTS_UTMI);
		lpm = DEVLC_PTS(PTS_UTMI);
		break;
	case USBPHY_INTERFACE_MODE_UTMIW:
		portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
		lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
		break;
	case USBPHY_INTERFACE_MODE_ULPI:
		portsc = PORTSC_PTS(PTS_ULPI);
		lpm = DEVLC_PTS(PTS_ULPI);
		break;
	case USBPHY_INTERFACE_MODE_SERIAL:
		portsc = PORTSC_PTS(PTS_SERIAL);
		lpm = DEVLC_PTS(PTS_SERIAL);
		sts = 1;
		break;
	case USBPHY_INTERFACE_MODE_HSIC:
		portsc = PORTSC_PTS(PTS_HSIC);
		lpm = DEVLC_PTS(PTS_HSIC);
		break;
	default:
		return;
	}

	if (ci->hw_bank.lpm) {
		hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
		hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
	} else {
		hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
		hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
	}
}

/**
 * hw_device_reset: resets chip (execute without interruption)
 * @ci: the controller
  *
 * This function returns an error code
 */
int hw_device_reset(struct ci_hdrc *ci, u32 mode)
{
	/* should flush & stop before reset */
	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);

	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
		udelay(10);		/* not RTOS friendly */

	if (ci->platdata->notify_event)
		ci->platdata->notify_event(ci,
			CI_HDRC_CONTROLLER_RESET_EVENT);

	if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
		hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);

	/* USBMODE should be configured step by step */
	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
	/* HW >= 2.3 */
	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);

	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
		pr_err("cannot enter in %s mode", ci_role(ci)->name);
		pr_err("lpm = %i", ci->hw_bank.lpm);
		return -ENODEV;
	}

	return 0;
}

/**
 * ci_otg_role - pick role based on ID pin state
 * @ci: the controller
 */
static enum ci_role ci_otg_role(struct ci_hdrc *ci)
{
	u32 sts = hw_read(ci, OP_OTGSC, ~0);
	enum ci_role role = sts & OTGSC_ID
		? CI_ROLE_GADGET
		: CI_ROLE_HOST;

	return role;
}

/**
 * ci_role_work - perform role changing based on ID pin
 * @work: work struct
 */
static void ci_role_work(struct work_struct *work)
{
	struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
	enum ci_role role = ci_otg_role(ci);

	if (role != ci->role) {
		dev_dbg(ci->dev, "switching from %s to %s\n",
			ci_role(ci)->name, ci->roles[role]->name);

		ci_role_stop(ci);
		ci_role_start(ci, role);
	}

	enable_irq(ci->irq);
}

static irqreturn_t ci_irq(int irq, void *data)
{
	struct ci_hdrc *ci = data;
	irqreturn_t ret = IRQ_NONE;
	u32 otgsc = 0;

	if (ci->is_otg)
		otgsc = hw_read(ci, OP_OTGSC, ~0);

	if (ci->role != CI_ROLE_END)
		ret = ci_role(ci)->irq(ci);

	if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
		hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
		disable_irq_nosync(ci->irq);
		queue_work(ci->wq, &ci->work);
		ret = IRQ_HANDLED;
	}

	return ret;
}

static int ci_get_platdata(struct device *dev,
		struct ci_hdrc_platform_data *platdata)
{
	/* Get the vbus regulator */
	platdata->reg_vbus = devm_regulator_get(dev, "vbus");
	if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
		return -EPROBE_DEFER;
	} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
		platdata->reg_vbus = NULL; /* no vbus regualator is needed */
	} else if (IS_ERR(platdata->reg_vbus)) {
		dev_err(dev, "Getting regulator error: %ld\n",
			PTR_ERR(platdata->reg_vbus));
		return PTR_ERR(platdata->reg_vbus);
	}

	return 0;
}

static DEFINE_IDA(ci_ida);

struct platform_device *ci_hdrc_add_device(struct device *dev,
			struct resource *res, int nres,
			struct ci_hdrc_platform_data *platdata)
{
	struct platform_device *pdev;
	int id, ret;

	ret = ci_get_platdata(dev, platdata);
	if (ret)
		return ERR_PTR(ret);

	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
	if (id < 0)
		return ERR_PTR(id);

	pdev = platform_device_alloc("ci_hdrc", id);
	if (!pdev) {
		ret = -ENOMEM;
		goto put_id;
	}

	pdev->dev.parent = dev;
	pdev->dev.dma_mask = dev->dma_mask;
	pdev->dev.dma_parms = dev->dma_parms;
	dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);

	ret = platform_device_add_resources(pdev, res, nres);
	if (ret)
		goto err;

	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
	if (ret)
		goto err;

	ret = platform_device_add(pdev);
	if (ret)
		goto err;

	return pdev;

err:
	platform_device_put(pdev);
put_id:
	ida_simple_remove(&ci_ida, id);
	return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(ci_hdrc_add_device);

void ci_hdrc_remove_device(struct platform_device *pdev)
{
	int id = pdev->id;
	platform_device_unregister(pdev);
	ida_simple_remove(&ci_ida, id);
}
EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);

static inline void ci_role_destroy(struct ci_hdrc *ci)
{
	ci_hdrc_gadget_destroy(ci);
	ci_hdrc_host_destroy(ci);
}

static int ci_hdrc_probe(struct platform_device *pdev)
{
	struct device	*dev = &pdev->dev;
	struct ci_hdrc	*ci;
	struct resource	*res;
	void __iomem	*base;
	int		ret;
	enum usb_dr_mode dr_mode;
	struct device_node *of_node = dev->of_node ?: dev->parent->of_node;

	if (!dev->platform_data) {
		dev_err(dev, "platform data missing\n");
		return -ENODEV;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	if (!ci) {
		dev_err(dev, "can't allocate device\n");
		return -ENOMEM;
	}

	ci->dev = dev;
	ci->platdata = dev->platform_data;
	if (ci->platdata->phy)
		ci->transceiver = ci->platdata->phy;
	else
		ci->global_phy = true;

	ret = hw_device_init(ci, base);
	if (ret < 0) {
		dev_err(dev, "can't initialize hardware\n");
		return -ENODEV;
	}

	ci->hw_bank.phys = res->start;

	ci->irq = platform_get_irq(pdev, 0);
	if (ci->irq < 0) {
		dev_err(dev, "missing IRQ\n");
		return -ENODEV;
	}

	INIT_WORK(&ci->work, ci_role_work);
	ci->wq = create_singlethread_workqueue("ci_otg");
	if (!ci->wq) {
		dev_err(dev, "can't create workqueue\n");
		return -ENODEV;
	}

	if (!ci->platdata->phy_mode)
		ci->platdata->phy_mode = of_usb_get_phy_mode(of_node);

	hw_phymode_configure(ci);

	if (!ci->platdata->dr_mode)
		ci->platdata->dr_mode = of_usb_get_dr_mode(of_node);

	if (ci->platdata->dr_mode == USB_DR_MODE_UNKNOWN)
		ci->platdata->dr_mode = USB_DR_MODE_OTG;

	dr_mode = ci->platdata->dr_mode;
	/* initialize role(s) before the interrupt is requested */
	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
		ret = ci_hdrc_host_init(ci);
		if (ret)
			dev_info(dev, "doesn't support host\n");
	}

	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
		ret = ci_hdrc_gadget_init(ci);
		if (ret)
			dev_info(dev, "doesn't support gadget\n");
	}

	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
		dev_err(dev, "no supported roles\n");
		ret = -ENODEV;
		goto rm_wq;
	}

	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
		ci->is_otg = true;
		/* ID pin needs 1ms debouce time, we delay 2ms for safe */
		mdelay(2);
		ci->role = ci_otg_role(ci);
	} else {
		ci->role = ci->roles[CI_ROLE_HOST]
			? CI_ROLE_HOST
			: CI_ROLE_GADGET;
	}

	ret = ci_role_start(ci, ci->role);
	if (ret) {
		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
		goto rm_wq;
	}

	platform_set_drvdata(pdev, ci);
	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
			  ci);
	if (ret)
		goto stop;

	if (ci->is_otg)
		ci_hdrc_otg_init(ci);

	ret = dbg_create_files(ci);
	if (!ret)
		return 0;

	free_irq(ci->irq, ci);
stop:
	ci_role_destroy(ci);
rm_wq:
	flush_workqueue(ci->wq);
	destroy_workqueue(ci->wq);

	return ret;
}

static int ci_hdrc_remove(struct platform_device *pdev)
{
	struct ci_hdrc *ci = platform_get_drvdata(pdev);

	dbg_remove_files(ci);
	flush_workqueue(ci->wq);
	destroy_workqueue(ci->wq);
	free_irq(ci->irq, ci);
	ci_role_destroy(ci);

	return 0;
}

static struct platform_driver ci_hdrc_driver = {
	.probe	= ci_hdrc_probe,
	.remove	= ci_hdrc_remove,
	.driver	= {
		.name	= "ci_hdrc",
	},
};

module_platform_driver(ci_hdrc_driver);

MODULE_ALIAS("platform:ci_hdrc");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
MODULE_DESCRIPTION("ChipIdea HDRC Driver");
Commit	Line	Data
e443b333 AS	1	/*
	2	* core.c - ChipIdea USB IP core family device controller
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	/*
	14	* Description: ChipIdea USB IP core family device controller
	15	*
	16	* This driver is composed of several blocks:
	17	* - HW: hardware interface
	18	* - DBG: debug facilities (optional)
	19	* - UTIL: utilities
	20	* - ISR: interrupts handling
	21	* - ENDPT: endpoint operations (Gadget API)
	22	* - GADGET: gadget operations (Gadget API)
	23	* - BUS: bus glue code, bus abstraction layer
	24	*
	25	* Compile Options
	26	* - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
	27	* - STALL_IN: non-empty bulk-in pipes cannot be halted
	28	* if defined mass storage compliance succeeds but with warnings
	29	* => case 4: Hi > Dn
	30	* => case 5: Hi > Di
	31	* => case 8: Hi <> Do
	32	* if undefined usbtest 13 fails
	33	* - TRACE: enable function tracing (depends on DEBUG)
	34	*
	35	* Main Features
	36	* - Chapter 9 & Mass Storage Compliance with Gadget File Storage
	37	* - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
	38	* - Normal & LPM support
	39	*
	40	* USBTEST Report
	41	* - OK: 0-12, 13 (STALL_IN defined) & 14
	42	* - Not Supported: 15 & 16 (ISO)
	43	*
	44	* TODO List
	45	* - OTG
e4ce4ecd	46	* - Interrupt Traffic
e443b333 AS	47	* - GET_STATUS(device) - always reports 0
	48	* - Gadget API (majority of optional features)
	49	* - Suspend & Remote Wakeup
	50	*/
	51	#include <linux/delay.h>
	52	#include <linux/device.h>
e443b333	53	#include <linux/dma-mapping.h>
e443b333 AS	54	#include <linux/platform_device.h>
e443b333 AS	55	#include <linux/module.h>
fe6e125e	56	#include <linux/idr.h>
e443b333 AS	57	#include <linux/interrupt.h>
e443b333 AS	58	#include <linux/io.h>
e443b333 AS	59	#include <linux/kernel.h>
	60	#include <linux/slab.h>
	61	#include <linux/pm_runtime.h>
	62	#include <linux/usb/ch9.h>
	63	#include <linux/usb/gadget.h>
	64	#include <linux/usb/otg.h>
	65	#include <linux/usb/chipidea.h>
40dcd0e8 MG	66	#include <linux/usb/of.h>
40dcd0e8 MG	67	#include <linux/phy.h>
1542d9c3	68	#include <linux/regulator/consumer.h>
e443b333 AS	69
	70	#include "ci.h"
	71	#include "udc.h"
	72	#include "bits.h"
eb70e5ab	73	#include "host.h"
e443b333	74	#include "debug.h"
c10b4f03	75	#include "otg.h"
e443b333	76
5f36e231	77	/* Controller register map */
e443b333 AS	78	static uintptr_t ci_regs_nolpm[] = {
	79	[CAP_CAPLENGTH] = 0x000UL,
	80	[CAP_HCCPARAMS] = 0x008UL,
	81	[CAP_DCCPARAMS] = 0x024UL,
	82	[CAP_TESTMODE] = 0x038UL,
	83	[OP_USBCMD] = 0x000UL,
	84	[OP_USBSTS] = 0x004UL,
	85	[OP_USBINTR] = 0x008UL,
	86	[OP_DEVICEADDR] = 0x014UL,
	87	[OP_ENDPTLISTADDR] = 0x018UL,
	88	[OP_PORTSC] = 0x044UL,
	89	[OP_DEVLC] = 0x084UL,
5f36e231	90	[OP_OTGSC] = 0x064UL,
e443b333 AS	91	[OP_USBMODE] = 0x068UL,
	92	[OP_ENDPTSETUPSTAT] = 0x06CUL,
	93	[OP_ENDPTPRIME] = 0x070UL,
	94	[OP_ENDPTFLUSH] = 0x074UL,
	95	[OP_ENDPTSTAT] = 0x078UL,
	96	[OP_ENDPTCOMPLETE] = 0x07CUL,
	97	[OP_ENDPTCTRL] = 0x080UL,
	98	};
	99
	100	static uintptr_t ci_regs_lpm[] = {
	101	[CAP_CAPLENGTH] = 0x000UL,
	102	[CAP_HCCPARAMS] = 0x008UL,
	103	[CAP_DCCPARAMS] = 0x024UL,
	104	[CAP_TESTMODE] = 0x0FCUL,
	105	[OP_USBCMD] = 0x000UL,
	106	[OP_USBSTS] = 0x004UL,
	107	[OP_USBINTR] = 0x008UL,
	108	[OP_DEVICEADDR] = 0x014UL,
	109	[OP_ENDPTLISTADDR] = 0x018UL,
	110	[OP_PORTSC] = 0x044UL,
	111	[OP_DEVLC] = 0x084UL,
5f36e231	112	[OP_OTGSC] = 0x0C4UL,
e443b333 AS	113	[OP_USBMODE] = 0x0C8UL,
	114	[OP_ENDPTSETUPSTAT] = 0x0D8UL,
	115	[OP_ENDPTPRIME] = 0x0DCUL,
	116	[OP_ENDPTFLUSH] = 0x0E0UL,
	117	[OP_ENDPTSTAT] = 0x0E4UL,
	118	[OP_ENDPTCOMPLETE] = 0x0E8UL,
	119	[OP_ENDPTCTRL] = 0x0ECUL,
	120	};
	121
8e22978c	122	static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
e443b333 AS	123	{
	124	int i;
	125
5f36e231	126	kfree(ci->hw_bank.regmap);
e443b333	127
5f36e231 AS	128	ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
	129	GFP_KERNEL);
	130	if (!ci->hw_bank.regmap)
e443b333 AS	131	return -ENOMEM;
	132
	133	for (i = 0; i < OP_ENDPTCTRL; i++)
5f36e231 AS	134	ci->hw_bank.regmap[i] =
5f36e231 AS	135	(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
e443b333 AS	136	(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
	137
	138	for (; i <= OP_LAST; i++)
5f36e231	139	ci->hw_bank.regmap[i] = ci->hw_bank.op +
e443b333 AS	140	4 * (i - OP_ENDPTCTRL) +
	141	(is_lpm
	142	? ci_regs_lpm[OP_ENDPTCTRL]
	143	: ci_regs_nolpm[OP_ENDPTCTRL]);
	144
	145	return 0;
	146	}
	147
	148	/**
	149	* hw_port_test_set: writes port test mode (execute without interruption)
	150	* @mode: new value
	151	*
	152	* This function returns an error code
	153	*/
8e22978c	154	int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
e443b333 AS	155	{
	156	const u8 TEST_MODE_MAX = 7;
	157
	158	if (mode > TEST_MODE_MAX)
	159	return -EINVAL;
	160
727b4ddb	161	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
e443b333 AS	162	return 0;
	163	}
	164
	165	/**
	166	* hw_port_test_get: reads port test mode value
	167	*
	168	* This function returns port test mode value
	169	*/
8e22978c	170	u8 hw_port_test_get(struct ci_hdrc *ci)
e443b333	171	{
727b4ddb	172	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
e443b333 AS	173	}
e443b333 AS	174
8e22978c	175	static int hw_device_init(struct ci_hdrc ci, void __iomem base)
e443b333 AS	176	{
	177	u32 reg;
	178
	179	/* bank is a module variable */
5f36e231	180	ci->hw_bank.abs = base;
e443b333	181
5f36e231	182	ci->hw_bank.cap = ci->hw_bank.abs;
77c4400f	183	ci->hw_bank.cap += ci->platdata->capoffset;
938d323f	184	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
e443b333	185
5f36e231 AS	186	hw_alloc_regmap(ci, false);
5f36e231 AS	187	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
727b4ddb	188	__ffs(HCCPARAMS_LEN);
5f36e231 AS	189	ci->hw_bank.lpm = reg;
	190	hw_alloc_regmap(ci, !!reg);
	191	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	192	ci->hw_bank.size += OP_LAST;
	193	ci->hw_bank.size /= sizeof(u32);
e443b333	194
5f36e231	195	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
727b4ddb	196	__ffs(DCCPARAMS_DEN);
5f36e231	197	ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
e443b333	198
09c94e62	199	if (ci->hw_ep_max > ENDPT_MAX)
e443b333 AS	200	return -ENODEV;
e443b333 AS	201
5f36e231 AS	202	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
5f36e231 AS	203	ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
e443b333 AS	204
	205	/* setup lock mode ? */
	206
	207	/* ENDPTSETUPSTAT is '0' by default */
	208
	209	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
	210
	211	return 0;
	212	}
	213
8e22978c	214	static void hw_phymode_configure(struct ci_hdrc *ci)
40dcd0e8 MG	215	{
	216	u32 portsc, lpm, sts;
	217
	218	switch (ci->platdata->phy_mode) {
	219	case USBPHY_INTERFACE_MODE_UTMI:
	220	portsc = PORTSC_PTS(PTS_UTMI);
	221	lpm = DEVLC_PTS(PTS_UTMI);
	222	break;
	223	case USBPHY_INTERFACE_MODE_UTMIW:
	224	portsc = PORTSC_PTS(PTS_UTMI) \| PORTSC_PTW;
	225	lpm = DEVLC_PTS(PTS_UTMI) \| DEVLC_PTW;
	226	break;
	227	case USBPHY_INTERFACE_MODE_ULPI:
	228	portsc = PORTSC_PTS(PTS_ULPI);
	229	lpm = DEVLC_PTS(PTS_ULPI);
	230	break;
	231	case USBPHY_INTERFACE_MODE_SERIAL:
	232	portsc = PORTSC_PTS(PTS_SERIAL);
	233	lpm = DEVLC_PTS(PTS_SERIAL);
	234	sts = 1;
	235	break;
	236	case USBPHY_INTERFACE_MODE_HSIC:
	237	portsc = PORTSC_PTS(PTS_HSIC);
	238	lpm = DEVLC_PTS(PTS_HSIC);
	239	break;
	240	default:
	241	return;
	242	}
	243
	244	if (ci->hw_bank.lpm) {
	245	hw_write(ci, OP_DEVLC, DEVLC_PTS(7) \| DEVLC_PTW, lpm);
	246	hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
	247	} else {
	248	hw_write(ci, OP_PORTSC, PORTSC_PTS(7) \| PORTSC_PTW, portsc);
	249	hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
	250	}
	251	}
	252
e443b333 AS	253	/**
	254	* hw_device_reset: resets chip (execute without interruption)
	255	* @ci: the controller
	256	*
	257	* This function returns an error code
	258	*/
8e22978c	259	int hw_device_reset(struct ci_hdrc *ci, u32 mode)
e443b333 AS	260	{
	261	/* should flush & stop before reset */
	262	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	263	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
	264
	265	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	266	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
	267	udelay(10); /* not RTOS friendly */
	268
77c4400f RZ	269	if (ci->platdata->notify_event)
77c4400f RZ	270	ci->platdata->notify_event(ci,
8e22978c	271	CI_HDRC_CONTROLLER_RESET_EVENT);
e443b333	272
8e22978c	273	if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
758fc986	274	hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
e443b333 AS	275
	276	/* USBMODE should be configured step by step */
	277	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
eb70e5ab	278	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
e443b333 AS	279	/* HW >= 2.3 */
	280	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
	281
eb70e5ab AS	282	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
eb70e5ab AS	283	pr_err("cannot enter in %s mode", ci_role(ci)->name);
e443b333 AS	284	pr_err("lpm = %i", ci->hw_bank.lpm);
	285	return -ENODEV;
	286	}
	287
	288	return 0;
	289	}
	290
5f36e231 AS	291	/**
	292	* ci_otg_role - pick role based on ID pin state
	293	* @ci: the controller
	294	*/
8e22978c	295	static enum ci_role ci_otg_role(struct ci_hdrc *ci)
5f36e231 AS	296	{
	297	u32 sts = hw_read(ci, OP_OTGSC, ~0);
	298	enum ci_role role = sts & OTGSC_ID
	299	? CI_ROLE_GADGET
	300	: CI_ROLE_HOST;
	301
	302	return role;
	303	}
	304
	305	/**
	306	* ci_role_work - perform role changing based on ID pin
	307	* @work: work struct
	308	*/
	309	static void ci_role_work(struct work_struct *work)
	310	{
8e22978c	311	struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
5f36e231 AS	312	enum ci_role role = ci_otg_role(ci);
5f36e231 AS	313
5f36e231 AS	314	if (role != ci->role) {
	315	dev_dbg(ci->dev, "switching from %s to %s\n",
	316	ci_role(ci)->name, ci->roles[role]->name);
	317
	318	ci_role_stop(ci);
	319	ci_role_start(ci, role);
	320	}
0c3f3dc6 AS	321
0c3f3dc6 AS	322	enable_irq(ci->irq);
5f36e231 AS	323	}
5f36e231 AS	324
5f36e231 AS	325	static irqreturn_t ci_irq(int irq, void *data)
5f36e231 AS	326	{
8e22978c	327	struct ci_hdrc *ci = data;
5f36e231	328	irqreturn_t ret = IRQ_NONE;
b183c19f	329	u32 otgsc = 0;
5f36e231	330
b183c19f RZ	331	if (ci->is_otg)
b183c19f RZ	332	otgsc = hw_read(ci, OP_OTGSC, ~0);
5f36e231	333
b183c19f RZ	334	if (ci->role != CI_ROLE_END)
	335	ret = ci_role(ci)->irq(ci);
	336
	337	if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
	338	hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
	339	disable_irq_nosync(ci->irq);
	340	queue_work(ci->wq, &ci->work);
	341	ret = IRQ_HANDLED;
5f36e231 AS	342	}
5f36e231 AS	343
b183c19f	344	return ret;
5f36e231 AS	345	}
5f36e231 AS	346
1542d9c3 PC	347	static int ci_get_platdata(struct device *dev,
	348	struct ci_hdrc_platform_data *platdata)
	349	{
	350	/* Get the vbus regulator */
	351	platdata->reg_vbus = devm_regulator_get(dev, "vbus");
	352	if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
	353	return -EPROBE_DEFER;
	354	} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
	355	platdata->reg_vbus = NULL; /* no vbus regualator is needed */
	356	} else if (IS_ERR(platdata->reg_vbus)) {
	357	dev_err(dev, "Getting regulator error: %ld\n",
	358	PTR_ERR(platdata->reg_vbus));
	359	return PTR_ERR(platdata->reg_vbus);
	360	}
	361
	362	return 0;
	363	}
	364
fe6e125e RZ	365	static DEFINE_IDA(ci_ida);
fe6e125e RZ	366
8e22978c	367	struct platform_device ci_hdrc_add_device(struct device dev,
cbc6dc2a	368	struct resource *res, int nres,
8e22978c	369	struct ci_hdrc_platform_data *platdata)
cbc6dc2a RZ	370	{
cbc6dc2a RZ	371	struct platform_device *pdev;
fe6e125e	372	int id, ret;
cbc6dc2a	373
1542d9c3 PC	374	ret = ci_get_platdata(dev, platdata);
	375	if (ret)
	376	return ERR_PTR(ret);
	377
fe6e125e RZ	378	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
	379	if (id < 0)
	380	return ERR_PTR(id);
	381
	382	pdev = platform_device_alloc("ci_hdrc", id);
	383	if (!pdev) {
	384	ret = -ENOMEM;
	385	goto put_id;
	386	}
cbc6dc2a RZ	387
	388	pdev->dev.parent = dev;
	389	pdev->dev.dma_mask = dev->dma_mask;
	390	pdev->dev.dma_parms = dev->dma_parms;
	391	dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
	392
	393	ret = platform_device_add_resources(pdev, res, nres);
	394	if (ret)
	395	goto err;
	396
	397	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
	398	if (ret)
	399	goto err;
	400
	401	ret = platform_device_add(pdev);
	402	if (ret)
	403	goto err;
	404
	405	return pdev;
	406
	407	err:
	408	platform_device_put(pdev);
fe6e125e RZ	409	put_id:
fe6e125e RZ	410	ida_simple_remove(&ci_ida, id);
cbc6dc2a RZ	411	return ERR_PTR(ret);
cbc6dc2a RZ	412	}
8e22978c	413	EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
cbc6dc2a	414
8e22978c	415	void ci_hdrc_remove_device(struct platform_device *pdev)
cbc6dc2a	416	{
98c35534	417	int id = pdev->id;
cbc6dc2a	418	platform_device_unregister(pdev);
98c35534	419	ida_simple_remove(&ci_ida, id);
cbc6dc2a	420	}
8e22978c	421	EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
cbc6dc2a	422
3f124d23 PC	423	static inline void ci_role_destroy(struct ci_hdrc *ci)
	424	{
	425	ci_hdrc_gadget_destroy(ci);
	426	ci_hdrc_host_destroy(ci);
	427	}
	428
41ac7b3a	429	static int ci_hdrc_probe(struct platform_device *pdev)
e443b333 AS	430	{
e443b333 AS	431	struct device *dev = &pdev->dev;
8e22978c	432	struct ci_hdrc *ci;
e443b333 AS	433	struct resource *res;
	434	void __iomem *base;
	435	int ret;
691962d1	436	enum usb_dr_mode dr_mode;
e98b44e9	437	struct device_node *of_node = dev->of_node ?: dev->parent->of_node;
e443b333	438
5f36e231	439	if (!dev->platform_data) {
e443b333 AS	440	dev_err(dev, "platform data missing\n");
	441	return -ENODEV;
	442	}
	443
	444	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
19290816 FB	445	base = devm_ioremap_resource(dev, res);
	446	if (IS_ERR(base))
	447	return PTR_ERR(base);
e443b333	448
5f36e231 AS	449	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	450	if (!ci) {
	451	dev_err(dev, "can't allocate device\n");
	452	return -ENOMEM;
	453	}
	454
	455	ci->dev = dev;
77c4400f	456	ci->platdata = dev->platform_data;
a2c3d690 RZ	457	if (ci->platdata->phy)
	458	ci->transceiver = ci->platdata->phy;
	459	else
	460	ci->global_phy = true;
5f36e231 AS	461
	462	ret = hw_device_init(ci, base);
	463	if (ret < 0) {
	464	dev_err(dev, "can't initialize hardware\n");
	465	return -ENODEV;
	466	}
e443b333	467
eb70e5ab AS	468	ci->hw_bank.phys = res->start;
eb70e5ab AS	469
5f36e231 AS	470	ci->irq = platform_get_irq(pdev, 0);
5f36e231 AS	471	if (ci->irq < 0) {
e443b333	472	dev_err(dev, "missing IRQ\n");
5f36e231 AS	473	return -ENODEV;
	474	}
	475
	476	INIT_WORK(&ci->work, ci_role_work);
	477	ci->wq = create_singlethread_workqueue("ci_otg");
	478	if (!ci->wq) {
	479	dev_err(dev, "can't create workqueue\n");
	480	return -ENODEV;
	481	}
	482
40dcd0e8	483	if (!ci->platdata->phy_mode)
e98b44e9	484	ci->platdata->phy_mode = of_usb_get_phy_mode(of_node);
40dcd0e8	485
03779f05 FE	486	hw_phymode_configure(ci);
03779f05 FE	487
691962d1	488	if (!ci->platdata->dr_mode)
e98b44e9	489	ci->platdata->dr_mode = of_usb_get_dr_mode(of_node);
691962d1 SH	490
	491	if (ci->platdata->dr_mode == USB_DR_MODE_UNKNOWN)
	492	ci->platdata->dr_mode = USB_DR_MODE_OTG;
	493
	494	dr_mode = ci->platdata->dr_mode;
5f36e231	495	/* initialize role(s) before the interrupt is requested */
691962d1 SH	496	if (dr_mode == USB_DR_MODE_OTG \|\| dr_mode == USB_DR_MODE_HOST) {
	497	ret = ci_hdrc_host_init(ci);
	498	if (ret)
	499	dev_info(dev, "doesn't support host\n");
	500	}
eb70e5ab	501
691962d1 SH	502	if (dr_mode == USB_DR_MODE_OTG \|\| dr_mode == USB_DR_MODE_PERIPHERAL) {
	503	ret = ci_hdrc_gadget_init(ci);
	504	if (ret)
	505	dev_info(dev, "doesn't support gadget\n");
	506	}
5f36e231 AS	507
	508	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
	509	dev_err(dev, "no supported roles\n");
	510	ret = -ENODEV;
	511	goto rm_wq;
	512	}
	513
	514	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
	515	ci->is_otg = true;
86ad01a9 RZ	516	/* ID pin needs 1ms debouce time, we delay 2ms for safe */
86ad01a9 RZ	517	mdelay(2);
5f36e231 AS	518	ci->role = ci_otg_role(ci);
	519	} else {
	520	ci->role = ci->roles[CI_ROLE_HOST]
	521	? CI_ROLE_HOST
	522	: CI_ROLE_GADGET;
	523	}
	524
	525	ret = ci_role_start(ci, ci->role);
	526	if (ret) {
	527	dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
5f36e231	528	goto rm_wq;
e443b333 AS	529	}
e443b333 AS	530
5f36e231	531	platform_set_drvdata(pdev, ci);
77c4400f	532	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
5f36e231 AS	533	ci);
	534	if (ret)
	535	goto stop;
e443b333	536
5f36e231	537	if (ci->is_otg)
c10b4f03	538	ci_hdrc_otg_init(ci);
5f36e231	539
adf0f735 AS	540	ret = dbg_create_files(ci);
	541	if (!ret)
	542	return 0;
5f36e231	543
adf0f735	544	free_irq(ci->irq, ci);
5f36e231	545	stop:
3f124d23	546	ci_role_destroy(ci);
5f36e231 AS	547	rm_wq:
	548	flush_workqueue(ci->wq);
	549	destroy_workqueue(ci->wq);
e443b333 AS	550
	551	return ret;
	552	}
	553
fb4e98ab	554	static int ci_hdrc_remove(struct platform_device *pdev)
e443b333	555	{
8e22978c	556	struct ci_hdrc *ci = platform_get_drvdata(pdev);
e443b333	557
adf0f735	558	dbg_remove_files(ci);
5f36e231 AS	559	flush_workqueue(ci->wq);
5f36e231 AS	560	destroy_workqueue(ci->wq);
5f36e231	561	free_irq(ci->irq, ci);
3f124d23	562	ci_role_destroy(ci);
e443b333 AS	563
	564	return 0;
	565	}
	566
5f36e231 AS	567	static struct platform_driver ci_hdrc_driver = {
5f36e231 AS	568	.probe = ci_hdrc_probe,
7690417d	569	.remove = ci_hdrc_remove,
e443b333	570	.driver = {
5f36e231	571	.name = "ci_hdrc",
e443b333 AS	572	},
	573	};
	574
5f36e231	575	module_platform_driver(ci_hdrc_driver);
e443b333	576
5f36e231	577	MODULE_ALIAS("platform:ci_hdrc");
e443b333 AS	578	MODULE_LICENSE("GPL v2");
e443b333 AS	579	MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
5f36e231	580	MODULE_DESCRIPTION("ChipIdea HDRC Driver");