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usb: move ci13xxx and related code to drivers/usb/chipidea
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / chipidea / ci13xxx_udc.c
CommitLineData
aa69a809
DL		 1/*
2 * ci13xxx_udc.c - MIPS USB IP core family device controller
3 *
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
5 *
6 * Author: David Lopo
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 * Description: MIPS USB IP core family device controller
15 * Currently it only supports IP part number CI13412
16 *
17 * This driver is composed of several blocks:
18 * - HW: hardware interface
19 * - DBG: debug facilities (optional)
20 * - UTIL: utilities
21 * - ISR: interrupts handling
22 * - ENDPT: endpoint operations (Gadget API)
23 * - GADGET: gadget operations (Gadget API)
24 * - BUS: bus glue code, bus abstraction layer
aa69a809
DL		 25 *
26 * Compile Options
27 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
28 * - STALL_IN: non-empty bulk-in pipes cannot be halted
29 * if defined mass storage compliance succeeds but with warnings
30 * => case 4: Hi > Dn
31 * => case 5: Hi > Di
32 * => case 8: Hi <> Do
33 * if undefined usbtest 13 fails
34 * - TRACE: enable function tracing (depends on DEBUG)
35 *
36 * Main Features
37 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
38 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
39 * - Normal & LPM support
40 *
41 * USBTEST Report
42 * - OK: 0-12, 13 (STALL_IN defined) & 14
43 * - Not Supported: 15 & 16 (ISO)
44 *
45 * TODO List
46 * - OTG
47 * - Isochronous & Interrupt Traffic
48 * - Handle requests which spawns into several TDs
49 * - GET_STATUS(device) - always reports 0
50 * - Gadget API (majority of optional features)
51 * - Suspend & Remote Wakeup
52 */
36825a2d 53#include <linux/delay.h>
aa69a809
DL		 54#include <linux/device.h>
55#include <linux/dmapool.h>
56#include <linux/dma-mapping.h>
57#include <linux/init.h>
62bb84ed
AS		 58#include <linux/platform_device.h>
59#include <linux/module.h>
aa69a809 60#include <linux/interrupt.h>
aa69a809
DL		 61#include <linux/io.h>
62#include <linux/irq.h>
63#include <linux/kernel.h>
5a0e3ad6 64#include <linux/slab.h>
c036019e 65#include <linux/pm_runtime.h>
aa69a809
DL		 66#include <linux/usb/ch9.h>
67#include <linux/usb/gadget.h>
f01ef574 68#include <linux/usb/otg.h>
aa69a809
DL		 69
70#include "ci13xxx_udc.h"
71
aa69a809
DL		 72/******************************************************************************
73 * DEFINE
74 *****************************************************************************/
954aad8c
MG		 75
76#define DMA_ADDR_INVALID (~(dma_addr_t)0)
77
aa69a809
DL		 78/* control endpoint description */
79static const struct usb_endpoint_descriptor
ca9cfea0 80ctrl_endpt_out_desc = {
aa69a809
DL		 81 .bLength = USB_DT_ENDPOINT_SIZE,
82 .bDescriptorType = USB_DT_ENDPOINT,
83
ca9cfea0
PK		 84 .bEndpointAddress = USB_DIR_OUT,
85 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
86 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
87};
88
89static const struct usb_endpoint_descriptor
90ctrl_endpt_in_desc = {
91 .bLength = USB_DT_ENDPOINT_SIZE,
92 .bDescriptorType = USB_DT_ENDPOINT,
93
94 .bEndpointAddress = USB_DIR_IN,
aa69a809
DL		 95 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
96 .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
97};
98
aa69a809
DL		 99/* Interrupt statistics */
100#define ISR_MASK 0x1F
101static struct {
102 u32 test;
103 u32 ui;
104 u32 uei;
105 u32 pci;
106 u32 uri;
107 u32 sli;
108 u32 none;
109 struct {
110 u32 cnt;
111 u32 buf[ISR_MASK+1];
112 u32 idx;
113 } hndl;
114} isr_statistics;
115
116/**
117 * ffs_nr: find first (least significant) bit set
118 * @x: the word to search
119 *
120 * This function returns bit number (instead of position)
121 */
122static int ffs_nr(u32 x)
123{
124 int n = ffs(x);
125
126 return n ? n-1 : 32;
127}
128
129/******************************************************************************
130 * HW block
131 *****************************************************************************/
aa69a809 132
f01ef574
PK		 133/* MSM specific */
134#define ABS_AHBBURST (0x0090UL)
135#define ABS_AHBMODE (0x0098UL)
aa69a809 136/* UDC register map */
262c1632
AS		 137static uintptr_t ci_regs_nolpm[] = {
138 [CAP_CAPLENGTH] = 0x000UL,
139 [CAP_HCCPARAMS] = 0x008UL,
140 [CAP_DCCPARAMS] = 0x024UL,
141 [CAP_TESTMODE] = 0x038UL,
142 [OP_USBCMD] = 0x000UL,
143 [OP_USBSTS] = 0x004UL,
144 [OP_USBINTR] = 0x008UL,
145 [OP_DEVICEADDR] = 0x014UL,
146 [OP_ENDPTLISTADDR] = 0x018UL,
147 [OP_PORTSC] = 0x044UL,
148 [OP_DEVLC] = 0x084UL,
149 [OP_USBMODE] = 0x068UL,
150 [OP_ENDPTSETUPSTAT] = 0x06CUL,
151 [OP_ENDPTPRIME] = 0x070UL,
152 [OP_ENDPTFLUSH] = 0x074UL,
153 [OP_ENDPTSTAT] = 0x078UL,
154 [OP_ENDPTCOMPLETE] = 0x07CUL,
155 [OP_ENDPTCTRL] = 0x080UL,
156};
157
158static uintptr_t ci_regs_lpm[] = {
159 [CAP_CAPLENGTH] = 0x000UL,
160 [CAP_HCCPARAMS] = 0x008UL,
161 [CAP_DCCPARAMS] = 0x024UL,
162 [CAP_TESTMODE] = 0x0FCUL,
163 [OP_USBCMD] = 0x000UL,
164 [OP_USBSTS] = 0x004UL,
165 [OP_USBINTR] = 0x008UL,
166 [OP_DEVICEADDR] = 0x014UL,
167 [OP_ENDPTLISTADDR] = 0x018UL,
168 [OP_PORTSC] = 0x044UL,
169 [OP_DEVLC] = 0x084UL,
170 [OP_USBMODE] = 0x0C8UL,
171 [OP_ENDPTSETUPSTAT] = 0x0D8UL,
172 [OP_ENDPTPRIME] = 0x0DCUL,
173 [OP_ENDPTFLUSH] = 0x0E0UL,
174 [OP_ENDPTSTAT] = 0x0E4UL,
175 [OP_ENDPTCOMPLETE] = 0x0E8UL,
176 [OP_ENDPTCTRL] = 0x0ECUL,
177};
178
179static int hw_alloc_regmap(struct ci13xxx *udc, bool is_lpm)
180{
181 int i;
182
183 kfree(udc->hw_bank.regmap);
184
185 udc->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
186 GFP_KERNEL);
187 if (!udc->hw_bank.regmap)
188 return -ENOMEM;
189
190 for (i = 0; i < OP_ENDPTCTRL; i++)
191 udc->hw_bank.regmap[i] =
192 (i <= CAP_LAST ? udc->hw_bank.cap : udc->hw_bank.op) +
193 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
194
195 for (; i <= OP_LAST; i++)
196 udc->hw_bank.regmap[i] = udc->hw_bank.op +
197 4 * (i - OP_ENDPTCTRL) +
198 (is_lpm
199 ? ci_regs_lpm[OP_ENDPTCTRL]
200 : ci_regs_nolpm[OP_ENDPTCTRL]);
201
202 return 0;
203}
aa69a809
DL		 204
205/**
206 * hw_ep_bit: calculates the bit number
207 * @num: endpoint number
208 * @dir: endpoint direction
209 *
210 * This function returns bit number
211 */
212static inline int hw_ep_bit(int num, int dir)
213{
214 return num + (dir ? 16 : 0);
215}
216
d3595d13 217static int ep_to_bit(struct ci13xxx *udc, int n)
dd39c358 218{
d3595d13 219 int fill = 16 - udc->hw_ep_max / 2;
dd39c358 220
d3595d13 221 if (n >= udc->hw_ep_max / 2)
dd39c358
MKB		 222 n += fill;
223
224 return n;
225}
226
aa69a809 227/**
262c1632
AS		 228 * hw_read: reads from a hw register
229 * @reg: register index
aa69a809
DL		 230 * @mask: bitfield mask
231 *
262c1632 232 * This function returns register contents
aa69a809 233 */
262c1632 234static u32 hw_read(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask)
aa69a809 235{
262c1632 236 return ioread32(udc->hw_bank.regmap[reg]) & mask;
aa69a809
DL		 237}
238
239/**
262c1632
AS		 240 * hw_write: writes to a hw register
241 * @reg: register index
aa69a809 242 * @mask: bitfield mask
262c1632 243 * @data: new value
aa69a809 244 */
262c1632
AS		 245static void hw_write(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask,
246 u32 data)
aa69a809 247{
262c1632
AS		 248 if (~mask)
249 data = (ioread32(udc->hw_bank.regmap[reg]) & ~mask)
250 | (data & mask);
251
252 iowrite32(data, udc->hw_bank.regmap[reg]);
aa69a809
DL		 253}
254
255/**
262c1632
AS		 256 * hw_test_and_clear: tests & clears a hw register
257 * @reg: register index
aa69a809
DL		 258 * @mask: bitfield mask
259 *
262c1632 260 * This function returns register contents
aa69a809 261 */
262c1632
AS		 262static u32 hw_test_and_clear(struct ci13xxx *udc, enum ci13xxx_regs reg,
263 u32 mask)
aa69a809 264{
262c1632 265 u32 val = ioread32(udc->hw_bank.regmap[reg]) & mask;
aa69a809 266
262c1632
AS		 267 iowrite32(val, udc->hw_bank.regmap[reg]);
268 return val;
aa69a809
DL		 269}
270
271/**
262c1632
AS		 272 * hw_test_and_write: tests & writes a hw register
273 * @reg: register index
aa69a809 274 * @mask: bitfield mask
262c1632 275 * @data: new value
aa69a809 276 *
262c1632 277 * This function returns register contents
aa69a809 278 */
262c1632
AS		 279static u32 hw_test_and_write(struct ci13xxx *udc, enum ci13xxx_regs reg,
280 u32 mask, u32 data)
aa69a809 281{
262c1632 282 u32 val = hw_read(udc, reg, ~0);
aa69a809 283
262c1632
AS		 284 hw_write(udc, reg, mask, data);
285 return (val & mask) >> ffs_nr(mask);
aa69a809
DL		 286}
287
d3595d13
AS		 288static int hw_device_init(struct ci13xxx *udc, void __iomem *base,
289 uintptr_t cap_offset)
aa69a809
DL		 290{
291 u32 reg;
292
293 /* bank is a module variable */
d3595d13 294 udc->hw_bank.abs = base;
aa69a809 295
d3595d13
AS		 296 udc->hw_bank.cap = udc->hw_bank.abs;
297 udc->hw_bank.cap += cap_offset;
298 udc->hw_bank.op = udc->hw_bank.cap + ioread8(udc->hw_bank.cap);
aa69a809 299
262c1632
AS		 300 hw_alloc_regmap(udc, false);
301 reg = hw_read(udc, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
f9df8395 302 ffs_nr(HCCPARAMS_LEN);
d3595d13 303 udc->hw_bank.lpm = reg;
262c1632 304 hw_alloc_regmap(udc, !!reg);
d3595d13
AS		 305 udc->hw_bank.size = udc->hw_bank.op - udc->hw_bank.abs;
306 udc->hw_bank.size += OP_LAST;
307 udc->hw_bank.size /= sizeof(u32);
aa69a809 308
262c1632 309 reg = hw_read(udc, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
f9df8395 310 ffs_nr(DCCPARAMS_DEN);
d3595d13 311 udc->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
f01ef574 312
d3595d13 313 if (udc->hw_ep_max == 0 || udc->hw_ep_max > ENDPT_MAX)
ca9cfea0 314 return -ENODEV;
f01ef574 315
ce9d6fbc
AS		 316 dev_dbg(udc->dev, "ChipIdea UDC found, lpm: %d; cap: %p op: %p\n",
317 udc->hw_bank.lpm, udc->hw_bank.cap, udc->hw_bank.op);
318
f01ef574
PK		 319 /* setup lock mode ? */
320
321 /* ENDPTSETUPSTAT is '0' by default */
322
323 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
324
325 return 0;
326}
327/**
328 * hw_device_reset: resets chip (execute without interruption)
329 * @base: register base address
330 *
331 * This function returns an error code
332 */
333static int hw_device_reset(struct ci13xxx *udc)
334{
aa69a809 335 /* should flush & stop before reset */
262c1632
AS		 336 hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
337 hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
aa69a809 338
262c1632
AS		 339 hw_write(udc, OP_USBCMD, USBCMD_RST, USBCMD_RST);
340 while (hw_read(udc, OP_USBCMD, USBCMD_RST))
aa69a809
DL		 341 udelay(10); /* not RTOS friendly */
342
f01ef574
PK		 343
344 if (udc->udc_driver->notify_event)
345 udc->udc_driver->notify_event(udc,
346 CI13XXX_CONTROLLER_RESET_EVENT);
347
8c2387a7 348 if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
262c1632 349 hw_write(udc, OP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
f01ef574 350
aa69a809 351 /* USBMODE should be configured step by step */
262c1632
AS		 352 hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
353 hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
f9df8395 354 /* HW >= 2.3 */
262c1632 355 hw_write(udc, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
aa69a809 356
262c1632 357 if (hw_read(udc, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
aa69a809 358 pr_err("cannot enter in device mode");
d3595d13 359 pr_err("lpm = %i", udc->hw_bank.lpm);
aa69a809
DL		 360 return -ENODEV;
361 }
362
aa69a809
DL		 363 return 0;
364}
365
366/**
367 * hw_device_state: enables/disables interrupts & starts/stops device (execute
368 * without interruption)
369 * @dma: 0 => disable, !0 => enable and set dma engine
370 *
371 * This function returns an error code
372 */
d3595d13 373static int hw_device_state(struct ci13xxx *udc, u32 dma)
aa69a809
DL		 374{
375 if (dma) {
262c1632 376 hw_write(udc, OP_ENDPTLISTADDR, ~0, dma);
aa69a809 377 /* interrupt, error, port change, reset, sleep/suspend */
262c1632 378 hw_write(udc, OP_USBINTR, ~0,
aa69a809 379 USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
262c1632 380 hw_write(udc, OP_USBCMD, USBCMD_RS, USBCMD_RS);
aa69a809 381 } else {
262c1632
AS		 382 hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
383 hw_write(udc, OP_USBINTR, ~0, 0);
aa69a809
DL		 384 }
385 return 0;
386}
387
388/**
389 * hw_ep_flush: flush endpoint fifo (execute without interruption)
390 * @num: endpoint number
391 * @dir: endpoint direction
392 *
393 * This function returns an error code
394 */
d3595d13 395static int hw_ep_flush(struct ci13xxx *udc, int num, int dir)
aa69a809
DL		 396{
397 int n = hw_ep_bit(num, dir);
398
399 do {
400 /* flush any pending transfer */
262c1632
AS		 401 hw_write(udc, OP_ENDPTFLUSH, BIT(n), BIT(n));
402 while (hw_read(udc, OP_ENDPTFLUSH, BIT(n)))
aa69a809 403 cpu_relax();
262c1632 404 } while (hw_read(udc, OP_ENDPTSTAT, BIT(n)));
aa69a809
DL		 405
406 return 0;
407}
408
409/**
410 * hw_ep_disable: disables endpoint (execute without interruption)
411 * @num: endpoint number
412 * @dir: endpoint direction
413 *
414 * This function returns an error code
415 */
d3595d13 416static int hw_ep_disable(struct ci13xxx *udc, int num, int dir)
aa69a809 417{
d3595d13 418 hw_ep_flush(udc, num, dir);
262c1632 419 hw_write(udc, OP_ENDPTCTRL + num,
d3595d13 420 dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
aa69a809
DL		 421 return 0;
422}
423
424/**
425 * hw_ep_enable: enables endpoint (execute without interruption)
426 * @num: endpoint number
427 * @dir: endpoint direction
428 * @type: endpoint type
429 *
430 * This function returns an error code
431 */
d3595d13 432static int hw_ep_enable(struct ci13xxx *udc, int num, int dir, int type)
aa69a809
DL		 433{
434 u32 mask, data;
435
436 if (dir) {
437 mask = ENDPTCTRL_TXT; /* type */
438 data = type << ffs_nr(mask);
439
440 mask |= ENDPTCTRL_TXS; /* unstall */
441 mask |= ENDPTCTRL_TXR; /* reset data toggle */
442 data |= ENDPTCTRL_TXR;
443 mask |= ENDPTCTRL_TXE; /* enable */
444 data |= ENDPTCTRL_TXE;
445 } else {
446 mask = ENDPTCTRL_RXT; /* type */
447 data = type << ffs_nr(mask);
448
449 mask |= ENDPTCTRL_RXS; /* unstall */
450 mask |= ENDPTCTRL_RXR; /* reset data toggle */
451 data |= ENDPTCTRL_RXR;
452 mask |= ENDPTCTRL_RXE; /* enable */
453 data |= ENDPTCTRL_RXE;
454 }
262c1632 455 hw_write(udc, OP_ENDPTCTRL + num, mask, data);
aa69a809
DL		 456 return 0;
457}
458
459/**
460 * hw_ep_get_halt: return endpoint halt status
461 * @num: endpoint number
462 * @dir: endpoint direction
463 *
464 * This function returns 1 if endpoint halted
465 */
d3595d13 466static int hw_ep_get_halt(struct ci13xxx *udc, int num, int dir)
aa69a809
DL		 467{
468 u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
469
262c1632 470 return hw_read(udc, OP_ENDPTCTRL + num, mask) ? 1 : 0;
aa69a809
DL		 471}
472
aa69a809
DL		 473/**
474 * hw_test_and_clear_setup_status: test & clear setup status (execute without
475 * interruption)
dd39c358 476 * @n: endpoint number
aa69a809
DL		 477 *
478 * This function returns setup status
479 */
d3595d13 480static int hw_test_and_clear_setup_status(struct ci13xxx *udc, int n)
aa69a809 481{
d3595d13 482 n = ep_to_bit(udc, n);
262c1632 483 return hw_test_and_clear(udc, OP_ENDPTSETUPSTAT, BIT(n));
aa69a809
DL		 484}
485
486/**
487 * hw_ep_prime: primes endpoint (execute without interruption)
488 * @num: endpoint number
489 * @dir: endpoint direction
490 * @is_ctrl: true if control endpoint
491 *
492 * This function returns an error code
493 */
d3595d13 494static int hw_ep_prime(struct ci13xxx *udc, int num, int dir, int is_ctrl)
aa69a809
DL		 495{
496 int n = hw_ep_bit(num, dir);
497
262c1632 498 if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
aa69a809
DL		 499 return -EAGAIN;
500
262c1632 501 hw_write(udc, OP_ENDPTPRIME, BIT(n), BIT(n));
aa69a809 502
262c1632 503 while (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
aa69a809 504 cpu_relax();
262c1632 505 if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
aa69a809
DL		 506 return -EAGAIN;
507
508 /* status shoult be tested according with manual but it doesn't work */
509 return 0;
510}
511
512/**
513 * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
514 * without interruption)
515 * @num: endpoint number
516 * @dir: endpoint direction
517 * @value: true => stall, false => unstall
518 *
519 * This function returns an error code
520 */
d3595d13 521static int hw_ep_set_halt(struct ci13xxx *udc, int num, int dir, int value)
aa69a809
DL		 522{
523 if (value != 0 && value != 1)
524 return -EINVAL;
525
526 do {
262c1632 527 enum ci13xxx_regs reg = OP_ENDPTCTRL + num;
aa69a809
DL		 528 u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
529 u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
530
531 /* data toggle - reserved for EP0 but it's in ESS */
262c1632
AS		 532 hw_write(udc, reg, mask_xs|mask_xr,
533 value ? mask_xs : mask_xr);
d3595d13 534 } while (value != hw_ep_get_halt(udc, num, dir));
aa69a809
DL		 535
536 return 0;
537}
538
539/**
540 * hw_intr_clear: disables interrupt & clears interrupt status (execute without
541 * interruption)
542 * @n: interrupt bit
543 *
544 * This function returns an error code
545 */
d3595d13 546static int hw_intr_clear(struct ci13xxx *udc, int n)
aa69a809
DL		 547{
548 if (n >= REG_BITS)
549 return -EINVAL;
550
262c1632
AS		 551 hw_write(udc, OP_USBINTR, BIT(n), 0);
552 hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
aa69a809
DL		 553 return 0;
554}
555
556/**
557 * hw_intr_force: enables interrupt & forces interrupt status (execute without
558 * interruption)
559 * @n: interrupt bit
560 *
561 * This function returns an error code
562 */
d3595d13 563static int hw_intr_force(struct ci13xxx *udc, int n)
aa69a809
DL		 564{
565 if (n >= REG_BITS)
566 return -EINVAL;
567
262c1632
AS		 568 hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
569 hw_write(udc, OP_USBINTR, BIT(n), BIT(n));
570 hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
571 hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, 0);
aa69a809
DL		 572 return 0;
573}
574
575/**
576 * hw_is_port_high_speed: test if port is high speed
577 *
578 * This function returns true if high speed port
579 */
d3595d13 580static int hw_port_is_high_speed(struct ci13xxx *udc)
aa69a809 581{
262c1632
AS		 582 return udc->hw_bank.lpm ? hw_read(udc, OP_DEVLC, DEVLC_PSPD) :
583 hw_read(udc, OP_PORTSC, PORTSC_HSP);
aa69a809
DL		 584}
585
586/**
587 * hw_port_test_get: reads port test mode value
588 *
589 * This function returns port test mode value
590 */
d3595d13 591static u8 hw_port_test_get(struct ci13xxx *udc)
aa69a809 592{
262c1632 593 return hw_read(udc, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
aa69a809
DL		 594}
595
596/**
597 * hw_port_test_set: writes port test mode (execute without interruption)
598 * @mode: new value
599 *
600 * This function returns an error code
601 */
d3595d13 602static int hw_port_test_set(struct ci13xxx *udc, u8 mode)
aa69a809
DL		 603{
604 const u8 TEST_MODE_MAX = 7;
605
606 if (mode > TEST_MODE_MAX)
607 return -EINVAL;
608
262c1632 609 hw_write(udc, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
aa69a809
DL		 610 return 0;
611}
612
613/**
614 * hw_read_intr_enable: returns interrupt enable register
615 *
616 * This function returns register data
617 */
d3595d13 618static u32 hw_read_intr_enable(struct ci13xxx *udc)
aa69a809 619{
262c1632 620 return hw_read(udc, OP_USBINTR, ~0);
aa69a809
DL		 621}
622
623/**
624 * hw_read_intr_status: returns interrupt status register
625 *
626 * This function returns register data
627 */
d3595d13 628static u32 hw_read_intr_status(struct ci13xxx *udc)
aa69a809 629{
262c1632 630 return hw_read(udc, OP_USBSTS, ~0);
aa69a809
DL		 631}
632
633/**
634 * hw_register_read: reads all device registers (execute without interruption)
635 * @buf: destination buffer
636 * @size: buffer size
637 *
638 * This function returns number of registers read
639 */
d3595d13 640static size_t hw_register_read(struct ci13xxx *udc, u32 *buf, size_t size)
aa69a809
DL		 641{
642 unsigned i;
643
d3595d13
AS		 644 if (size > udc->hw_bank.size)
645 size = udc->hw_bank.size;
aa69a809
DL		 646
647 for (i = 0; i < size; i++)
262c1632 648 buf[i] = hw_read(udc, i * sizeof(u32), ~0);
aa69a809
DL		 649
650 return size;
651}
652
653/**
654 * hw_register_write: writes to register
655 * @addr: register address
656 * @data: register value
657 *
658 * This function returns an error code
659 */
d3595d13 660static int hw_register_write(struct ci13xxx *udc, u16 addr, u32 data)
aa69a809
DL		 661{
662 /* align */
663 addr /= sizeof(u32);
664
d3595d13 665 if (addr >= udc->hw_bank.size)
aa69a809
DL		 666 return -EINVAL;
667
668 /* align */
669 addr *= sizeof(u32);
670
262c1632 671 hw_write(udc, addr, ~0, data);
aa69a809
DL		 672 return 0;
673}
674
675/**
676 * hw_test_and_clear_complete: test & clear complete status (execute without
677 * interruption)
dd39c358 678 * @n: endpoint number
aa69a809
DL		 679 *
680 * This function returns complete status
681 */
d3595d13 682static int hw_test_and_clear_complete(struct ci13xxx *udc, int n)
aa69a809 683{
d3595d13 684 n = ep_to_bit(udc, n);
262c1632 685 return hw_test_and_clear(udc, OP_ENDPTCOMPLETE, BIT(n));
aa69a809
DL		 686}
687
688/**
689 * hw_test_and_clear_intr_active: test & clear active interrupts (execute
690 * without interruption)
691 *
692 * This function returns active interrutps
693 */
d3595d13 694static u32 hw_test_and_clear_intr_active(struct ci13xxx *udc)
aa69a809 695{
d3595d13 696 u32 reg = hw_read_intr_status(udc) & hw_read_intr_enable(udc);
aa69a809 697
262c1632 698 hw_write(udc, OP_USBSTS, ~0, reg);
aa69a809
DL		 699 return reg;
700}
701
702/**
703 * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
704 * interruption)
705 *
706 * This function returns guard value
707 */
d3595d13 708static int hw_test_and_clear_setup_guard(struct ci13xxx *udc)
aa69a809 709{
262c1632 710 return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, 0);
aa69a809
DL		 711}
712
713/**
714 * hw_test_and_set_setup_guard: test & set setup guard (execute without
715 * interruption)
716 *
717 * This function returns guard value
718 */
d3595d13 719static int hw_test_and_set_setup_guard(struct ci13xxx *udc)
aa69a809 720{
262c1632 721 return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
aa69a809
DL		 722}
723
724/**
725 * hw_usb_set_address: configures USB address (execute without interruption)
726 * @value: new USB address
727 *
ef15e549
AS		 728 * This function explicitly sets the address, without the "USBADRA" (advance)
729 * feature, which is not supported by older versions of the controller.
aa69a809 730 */
ef15e549 731static void hw_usb_set_address(struct ci13xxx *udc, u8 value)
aa69a809 732{
ef15e549
AS		 733 hw_write(udc, OP_DEVICEADDR, DEVICEADDR_USBADR,
734 value << ffs_nr(DEVICEADDR_USBADR));
aa69a809
DL		 735}
736
737/**
738 * hw_usb_reset: restart device after a bus reset (execute without
739 * interruption)
740 *
741 * This function returns an error code
742 */
d3595d13 743static int hw_usb_reset(struct ci13xxx *udc)
aa69a809 744{
d3595d13 745 hw_usb_set_address(udc, 0);
aa69a809
DL		 746
747 /* ESS flushes only at end?!? */
262c1632 748 hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
aa69a809
DL		 749
750 /* clear setup token semaphores */
262c1632 751 hw_write(udc, OP_ENDPTSETUPSTAT, 0, 0);
aa69a809
DL		 752
753 /* clear complete status */
262c1632 754 hw_write(udc, OP_ENDPTCOMPLETE, 0, 0);
aa69a809
DL		 755
756 /* wait until all bits cleared */
262c1632 757 while (hw_read(udc, OP_ENDPTPRIME, ~0))
aa69a809
DL		 758 udelay(10); /* not RTOS friendly */
759
760 /* reset all endpoints ? */
761
762 /* reset internal status and wait for further instructions
763 no need to verify the port reset status (ESS does it) */
764
765 return 0;
766}
767
768/******************************************************************************
769 * DBG block
770 *****************************************************************************/
771/**
772 * show_device: prints information about device capabilities and status
773 *
774 * Check "device.h" for details
775 */
776static ssize_t show_device(struct device *dev, struct device_attribute *attr,
777 char *buf)
778{
779 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
780 struct usb_gadget *gadget = &udc->gadget;
781 int n = 0;
782
aa69a809 783 if (attr == NULL || buf == NULL) {
0f089094 784 dev_err(udc->dev, "[%s] EINVAL\n", __func__);
aa69a809
DL		 785 return 0;
786 }
787
788 n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
789 gadget->speed);
d327ab5b
MN		 790 n += scnprintf(buf + n, PAGE_SIZE - n, "max_speed = %d\n",
791 gadget->max_speed);
792 /* TODO: Scheduled for removal in 3.8. */
aa69a809 793 n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
d327ab5b 794 gadget_is_dualspeed(gadget));
aa69a809
DL		 795 n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
796 gadget->is_otg);
797 n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
798 gadget->is_a_peripheral);
799 n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
800 gadget->b_hnp_enable);
801 n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
802 gadget->a_hnp_support);
803 n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
804 gadget->a_alt_hnp_support);
805 n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
806 (gadget->name ? gadget->name : ""));
807
808 return n;
809}
810static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
811
812/**
813 * show_driver: prints information about attached gadget (if any)
814 *
815 * Check "device.h" for details
816 */
817static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
818 char *buf)
819{
820 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
821 struct usb_gadget_driver *driver = udc->driver;
822 int n = 0;
823
aa69a809
DL		 824 if (attr == NULL || buf == NULL) {
825 dev_err(dev, "[%s] EINVAL\n", __func__);
826 return 0;
827 }
828
829 if (driver == NULL)
830 return scnprintf(buf, PAGE_SIZE,
831 "There is no gadget attached!\n");
832
833 n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
834 (driver->function ? driver->function : ""));
835 n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
7177aed4 836 driver->max_speed);
aa69a809
DL		 837
838 return n;
839}
840static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
841
842/* Maximum event message length */
843#define DBG_DATA_MSG 64UL
844
845/* Maximum event messages */
846#define DBG_DATA_MAX 128UL
847
848/* Event buffer descriptor */
849static struct {
850 char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
851 unsigned idx; /* index */
852 unsigned tty; /* print to console? */
853 rwlock_t lck; /* lock */
854} dbg_data = {
855 .idx = 0,
856 .tty = 0,
857 .lck = __RW_LOCK_UNLOCKED(lck)
858};
859
860/**
861 * dbg_dec: decrements debug event index
862 * @idx: buffer index
863 */
864static void dbg_dec(unsigned *idx)
865{
866 *idx = (*idx - 1) & (DBG_DATA_MAX-1);
867}
868
869/**
870 * dbg_inc: increments debug event index
871 * @idx: buffer index
872 */
873static void dbg_inc(unsigned *idx)
874{
875 *idx = (*idx + 1) & (DBG_DATA_MAX-1);
876}
877
878/**
879 * dbg_print: prints the common part of the event
880 * @addr: endpoint address
881 * @name: event name
882 * @status: status
883 * @extra: extra information
884 */
885static void dbg_print(u8 addr, const char *name, int status, const char *extra)
886{
887 struct timeval tval;
888 unsigned int stamp;
889 unsigned long flags;
890
891 write_lock_irqsave(&dbg_data.lck, flags);
892
893 do_gettimeofday(&tval);
894 stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
895 stamp = stamp * 1000000 + tval.tv_usec;
896
897 scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
0f91349b 898 "%04X\t? %02X %-7.7s %4i ?\t%s\n",
aa69a809
DL		 899 stamp, addr, name, status, extra);
900
901 dbg_inc(&dbg_data.idx);
902
903 write_unlock_irqrestore(&dbg_data.lck, flags);
904
905 if (dbg_data.tty != 0)
0f91349b 906 pr_notice("%04X\t? %02X %-7.7s %4i ?\t%s\n",
aa69a809
DL		 907 stamp, addr, name, status, extra);
908}
909
910/**
911 * dbg_done: prints a DONE event
912 * @addr: endpoint address
913 * @td: transfer descriptor
914 * @status: status
915 */
916static void dbg_done(u8 addr, const u32 token, int status)
917{
918 char msg[DBG_DATA_MSG];
919
920 scnprintf(msg, sizeof(msg), "%d %02X",
921 (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
922 (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
923 dbg_print(addr, "DONE", status, msg);
924}
925
926/**
927 * dbg_event: prints a generic event
928 * @addr: endpoint address
929 * @name: event name
930 * @status: status
931 */
932static void dbg_event(u8 addr, const char *name, int status)
933{
934 if (name != NULL)
935 dbg_print(addr, name, status, "");
936}
937
938/*
939 * dbg_queue: prints a QUEUE event
940 * @addr: endpoint address
941 * @req: USB request
942 * @status: status
943 */
944static void dbg_queue(u8 addr, const struct usb_request *req, int status)
945{
946 char msg[DBG_DATA_MSG];
947
948 if (req != NULL) {
949 scnprintf(msg, sizeof(msg),
950 "%d %d", !req->no_interrupt, req->length);
951 dbg_print(addr, "QUEUE", status, msg);
952 }
953}
954
955/**
956 * dbg_setup: prints a SETUP event
957 * @addr: endpoint address
958 * @req: setup request
959 */
960static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
961{
962 char msg[DBG_DATA_MSG];
963
964 if (req != NULL) {
965 scnprintf(msg, sizeof(msg),
966 "%02X %02X %04X %04X %d", req->bRequestType,
967 req->bRequest, le16_to_cpu(req->wValue),
968 le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
969 dbg_print(addr, "SETUP", 0, msg);
970 }
971}
972
973/**
974 * show_events: displays the event buffer
975 *
976 * Check "device.h" for details
977 */
978static ssize_t show_events(struct device *dev, struct device_attribute *attr,
979 char *buf)
980{
981 unsigned long flags;
982 unsigned i, j, n = 0;
983
aa69a809 984 if (attr == NULL || buf == NULL) {
0f089094 985 dev_err(dev->parent, "[%s] EINVAL\n", __func__);
aa69a809
DL		 986 return 0;
987 }
988
989 read_lock_irqsave(&dbg_data.lck, flags);
990
991 i = dbg_data.idx;
992 for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
993 n += strlen(dbg_data.buf[i]);
994 if (n >= PAGE_SIZE) {
995 n -= strlen(dbg_data.buf[i]);
996 break;
997 }
998 }
999 for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
1000 j += scnprintf(buf + j, PAGE_SIZE - j,
1001 "%s", dbg_data.buf[i]);
1002
1003 read_unlock_irqrestore(&dbg_data.lck, flags);
1004
1005 return n;
1006}
1007
1008/**
1009 * store_events: configure if events are going to be also printed to console
1010 *
1011 * Check "device.h" for details
1012 */
1013static ssize_t store_events(struct device *dev, struct device_attribute *attr,
1014 const char *buf, size_t count)
1015{
1016 unsigned tty;
1017
aa69a809
DL		 1018 if (attr == NULL || buf == NULL) {
1019 dev_err(dev, "[%s] EINVAL\n", __func__);
1020 goto done;
1021 }
1022
1023 if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
1024 dev_err(dev, "<1|0>: enable|disable console log\n");
1025 goto done;
1026 }
1027
1028 dbg_data.tty = tty;
1029 dev_info(dev, "tty = %u", dbg_data.tty);
1030
1031 done:
1032 return count;
1033}
1034static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
1035
1036/**
1037 * show_inters: interrupt status, enable status and historic
1038 *
1039 * Check "device.h" for details
1040 */
1041static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
1042 char *buf)
1043{
1044 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1045 unsigned long flags;
1046 u32 intr;
1047 unsigned i, j, n = 0;
1048
aa69a809 1049 if (attr == NULL || buf == NULL) {
0f089094 1050 dev_err(udc->dev, "[%s] EINVAL\n", __func__);
aa69a809
DL		 1051 return 0;
1052 }
1053
d3595d13 1054 spin_lock_irqsave(&udc->lock, flags);
aa69a809
DL		 1055
1056 n += scnprintf(buf + n, PAGE_SIZE - n,
d3595d13 1057 "status = %08x\n", hw_read_intr_status(udc));
aa69a809 1058 n += scnprintf(buf + n, PAGE_SIZE - n,
d3595d13 1059 "enable = %08x\n", hw_read_intr_enable(udc));
aa69a809
DL		 1060
1061 n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
1062 isr_statistics.test);
0f91349b 1063 n += scnprintf(buf + n, PAGE_SIZE - n, "? ui = %d\n",
aa69a809 1064 isr_statistics.ui);
0f91349b 1065 n += scnprintf(buf + n, PAGE_SIZE - n, "? uei = %d\n",
aa69a809 1066 isr_statistics.uei);
0f91349b 1067 n += scnprintf(buf + n, PAGE_SIZE - n, "? pci = %d\n",
aa69a809 1068 isr_statistics.pci);
0f91349b 1069 n += scnprintf(buf + n, PAGE_SIZE - n, "? uri = %d\n",
aa69a809 1070 isr_statistics.uri);
0f91349b 1071 n += scnprintf(buf + n, PAGE_SIZE - n, "? sli = %d\n",
aa69a809
DL		 1072 isr_statistics.sli);
1073 n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
1074 isr_statistics.none);
1075 n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
1076 isr_statistics.hndl.cnt);
1077
1078 for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
1079 i &= ISR_MASK;
1080 intr = isr_statistics.hndl.buf[i];
1081
1082 if (USBi_UI & intr)
1083 n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
1084 intr &= ~USBi_UI;
1085 if (USBi_UEI & intr)
1086 n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
1087 intr &= ~USBi_UEI;
1088 if (USBi_PCI & intr)
1089 n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
1090 intr &= ~USBi_PCI;
1091 if (USBi_URI & intr)
1092 n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
1093 intr &= ~USBi_URI;
1094 if (USBi_SLI & intr)
1095 n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
1096 intr &= ~USBi_SLI;
1097 if (intr)
1098 n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
1099 if (isr_statistics.hndl.buf[i])
1100 n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
1101 }
1102
d3595d13 1103 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809
DL		 1104
1105 return n;
1106}
1107
1108/**
1109 * store_inters: enable & force or disable an individual interrutps
1110 * (to be used for test purposes only)
1111 *
1112 * Check "device.h" for details
1113 */
1114static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
1115 const char *buf, size_t count)
1116{
1117 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1118 unsigned long flags;
1119 unsigned en, bit;
1120
aa69a809 1121 if (attr == NULL || buf == NULL) {
0f089094 1122 dev_err(udc->dev, "EINVAL\n");
aa69a809
DL		 1123 goto done;
1124 }
1125
1126 if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
0f089094 1127 dev_err(udc->dev, "<1|0> <bit>: enable|disable interrupt\n");
aa69a809
DL		 1128 goto done;
1129 }
1130
d3595d13 1131 spin_lock_irqsave(&udc->lock, flags);
aa69a809 1132 if (en) {
d3595d13 1133 if (hw_intr_force(udc, bit))
aa69a809
DL		 1134 dev_err(dev, "invalid bit number\n");
1135 else
1136 isr_statistics.test++;
1137 } else {
d3595d13 1138 if (hw_intr_clear(udc, bit))
aa69a809
DL		 1139 dev_err(dev, "invalid bit number\n");
1140 }
d3595d13 1141 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809
DL		 1142
1143 done:
1144 return count;
1145}
1146static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
1147
1148/**
1149 * show_port_test: reads port test mode
1150 *
1151 * Check "device.h" for details
1152 */
1153static ssize_t show_port_test(struct device *dev,
1154 struct device_attribute *attr, char *buf)
1155{
1156 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1157 unsigned long flags;
1158 unsigned mode;
1159
aa69a809 1160 if (attr == NULL || buf == NULL) {
0f089094 1161 dev_err(udc->dev, "EINVAL\n");
aa69a809
DL		 1162 return 0;
1163 }
1164
d3595d13
AS		 1165 spin_lock_irqsave(&udc->lock, flags);
1166 mode = hw_port_test_get(udc);
1167 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809
DL		 1168
1169 return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
1170}
1171
1172/**
1173 * store_port_test: writes port test mode
1174 *
1175 * Check "device.h" for details
1176 */
1177static ssize_t store_port_test(struct device *dev,
1178 struct device_attribute *attr,
1179 const char *buf, size_t count)
1180{
1181 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1182 unsigned long flags;
1183 unsigned mode;
1184
aa69a809 1185 if (attr == NULL || buf == NULL) {
0f089094 1186 dev_err(udc->dev, "[%s] EINVAL\n", __func__);
aa69a809
DL		 1187 goto done;
1188 }
1189
1190 if (sscanf(buf, "%u", &mode) != 1) {
0f089094 1191 dev_err(udc->dev, "<mode>: set port test mode");
aa69a809
DL		 1192 goto done;
1193 }
1194
d3595d13
AS		 1195 spin_lock_irqsave(&udc->lock, flags);
1196 if (hw_port_test_set(udc, mode))
0f089094 1197 dev_err(udc->dev, "invalid mode\n");
d3595d13 1198 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809
DL		 1199
1200 done:
1201 return count;
1202}
1203static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
1204 show_port_test, store_port_test);
1205
1206/**
1207 * show_qheads: DMA contents of all queue heads
1208 *
1209 * Check "device.h" for details
1210 */
1211static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
1212 char *buf)
1213{
1214 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1215 unsigned long flags;
1216 unsigned i, j, n = 0;
1217
aa69a809 1218 if (attr == NULL || buf == NULL) {
0f089094 1219 dev_err(udc->dev, "[%s] EINVAL\n", __func__);
aa69a809
DL		 1220 return 0;
1221 }
1222
d3595d13
AS		 1223 spin_lock_irqsave(&udc->lock, flags);
1224 for (i = 0; i < udc->hw_ep_max/2; i++) {
ca9cfea0 1225 struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
d3595d13
AS		 1226 struct ci13xxx_ep *mEpTx =
1227 &udc->ci13xxx_ep[i + udc->hw_ep_max/2];
aa69a809
DL		 1228 n += scnprintf(buf + n, PAGE_SIZE - n,
1229 "EP=%02i: RX=%08X TX=%08X\n",
ca9cfea0 1230 i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
aa69a809
DL		 1231 for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
1232 n += scnprintf(buf + n, PAGE_SIZE - n,
1233 " %04X: %08X %08X\n", j,
ca9cfea0
PK		 1234 *((u32 *)mEpRx->qh.ptr + j),
1235 *((u32 *)mEpTx->qh.ptr + j));
aa69a809
DL		 1236 }
1237 }
d3595d13 1238 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809
DL		 1239
1240 return n;
1241}
1242static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
1243
1244/**
1245 * show_registers: dumps all registers
1246 *
1247 * Check "device.h" for details
1248 */
c2b65f84 1249#define DUMP_ENTRIES 512
aa69a809
DL		 1250static ssize_t show_registers(struct device *dev,
1251 struct device_attribute *attr, char *buf)
1252{
1253 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1254 unsigned long flags;
c2b65f84 1255 u32 *dump;
aa69a809
DL		 1256 unsigned i, k, n = 0;
1257
aa69a809 1258 if (attr == NULL || buf == NULL) {
0f089094 1259 dev_err(udc->dev, "[%s] EINVAL\n", __func__);
aa69a809
DL		 1260 return 0;
1261 }
1262
c2b65f84
SAS		 1263 dump = kmalloc(sizeof(u32) * DUMP_ENTRIES, GFP_KERNEL);
1264 if (!dump) {
0f089094 1265 dev_err(udc->dev, "%s: out of memory\n", __func__);
c2b65f84
SAS		 1266 return 0;
1267 }
1268
d3595d13
AS		 1269 spin_lock_irqsave(&udc->lock, flags);
1270 k = hw_register_read(udc, dump, DUMP_ENTRIES);
1271 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809
DL		 1272
1273 for (i = 0; i < k; i++) {
1274 n += scnprintf(buf + n, PAGE_SIZE - n,
1275 "reg[0x%04X] = 0x%08X\n",
1276 i * (unsigned)sizeof(u32), dump[i]);
1277 }
c2b65f84 1278 kfree(dump);
aa69a809
DL		 1279
1280 return n;
1281}
1282
1283/**
1284 * store_registers: writes value to register address
1285 *
1286 * Check "device.h" for details
1287 */
1288static ssize_t store_registers(struct device *dev,
1289 struct device_attribute *attr,
1290 const char *buf, size_t count)
1291{
1292 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1293 unsigned long addr, data, flags;
1294
aa69a809 1295 if (attr == NULL || buf == NULL) {
0f089094 1296 dev_err(udc->dev, "[%s] EINVAL\n", __func__);
aa69a809
DL		 1297 goto done;
1298 }
1299
1300 if (sscanf(buf, "%li %li", &addr, &data) != 2) {
0f089094
AS		 1301 dev_err(udc->dev,
1302 "<addr> <data>: write data to register address\n");
aa69a809
DL		 1303 goto done;
1304 }
1305
d3595d13
AS		 1306 spin_lock_irqsave(&udc->lock, flags);
1307 if (hw_register_write(udc, addr, data))
0f089094 1308 dev_err(udc->dev, "invalid address range\n");
d3595d13 1309 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809
DL		 1310
1311 done:
1312 return count;
1313}
1314static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
1315 show_registers, store_registers);
1316
1317/**
1318 * show_requests: DMA contents of all requests currently queued (all endpts)
1319 *
1320 * Check "device.h" for details
1321 */
1322static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
1323 char *buf)
1324{
1325 struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
1326 unsigned long flags;
1327 struct list_head *ptr = NULL;
1328 struct ci13xxx_req *req = NULL;
ca9cfea0 1329 unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
aa69a809 1330
aa69a809 1331 if (attr == NULL || buf == NULL) {
0f089094 1332 dev_err(udc->dev, "[%s] EINVAL\n", __func__);
aa69a809
DL		 1333 return 0;
1334 }
1335
d3595d13
AS		 1336 spin_lock_irqsave(&udc->lock, flags);
1337 for (i = 0; i < udc->hw_ep_max; i++)
ca9cfea0
PK		 1338 list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
1339 {
1340 req = list_entry(ptr, struct ci13xxx_req, queue);
aa69a809 1341
ca9cfea0
PK		 1342 n += scnprintf(buf + n, PAGE_SIZE - n,
1343 "EP=%02i: TD=%08X %s\n",
d3595d13
AS		 1344 i % udc->hw_ep_max/2, (u32)req->dma,
1345 ((i < udc->hw_ep_max/2) ? "RX" : "TX"));
ca9cfea0
PK		 1346
1347 for (j = 0; j < qSize; j++)
aa69a809 1348 n += scnprintf(buf + n, PAGE_SIZE - n,
ca9cfea0
PK		 1349 " %04X: %08X\n", j,
1350 *((u32 *)req->ptr + j));
1351 }
d3595d13 1352 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809
DL		 1353
1354 return n;
1355}
1356static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
1357
1358/**
1359 * dbg_create_files: initializes the attribute interface
1360 * @dev: device
1361 *
1362 * This function returns an error code
1363 */
1364__maybe_unused static int dbg_create_files(struct device *dev)
1365{
1366 int retval = 0;
1367
1368 if (dev == NULL)
1369 return -EINVAL;
1370 retval = device_create_file(dev, &dev_attr_device);
1371 if (retval)
1372 goto done;
1373 retval = device_create_file(dev, &dev_attr_driver);
1374 if (retval)
1375 goto rm_device;
1376 retval = device_create_file(dev, &dev_attr_events);
1377 if (retval)
1378 goto rm_driver;
1379 retval = device_create_file(dev, &dev_attr_inters);
1380 if (retval)
1381 goto rm_events;
1382 retval = device_create_file(dev, &dev_attr_port_test);
1383 if (retval)
1384 goto rm_inters;
1385 retval = device_create_file(dev, &dev_attr_qheads);
1386 if (retval)
1387 goto rm_port_test;
1388 retval = device_create_file(dev, &dev_attr_registers);
1389 if (retval)
1390 goto rm_qheads;
1391 retval = device_create_file(dev, &dev_attr_requests);
1392 if (retval)
1393 goto rm_registers;
1394 return 0;
1395
1396 rm_registers:
1397 device_remove_file(dev, &dev_attr_registers);
1398 rm_qheads:
1399 device_remove_file(dev, &dev_attr_qheads);
1400 rm_port_test:
1401 device_remove_file(dev, &dev_attr_port_test);
1402 rm_inters:
1403 device_remove_file(dev, &dev_attr_inters);
1404 rm_events:
1405 device_remove_file(dev, &dev_attr_events);
1406 rm_driver:
1407 device_remove_file(dev, &dev_attr_driver);
1408 rm_device:
1409 device_remove_file(dev, &dev_attr_device);
1410 done:
1411 return retval;
1412}
1413
1414/**
1415 * dbg_remove_files: destroys the attribute interface
1416 * @dev: device
1417 *
1418 * This function returns an error code
1419 */
1420__maybe_unused static int dbg_remove_files(struct device *dev)
1421{
1422 if (dev == NULL)
1423 return -EINVAL;
1424 device_remove_file(dev, &dev_attr_requests);
1425 device_remove_file(dev, &dev_attr_registers);
1426 device_remove_file(dev, &dev_attr_qheads);
1427 device_remove_file(dev, &dev_attr_port_test);
1428 device_remove_file(dev, &dev_attr_inters);
1429 device_remove_file(dev, &dev_attr_events);
1430 device_remove_file(dev, &dev_attr_driver);
1431 device_remove_file(dev, &dev_attr_device);
1432 return 0;
1433}
1434
1435/******************************************************************************
1436 * UTIL block
1437 *****************************************************************************/
1438/**
1439 * _usb_addr: calculates endpoint address from direction & number
1440 * @ep: endpoint
1441 */
1442static inline u8 _usb_addr(struct ci13xxx_ep *ep)
1443{
1444 return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
1445}
1446
1447/**
1448 * _hardware_queue: configures a request at hardware level
1449 * @gadget: gadget
1450 * @mEp: endpoint
1451 *
1452 * This function returns an error code
1453 */
1454static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1455{
d3595d13 1456 struct ci13xxx *udc = mEp->udc;
aa69a809 1457 unsigned i;
0e6ca199
PK		 1458 int ret = 0;
1459 unsigned length = mReq->req.length;
aa69a809 1460
aa69a809
DL		 1461 /* don't queue twice */
1462 if (mReq->req.status == -EALREADY)
1463 return -EALREADY;
1464
aa69a809 1465 mReq->req.status = -EALREADY;
954aad8c 1466 if (length && mReq->req.dma == DMA_ADDR_INVALID) {
aa69a809
DL		 1467 mReq->req.dma = \
1468 dma_map_single(mEp->device, mReq->req.buf,
0e6ca199
PK		 1469 length, mEp->dir ? DMA_TO_DEVICE :
1470 DMA_FROM_DEVICE);
aa69a809
DL		 1471 if (mReq->req.dma == 0)
1472 return -ENOMEM;
1473
1474 mReq->map = 1;
1475 }
1476
0e6ca199
PK		 1477 if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
1478 mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
1479 &mReq->zdma);
1480 if (mReq->zptr == NULL) {
1481 if (mReq->map) {
1482 dma_unmap_single(mEp->device, mReq->req.dma,
1483 length, mEp->dir ? DMA_TO_DEVICE :
1484 DMA_FROM_DEVICE);
954aad8c 1485 mReq->req.dma = DMA_ADDR_INVALID;
0e6ca199
PK		 1486 mReq->map = 0;
1487 }
1488 return -ENOMEM;
1489 }
1490 memset(mReq->zptr, 0, sizeof(*mReq->zptr));
1491 mReq->zptr->next = TD_TERMINATE;
1492 mReq->zptr->token = TD_STATUS_ACTIVE;
1493 if (!mReq->req.no_interrupt)
1494 mReq->zptr->token |= TD_IOC;
1495 }
aa69a809
DL		 1496 /*
1497 * TD configuration
1498 * TODO - handle requests which spawns into several TDs
1499 */
1500 memset(mReq->ptr, 0, sizeof(*mReq->ptr));
0e6ca199 1501 mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
aa69a809 1502 mReq->ptr->token &= TD_TOTAL_BYTES;
aa69a809 1503 mReq->ptr->token |= TD_STATUS_ACTIVE;
0e6ca199
PK		 1504 if (mReq->zptr) {
1505 mReq->ptr->next = mReq->zdma;
1506 } else {
1507 mReq->ptr->next = TD_TERMINATE;
1508 if (!mReq->req.no_interrupt)
1509 mReq->ptr->token |= TD_IOC;
1510 }
aa69a809
DL		 1511 mReq->ptr->page[0] = mReq->req.dma;
1512 for (i = 1; i < 5; i++)
1513 mReq->ptr->page[i] =
0a313c4d 1514 (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
aa69a809 1515
0e6ca199
PK		 1516 if (!list_empty(&mEp->qh.queue)) {
1517 struct ci13xxx_req *mReqPrev;
1518 int n = hw_ep_bit(mEp->num, mEp->dir);
1519 int tmp_stat;
1520
1521 mReqPrev = list_entry(mEp->qh.queue.prev,
1522 struct ci13xxx_req, queue);
1523 if (mReqPrev->zptr)
1524 mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
1525 else
1526 mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
1527 wmb();
262c1632 1528 if (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
0e6ca199
PK		 1529 goto done;
1530 do {
262c1632
AS		 1531 hw_write(udc, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
1532 tmp_stat = hw_read(udc, OP_ENDPTSTAT, BIT(n));
1533 } while (!hw_read(udc, OP_USBCMD, USBCMD_ATDTW));
1534 hw_write(udc, OP_USBCMD, USBCMD_ATDTW, 0);
0e6ca199
PK		 1535 if (tmp_stat)
1536 goto done;
1537 }
1538
1539 /* QH configuration */
ca9cfea0
PK		 1540 mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
1541 mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
0e6ca199 1542 mEp->qh.ptr->cap |= QH_ZLT;
aa69a809
DL		 1543
1544 wmb(); /* synchronize before ep prime */
1545
d3595d13 1546 ret = hw_ep_prime(udc, mEp->num, mEp->dir,
aa69a809 1547 mEp->type == USB_ENDPOINT_XFER_CONTROL);
0e6ca199
PK		 1548done:
1549 return ret;
aa69a809
DL		 1550}
1551
1552/**
1553 * _hardware_dequeue: handles a request at hardware level
1554 * @gadget: gadget
1555 * @mEp: endpoint
1556 *
1557 * This function returns an error code
1558 */
1559static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
1560{
aa69a809
DL		 1561 if (mReq->req.status != -EALREADY)
1562 return -EINVAL;
1563
0e6ca199
PK		 1564 if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
1565 return -EBUSY;
1566
1567 if (mReq->zptr) {
1568 if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
1569 return -EBUSY;
1570 dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
1571 mReq->zptr = NULL;
1572 }
aa69a809
DL		 1573
1574 mReq->req.status = 0;
1575
1576 if (mReq->map) {
1577 dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
1578 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
954aad8c 1579 mReq->req.dma = DMA_ADDR_INVALID;
aa69a809
DL		 1580 mReq->map = 0;
1581 }
1582
1583 mReq->req.status = mReq->ptr->token & TD_STATUS;
0e6ca199 1584 if ((TD_STATUS_HALTED & mReq->req.status) != 0)
aa69a809
DL		 1585 mReq->req.status = -1;
1586 else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
1587 mReq->req.status = -1;
1588 else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
1589 mReq->req.status = -1;
1590
1591 mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
1592 mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
1593 mReq->req.actual = mReq->req.length - mReq->req.actual;
1594 mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
1595
1596 return mReq->req.actual;
1597}
1598
1599/**
1600 * _ep_nuke: dequeues all endpoint requests
1601 * @mEp: endpoint
1602 *
1603 * This function returns an error code
1604 * Caller must hold lock
1605 */
1606static int _ep_nuke(struct ci13xxx_ep *mEp)
1607__releases(mEp->lock)
1608__acquires(mEp->lock)
1609{
aa69a809
DL		 1610 if (mEp == NULL)
1611 return -EINVAL;
1612
d3595d13 1613 hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
aa69a809 1614
ca9cfea0 1615 while (!list_empty(&mEp->qh.queue)) {
aa69a809
DL		 1616
1617 /* pop oldest request */
1618 struct ci13xxx_req *mReq = \
ca9cfea0 1619 list_entry(mEp->qh.queue.next,
aa69a809
DL		 1620 struct ci13xxx_req, queue);
1621 list_del_init(&mReq->queue);
1622 mReq->req.status = -ESHUTDOWN;
1623
7c25a826 1624 if (mReq->req.complete != NULL) {
aa69a809
DL		 1625 spin_unlock(mEp->lock);
1626 mReq->req.complete(&mEp->ep, &mReq->req);
1627 spin_lock(mEp->lock);
1628 }
1629 }
1630 return 0;
1631}
1632
1633/**
1634 * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
1635 * @gadget: gadget
1636 *
1637 * This function returns an error code
aa69a809
DL		 1638 */
1639static int _gadget_stop_activity(struct usb_gadget *gadget)
aa69a809
DL		 1640{
1641 struct usb_ep *ep;
1642 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
e2b61c1d 1643 unsigned long flags;
aa69a809 1644
aa69a809
DL		 1645 if (gadget == NULL)
1646 return -EINVAL;
1647
d3595d13 1648 spin_lock_irqsave(&udc->lock, flags);
e2b61c1d
PK		 1649 udc->gadget.speed = USB_SPEED_UNKNOWN;
1650 udc->remote_wakeup = 0;
1651 udc->suspended = 0;
d3595d13 1652 spin_unlock_irqrestore(&udc->lock, flags);
e2b61c1d 1653
aa69a809
DL		 1654 /* flush all endpoints */
1655 gadget_for_each_ep(ep, gadget) {
1656 usb_ep_fifo_flush(ep);
1657 }
d36ade60
AS		 1658 usb_ep_fifo_flush(&udc->ep0out->ep);
1659 usb_ep_fifo_flush(&udc->ep0in->ep);
aa69a809 1660
1f339d84
AS		 1661 if (udc->driver)
1662 udc->driver->disconnect(gadget);
aa69a809
DL		 1663
1664 /* make sure to disable all endpoints */
1665 gadget_for_each_ep(ep, gadget) {
1666 usb_ep_disable(ep);
1667 }
aa69a809 1668
ca9cfea0 1669 if (udc->status != NULL) {
d36ade60 1670 usb_ep_free_request(&udc->ep0in->ep, udc->status);
ca9cfea0 1671 udc->status = NULL;
aa69a809
DL		 1672 }
1673
aa69a809
DL		 1674 return 0;
1675}
1676
1677/******************************************************************************
1678 * ISR block
1679 *****************************************************************************/
1680/**
1681 * isr_reset_handler: USB reset interrupt handler
1682 * @udc: UDC device
1683 *
1684 * This function resets USB engine after a bus reset occurred
1685 */
1686static void isr_reset_handler(struct ci13xxx *udc)
1687__releases(udc->lock)
1688__acquires(udc->lock)
1689{
aa69a809
DL		 1690 int retval;
1691
aa69a809
DL		 1692 dbg_event(0xFF, "BUS RST", 0);
1693
d3595d13 1694 spin_unlock(&udc->lock);
aa69a809
DL		 1695 retval = _gadget_stop_activity(&udc->gadget);
1696 if (retval)
1697 goto done;
1698
d3595d13 1699 retval = hw_usb_reset(udc);
aa69a809
DL		 1700 if (retval)
1701 goto done;
1702
d36ade60 1703 udc->status = usb_ep_alloc_request(&udc->ep0in->ep, GFP_ATOMIC);
ac1aa6a2
A		 1704 if (udc->status == NULL)
1705 retval = -ENOMEM;
ca9cfea0 1706
d3595d13 1707 spin_lock(&udc->lock);
aa69a809
DL		 1708
1709 done:
1710 if (retval)
0f089094 1711 dev_err(udc->dev, "error: %i\n", retval);
aa69a809
DL		 1712}
1713
1714/**
1715 * isr_get_status_complete: get_status request complete function
1716 * @ep: endpoint
1717 * @req: request handled
1718 *
1719 * Caller must release lock
1720 */
1721static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
1722{
0f089094 1723 if (ep == NULL || req == NULL)
aa69a809 1724 return;
aa69a809
DL		 1725
1726 kfree(req->buf);
1727 usb_ep_free_request(ep, req);
1728}
1729
1730/**
1731 * isr_get_status_response: get_status request response
ca9cfea0 1732 * @udc: udc struct
aa69a809
DL		 1733 * @setup: setup request packet
1734 *
1735 * This function returns an error code
1736 */
ca9cfea0 1737static int isr_get_status_response(struct ci13xxx *udc,
aa69a809
DL		 1738 struct usb_ctrlrequest *setup)
1739__releases(mEp->lock)
1740__acquires(mEp->lock)
1741{
d36ade60 1742 struct ci13xxx_ep *mEp = udc->ep0in;
aa69a809
DL		 1743 struct usb_request *req = NULL;
1744 gfp_t gfp_flags = GFP_ATOMIC;
1745 int dir, num, retval;
1746
aa69a809
DL		 1747 if (mEp == NULL || setup == NULL)
1748 return -EINVAL;
1749
1750 spin_unlock(mEp->lock);
1751 req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
1752 spin_lock(mEp->lock);
1753 if (req == NULL)
1754 return -ENOMEM;
1755
1756 req->complete = isr_get_status_complete;
1757 req->length = 2;
1758 req->buf = kzalloc(req->length, gfp_flags);
1759 if (req->buf == NULL) {
1760 retval = -ENOMEM;
1761 goto err_free_req;
1762 }
1763
1764 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
e2b61c1d 1765 /* Assume that device is bus powered for now. */
1f339d84 1766 *(u16 *)req->buf = udc->remote_wakeup << 1;
aa69a809
DL		 1767 retval = 0;
1768 } else if ((setup->bRequestType & USB_RECIP_MASK) \
1769 == USB_RECIP_ENDPOINT) {
1770 dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
1771 TX : RX;
1772 num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
d3595d13 1773 *(u16 *)req->buf = hw_ep_get_halt(udc, num, dir);
aa69a809
DL		 1774 }
1775 /* else do nothing; reserved for future use */
1776
1777 spin_unlock(mEp->lock);
1778 retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
1779 spin_lock(mEp->lock);
1780 if (retval)
1781 goto err_free_buf;
1782
1783 return 0;
1784
1785 err_free_buf:
1786 kfree(req->buf);
1787 err_free_req:
1788 spin_unlock(mEp->lock);
1789 usb_ep_free_request(&mEp->ep, req);
1790 spin_lock(mEp->lock);
1791 return retval;
1792}
1793
541cace8
PK		 1794/**
1795 * isr_setup_status_complete: setup_status request complete function
1796 * @ep: endpoint
1797 * @req: request handled
1798 *
1799 * Caller must release lock. Put the port in test mode if test mode
1800 * feature is selected.
1801 */
1802static void
1803isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
1804{
1805 struct ci13xxx *udc = req->context;
1806 unsigned long flags;
1807
ef15e549
AS		 1808 if (udc->setaddr) {
1809 hw_usb_set_address(udc, udc->address);
1810 udc->setaddr = false;
1811 }
1812
d3595d13 1813 spin_lock_irqsave(&udc->lock, flags);
541cace8 1814 if (udc->test_mode)
d3595d13
AS		 1815 hw_port_test_set(udc, udc->test_mode);
1816 spin_unlock_irqrestore(&udc->lock, flags);
541cace8
PK		 1817}
1818
aa69a809
DL		 1819/**
1820 * isr_setup_status_phase: queues the status phase of a setup transation
ca9cfea0 1821 * @udc: udc struct
aa69a809
DL		 1822 *
1823 * This function returns an error code
1824 */
ca9cfea0 1825static int isr_setup_status_phase(struct ci13xxx *udc)
aa69a809
DL		 1826__releases(mEp->lock)
1827__acquires(mEp->lock)
1828{
1829 int retval;
ca9cfea0 1830 struct ci13xxx_ep *mEp;
aa69a809 1831
d36ade60 1832 mEp = (udc->ep0_dir == TX) ? udc->ep0out : udc->ep0in;
541cace8
PK		 1833 udc->status->context = udc;
1834 udc->status->complete = isr_setup_status_complete;
aa69a809
DL		 1835
1836 spin_unlock(mEp->lock);
ca9cfea0 1837 retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
aa69a809
DL		 1838 spin_lock(mEp->lock);
1839
1840 return retval;
1841}
1842
1843/**
1844 * isr_tr_complete_low: transaction complete low level handler
1845 * @mEp: endpoint
1846 *
1847 * This function returns an error code
1848 * Caller must hold lock
1849 */
1850static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
1851__releases(mEp->lock)
1852__acquires(mEp->lock)
1853{
0e6ca199 1854 struct ci13xxx_req *mReq, *mReqTemp;
76cd9cfb 1855 struct ci13xxx_ep *mEpTemp = mEp;
986b11b8 1856 int uninitialized_var(retval);
aa69a809 1857
ca9cfea0 1858 if (list_empty(&mEp->qh.queue))
aa69a809
DL		 1859 return -EINVAL;
1860
0e6ca199
PK		 1861 list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
1862 queue) {
1863 retval = _hardware_dequeue(mEp, mReq);
1864 if (retval < 0)
1865 break;
1866 list_del_init(&mReq->queue);
1867 dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
1868 if (mReq->req.complete != NULL) {
1869 spin_unlock(mEp->lock);
76cd9cfb
PK		 1870 if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
1871 mReq->req.length)
1f339d84 1872 mEpTemp = mEp->udc->ep0in;
76cd9cfb 1873 mReq->req.complete(&mEpTemp->ep, &mReq->req);
0e6ca199
PK		 1874 spin_lock(mEp->lock);
1875 }
d9bb9c18
AL		 1876 }
1877
ef907482 1878 if (retval == -EBUSY)
0e6ca199
PK		 1879 retval = 0;
1880 if (retval < 0)
1881 dbg_event(_usb_addr(mEp), "DONE", retval);
aa69a809 1882
aa69a809
DL		 1883 return retval;
1884}
1885
1886/**
1887 * isr_tr_complete_handler: transaction complete interrupt handler
1888 * @udc: UDC descriptor
1889 *
1890 * This function handles traffic events
1891 */
1892static void isr_tr_complete_handler(struct ci13xxx *udc)
1893__releases(udc->lock)
1894__acquires(udc->lock)
1895{
1896 unsigned i;
541cace8 1897 u8 tmode = 0;
aa69a809 1898
d3595d13 1899 for (i = 0; i < udc->hw_ep_max; i++) {
aa69a809 1900 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
4c5212b7 1901 int type, num, dir, err = -EINVAL;
aa69a809
DL		 1902 struct usb_ctrlrequest req;
1903
31fb6014 1904 if (mEp->ep.desc == NULL)
aa69a809
DL		 1905 continue; /* not configured */
1906
d3595d13 1907 if (hw_test_and_clear_complete(udc, i)) {
aa69a809
DL		 1908 err = isr_tr_complete_low(mEp);
1909 if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
1910 if (err > 0) /* needs status phase */
ca9cfea0 1911 err = isr_setup_status_phase(udc);
aa69a809
DL		 1912 if (err < 0) {
1913 dbg_event(_usb_addr(mEp),
1914 "ERROR", err);
d3595d13 1915 spin_unlock(&udc->lock);
aa69a809 1916 if (usb_ep_set_halt(&mEp->ep))
0f089094 1917 dev_err(udc->dev,
0917ba84 1918 "error: ep_set_halt\n");
d3595d13 1919 spin_lock(&udc->lock);
aa69a809
DL		 1920 }
1921 }
1922 }
1923
1924 if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
d3595d13 1925 !hw_test_and_clear_setup_status(udc, i))
aa69a809
DL		 1926 continue;
1927
1928 if (i != 0) {
0f089094 1929 dev_warn(udc->dev, "ctrl traffic at endpoint %d\n", i);
aa69a809
DL		 1930 continue;
1931 }
1932
ca9cfea0
PK		 1933 /*
1934 * Flush data and handshake transactions of previous
1935 * setup packet.
1936 */
d36ade60
AS		 1937 _ep_nuke(udc->ep0out);
1938 _ep_nuke(udc->ep0in);
ca9cfea0 1939
aa69a809
DL		 1940 /* read_setup_packet */
1941 do {
d3595d13 1942 hw_test_and_set_setup_guard(udc);
ca9cfea0 1943 memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
d3595d13 1944 } while (!hw_test_and_clear_setup_guard(udc));
aa69a809
DL		 1945
1946 type = req.bRequestType;
1947
ca9cfea0 1948 udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
aa69a809
DL		 1949
1950 dbg_setup(_usb_addr(mEp), &req);
1951
1952 switch (req.bRequest) {
1953 case USB_REQ_CLEAR_FEATURE:
e2b61c1d
PK		 1954 if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
1955 le16_to_cpu(req.wValue) ==
1956 USB_ENDPOINT_HALT) {
1957 if (req.wLength != 0)
1958 break;
1959 num = le16_to_cpu(req.wIndex);
4c5212b7 1960 dir = num & USB_ENDPOINT_DIR_MASK;
e2b61c1d 1961 num &= USB_ENDPOINT_NUMBER_MASK;
4c5212b7 1962 if (dir) /* TX */
d3595d13 1963 num += udc->hw_ep_max/2;
e2b61c1d 1964 if (!udc->ci13xxx_ep[num].wedge) {
d3595d13 1965 spin_unlock(&udc->lock);
e2b61c1d
PK		 1966 err = usb_ep_clear_halt(
1967 &udc->ci13xxx_ep[num].ep);
d3595d13 1968 spin_lock(&udc->lock);
e2b61c1d
PK		 1969 if (err)
1970 break;
1971 }
1972 err = isr_setup_status_phase(udc);
1973 } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
1974 le16_to_cpu(req.wValue) ==
1975 USB_DEVICE_REMOTE_WAKEUP) {
1976 if (req.wLength != 0)
aa69a809 1977 break;
e2b61c1d
PK		 1978 udc->remote_wakeup = 0;
1979 err = isr_setup_status_phase(udc);
1980 } else {
1981 goto delegate;
aa69a809 1982 }
aa69a809
DL		 1983 break;
1984 case USB_REQ_GET_STATUS:
1985 if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
1986 type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
1987 type != (USB_DIR_IN|USB_RECIP_INTERFACE))
1988 goto delegate;
1989 if (le16_to_cpu(req.wLength) != 2 ||
1990 le16_to_cpu(req.wValue) != 0)
1991 break;
ca9cfea0 1992 err = isr_get_status_response(udc, &req);
aa69a809
DL		 1993 break;
1994 case USB_REQ_SET_ADDRESS:
1995 if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
1996 goto delegate;
1997 if (le16_to_cpu(req.wLength) != 0 ||
1998 le16_to_cpu(req.wIndex) != 0)
1999 break;
ef15e549
AS		 2000 udc->address = (u8)le16_to_cpu(req.wValue);
2001 udc->setaddr = true;
ca9cfea0 2002 err = isr_setup_status_phase(udc);
aa69a809
DL		 2003 break;
2004 case USB_REQ_SET_FEATURE:
e2b61c1d
PK		 2005 if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
2006 le16_to_cpu(req.wValue) ==
2007 USB_ENDPOINT_HALT) {
2008 if (req.wLength != 0)
2009 break;
2010 num = le16_to_cpu(req.wIndex);
4c5212b7 2011 dir = num & USB_ENDPOINT_DIR_MASK;
e2b61c1d 2012 num &= USB_ENDPOINT_NUMBER_MASK;
4c5212b7 2013 if (dir) /* TX */
d3595d13 2014 num += udc->hw_ep_max/2;
aa69a809 2015
d3595d13 2016 spin_unlock(&udc->lock);
e2b61c1d 2017 err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
d3595d13 2018 spin_lock(&udc->lock);
e2b61c1d 2019 if (!err)
541cace8
PK		 2020 isr_setup_status_phase(udc);
2021 } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
e2b61c1d
PK		 2022 if (req.wLength != 0)
2023 break;
541cace8
PK		 2024 switch (le16_to_cpu(req.wValue)) {
2025 case USB_DEVICE_REMOTE_WAKEUP:
2026 udc->remote_wakeup = 1;
2027 err = isr_setup_status_phase(udc);
2028 break;
2029 case USB_DEVICE_TEST_MODE:
2030 tmode = le16_to_cpu(req.wIndex) >> 8;
2031 switch (tmode) {
2032 case TEST_J:
2033 case TEST_K:
2034 case TEST_SE0_NAK:
2035 case TEST_PACKET:
2036 case TEST_FORCE_EN:
2037 udc->test_mode = tmode;
2038 err = isr_setup_status_phase(
2039 udc);
2040 break;
2041 default:
2042 break;
2043 }
2044 default:
2045 goto delegate;
2046 }
e2b61c1d
PK		 2047 } else {
2048 goto delegate;
2049 }
aa69a809
DL		 2050 break;
2051 default:
2052delegate:
2053 if (req.wLength == 0) /* no data phase */
ca9cfea0 2054 udc->ep0_dir = TX;
aa69a809 2055
d3595d13 2056 spin_unlock(&udc->lock);
aa69a809 2057 err = udc->driver->setup(&udc->gadget, &req);
d3595d13 2058 spin_lock(&udc->lock);
aa69a809
DL		 2059 break;
2060 }
2061
2062 if (err < 0) {
2063 dbg_event(_usb_addr(mEp), "ERROR", err);
2064
d3595d13 2065 spin_unlock(&udc->lock);
aa69a809 2066 if (usb_ep_set_halt(&mEp->ep))
0f089094 2067 dev_err(udc->dev, "error: ep_set_halt\n");
d3595d13 2068 spin_lock(&udc->lock);
aa69a809
DL		 2069 }
2070 }
2071}
2072
2073/******************************************************************************
2074 * ENDPT block
2075 *****************************************************************************/
2076/**
2077 * ep_enable: configure endpoint, making it usable
2078 *
2079 * Check usb_ep_enable() at "usb_gadget.h" for details
2080 */
2081static int ep_enable(struct usb_ep *ep,
2082 const struct usb_endpoint_descriptor *desc)
2083{
2084 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
ca9cfea0 2085 int retval = 0;
aa69a809
DL		 2086 unsigned long flags;
2087
aa69a809
DL		 2088 if (ep == NULL || desc == NULL)
2089 return -EINVAL;
2090
2091 spin_lock_irqsave(mEp->lock, flags);
2092
2093 /* only internal SW should enable ctrl endpts */
2094
31fb6014 2095 mEp->ep.desc = desc;
aa69a809 2096
ca9cfea0 2097 if (!list_empty(&mEp->qh.queue))
0f089094 2098 dev_warn(mEp->udc->dev, "enabling a non-empty endpoint!\n");
aa69a809 2099
15739bb5
MK		 2100 mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
2101 mEp->num = usb_endpoint_num(desc);
2102 mEp->type = usb_endpoint_type(desc);
aa69a809 2103
29cc8897 2104 mEp->ep.maxpacket = usb_endpoint_maxp(desc);
aa69a809 2105
ca9cfea0 2106 dbg_event(_usb_addr(mEp), "ENABLE", 0);
aa69a809 2107
ca9cfea0 2108 mEp->qh.ptr->cap = 0;
aa69a809 2109
ca9cfea0
PK		 2110 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2111 mEp->qh.ptr->cap |= QH_IOS;
2112 else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
2113 mEp->qh.ptr->cap &= ~QH_MULT;
2114 else
2115 mEp->qh.ptr->cap &= ~QH_ZLT;
aa69a809 2116
ca9cfea0
PK		 2117 mEp->qh.ptr->cap |=
2118 (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
2119 mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
aa69a809 2120
ac1aa6a2
A		 2121 /*
2122 * Enable endpoints in the HW other than ep0 as ep0
2123 * is always enabled
2124 */
2125 if (mEp->num)
d3595d13 2126 retval |= hw_ep_enable(mEp->udc, mEp->num, mEp->dir, mEp->type);
aa69a809
DL		 2127
2128 spin_unlock_irqrestore(mEp->lock, flags);
2129 return retval;
2130}
2131
2132/**
2133 * ep_disable: endpoint is no longer usable
2134 *
2135 * Check usb_ep_disable() at "usb_gadget.h" for details
2136 */
2137static int ep_disable(struct usb_ep *ep)
2138{
2139 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2140 int direction, retval = 0;
2141 unsigned long flags;
2142
aa69a809
DL		 2143 if (ep == NULL)
2144 return -EINVAL;
31fb6014 2145 else if (mEp->ep.desc == NULL)
aa69a809
DL		 2146 return -EBUSY;
2147
2148 spin_lock_irqsave(mEp->lock, flags);
2149
2150 /* only internal SW should disable ctrl endpts */
2151
2152 direction = mEp->dir;
2153 do {
2154 dbg_event(_usb_addr(mEp), "DISABLE", 0);
2155
2156 retval |= _ep_nuke(mEp);
d3595d13 2157 retval |= hw_ep_disable(mEp->udc, mEp->num, mEp->dir);
aa69a809
DL		 2158
2159 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2160 mEp->dir = (mEp->dir == TX) ? RX : TX;
2161
2162 } while (mEp->dir != direction);
2163
f9c56cdd 2164 mEp->ep.desc = NULL;
aa69a809
DL		 2165
2166 spin_unlock_irqrestore(mEp->lock, flags);
2167 return retval;
2168}
2169
2170/**
2171 * ep_alloc_request: allocate a request object to use with this endpoint
2172 *
2173 * Check usb_ep_alloc_request() at "usb_gadget.h" for details
2174 */
2175static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
2176{
2177 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2178 struct ci13xxx_req *mReq = NULL;
aa69a809 2179
0f089094 2180 if (ep == NULL)
aa69a809 2181 return NULL;
aa69a809 2182
aa69a809
DL		 2183 mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
2184 if (mReq != NULL) {
2185 INIT_LIST_HEAD(&mReq->queue);
954aad8c 2186 mReq->req.dma = DMA_ADDR_INVALID;
aa69a809
DL		 2187
2188 mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
2189 &mReq->dma);
2190 if (mReq->ptr == NULL) {
2191 kfree(mReq);
2192 mReq = NULL;
2193 }
2194 }
2195
2196 dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
2197
aa69a809
DL		 2198 return (mReq == NULL) ? NULL : &mReq->req;
2199}
2200
2201/**
2202 * ep_free_request: frees a request object
2203 *
2204 * Check usb_ep_free_request() at "usb_gadget.h" for details
2205 */
2206static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
2207{
2208 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2209 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2210 unsigned long flags;
2211
aa69a809 2212 if (ep == NULL || req == NULL) {
aa69a809
DL		 2213 return;
2214 } else if (!list_empty(&mReq->queue)) {
0f089094 2215 dev_err(mEp->udc->dev, "freeing queued request\n");
aa69a809
DL		 2216 return;
2217 }
2218
2219 spin_lock_irqsave(mEp->lock, flags);
2220
2221 if (mReq->ptr)
2222 dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
2223 kfree(mReq);
2224
2225 dbg_event(_usb_addr(mEp), "FREE", 0);
2226
2227 spin_unlock_irqrestore(mEp->lock, flags);
2228}
2229
2230/**
2231 * ep_queue: queues (submits) an I/O request to an endpoint
2232 *
2233 * Check usb_ep_queue()* at usb_gadget.h" for details
2234 */
2235static int ep_queue(struct usb_ep *ep, struct usb_request *req,
2236 gfp_t __maybe_unused gfp_flags)
2237{
2238 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2239 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
1f339d84 2240 struct ci13xxx *udc = mEp->udc;
aa69a809
DL		 2241 int retval = 0;
2242 unsigned long flags;
2243
31fb6014 2244 if (ep == NULL || req == NULL || mEp->ep.desc == NULL)
aa69a809
DL		 2245 return -EINVAL;
2246
2247 spin_lock_irqsave(mEp->lock, flags);
2248
76cd9cfb
PK		 2249 if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
2250 if (req->length)
1f339d84
AS		 2251 mEp = (udc->ep0_dir == RX) ?
2252 udc->ep0out : udc->ep0in;
76cd9cfb
PK		 2253 if (!list_empty(&mEp->qh.queue)) {
2254 _ep_nuke(mEp);
2255 retval = -EOVERFLOW;
0f089094
AS		 2256 dev_warn(mEp->udc->dev, "endpoint ctrl %X nuked\n",
2257 _usb_addr(mEp));
76cd9cfb 2258 }
aa69a809
DL		 2259 }
2260
2261 /* first nuke then test link, e.g. previous status has not sent */
2262 if (!list_empty(&mReq->queue)) {
2263 retval = -EBUSY;
0f089094 2264 dev_err(mEp->udc->dev, "request already in queue\n");
aa69a809
DL		 2265 goto done;
2266 }
2267
1155a7b8
AS		 2268 if (req->length > 4 * CI13XXX_PAGE_SIZE) {
2269 req->length = 4 * CI13XXX_PAGE_SIZE;
aa69a809 2270 retval = -EMSGSIZE;
0f089094 2271 dev_warn(mEp->udc->dev, "request length truncated\n");
aa69a809
DL		 2272 }
2273
2274 dbg_queue(_usb_addr(mEp), req, retval);
2275
2276 /* push request */
2277 mReq->req.status = -EINPROGRESS;
2278 mReq->req.actual = 0;
aa69a809 2279
0e6ca199 2280 retval = _hardware_enqueue(mEp, mReq);
d9bb9c18
AL		 2281
2282 if (retval == -EALREADY) {
aa69a809
DL		 2283 dbg_event(_usb_addr(mEp), "QUEUE", retval);
2284 retval = 0;
2285 }
0e6ca199
PK		 2286 if (!retval)
2287 list_add_tail(&mReq->queue, &mEp->qh.queue);
aa69a809
DL		 2288
2289 done:
2290 spin_unlock_irqrestore(mEp->lock, flags);
2291 return retval;
2292}
2293
2294/**
2295 * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
2296 *
2297 * Check usb_ep_dequeue() at "usb_gadget.h" for details
2298 */
2299static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2300{
2301 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2302 struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
2303 unsigned long flags;
2304
0e6ca199 2305 if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
31fb6014 2306 mEp->ep.desc == NULL || list_empty(&mReq->queue) ||
0e6ca199 2307 list_empty(&mEp->qh.queue))
aa69a809
DL		 2308 return -EINVAL;
2309
2310 spin_lock_irqsave(mEp->lock, flags);
2311
2312 dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
2313
d3595d13 2314 hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
aa69a809
DL		 2315
2316 /* pop request */
2317 list_del_init(&mReq->queue);
0e6ca199
PK		 2318 if (mReq->map) {
2319 dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
2320 mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
954aad8c 2321 mReq->req.dma = DMA_ADDR_INVALID;
0e6ca199
PK		 2322 mReq->map = 0;
2323 }
aa69a809
DL		 2324 req->status = -ECONNRESET;
2325
7c25a826 2326 if (mReq->req.complete != NULL) {
aa69a809
DL		 2327 spin_unlock(mEp->lock);
2328 mReq->req.complete(&mEp->ep, &mReq->req);
2329 spin_lock(mEp->lock);
2330 }
2331
2332 spin_unlock_irqrestore(mEp->lock, flags);
2333 return 0;
2334}
2335
2336/**
2337 * ep_set_halt: sets the endpoint halt feature
2338 *
2339 * Check usb_ep_set_halt() at "usb_gadget.h" for details
2340 */
2341static int ep_set_halt(struct usb_ep *ep, int value)
2342{
2343 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2344 int direction, retval = 0;
2345 unsigned long flags;
2346
31fb6014 2347 if (ep == NULL || mEp->ep.desc == NULL)
aa69a809
DL		 2348 return -EINVAL;
2349
2350 spin_lock_irqsave(mEp->lock, flags);
2351
2352#ifndef STALL_IN
2353 /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
2354 if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
ca9cfea0 2355 !list_empty(&mEp->qh.queue)) {
aa69a809
DL		 2356 spin_unlock_irqrestore(mEp->lock, flags);
2357 return -EAGAIN;
2358 }
2359#endif
2360
2361 direction = mEp->dir;
2362 do {
2363 dbg_event(_usb_addr(mEp), "HALT", value);
d3595d13 2364 retval |= hw_ep_set_halt(mEp->udc, mEp->num, mEp->dir, value);
aa69a809
DL		 2365
2366 if (!value)
2367 mEp->wedge = 0;
2368
2369 if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
2370 mEp->dir = (mEp->dir == TX) ? RX : TX;
2371
2372 } while (mEp->dir != direction);
2373
2374 spin_unlock_irqrestore(mEp->lock, flags);
2375 return retval;
2376}
2377
2378/**
2379 * ep_set_wedge: sets the halt feature and ignores clear requests
2380 *
2381 * Check usb_ep_set_wedge() at "usb_gadget.h" for details
2382 */
2383static int ep_set_wedge(struct usb_ep *ep)
2384{
2385 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2386 unsigned long flags;
2387
31fb6014 2388 if (ep == NULL || mEp->ep.desc == NULL)
aa69a809
DL		 2389 return -EINVAL;
2390
2391 spin_lock_irqsave(mEp->lock, flags);
2392
2393 dbg_event(_usb_addr(mEp), "WEDGE", 0);
2394 mEp->wedge = 1;
2395
2396 spin_unlock_irqrestore(mEp->lock, flags);
2397
2398 return usb_ep_set_halt(ep);
2399}
2400
2401/**
2402 * ep_fifo_flush: flushes contents of a fifo
2403 *
2404 * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
2405 */
2406static void ep_fifo_flush(struct usb_ep *ep)
2407{
2408 struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
2409 unsigned long flags;
2410
aa69a809 2411 if (ep == NULL) {
0f089094 2412 dev_err(mEp->udc->dev, "%02X: -EINVAL\n", _usb_addr(mEp));
aa69a809
DL		 2413 return;
2414 }
2415
2416 spin_lock_irqsave(mEp->lock, flags);
2417
2418 dbg_event(_usb_addr(mEp), "FFLUSH", 0);
d3595d13 2419 hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
aa69a809
DL		 2420
2421 spin_unlock_irqrestore(mEp->lock, flags);
2422}
2423
2424/**
2425 * Endpoint-specific part of the API to the USB controller hardware
2426 * Check "usb_gadget.h" for details
2427 */
2428static const struct usb_ep_ops usb_ep_ops = {
2429 .enable = ep_enable,
2430 .disable = ep_disable,
2431 .alloc_request = ep_alloc_request,
2432 .free_request = ep_free_request,
2433 .queue = ep_queue,
2434 .dequeue = ep_dequeue,
2435 .set_halt = ep_set_halt,
2436 .set_wedge = ep_set_wedge,
2437 .fifo_flush = ep_fifo_flush,
2438};
2439
2440/******************************************************************************
2441 * GADGET block
2442 *****************************************************************************/
f01ef574
PK		 2443static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
2444{
2445 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
2446 unsigned long flags;
2447 int gadget_ready = 0;
2448
2449 if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
2450 return -EOPNOTSUPP;
2451
d3595d13 2452 spin_lock_irqsave(&udc->lock, flags);
f01ef574
PK		 2453 udc->vbus_active = is_active;
2454 if (udc->driver)
2455 gadget_ready = 1;
d3595d13 2456 spin_unlock_irqrestore(&udc->lock, flags);
f01ef574
PK		 2457
2458 if (gadget_ready) {
2459 if (is_active) {
c036019e 2460 pm_runtime_get_sync(&_gadget->dev);
f01ef574 2461 hw_device_reset(udc);
d3595d13 2462 hw_device_state(udc, udc->ep0out->qh.dma);
f01ef574 2463 } else {
d3595d13 2464 hw_device_state(udc, 0);
f01ef574
PK		 2465 if (udc->udc_driver->notify_event)
2466 udc->udc_driver->notify_event(udc,
2467 CI13XXX_CONTROLLER_STOPPED_EVENT);
2468 _gadget_stop_activity(&udc->gadget);
c036019e 2469 pm_runtime_put_sync(&_gadget->dev);
f01ef574
PK		 2470 }
2471 }
2472
2473 return 0;
2474}
2475
e2b61c1d
PK		 2476static int ci13xxx_wakeup(struct usb_gadget *_gadget)
2477{
2478 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
2479 unsigned long flags;
2480 int ret = 0;
2481
d3595d13 2482 spin_lock_irqsave(&udc->lock, flags);
e2b61c1d
PK		 2483 if (!udc->remote_wakeup) {
2484 ret = -EOPNOTSUPP;
e2b61c1d
PK		 2485 goto out;
2486 }
262c1632 2487 if (!hw_read(udc, OP_PORTSC, PORTSC_SUSP)) {
e2b61c1d 2488 ret = -EINVAL;
e2b61c1d
PK		 2489 goto out;
2490 }
262c1632 2491 hw_write(udc, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
e2b61c1d 2492out:
d3595d13 2493 spin_unlock_irqrestore(&udc->lock, flags);
e2b61c1d
PK		 2494 return ret;
2495}
2496
d860852e
PK		 2497static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
2498{
2499 struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
2500
2501 if (udc->transceiver)
b96d3b08 2502 return usb_phy_set_power(udc->transceiver, mA);
d860852e
PK		 2503 return -ENOTSUPP;
2504}
2505
1f339d84
AS		 2506static int ci13xxx_start(struct usb_gadget *gadget,
2507 struct usb_gadget_driver *driver);
2508static int ci13xxx_stop(struct usb_gadget *gadget,
2509 struct usb_gadget_driver *driver);
aa69a809
DL		 2510/**
2511 * Device operations part of the API to the USB controller hardware,
2512 * which don't involve endpoints (or i/o)
2513 * Check "usb_gadget.h" for details
2514 */
f01ef574
PK		 2515static const struct usb_gadget_ops usb_gadget_ops = {
2516 .vbus_session = ci13xxx_vbus_session,
e2b61c1d 2517 .wakeup = ci13xxx_wakeup,
d860852e 2518 .vbus_draw = ci13xxx_vbus_draw,
1f339d84
AS		 2519 .udc_start = ci13xxx_start,
2520 .udc_stop = ci13xxx_stop,
f01ef574 2521};
aa69a809 2522
790c2d52 2523static int init_eps(struct ci13xxx *udc)
aa69a809 2524{
790c2d52 2525 int retval = 0, i, j;
aa69a809 2526
790c2d52 2527 for (i = 0; i < udc->hw_ep_max/2; i++)
ca9cfea0 2528 for (j = RX; j <= TX; j++) {
d3595d13 2529 int k = i + j * udc->hw_ep_max/2;
ca9cfea0 2530 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
aa69a809 2531
ca9cfea0
PK		 2532 scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
2533 (j == TX) ? "in" : "out");
aa69a809 2534
d3595d13
AS		 2535 mEp->udc = udc;
2536 mEp->lock = &udc->lock;
ca9cfea0
PK		 2537 mEp->device = &udc->gadget.dev;
2538 mEp->td_pool = udc->td_pool;
aa69a809 2539
ca9cfea0
PK		 2540 mEp->ep.name = mEp->name;
2541 mEp->ep.ops = &usb_ep_ops;
2542 mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
aa69a809 2543
ca9cfea0 2544 INIT_LIST_HEAD(&mEp->qh.queue);
ca9cfea0 2545 mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
790c2d52 2546 &mEp->qh.dma);
ca9cfea0 2547 if (mEp->qh.ptr == NULL)
aa69a809
DL		 2548 retval = -ENOMEM;
2549 else
ca9cfea0
PK		 2550 memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
2551
d36ade60
AS		 2552 /*
2553 * set up shorthands for ep0 out and in endpoints,
2554 * don't add to gadget's ep_list
2555 */
2556 if (i == 0) {
2557 if (j == RX)
2558 udc->ep0out = mEp;
2559 else
2560 udc->ep0in = mEp;
2561
ca9cfea0 2562 continue;
d36ade60 2563 }
ca9cfea0 2564
aa69a809 2565 list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
ca9cfea0 2566 }
790c2d52
AS		 2567
2568 return retval;
2569}
2570
2571/**
2572 * ci13xxx_start: register a gadget driver
1f339d84 2573 * @gadget: our gadget
790c2d52 2574 * @driver: the driver being registered
790c2d52 2575 *
790c2d52
AS		 2576 * Interrupts are enabled here.
2577 */
1f339d84
AS		 2578static int ci13xxx_start(struct usb_gadget *gadget,
2579 struct usb_gadget_driver *driver)
790c2d52 2580{
1f339d84 2581 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
790c2d52 2582 unsigned long flags;
790c2d52
AS		 2583 int retval = -ENOMEM;
2584
1f339d84 2585 if (driver->disconnect == NULL)
790c2d52 2586 return -EINVAL;
790c2d52 2587
790c2d52 2588
d36ade60
AS		 2589 udc->ep0out->ep.desc = &ctrl_endpt_out_desc;
2590 retval = usb_ep_enable(&udc->ep0out->ep);
ac1aa6a2
A		 2591 if (retval)
2592 return retval;
877c1f54 2593
d36ade60
AS		 2594 udc->ep0in->ep.desc = &ctrl_endpt_in_desc;
2595 retval = usb_ep_enable(&udc->ep0in->ep);
ac1aa6a2
A		 2596 if (retval)
2597 return retval;
d3595d13 2598 spin_lock_irqsave(&udc->lock, flags);
aa69a809 2599
49d3df53 2600 udc->driver = driver;
c036019e 2601 pm_runtime_get_sync(&udc->gadget.dev);
f01ef574
PK		 2602 if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
2603 if (udc->vbus_active) {
2604 if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
2605 hw_device_reset(udc);
2606 } else {
c036019e 2607 pm_runtime_put_sync(&udc->gadget.dev);
f01ef574
PK		 2608 goto done;
2609 }
2610 }
2611
d3595d13 2612 retval = hw_device_state(udc, udc->ep0out->qh.dma);
c036019e
PK		 2613 if (retval)
2614 pm_runtime_put_sync(&udc->gadget.dev);
aa69a809
DL		 2615
2616 done:
d3595d13 2617 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809
DL		 2618 return retval;
2619}
aa69a809
DL		 2620
2621/**
0f91349b 2622 * ci13xxx_stop: unregister a gadget driver
aa69a809 2623 */
1f339d84
AS		 2624static int ci13xxx_stop(struct usb_gadget *gadget,
2625 struct usb_gadget_driver *driver)
aa69a809 2626{
1f339d84
AS		 2627 struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
2628 unsigned long flags;
aa69a809 2629
d3595d13 2630 spin_lock_irqsave(&udc->lock, flags);
aa69a809 2631
f01ef574
PK		 2632 if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
2633 udc->vbus_active) {
d3595d13 2634 hw_device_state(udc, 0);
f01ef574
PK		 2635 if (udc->udc_driver->notify_event)
2636 udc->udc_driver->notify_event(udc,
2637 CI13XXX_CONTROLLER_STOPPED_EVENT);
1f339d84 2638 udc->driver = NULL;
d3595d13 2639 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809 2640 _gadget_stop_activity(&udc->gadget);
d3595d13 2641 spin_lock_irqsave(&udc->lock, flags);
c036019e 2642 pm_runtime_put(&udc->gadget.dev);
f01ef574 2643 }
aa69a809 2644
d3595d13 2645 spin_unlock_irqrestore(&udc->lock, flags);
aa69a809 2646
aa69a809
DL		 2647 return 0;
2648}
aa69a809
DL		 2649
2650/******************************************************************************
2651 * BUS block
2652 *****************************************************************************/
2653/**
2654 * udc_irq: global interrupt handler
2655 *
2656 * This function returns IRQ_HANDLED if the IRQ has been handled
2657 * It locks access to registers
2658 */
62bb84ed 2659static irqreturn_t udc_irq(int irq, void *data)
aa69a809 2660{
1f339d84 2661 struct ci13xxx *udc = data;
aa69a809
DL		 2662 irqreturn_t retval;
2663 u32 intr;
2664
f639554b 2665 if (udc == NULL)
aa69a809 2666 return IRQ_HANDLED;
aa69a809 2667
d3595d13 2668 spin_lock(&udc->lock);
f01ef574
PK		 2669
2670 if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
262c1632
AS		 2671 if (hw_read(udc, OP_USBMODE, USBMODE_CM) !=
2672 USBMODE_CM_DEVICE) {
d3595d13 2673 spin_unlock(&udc->lock);
f01ef574
PK		 2674 return IRQ_NONE;
2675 }
2676 }
d3595d13 2677 intr = hw_test_and_clear_intr_active(udc);
aa69a809
DL		 2678 if (intr) {
2679 isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
2680 isr_statistics.hndl.idx &= ISR_MASK;
2681 isr_statistics.hndl.cnt++;
2682
2683 /* order defines priority - do NOT change it */
2684 if (USBi_URI & intr) {
2685 isr_statistics.uri++;
2686 isr_reset_handler(udc);
2687 }
2688 if (USBi_PCI & intr) {
2689 isr_statistics.pci++;
d3595d13 2690 udc->gadget.speed = hw_port_is_high_speed(udc) ?
aa69a809 2691 USB_SPEED_HIGH : USB_SPEED_FULL;
7bb4fdc6 2692 if (udc->suspended && udc->driver->resume) {
d3595d13 2693 spin_unlock(&udc->lock);
e2b61c1d 2694 udc->driver->resume(&udc->gadget);
d3595d13 2695 spin_lock(&udc->lock);
e2b61c1d
PK		 2696 udc->suspended = 0;
2697 }
aa69a809
DL		 2698 }
2699 if (USBi_UEI & intr)
2700 isr_statistics.uei++;
2701 if (USBi_UI & intr) {
2702 isr_statistics.ui++;
2703 isr_tr_complete_handler(udc);
2704 }
e2b61c1d 2705 if (USBi_SLI & intr) {
7bb4fdc6
MKB		 2706 if (udc->gadget.speed != USB_SPEED_UNKNOWN &&
2707 udc->driver->suspend) {
e2b61c1d 2708 udc->suspended = 1;
d3595d13 2709 spin_unlock(&udc->lock);
e2b61c1d 2710 udc->driver->suspend(&udc->gadget);
d3595d13 2711 spin_lock(&udc->lock);
e2b61c1d 2712 }
aa69a809 2713 isr_statistics.sli++;
e2b61c1d 2714 }
aa69a809
DL		 2715 retval = IRQ_HANDLED;
2716 } else {
2717 isr_statistics.none++;
2718 retval = IRQ_NONE;
2719 }
d3595d13 2720 spin_unlock(&udc->lock);
aa69a809
DL		 2721
2722 return retval;
2723}
2724
2725/**
2726 * udc_release: driver release function
2727 * @dev: device
2728 *
2729 * Currently does nothing
2730 */
2731static void udc_release(struct device *dev)
2732{
aa69a809
DL		 2733}
2734
2735/**
2736 * udc_probe: parent probe must call this to initialize UDC
2737 * @dev: parent device
2738 * @regs: registers base address
2739 * @name: driver name
2740 *
2741 * This function returns an error code
2742 * No interrupts active, the IRQ has not been requested yet
2743 * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
2744 */
f01ef574 2745static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
1f339d84 2746 void __iomem *regs, struct ci13xxx **_udc)
aa69a809
DL		 2747{
2748 struct ci13xxx *udc;
2749 int retval = 0;
2750
f01ef574
PK		 2751 if (dev == NULL || regs == NULL || driver == NULL ||
2752 driver->name == NULL)
aa69a809
DL		 2753 return -EINVAL;
2754
2755 udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
2756 if (udc == NULL)
2757 return -ENOMEM;
2758
d3595d13 2759 spin_lock_init(&udc->lock);
f01ef574
PK		 2760 udc->regs = regs;
2761 udc->udc_driver = driver;
aa69a809 2762
f01ef574 2763 udc->gadget.ops = &usb_gadget_ops;
aa69a809 2764 udc->gadget.speed = USB_SPEED_UNKNOWN;
d327ab5b 2765 udc->gadget.max_speed = USB_SPEED_HIGH;
aa69a809 2766 udc->gadget.is_otg = 0;
f01ef574 2767 udc->gadget.name = driver->name;
aa69a809
DL		 2768
2769 INIT_LIST_HEAD(&udc->gadget.ep_list);
aa69a809 2770
5df58524 2771 dev_set_name(&udc->gadget.dev, "gadget");
aa69a809 2772 udc->gadget.dev.dma_mask = dev->dma_mask;
61948ee4 2773 udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
aa69a809
DL		 2774 udc->gadget.dev.parent = dev;
2775 udc->gadget.dev.release = udc_release;
2776
0f089094
AS		 2777 udc->dev = dev;
2778
790c2d52
AS		 2779 /* alloc resources */
2780 udc->qh_pool = dma_pool_create("ci13xxx_qh", dev,
2781 sizeof(struct ci13xxx_qh),
2782 64, CI13XXX_PAGE_SIZE);
2783 if (udc->qh_pool == NULL) {
2784 retval = -ENOMEM;
2785 goto free_udc;
2786 }
2787
2788 udc->td_pool = dma_pool_create("ci13xxx_td", dev,
2789 sizeof(struct ci13xxx_td),
2790 64, CI13XXX_PAGE_SIZE);
2791 if (udc->td_pool == NULL) {
2792 retval = -ENOMEM;
2793 goto free_qh_pool;
2794 }
2795
62bb84ed 2796 retval = hw_device_init(udc, regs, driver->capoffset);
f01ef574 2797 if (retval < 0)
790c2d52
AS		 2798 goto free_pools;
2799
2800 retval = init_eps(udc);
2801 if (retval)
2802 goto free_pools;
2803
2804 udc->gadget.ep0 = &udc->ep0in->ep;
f01ef574 2805
b96d3b08 2806 udc->transceiver = usb_get_transceiver();
f01ef574
PK		 2807
2808 if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
2809 if (udc->transceiver == NULL) {
2810 retval = -ENODEV;
790c2d52 2811 goto free_pools;
f01ef574
PK		 2812 }
2813 }
2814
2815 if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
2816 retval = hw_device_reset(udc);
2817 if (retval)
2818 goto put_transceiver;
2819 }
2820
aa69a809 2821 retval = device_register(&udc->gadget.dev);
f01ef574
PK		 2822 if (retval) {
2823 put_device(&udc->gadget.dev);
2824 goto put_transceiver;
2825 }
aa69a809
DL		 2826
2827#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2828 retval = dbg_create_files(&udc->gadget.dev);
2829#endif
f01ef574
PK		 2830 if (retval)
2831 goto unreg_device;
2832
2833 if (udc->transceiver) {
6e13c650
HK		 2834 retval = otg_set_peripheral(udc->transceiver->otg,
2835 &udc->gadget);
f01ef574
PK		 2836 if (retval)
2837 goto remove_dbg;
aa69a809 2838 }
0f91349b
SAS		 2839
2840 retval = usb_add_gadget_udc(dev, &udc->gadget);
2841 if (retval)
2842 goto remove_trans;
2843
c036019e
PK		 2844 pm_runtime_no_callbacks(&udc->gadget.dev);
2845 pm_runtime_enable(&udc->gadget.dev);
aa69a809 2846
1f339d84 2847 *_udc = udc;
aa69a809
DL		 2848 return retval;
2849
0f91349b
SAS		 2850remove_trans:
2851 if (udc->transceiver) {
6e13c650 2852 otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
b96d3b08 2853 usb_put_transceiver(udc->transceiver);
0f91349b
SAS		 2854 }
2855
0917ba84 2856 dev_err(dev, "error = %i\n", retval);
f01ef574
PK		 2857remove_dbg:
2858#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2859 dbg_remove_files(&udc->gadget.dev);
2860#endif
2861unreg_device:
2862 device_unregister(&udc->gadget.dev);
2863put_transceiver:
2864 if (udc->transceiver)
b96d3b08 2865 usb_put_transceiver(udc->transceiver);
790c2d52
AS		 2866free_pools:
2867 dma_pool_destroy(udc->td_pool);
2868free_qh_pool:
2869 dma_pool_destroy(udc->qh_pool);
f01ef574 2870free_udc:
aa69a809 2871 kfree(udc);
1f339d84 2872 *_udc = NULL;
aa69a809
DL		 2873 return retval;
2874}
2875
2876/**
2877 * udc_remove: parent remove must call this to remove UDC
2878 *
2879 * No interrupts active, the IRQ has been released
2880 */
1f339d84 2881static void udc_remove(struct ci13xxx *udc)
aa69a809 2882{
790c2d52 2883 int i;
aa69a809 2884
0f089094 2885 if (udc == NULL)
aa69a809 2886 return;
0f089094 2887
0f91349b 2888 usb_del_gadget_udc(&udc->gadget);
aa69a809 2889
790c2d52
AS		 2890 for (i = 0; i < udc->hw_ep_max; i++) {
2891 struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
2892
2893 dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
2894 }
2895
2896 dma_pool_destroy(udc->td_pool);
2897 dma_pool_destroy(udc->qh_pool);
2898
f01ef574 2899 if (udc->transceiver) {
6e13c650 2900 otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
b96d3b08 2901 usb_put_transceiver(udc->transceiver);
f01ef574 2902 }
aa69a809
DL		 2903#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2904 dbg_remove_files(&udc->gadget.dev);
2905#endif
2906 device_unregister(&udc->gadget.dev);
2907
262c1632 2908 kfree(udc->hw_bank.regmap);
aa69a809 2909 kfree(udc);
aa69a809 2910}
62bb84ed
AS		 2911
2912static int __devinit ci_udc_probe(struct platform_device *pdev)
2913{
2914 struct device *dev = &pdev->dev;
2915 struct ci13xxx_udc_driver *driver = dev->platform_data;
1f339d84 2916 struct ci13xxx *udc;
62bb84ed
AS		 2917 struct resource *res;
2918 void __iomem *base;
2919 int ret;
2920
2921 if (!driver) {
2922 dev_err(dev, "platform data missing\n");
2923 return -ENODEV;
2924 }
2925
2926 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2927 if (!res) {
2928 dev_err(dev, "missing resource\n");
2929 return -ENODEV;
2930 }
2931
2932 base = devm_request_and_ioremap(dev, res);
2933 if (!res) {
2934 dev_err(dev, "can't request and ioremap resource\n");
2935 return -ENOMEM;
2936 }
2937
1f339d84 2938 ret = udc_probe(driver, dev, base, &udc);
62bb84ed
AS		 2939 if (ret)
2940 return ret;
2941
1f339d84
AS		 2942 udc->irq = platform_get_irq(pdev, 0);
2943 if (udc->irq < 0) {
62bb84ed
AS		 2944 dev_err(dev, "missing IRQ\n");
2945 ret = -ENODEV;
2946 goto out;
2947 }
2948
1f339d84
AS		 2949 platform_set_drvdata(pdev, udc);
2950 ret = request_irq(udc->irq, udc_irq, IRQF_SHARED, driver->name, udc);
62bb84ed
AS		 2951
2952out:
2953 if (ret)
1f339d84 2954 udc_remove(udc);
62bb84ed
AS		 2955
2956 return ret;
2957}
2958
2959static int __devexit ci_udc_remove(struct platform_device *pdev)
2960{
1f339d84
AS		 2961 struct ci13xxx *udc = platform_get_drvdata(pdev);
2962
2963 free_irq(udc->irq, udc);
2964 udc_remove(udc);
62bb84ed
AS		 2965
2966 return 0;
2967}
2968
2969static struct platform_driver ci_udc_driver = {
2970 .probe = ci_udc_probe,
2971 .remove = __devexit_p(ci_udc_remove),
2972 .driver = {
2973 .name = "ci_udc",
2974 },
2975};
2976
2977module_platform_driver(ci_udc_driver);
2978
2979MODULE_ALIAS("platform:ci_udc");
2980MODULE_ALIAS("platform:ci13xxx");
2981MODULE_LICENSE("GPL v2");
2982MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
2983MODULE_DESCRIPTION("ChipIdea UDC Driver");
kernel source for telekom puls (alcatel/mediatek)