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tty: remove use of __devinitconst
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / xilinx_uartps.c
CommitLineData
61ec9016
JL		 1/*
2 * Xilinx PS UART driver
3 *
4 * 2011 (c) Xilinx Inc.
5 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
11 *
12 */
13
14#include <linux/platform_device.h>
ee160a38 15#include <linux/serial.h>
61ec9016 16#include <linux/serial_core.h>
ee160a38
JS		 17#include <linux/tty.h>
18#include <linux/tty_flip.h>
61ec9016 19#include <linux/console.h>
61ec9016
JL		 20#include <linux/irq.h>
21#include <linux/io.h>
22#include <linux/of.h>
578b9ce0 23#include <linux/module.h>
61ec9016
JL		 24
25#define XUARTPS_TTY_NAME "ttyPS"
26#define XUARTPS_NAME "xuartps"
27#define XUARTPS_MAJOR 0 /* use dynamic node allocation */
28#define XUARTPS_MINOR 0 /* works best with devtmpfs */
29#define XUARTPS_NR_PORTS 2
30#define XUARTPS_FIFO_SIZE 16 /* FIFO size */
31#define XUARTPS_REGISTER_SPACE 0xFFF
32
33#define xuartps_readl(offset) ioread32(port->membase + offset)
34#define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
35
36/********************************Register Map********************************/
37/** UART
38 *
39 * Register offsets for the UART.
40 *
41 */
42#define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */
43#define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */
44#define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
45#define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
46#define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
47#define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
48#define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
49#define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
50#define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
51#define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
52#define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
53#define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */
54#define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
55#define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
56#define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
57#define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse
58 Width [15:0] */
59#define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse
60 Width [7:0] */
61#define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */
62
63/** Control Register
64 *
65 * The Control register (CR) controls the major functions of the device.
66 *
67 * Control Register Bit Definitions
68 */
69#define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
70#define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
71#define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
72#define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
73#define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
74#define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
75#define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
76#define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
77#define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
78
79/** Mode Register
80 *
81 * The mode register (MR) defines the mode of transfer as well as the data
82 * format. If this register is modified during transmission or reception,
83 * data validity cannot be guaranteed.
84 *
85 * Mode Register Bit Definitions
86 *
87 */
88#define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
89#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
90#define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */
91
92#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
93#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
94
95#define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */
96#define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
97#define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
98#define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
99#define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
100
101#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
102#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
103#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
104
105/** Interrupt Registers
106 *
107 * Interrupt control logic uses the interrupt enable register (IER) and the
108 * interrupt disable register (IDR) to set the value of the bits in the
109 * interrupt mask register (IMR). The IMR determines whether to pass an
110 * interrupt to the interrupt status register (ISR).
111 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
112 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
113 * Reading either IER or IDR returns 0x00.
114 *
115 * All four registers have the same bit definitions.
116 */
117#define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
118#define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */
119#define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */
120#define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
121#define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
122#define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
123#define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
124#define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
125#define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
126#define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
127#define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */
128
129/** Channel Status Register
130 *
131 * The channel status register (CSR) is provided to enable the control logic
132 * to monitor the status of bits in the channel interrupt status register,
133 * even if these are masked out by the interrupt mask register.
134 */
135#define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
136#define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
137#define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
138#define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
139
140/**
141 * xuartps_isr - Interrupt handler
142 * @irq: Irq number
143 * @dev_id: Id of the port
144 *
145 * Returns IRQHANDLED
146 **/
147static irqreturn_t xuartps_isr(int irq, void *dev_id)
148{
149 struct uart_port *port = (struct uart_port *)dev_id;
150 struct tty_struct *tty;
151 unsigned long flags;
152 unsigned int isrstatus, numbytes;
153 unsigned int data;
154 char status = TTY_NORMAL;
155
156 /* Get the tty which could be NULL so don't assume it's valid */
157 tty = tty_port_tty_get(&port->state->port);
158
159 spin_lock_irqsave(&port->lock, flags);
160
161 /* Read the interrupt status register to determine which
162 * interrupt(s) is/are active.
163 */
164 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET);
165
166 /* drop byte with parity error if IGNPAR specified */
167 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY)
168 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT);
169
170 isrstatus &= port->read_status_mask;
171 isrstatus &= ~port->ignore_status_mask;
172
173 if ((isrstatus & XUARTPS_IXR_TOUT) ||
174 (isrstatus & XUARTPS_IXR_RXTRIG)) {
175 /* Receive Timeout Interrupt */
176 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
177 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
178 data = xuartps_readl(XUARTPS_FIFO_OFFSET);
179 port->icount.rx++;
180
181 if (isrstatus & XUARTPS_IXR_PARITY) {
182 port->icount.parity++;
183 status = TTY_PARITY;
184 } else if (isrstatus & XUARTPS_IXR_FRAMING) {
185 port->icount.frame++;
186 status = TTY_FRAME;
187 } else if (isrstatus & XUARTPS_IXR_OVERRUN)
188 port->icount.overrun++;
189
190 if (tty)
191 uart_insert_char(port, isrstatus,
192 XUARTPS_IXR_OVERRUN, data,
193 status);
194 }
195 spin_unlock(&port->lock);
196 if (tty)
197 tty_flip_buffer_push(tty);
198 spin_lock(&port->lock);
199 }
200
201 /* Dispatch an appropriate handler */
202 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) {
203 if (uart_circ_empty(&port->state->xmit)) {
204 xuartps_writel(XUARTPS_IXR_TXEMPTY,
205 XUARTPS_IDR_OFFSET);
206 } else {
207 numbytes = port->fifosize;
208 /* Break if no more data available in the UART buffer */
209 while (numbytes--) {
210 if (uart_circ_empty(&port->state->xmit))
211 break;
212 /* Get the data from the UART circular buffer
213 * and write it to the xuartps's TX_FIFO
214 * register.
215 */
216 xuartps_writel(
217 port->state->xmit.buf[port->state->xmit.
218 tail], XUARTPS_FIFO_OFFSET);
219
220 port->icount.tx++;
221
222 /* Adjust the tail of the UART buffer and wrap
223 * the buffer if it reaches limit.
224 */
225 port->state->xmit.tail =
226 (port->state->xmit.tail + 1) & \
227 (UART_XMIT_SIZE - 1);
228 }
229
230 if (uart_circ_chars_pending(
231 &port->state->xmit) < WAKEUP_CHARS)
232 uart_write_wakeup(port);
233 }
234 }
235
236 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET);
237
238 /* be sure to release the lock and tty before leaving */
239 spin_unlock_irqrestore(&port->lock, flags);
240 tty_kref_put(tty);
241
242 return IRQ_HANDLED;
243}
244
245/**
246 * xuartps_set_baud_rate - Calculate and set the baud rate
247 * @port: Handle to the uart port structure
248 * @baud: Baud rate to set
249 *
250 * Returns baud rate, requested baud when possible, or actual baud when there
251 * was too much error
252 **/
253static unsigned int xuartps_set_baud_rate(struct uart_port *port,
254 unsigned int baud)
255{
256 unsigned int sel_clk;
257 unsigned int calc_baud = 0;
258 unsigned int brgr_val, brdiv_val;
259 unsigned int bauderror;
260
261 /* Formula to obtain baud rate is
262 * baud_tx/rx rate = sel_clk/CD * (BDIV + 1)
263 * input_clk = (Uart User Defined Clock or Apb Clock)
264 * depends on UCLKEN in MR Reg
265 * sel_clk = input_clk or input_clk/8;
266 * depends on CLKS in MR reg
267 * CD and BDIV depends on values in
268 * baud rate generate register
269 * baud rate clock divisor register
270 */
271 sel_clk = port->uartclk;
272 if (xuartps_readl(XUARTPS_MR_OFFSET) & XUARTPS_MR_CLKSEL)
273 sel_clk = sel_clk / 8;
274
275 /* Find the best values for baud generation */
276 for (brdiv_val = 4; brdiv_val < 255; brdiv_val++) {
277
278 brgr_val = sel_clk / (baud * (brdiv_val + 1));
279 if (brgr_val < 2 || brgr_val > 65535)
280 continue;
281
282 calc_baud = sel_clk / (brgr_val * (brdiv_val + 1));
283
284 if (baud > calc_baud)
285 bauderror = baud - calc_baud;
286 else
287 bauderror = calc_baud - baud;
288
289 /* use the values when percent error is acceptable */
290 if (((bauderror * 100) / baud) < 3) {
291 calc_baud = baud;
292 break;
293 }
294 }
295
296 /* Set the values for the new baud rate */
297 xuartps_writel(brgr_val, XUARTPS_BAUDGEN_OFFSET);
298 xuartps_writel(brdiv_val, XUARTPS_BAUDDIV_OFFSET);
299
300 return calc_baud;
301}
302
303/*----------------------Uart Operations---------------------------*/
304
305/**
306 * xuartps_start_tx - Start transmitting bytes
307 * @port: Handle to the uart port structure
308 *
309 **/
310static void xuartps_start_tx(struct uart_port *port)
311{
312 unsigned int status, numbytes = port->fifosize;
313
314 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
315 return;
316
317 status = xuartps_readl(XUARTPS_CR_OFFSET);
318 /* Set the TX enable bit and clear the TX disable bit to enable the
319 * transmitter.
320 */
321 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
322 XUARTPS_CR_OFFSET);
323
324 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
325 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
326
327 /* Break if no more data available in the UART buffer */
328 if (uart_circ_empty(&port->state->xmit))
329 break;
330
331 /* Get the data from the UART circular buffer and
332 * write it to the xuartps's TX_FIFO register.
333 */
334 xuartps_writel(
335 port->state->xmit.buf[port->state->xmit.tail],
336 XUARTPS_FIFO_OFFSET);
337 port->icount.tx++;
338
339 /* Adjust the tail of the UART buffer and wrap
340 * the buffer if it reaches limit.
341 */
342 port->state->xmit.tail = (port->state->xmit.tail + 1) &
343 (UART_XMIT_SIZE - 1);
344 }
345
346 /* Enable the TX Empty interrupt */
347 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET);
348
349 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
350 uart_write_wakeup(port);
351}
352
353/**
354 * xuartps_stop_tx - Stop TX
355 * @port: Handle to the uart port structure
356 *
357 **/
358static void xuartps_stop_tx(struct uart_port *port)
359{
360 unsigned int regval;
361
362 regval = xuartps_readl(XUARTPS_CR_OFFSET);
363 regval |= XUARTPS_CR_TX_DIS;
364 /* Disable the transmitter */
365 xuartps_writel(regval, XUARTPS_CR_OFFSET);
366}
367
368/**
369 * xuartps_stop_rx - Stop RX
370 * @port: Handle to the uart port structure
371 *
372 **/
373static void xuartps_stop_rx(struct uart_port *port)
374{
375 unsigned int regval;
376
377 regval = xuartps_readl(XUARTPS_CR_OFFSET);
378 regval |= XUARTPS_CR_RX_DIS;
379 /* Disable the receiver */
380 xuartps_writel(regval, XUARTPS_CR_OFFSET);
381}
382
383/**
384 * xuartps_tx_empty - Check whether TX is empty
385 * @port: Handle to the uart port structure
386 *
387 * Returns TIOCSER_TEMT on success, 0 otherwise
388 **/
389static unsigned int xuartps_tx_empty(struct uart_port *port)
390{
391 unsigned int status;
392
393 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY;
394 return status ? TIOCSER_TEMT : 0;
395}
396
397/**
398 * xuartps_break_ctl - Based on the input ctl we have to start or stop
399 * transmitting char breaks
400 * @port: Handle to the uart port structure
401 * @ctl: Value based on which start or stop decision is taken
402 *
403 **/
404static void xuartps_break_ctl(struct uart_port *port, int ctl)
405{
406 unsigned int status;
407 unsigned long flags;
408
409 spin_lock_irqsave(&port->lock, flags);
410
411 status = xuartps_readl(XUARTPS_CR_OFFSET);
412
413 if (ctl == -1)
414 xuartps_writel(XUARTPS_CR_STARTBRK | status,
415 XUARTPS_CR_OFFSET);
416 else {
417 if ((status & XUARTPS_CR_STOPBRK) == 0)
418 xuartps_writel(XUARTPS_CR_STOPBRK | status,
419 XUARTPS_CR_OFFSET);
420 }
421 spin_unlock_irqrestore(&port->lock, flags);
422}
423
424/**
425 * xuartps_set_termios - termios operations, handling data length, parity,
426 * stop bits, flow control, baud rate
427 * @port: Handle to the uart port structure
428 * @termios: Handle to the input termios structure
429 * @old: Values of the previously saved termios structure
430 *
431 **/
432static void xuartps_set_termios(struct uart_port *port,
433 struct ktermios *termios, struct ktermios *old)
434{
435 unsigned int cval = 0;
436 unsigned int baud;
437 unsigned long flags;
438 unsigned int ctrl_reg, mode_reg;
439
440 spin_lock_irqsave(&port->lock, flags);
441
442 /* Empty the receive FIFO 1st before making changes */
443 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
444 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
445 xuartps_readl(XUARTPS_FIFO_OFFSET);
446 }
447
448 /* Disable the TX and RX to set baud rate */
449 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
450 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
451 XUARTPS_CR_OFFSET);
452
453 /* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk */
454 baud = uart_get_baud_rate(port, termios, old, 0, 10000000);
455 baud = xuartps_set_baud_rate(port, baud);
456 if (tty_termios_baud_rate(termios))
457 tty_termios_encode_baud_rate(termios, baud, baud);
458
459 /*
460 * Update the per-port timeout.
461 */
462 uart_update_timeout(port, termios->c_cflag, baud);
463
464 /* Set TX/RX Reset */
465 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
466 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
467 XUARTPS_CR_OFFSET);
468
469 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
470
471 /* Clear the RX disable and TX disable bits and then set the TX enable
472 * bit and RX enable bit to enable the transmitter and receiver.
473 */
474 xuartps_writel(
475 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
476 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
477 XUARTPS_CR_OFFSET);
478
479 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET);
480
481 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG |
482 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT;
483 port->ignore_status_mask = 0;
484
485 if (termios->c_iflag & INPCK)
486 port->read_status_mask |= XUARTPS_IXR_PARITY |
487 XUARTPS_IXR_FRAMING;
488
489 if (termios->c_iflag & IGNPAR)
490 port->ignore_status_mask |= XUARTPS_IXR_PARITY |
491 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
492
493 /* ignore all characters if CREAD is not set */
494 if ((termios->c_cflag & CREAD) == 0)
495 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG |
496 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY |
497 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
498
499 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET);
500
501 /* Handling Data Size */
502 switch (termios->c_cflag & CSIZE) {
503 case CS6:
504 cval |= XUARTPS_MR_CHARLEN_6_BIT;
505 break;
506 case CS7:
507 cval |= XUARTPS_MR_CHARLEN_7_BIT;
508 break;
509 default:
510 case CS8:
511 cval |= XUARTPS_MR_CHARLEN_8_BIT;
512 termios->c_cflag &= ~CSIZE;
513 termios->c_cflag |= CS8;
514 break;
515 }
516
517 /* Handling Parity and Stop Bits length */
518 if (termios->c_cflag & CSTOPB)
519 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */
520 else
521 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */
522
523 if (termios->c_cflag & PARENB) {
524 /* Mark or Space parity */
525 if (termios->c_cflag & CMSPAR) {
526 if (termios->c_cflag & PARODD)
527 cval |= XUARTPS_MR_PARITY_MARK;
528 else
529 cval |= XUARTPS_MR_PARITY_SPACE;
530 } else if (termios->c_cflag & PARODD)
531 cval |= XUARTPS_MR_PARITY_ODD;
532 else
533 cval |= XUARTPS_MR_PARITY_EVEN;
534 } else
535 cval |= XUARTPS_MR_PARITY_NONE;
536 xuartps_writel(cval , XUARTPS_MR_OFFSET);
537
538 spin_unlock_irqrestore(&port->lock, flags);
539}
540
541/**
542 * xuartps_startup - Called when an application opens a xuartps port
543 * @port: Handle to the uart port structure
544 *
545 * Returns 0 on success, negative error otherwise
546 **/
547static int xuartps_startup(struct uart_port *port)
548{
549 unsigned int retval = 0, status = 0;
550
551 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME,
552 (void *)port);
553 if (retval)
554 return retval;
555
556 /* Disable the TX and RX */
557 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
558 XUARTPS_CR_OFFSET);
559
560 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
561 * no break chars.
562 */
563 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST,
564 XUARTPS_CR_OFFSET);
565
566 status = xuartps_readl(XUARTPS_CR_OFFSET);
567
568 /* Clear the RX disable and TX disable bits and then set the TX enable
569 * bit and RX enable bit to enable the transmitter and receiver.
570 */
571 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
572 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN |
573 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET);
574
575 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
576 * no parity.
577 */
578 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT
579 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT,
580 XUARTPS_MR_OFFSET);
581
582 /* Set the RX FIFO Trigger level to 14 assuming FIFO size as 16 */
583 xuartps_writel(14, XUARTPS_RXWM_OFFSET);
584
585 /* Receive Timeout register is enabled with value of 10 */
586 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET);
587
588
589 /* Set the Interrupt Registers with desired interrupts */
590 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
591 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
592 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
593 xuartps_writel(~(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
594 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
595 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT), XUARTPS_IDR_OFFSET);
596
597 return retval;
598}
599
600/**
601 * xuartps_shutdown - Called when an application closes a xuartps port
602 * @port: Handle to the uart port structure
603 *
604 **/
605static void xuartps_shutdown(struct uart_port *port)
606{
607 int status;
608
609 /* Disable interrupts */
610 status = xuartps_readl(XUARTPS_IMR_OFFSET);
611 xuartps_writel(status, XUARTPS_IDR_OFFSET);
612
613 /* Disable the TX and RX */
614 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
615 XUARTPS_CR_OFFSET);
616 free_irq(port->irq, port);
617}
618
619/**
620 * xuartps_type - Set UART type to xuartps port
621 * @port: Handle to the uart port structure
622 *
623 * Returns string on success, NULL otherwise
624 **/
625static const char *xuartps_type(struct uart_port *port)
626{
627 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL;
628}
629
630/**
631 * xuartps_verify_port - Verify the port params
632 * @port: Handle to the uart port structure
633 * @ser: Handle to the structure whose members are compared
634 *
635 * Returns 0 if success otherwise -EINVAL
636 **/
637static int xuartps_verify_port(struct uart_port *port,
638 struct serial_struct *ser)
639{
640 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
641 return -EINVAL;
642 if (port->irq != ser->irq)
643 return -EINVAL;
644 if (ser->io_type != UPIO_MEM)
645 return -EINVAL;
646 if (port->iobase != ser->port)
647 return -EINVAL;
648 if (ser->hub6 != 0)
649 return -EINVAL;
650 return 0;
651}
652
653/**
654 * xuartps_request_port - Claim the memory region attached to xuartps port,
655 * called when the driver adds a xuartps port via
656 * uart_add_one_port()
657 * @port: Handle to the uart port structure
658 *
659 * Returns 0, -ENOMEM if request fails
660 **/
661static int xuartps_request_port(struct uart_port *port)
662{
663 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE,
664 XUARTPS_NAME)) {
665 return -ENOMEM;
666 }
667
668 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE);
669 if (!port->membase) {
670 dev_err(port->dev, "Unable to map registers\n");
671 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
672 return -ENOMEM;
673 }
674 return 0;
675}
676
677/**
678 * xuartps_release_port - Release the memory region attached to a xuartps
679 * port, called when the driver removes a xuartps
680 * port via uart_remove_one_port().
681 * @port: Handle to the uart port structure
682 *
683 **/
684static void xuartps_release_port(struct uart_port *port)
685{
686 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
687 iounmap(port->membase);
688 port->membase = NULL;
689}
690
691/**
692 * xuartps_config_port - Configure xuartps, called when the driver adds a
693 * xuartps port
694 * @port: Handle to the uart port structure
695 * @flags: If any
696 *
697 **/
698static void xuartps_config_port(struct uart_port *port, int flags)
699{
700 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0)
701 port->type = PORT_XUARTPS;
702}
703
704/**
705 * xuartps_get_mctrl - Get the modem control state
706 *
707 * @port: Handle to the uart port structure
708 *
709 * Returns the modem control state
710 *
711 **/
712static unsigned int xuartps_get_mctrl(struct uart_port *port)
713{
714 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
715}
716
717static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl)
718{
719 /* N/A */
720}
721
722static void xuartps_enable_ms(struct uart_port *port)
723{
724 /* N/A */
725}
726
727/** The UART operations structure
728 */
729static struct uart_ops xuartps_ops = {
730 .set_mctrl = xuartps_set_mctrl,
731 .get_mctrl = xuartps_get_mctrl,
732 .enable_ms = xuartps_enable_ms,
733
734 .start_tx = xuartps_start_tx, /* Start transmitting */
735 .stop_tx = xuartps_stop_tx, /* Stop transmission */
736 .stop_rx = xuartps_stop_rx, /* Stop reception */
737 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */
738 .break_ctl = xuartps_break_ctl, /* Start/stop
739 * transmitting break
740 */
741 .set_termios = xuartps_set_termios, /* Set termios */
742 .startup = xuartps_startup, /* App opens xuartps */
743 .shutdown = xuartps_shutdown, /* App closes xuartps */
744 .type = xuartps_type, /* Set UART type */
745 .verify_port = xuartps_verify_port, /* Verification of port
746 * params
747 */
748 .request_port = xuartps_request_port, /* Claim resources
749 * associated with a
750 * xuartps port
751 */
752 .release_port = xuartps_release_port, /* Release resources
753 * associated with a
754 * xuartps port
755 */
756 .config_port = xuartps_config_port, /* Configure when driver
757 * adds a xuartps port
758 */
759};
760
761static struct uart_port xuartps_port[2];
762
763/**
764 * xuartps_get_port - Configure the port from the platform device resource
765 * info
766 *
767 * Returns a pointer to a uart_port or NULL for failure
768 **/
769static struct uart_port *xuartps_get_port(void)
770{
771 struct uart_port *port;
772 int id;
773
774 /* Find the next unused port */
775 for (id = 0; id < XUARTPS_NR_PORTS; id++)
776 if (xuartps_port[id].mapbase == 0)
777 break;
778
779 if (id >= XUARTPS_NR_PORTS)
780 return NULL;
781
782 port = &xuartps_port[id];
783
784 /* At this point, we've got an empty uart_port struct, initialize it */
785 spin_lock_init(&port->lock);
786 port->membase = NULL;
787 port->iobase = 1; /* mark port in use */
788 port->irq = 0;
789 port->type = PORT_UNKNOWN;
790 port->iotype = UPIO_MEM32;
791 port->flags = UPF_BOOT_AUTOCONF;
792 port->ops = &xuartps_ops;
793 port->fifosize = XUARTPS_FIFO_SIZE;
794 port->line = id;
795 port->dev = NULL;
796 return port;
797}
798
799/*-----------------------Console driver operations--------------------------*/
800
801#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
802/**
803 * xuartps_console_wait_tx - Wait for the TX to be full
804 * @port: Handle to the uart port structure
805 *
806 **/
807static void xuartps_console_wait_tx(struct uart_port *port)
808{
809 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)
810 != XUARTPS_SR_TXEMPTY)
811 barrier();
812}
813
814/**
815 * xuartps_console_putchar - write the character to the FIFO buffer
816 * @port: Handle to the uart port structure
817 * @ch: Character to be written
818 *
819 **/
820static void xuartps_console_putchar(struct uart_port *port, int ch)
821{
822 xuartps_console_wait_tx(port);
823 xuartps_writel(ch, XUARTPS_FIFO_OFFSET);
824}
825
826/**
827 * xuartps_console_write - perform write operation
828 * @port: Handle to the uart port structure
829 * @s: Pointer to character array
830 * @count: No of characters
831 **/
832static void xuartps_console_write(struct console *co, const char *s,
833 unsigned int count)
834{
835 struct uart_port *port = &xuartps_port[co->index];
836 unsigned long flags;
837 unsigned int imr;
838 int locked = 1;
839
840 if (oops_in_progress)
841 locked = spin_trylock_irqsave(&port->lock, flags);
842 else
843 spin_lock_irqsave(&port->lock, flags);
844
845 /* save and disable interrupt */
846 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
847 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
848
849 uart_console_write(port, s, count, xuartps_console_putchar);
850 xuartps_console_wait_tx(port);
851
852 /* restore interrupt state, it seems like there may be a h/w bug
853 * in that the interrupt enable register should not need to be
854 * written based on the data sheet
855 */
856 xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
857 xuartps_writel(imr, XUARTPS_IER_OFFSET);
858
859 if (locked)
860 spin_unlock_irqrestore(&port->lock, flags);
861}
862
863/**
864 * xuartps_console_setup - Initialize the uart to default config
865 * @co: Console handle
866 * @options: Initial settings of uart
867 *
868 * Returns 0, -ENODEV if no device
869 **/
870static int __init xuartps_console_setup(struct console *co, char *options)
871{
872 struct uart_port *port = &xuartps_port[co->index];
873 int baud = 9600;
874 int bits = 8;
875 int parity = 'n';
876 int flow = 'n';
877
878 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS)
879 return -EINVAL;
880
881 if (!port->mapbase) {
882 pr_debug("console on ttyPS%i not present\n", co->index);
883 return -ENODEV;
884 }
885
886 if (options)
887 uart_parse_options(options, &baud, &parity, &bits, &flow);
888
889 return uart_set_options(port, co, baud, parity, bits, flow);
890}
891
892static struct uart_driver xuartps_uart_driver;
893
894static struct console xuartps_console = {
895 .name = XUARTPS_TTY_NAME,
896 .write = xuartps_console_write,
897 .device = uart_console_device,
898 .setup = xuartps_console_setup,
899 .flags = CON_PRINTBUFFER,
900 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
901 .data = &xuartps_uart_driver,
902};
903
904/**
905 * xuartps_console_init - Initialization call
906 *
907 * Returns 0 on success, negative error otherwise
908 **/
909static int __init xuartps_console_init(void)
910{
911 register_console(&xuartps_console);
912 return 0;
913}
914
915console_initcall(xuartps_console_init);
916
917#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
918
919/** Structure Definitions
920 */
921static struct uart_driver xuartps_uart_driver = {
922 .owner = THIS_MODULE, /* Owner */
923 .driver_name = XUARTPS_NAME, /* Driver name */
924 .dev_name = XUARTPS_TTY_NAME, /* Node name */
925 .major = XUARTPS_MAJOR, /* Major number */
926 .minor = XUARTPS_MINOR, /* Minor number */
927 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */
928#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
929 .cons = &xuartps_console, /* Console */
930#endif
931};
932
933/* ---------------------------------------------------------------------
934 * Platform bus binding
935 */
936/**
937 * xuartps_probe - Platform driver probe
938 * @pdev: Pointer to the platform device structure
939 *
940 * Returns 0 on success, negative error otherwise
941 **/
9671f099 942static int xuartps_probe(struct platform_device *pdev)
61ec9016
JL		 943{
944 int rc;
945 struct uart_port *port;
946 struct resource *res, *res2;
947 int clk = 0;
948
61ec9016
JL		 949 const unsigned int *prop;
950
951 prop = of_get_property(pdev->dev.of_node, "clock", NULL);
952 if (prop)
953 clk = be32_to_cpup(prop);
61ec9016
JL		 954 if (!clk) {
955 dev_err(&pdev->dev, "no clock specified\n");
956 return -ENODEV;
957 }
958
959 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
960 if (!res)
961 return -ENODEV;
962
963 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
964 if (!res2)
965 return -ENODEV;
966
967 /* Initialize the port structure */
968 port = xuartps_get_port();
969
970 if (!port) {
971 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
972 return -ENODEV;
973 } else {
974 /* Register the port.
975 * This function also registers this device with the tty layer
976 * and triggers invocation of the config_port() entry point.
977 */
978 port->mapbase = res->start;
979 port->irq = res2->start;
980 port->dev = &pdev->dev;
981 port->uartclk = clk;
982 dev_set_drvdata(&pdev->dev, port);
983 rc = uart_add_one_port(&xuartps_uart_driver, port);
984 if (rc) {
985 dev_err(&pdev->dev,
986 "uart_add_one_port() failed; err=%i\n", rc);
987 dev_set_drvdata(&pdev->dev, NULL);
988 return rc;
989 }
990 return 0;
991 }
992}
993
994/**
995 * xuartps_remove - called when the platform driver is unregistered
996 * @pdev: Pointer to the platform device structure
997 *
998 * Returns 0 on success, negative error otherwise
999 **/
1000static int __devexit xuartps_remove(struct platform_device *pdev)
1001{
1002 struct uart_port *port = dev_get_drvdata(&pdev->dev);
1003 int rc = 0;
1004
1005 /* Remove the xuartps port from the serial core */
1006 if (port) {
1007 rc = uart_remove_one_port(&xuartps_uart_driver, port);
1008 dev_set_drvdata(&pdev->dev, NULL);
1009 port->mapbase = 0;
1010 }
1011 return rc;
1012}
1013
1014/**
1015 * xuartps_suspend - suspend event
1016 * @pdev: Pointer to the platform device structure
1017 * @state: State of the device
1018 *
1019 * Returns 0
1020 **/
1021static int xuartps_suspend(struct platform_device *pdev, pm_message_t state)
1022{
1023 /* Call the API provided in serial_core.c file which handles
1024 * the suspend.
1025 */
1026 uart_suspend_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
1027 return 0;
1028}
1029
1030/**
1031 * xuartps_resume - Resume after a previous suspend
1032 * @pdev: Pointer to the platform device structure
1033 *
1034 * Returns 0
1035 **/
1036static int xuartps_resume(struct platform_device *pdev)
1037{
1038 uart_resume_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
1039 return 0;
1040}
1041
1042/* Match table for of_platform binding */
de88b340 1043static struct of_device_id xuartps_of_match[] = {
61ec9016
JL		 1044 { .compatible = "xlnx,xuartps", },
1045 {}
1046};
1047MODULE_DEVICE_TABLE(of, xuartps_of_match);
61ec9016
JL		 1048
1049static struct platform_driver xuartps_platform_driver = {
1050 .probe = xuartps_probe, /* Probe method */
1051 .remove = __exit_p(xuartps_remove), /* Detach method */
1052 .suspend = xuartps_suspend, /* Suspend */
1053 .resume = xuartps_resume, /* Resume after a suspend */
1054 .driver = {
1055 .owner = THIS_MODULE,
1056 .name = XUARTPS_NAME, /* Driver name */
1057 .of_match_table = xuartps_of_match,
1058 },
1059};
1060
1061/* ---------------------------------------------------------------------
1062 * Module Init and Exit
1063 */
1064/**
1065 * xuartps_init - Initial driver registration call
1066 *
1067 * Returns whether the registration was successful or not
1068 **/
1069static int __init xuartps_init(void)
1070{
1071 int retval = 0;
1072
1073 /* Register the xuartps driver with the serial core */
1074 retval = uart_register_driver(&xuartps_uart_driver);
1075 if (retval)
1076 return retval;
1077
1078 /* Register the platform driver */
1079 retval = platform_driver_register(&xuartps_platform_driver);
1080 if (retval)
1081 uart_unregister_driver(&xuartps_uart_driver);
1082
1083 return retval;
1084}
1085
1086/**
1087 * xuartps_exit - Driver unregistration call
1088 **/
1089static void __exit xuartps_exit(void)
1090{
1091 /* The order of unregistration is important. Unregister the
1092 * UART driver before the platform driver crashes the system.
1093 */
1094
1095 /* Unregister the platform driver */
1096 platform_driver_unregister(&xuartps_platform_driver);
1097
1098 /* Unregister the xuartps driver */
1099 uart_unregister_driver(&xuartps_uart_driver);
1100}
1101
1102module_init(xuartps_init);
1103module_exit(xuartps_exit);
1104
1105MODULE_DESCRIPTION("Driver for PS UART");
1106MODULE_AUTHOR("Xilinx Inc.");
1107MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)