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TTY: switch tty_flip_buffer_push
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / sunsu.c
CommitLineData
d87a6d95 1/*
1da177e4
LT		 2 * su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998-1999 Pete Zaitcev (zaitcev@yahoo.com)
6 *
7 * This is mainly a variation of 8250.c, credits go to authors mentioned
8 * therein. In fact this driver should be merged into the generic 8250.c
9 * infrastructure perhaps using a 8250_sparc.c module.
10 *
11 * Fixed to use tty_get_baud_rate().
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Converted to new 2.5.x UART layer.
9efc3715 15 * David S. Miller (davem@davemloft.net), 2002-Jul-29
1da177e4
LT		 16 */
17
1da177e4
LT		 18#include <linux/module.h>
19#include <linux/kernel.h>
1da177e4
LT		 20#include <linux/spinlock.h>
21#include <linux/errno.h>
22#include <linux/tty.h>
23#include <linux/tty_flip.h>
24#include <linux/major.h>
25#include <linux/string.h>
26#include <linux/ptrace.h>
27#include <linux/ioport.h>
28#include <linux/circ_buf.h>
29#include <linux/serial.h>
30#include <linux/sysrq.h>
31#include <linux/console.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#ifdef CONFIG_SERIO
34#include <linux/serio.h>
35#endif
36#include <linux/serial_reg.h>
37#include <linux/init.h>
38#include <linux/delay.h>
c6ed413d 39#include <linux/of_device.h>
1da177e4
LT		 40
41#include <asm/io.h>
42#include <asm/irq.h>
1708d242 43#include <asm/prom.h>
d550bbd4 44#include <asm/setup.h>
1da177e4
LT		 45
46#if defined(CONFIG_SERIAL_SUNSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
47#define SUPPORT_SYSRQ
48#endif
49
50#include <linux/serial_core.h>
6816383a 51#include <linux/sunserialcore.h>
1da177e4
LT		 52
53/* We are on a NS PC87303 clocked with 24.0 MHz, which results
54 * in a UART clock of 1.8462 MHz.
55 */
56#define SU_BASE_BAUD (1846200 / 16)
57
58enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT };
59static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" };
60
4b71598b
PG		 61struct serial_uart_config {
62 char *name;
63 int dfl_xmit_fifo_size;
64 int flags;
65};
66
1da177e4
LT		 67/*
68 * Here we define the default xmit fifo size used for each type of UART.
69 */
e2c65425 70static const struct serial_uart_config uart_config[] = {
1da177e4
LT		 71 { "unknown", 1, 0 },
72 { "8250", 1, 0 },
73 { "16450", 1, 0 },
74 { "16550", 1, 0 },
75 { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
76 { "Cirrus", 1, 0 },
77 { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
78 { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
79 { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO },
80 { "Startech", 1, 0 },
81 { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO },
82 { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
83 { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
84 { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO }
85};
86
87struct uart_sunsu_port {
88 struct uart_port port;
89 unsigned char acr;
90 unsigned char ier;
91 unsigned short rev;
92 unsigned char lcr;
93 unsigned int lsr_break_flag;
94 unsigned int cflag;
95
96 /* Probing information. */
97 enum su_type su_type;
98 unsigned int type_probed; /* XXX Stupid */
1708d242 99 unsigned long reg_size;
1da177e4
LT		 100
101#ifdef CONFIG_SERIO
1708d242 102 struct serio serio;
1da177e4
LT		 103 int serio_open;
104#endif
105};
106
41c28ff1 107static unsigned int serial_in(struct uart_sunsu_port *up, int offset)
1da177e4
LT		 108{
109 offset <<= up->port.regshift;
110
111 switch (up->port.iotype) {
9b4a1617 112 case UPIO_HUB6:
1da177e4
LT		 113 outb(up->port.hub6 - 1 + offset, up->port.iobase);
114 return inb(up->port.iobase + 1);
115
9b4a1617 116 case UPIO_MEM:
1da177e4
LT		 117 return readb(up->port.membase + offset);
118
119 default:
120 return inb(up->port.iobase + offset);
121 }
122}
123
41c28ff1 124static void serial_out(struct uart_sunsu_port *up, int offset, int value)
1da177e4
LT		 125{
126#ifndef CONFIG_SPARC64
127 /*
128 * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are
129 * connected with a gate then go to SlavIO. When IRQ4 goes tristated
130 * gate outputs a logical one. Since we use level triggered interrupts
131 * we have lockup and watchdog reset. We cannot mask IRQ because
132 * keyboard shares IRQ with us (Word has it as Bob Smelik's design).
133 * This problem is similar to what Alpha people suffer, see serial.c.
134 */
135 if (offset == UART_MCR)
136 value |= UART_MCR_OUT2;
137#endif
138 offset <<= up->port.regshift;
139
140 switch (up->port.iotype) {
9b4a1617 141 case UPIO_HUB6:
1da177e4
LT		 142 outb(up->port.hub6 - 1 + offset, up->port.iobase);
143 outb(value, up->port.iobase + 1);
144 break;
145
9b4a1617 146 case UPIO_MEM:
1da177e4
LT		 147 writeb(value, up->port.membase + offset);
148 break;
149
150 default:
151 outb(value, up->port.iobase + offset);
152 }
153}
154
155/*
156 * We used to support using pause I/O for certain machines. We
157 * haven't supported this for a while, but just in case it's badly
158 * needed for certain old 386 machines, I've left these #define's
159 * in....
160 */
161#define serial_inp(up, offset) serial_in(up, offset)
162#define serial_outp(up, offset, value) serial_out(up, offset, value)
163
164
165/*
166 * For the 16C950
167 */
168static void serial_icr_write(struct uart_sunsu_port *up, int offset, int value)
169{
170 serial_out(up, UART_SCR, offset);
171 serial_out(up, UART_ICR, value);
172}
173
174#if 0 /* Unused currently */
175static unsigned int serial_icr_read(struct uart_sunsu_port *up, int offset)
176{
177 unsigned int value;
178
179 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
180 serial_out(up, UART_SCR, offset);
181 value = serial_in(up, UART_ICR);
182 serial_icr_write(up, UART_ACR, up->acr);
183
184 return value;
185}
186#endif
187
188#ifdef CONFIG_SERIAL_8250_RSA
189/*
190 * Attempts to turn on the RSA FIFO. Returns zero on failure.
191 * We set the port uart clock rate if we succeed.
192 */
193static int __enable_rsa(struct uart_sunsu_port *up)
194{
195 unsigned char mode;
196 int result;
197
198 mode = serial_inp(up, UART_RSA_MSR);
199 result = mode & UART_RSA_MSR_FIFO;
200
201 if (!result) {
202 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
203 mode = serial_inp(up, UART_RSA_MSR);
204 result = mode & UART_RSA_MSR_FIFO;
205 }
206
207 if (result)
208 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
209
210 return result;
211}
212
213static void enable_rsa(struct uart_sunsu_port *up)
214{
215 if (up->port.type == PORT_RSA) {
216 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
217 spin_lock_irq(&up->port.lock);
218 __enable_rsa(up);
219 spin_unlock_irq(&up->port.lock);
220 }
221 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
222 serial_outp(up, UART_RSA_FRR, 0);
223 }
224}
225
226/*
227 * Attempts to turn off the RSA FIFO. Returns zero on failure.
228 * It is unknown why interrupts were disabled in here. However,
229 * the caller is expected to preserve this behaviour by grabbing
230 * the spinlock before calling this function.
231 */
232static void disable_rsa(struct uart_sunsu_port *up)
233{
234 unsigned char mode;
235 int result;
236
237 if (up->port.type == PORT_RSA &&
238 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
239 spin_lock_irq(&up->port.lock);
240
241 mode = serial_inp(up, UART_RSA_MSR);
242 result = !(mode & UART_RSA_MSR_FIFO);
243
244 if (!result) {
245 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
246 mode = serial_inp(up, UART_RSA_MSR);
247 result = !(mode & UART_RSA_MSR_FIFO);
248 }
249
250 if (result)
251 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
252 spin_unlock_irq(&up->port.lock);
253 }
254}
255#endif /* CONFIG_SERIAL_8250_RSA */
256
b129a8cc
RK		 257static inline void __stop_tx(struct uart_sunsu_port *p)
258{
259 if (p->ier & UART_IER_THRI) {
260 p->ier &= ~UART_IER_THRI;
261 serial_out(p, UART_IER, p->ier);
262 }
263}
264
265static void sunsu_stop_tx(struct uart_port *port)
1da177e4
LT		 266{
267 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
268
b129a8cc
RK		 269 __stop_tx(up);
270
3d9c9948
AV		 271 /*
272 * We really want to stop the transmitter from sending.
273 */
274 if (up->port.type == PORT_16C950) {
1da177e4
LT		 275 up->acr |= UART_ACR_TXDIS;
276 serial_icr_write(up, UART_ACR, up->acr);
277 }
278}
279
b129a8cc 280static void sunsu_start_tx(struct uart_port *port)
1da177e4
LT		 281{
282 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
283
284 if (!(up->ier & UART_IER_THRI)) {
285 up->ier |= UART_IER_THRI;
286 serial_out(up, UART_IER, up->ier);
287 }
3d9c9948 288
1da177e4 289 /*
3d9c9948 290 * Re-enable the transmitter if we disabled it.
1da177e4 291 */
3d9c9948 292 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 293 up->acr &= ~UART_ACR_TXDIS;
294 serial_icr_write(up, UART_ACR, up->acr);
295 }
296}
297
298static void sunsu_stop_rx(struct uart_port *port)
299{
300 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
1da177e4 301
1da177e4
LT		 302 up->ier &= ~UART_IER_RLSI;
303 up->port.read_status_mask &= ~UART_LSR_DR;
304 serial_out(up, UART_IER, up->ier);
1da177e4
LT		 305}
306
307static void sunsu_enable_ms(struct uart_port *port)
308{
309 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
310 unsigned long flags;
311
312 spin_lock_irqsave(&up->port.lock, flags);
313 up->ier |= UART_IER_MSI;
314 serial_out(up, UART_IER, up->ier);
315 spin_unlock_irqrestore(&up->port.lock, flags);
316}
317
2e124b4a 318static void
7d12e780 319receive_chars(struct uart_sunsu_port *up, unsigned char *status)
1da177e4 320{
92a19f9c 321 struct tty_port *port = &up->port.state->port;
33f0f88f 322 unsigned char ch, flag;
1da177e4
LT		 323 int max_count = 256;
324 int saw_console_brk = 0;
325
326 do {
1da177e4 327 ch = serial_inp(up, UART_RX);
33f0f88f 328 flag = TTY_NORMAL;
1da177e4
LT		 329 up->port.icount.rx++;
330
331 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
332 UART_LSR_FE | UART_LSR_OE))) {
333 /*
334 * For statistics only
335 */
336 if (*status & UART_LSR_BI) {
337 *status &= ~(UART_LSR_FE | UART_LSR_PE);
338 up->port.icount.brk++;
339 if (up->port.cons != NULL &&
340 up->port.line == up->port.cons->index)
341 saw_console_brk = 1;
342 /*
343 * We do the SysRQ and SAK checking
344 * here because otherwise the break
345 * may get masked by ignore_status_mask
346 * or read_status_mask.
347 */
348 if (uart_handle_break(&up->port))
349 goto ignore_char;
350 } else if (*status & UART_LSR_PE)
351 up->port.icount.parity++;
352 else if (*status & UART_LSR_FE)
353 up->port.icount.frame++;
354 if (*status & UART_LSR_OE)
355 up->port.icount.overrun++;
356
357 /*
358 * Mask off conditions which should be ingored.
359 */
360 *status &= up->port.read_status_mask;
361
362 if (up->port.cons != NULL &&
363 up->port.line == up->port.cons->index) {
364 /* Recover the break flag from console xmit */
365 *status |= up->lsr_break_flag;
366 up->lsr_break_flag = 0;
367 }
368
369 if (*status & UART_LSR_BI) {
33f0f88f 370 flag = TTY_BREAK;
1da177e4 371 } else if (*status & UART_LSR_PE)
33f0f88f 372 flag = TTY_PARITY;
1da177e4 373 else if (*status & UART_LSR_FE)
33f0f88f 374 flag = TTY_FRAME;
1da177e4 375 }
7d12e780 376 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 377 goto ignore_char;
33f0f88f 378 if ((*status & up->port.ignore_status_mask) == 0)
92a19f9c 379 tty_insert_flip_char(port, ch, flag);
33f0f88f 380 if (*status & UART_LSR_OE)
1da177e4
LT		 381 /*
382 * Overrun is special, since it's reported
383 * immediately, and doesn't affect the current
384 * character.
385 */
92a19f9c 386 tty_insert_flip_char(port, 0, TTY_OVERRUN);
1da177e4
LT		 387 ignore_char:
388 *status = serial_inp(up, UART_LSR);
389 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
390
391 if (saw_console_brk)
392 sun_do_break();
1da177e4
LT		 393}
394
41c28ff1 395static void transmit_chars(struct uart_sunsu_port *up)
1da177e4 396{
ebd2c8f6 397 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 398 int count;
399
400 if (up->port.x_char) {
401 serial_outp(up, UART_TX, up->port.x_char);
402 up->port.icount.tx++;
403 up->port.x_char = 0;
404 return;
405 }
b129a8cc
RK		 406 if (uart_tx_stopped(&up->port)) {
407 sunsu_stop_tx(&up->port);
408 return;
409 }
410 if (uart_circ_empty(xmit)) {
411 __stop_tx(up);
1da177e4
LT		 412 return;
413 }
414
415 count = up->port.fifosize;
416 do {
417 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
418 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
419 up->port.icount.tx++;
420 if (uart_circ_empty(xmit))
421 break;
422 } while (--count > 0);
423
424 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
425 uart_write_wakeup(&up->port);
426
427 if (uart_circ_empty(xmit))
b129a8cc 428 __stop_tx(up);
1da177e4
LT		 429}
430
41c28ff1 431static void check_modem_status(struct uart_sunsu_port *up)
1da177e4
LT		 432{
433 int status;
434
435 status = serial_in(up, UART_MSR);
436
437 if ((status & UART_MSR_ANY_DELTA) == 0)
438 return;
439
440 if (status & UART_MSR_TERI)
441 up->port.icount.rng++;
442 if (status & UART_MSR_DDSR)
443 up->port.icount.dsr++;
444 if (status & UART_MSR_DDCD)
445 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
446 if (status & UART_MSR_DCTS)
447 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
448
bdc04e31 449 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1da177e4
LT		 450}
451
7d12e780 452static irqreturn_t sunsu_serial_interrupt(int irq, void *dev_id)
1da177e4
LT		 453{
454 struct uart_sunsu_port *up = dev_id;
455 unsigned long flags;
456 unsigned char status;
457
458 spin_lock_irqsave(&up->port.lock, flags);
459
460 do {
1da177e4 461 status = serial_inp(up, UART_LSR);
1da177e4 462 if (status & UART_LSR_DR)
2e124b4a 463 receive_chars(up, &status);
1da177e4
LT		 464 check_modem_status(up);
465 if (status & UART_LSR_THRE)
466 transmit_chars(up);
467
468 spin_unlock_irqrestore(&up->port.lock, flags);
469
2e124b4a 470 tty_flip_buffer_push(&up->port.state->port);
1da177e4
LT		 471
472 spin_lock_irqsave(&up->port.lock, flags);
473
474 } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT));
475
476 spin_unlock_irqrestore(&up->port.lock, flags);
477
478 return IRQ_HANDLED;
479}
480
481/* Separate interrupt handling path for keyboard/mouse ports. */
482
483static void
484sunsu_change_speed(struct uart_port *port, unsigned int cflag,
485 unsigned int iflag, unsigned int quot);
486
487static void sunsu_change_mouse_baud(struct uart_sunsu_port *up)
488{
489 unsigned int cur_cflag = up->cflag;
490 int quot, new_baud;
491
492 up->cflag &= ~CBAUD;
493 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
494
495 quot = up->port.uartclk / (16 * new_baud);
496
1da177e4 497 sunsu_change_speed(&up->port, up->cflag, 0, quot);
1da177e4
LT		 498}
499
7d12e780 500static void receive_kbd_ms_chars(struct uart_sunsu_port *up, int is_break)
1da177e4
LT		 501{
502 do {
503 unsigned char ch = serial_inp(up, UART_RX);
504
505 /* Stop-A is handled by drivers/char/keyboard.c now. */
506 if (up->su_type == SU_PORT_KBD) {
507#ifdef CONFIG_SERIO
7d12e780 508 serio_interrupt(&up->serio, ch, 0);
1da177e4
LT		 509#endif
510 } else if (up->su_type == SU_PORT_MS) {
511 int ret = suncore_mouse_baud_detection(ch, is_break);
512
513 switch (ret) {
514 case 2:
515 sunsu_change_mouse_baud(up);
516 /* fallthru */
517 case 1:
518 break;
519
520 case 0:
521#ifdef CONFIG_SERIO
7d12e780 522 serio_interrupt(&up->serio, ch, 0);
1da177e4
LT		 523#endif
524 break;
525 };
526 }
527 } while (serial_in(up, UART_LSR) & UART_LSR_DR);
528}
529
7d12e780 530static irqreturn_t sunsu_kbd_ms_interrupt(int irq, void *dev_id)
1da177e4
LT		 531{
532 struct uart_sunsu_port *up = dev_id;
533
534 if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) {
535 unsigned char status = serial_inp(up, UART_LSR);
536
537 if ((status & UART_LSR_DR) || (status & UART_LSR_BI))
7d12e780 538 receive_kbd_ms_chars(up, (status & UART_LSR_BI) != 0);
1da177e4
LT		 539 }
540
541 return IRQ_HANDLED;
542}
543
544static unsigned int sunsu_tx_empty(struct uart_port *port)
545{
546 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
547 unsigned long flags;
548 unsigned int ret;
549
550 spin_lock_irqsave(&up->port.lock, flags);
551 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
552 spin_unlock_irqrestore(&up->port.lock, flags);
553
554 return ret;
555}
556
557static unsigned int sunsu_get_mctrl(struct uart_port *port)
558{
559 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
1da177e4
LT		 560 unsigned char status;
561 unsigned int ret;
562
1da177e4 563 status = serial_in(up, UART_MSR);
1da177e4
LT		 564
565 ret = 0;
566 if (status & UART_MSR_DCD)
567 ret |= TIOCM_CAR;
568 if (status & UART_MSR_RI)
569 ret |= TIOCM_RNG;
570 if (status & UART_MSR_DSR)
571 ret |= TIOCM_DSR;
572 if (status & UART_MSR_CTS)
573 ret |= TIOCM_CTS;
574 return ret;
575}
576
577static void sunsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
578{
579 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
580 unsigned char mcr = 0;
581
582 if (mctrl & TIOCM_RTS)
583 mcr |= UART_MCR_RTS;
584 if (mctrl & TIOCM_DTR)
585 mcr |= UART_MCR_DTR;
586 if (mctrl & TIOCM_OUT1)
587 mcr |= UART_MCR_OUT1;
588 if (mctrl & TIOCM_OUT2)
589 mcr |= UART_MCR_OUT2;
590 if (mctrl & TIOCM_LOOP)
591 mcr |= UART_MCR_LOOP;
592
593 serial_out(up, UART_MCR, mcr);
594}
595
596static void sunsu_break_ctl(struct uart_port *port, int break_state)
597{
598 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
599 unsigned long flags;
600
601 spin_lock_irqsave(&up->port.lock, flags);
602 if (break_state == -1)
603 up->lcr |= UART_LCR_SBC;
604 else
605 up->lcr &= ~UART_LCR_SBC;
606 serial_out(up, UART_LCR, up->lcr);
607 spin_unlock_irqrestore(&up->port.lock, flags);
608}
609
610static int sunsu_startup(struct uart_port *port)
611{
612 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
613 unsigned long flags;
614 int retval;
615
616 if (up->port.type == PORT_16C950) {
617 /* Wake up and initialize UART */
618 up->acr = 0;
619 serial_outp(up, UART_LCR, 0xBF);
620 serial_outp(up, UART_EFR, UART_EFR_ECB);
621 serial_outp(up, UART_IER, 0);
622 serial_outp(up, UART_LCR, 0);
623 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
624 serial_outp(up, UART_LCR, 0xBF);
625 serial_outp(up, UART_EFR, UART_EFR_ECB);
626 serial_outp(up, UART_LCR, 0);
627 }
628
629#ifdef CONFIG_SERIAL_8250_RSA
630 /*
631 * If this is an RSA port, see if we can kick it up to the
632 * higher speed clock.
633 */
634 enable_rsa(up);
635#endif
636
637 /*
638 * Clear the FIFO buffers and disable them.
7f927fcc 639 * (they will be reenabled in set_termios())
1da177e4
LT		 640 */
641 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) {
642 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
643 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
644 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
645 serial_outp(up, UART_FCR, 0);
646 }
647
648 /*
649 * Clear the interrupt registers.
650 */
651 (void) serial_inp(up, UART_LSR);
652 (void) serial_inp(up, UART_RX);
653 (void) serial_inp(up, UART_IIR);
654 (void) serial_inp(up, UART_MSR);
655
656 /*
657 * At this point, there's no way the LSR could still be 0xff;
658 * if it is, then bail out, because there's likely no UART
659 * here.
660 */
ce8337cb 661 if (!(up->port.flags & UPF_BUGGY_UART) &&
1da177e4
LT		 662 (serial_inp(up, UART_LSR) == 0xff)) {
663 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
664 return -ENODEV;
665 }
666
667 if (up->su_type != SU_PORT_PORT) {
668 retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt,
40663cc7 669 IRQF_SHARED, su_typev[up->su_type], up);
1da177e4
LT		 670 } else {
671 retval = request_irq(up->port.irq, sunsu_serial_interrupt,
40663cc7 672 IRQF_SHARED, su_typev[up->su_type], up);
1da177e4
LT		 673 }
674 if (retval) {
675 printk("su: Cannot register IRQ %d\n", up->port.irq);
676 return retval;
677 }
678
679 /*
680 * Now, initialize the UART
681 */
682 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
683
684 spin_lock_irqsave(&up->port.lock, flags);
685
686 up->port.mctrl |= TIOCM_OUT2;
687
688 sunsu_set_mctrl(&up->port, up->port.mctrl);
689 spin_unlock_irqrestore(&up->port.lock, flags);
690
691 /*
692 * Finally, enable interrupts. Note: Modem status interrupts
693 * are set via set_termios(), which will be occurring imminently
694 * anyway, so we don't enable them here.
695 */
696 up->ier = UART_IER_RLSI | UART_IER_RDI;
697 serial_outp(up, UART_IER, up->ier);
698
ce8337cb 699 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 700 unsigned int icp;
701 /*
702 * Enable interrupts on the AST Fourport board
703 */
704 icp = (up->port.iobase & 0xfe0) | 0x01f;
705 outb_p(0x80, icp);
706 (void) inb_p(icp);
707 }
708
709 /*
710 * And clear the interrupt registers again for luck.
711 */
712 (void) serial_inp(up, UART_LSR);
713 (void) serial_inp(up, UART_RX);
714 (void) serial_inp(up, UART_IIR);
715 (void) serial_inp(up, UART_MSR);
716
717 return 0;
718}
719
720static void sunsu_shutdown(struct uart_port *port)
721{
722 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
723 unsigned long flags;
724
725 /*
726 * Disable interrupts from this port
727 */
728 up->ier = 0;
729 serial_outp(up, UART_IER, 0);
730
731 spin_lock_irqsave(&up->port.lock, flags);
ce8337cb 732 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 733 /* reset interrupts on the AST Fourport board */
734 inb((up->port.iobase & 0xfe0) | 0x1f);
735 up->port.mctrl |= TIOCM_OUT1;
736 } else
737 up->port.mctrl &= ~TIOCM_OUT2;
738
739 sunsu_set_mctrl(&up->port, up->port.mctrl);
740 spin_unlock_irqrestore(&up->port.lock, flags);
741
742 /*
743 * Disable break condition and FIFOs
744 */
745 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
746 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
747 UART_FCR_CLEAR_RCVR |
748 UART_FCR_CLEAR_XMIT);
749 serial_outp(up, UART_FCR, 0);
750
751#ifdef CONFIG_SERIAL_8250_RSA
752 /*
753 * Reset the RSA board back to 115kbps compat mode.
754 */
755 disable_rsa(up);
756#endif
757
758 /*
759 * Read data port to reset things.
760 */
761 (void) serial_in(up, UART_RX);
762
763 free_irq(up->port.irq, up);
764}
765
766static void
767sunsu_change_speed(struct uart_port *port, unsigned int cflag,
768 unsigned int iflag, unsigned int quot)
769{
770 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
771 unsigned char cval, fcr = 0;
772 unsigned long flags;
773
774 switch (cflag & CSIZE) {
775 case CS5:
776 cval = 0x00;
777 break;
778 case CS6:
779 cval = 0x01;
780 break;
781 case CS7:
782 cval = 0x02;
783 break;
784 default:
785 case CS8:
786 cval = 0x03;
787 break;
788 }
789
790 if (cflag & CSTOPB)
791 cval |= 0x04;
792 if (cflag & PARENB)
793 cval |= UART_LCR_PARITY;
794 if (!(cflag & PARODD))
795 cval |= UART_LCR_EPAR;
796#ifdef CMSPAR
797 if (cflag & CMSPAR)
798 cval |= UART_LCR_SPAR;
799#endif
800
801 /*
802 * Work around a bug in the Oxford Semiconductor 952 rev B
803 * chip which causes it to seriously miscalculate baud rates
804 * when DLL is 0.
805 */
806 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
807 up->rev == 0x5201)
808 quot ++;
809
810 if (uart_config[up->port.type].flags & UART_USE_FIFO) {
811 if ((up->port.uartclk / quot) < (2400 * 16))
812 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
813#ifdef CONFIG_SERIAL_8250_RSA
814 else if (up->port.type == PORT_RSA)
815 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14;
816#endif
817 else
818 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8;
819 }
820 if (up->port.type == PORT_16750)
821 fcr |= UART_FCR7_64BYTE;
822
823 /*
824 * Ok, we're now changing the port state. Do it with
825 * interrupts disabled.
826 */
827 spin_lock_irqsave(&up->port.lock, flags);
828
829 /*
830 * Update the per-port timeout.
831 */
832 uart_update_timeout(port, cflag, (port->uartclk / (16 * quot)));
833
834 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
835 if (iflag & INPCK)
836 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
837 if (iflag & (BRKINT | PARMRK))
838 up->port.read_status_mask |= UART_LSR_BI;
839
840 /*
841 * Characteres to ignore
842 */
843 up->port.ignore_status_mask = 0;
844 if (iflag & IGNPAR)
845 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
846 if (iflag & IGNBRK) {
847 up->port.ignore_status_mask |= UART_LSR_BI;
848 /*
849 * If we're ignoring parity and break indicators,
850 * ignore overruns too (for real raw support).
851 */
852 if (iflag & IGNPAR)
853 up->port.ignore_status_mask |= UART_LSR_OE;
854 }
855
856 /*
857 * ignore all characters if CREAD is not set
858 */
859 if ((cflag & CREAD) == 0)
860 up->port.ignore_status_mask |= UART_LSR_DR;
861
862 /*
863 * CTS flow control flag and modem status interrupts
864 */
865 up->ier &= ~UART_IER_MSI;
866 if (UART_ENABLE_MS(&up->port, cflag))
867 up->ier |= UART_IER_MSI;
868
869 serial_out(up, UART_IER, up->ier);
870
871 if (uart_config[up->port.type].flags & UART_STARTECH) {
872 serial_outp(up, UART_LCR, 0xBF);
873 serial_outp(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0);
874 }
875 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
876 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
877 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
878 if (up->port.type == PORT_16750)
879 serial_outp(up, UART_FCR, fcr); /* set fcr */
880 serial_outp(up, UART_LCR, cval); /* reset DLAB */
881 up->lcr = cval; /* Save LCR */
882 if (up->port.type != PORT_16750) {
883 if (fcr & UART_FCR_ENABLE_FIFO) {
884 /* emulated UARTs (Lucent Venus 167x) need two steps */
885 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
886 }
887 serial_outp(up, UART_FCR, fcr); /* set fcr */
888 }
889
890 up->cflag = cflag;
891
892 spin_unlock_irqrestore(&up->port.lock, flags);
893}
894
895static void
606d099c
AC		 896sunsu_set_termios(struct uart_port *port, struct ktermios *termios,
897 struct ktermios *old)
1da177e4
LT		 898{
899 unsigned int baud, quot;
900
901 /*
902 * Ask the core to calculate the divisor for us.
903 */
904 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
905 quot = uart_get_divisor(port, baud);
906
907 sunsu_change_speed(port, termios->c_cflag, termios->c_iflag, quot);
908}
909
910static void sunsu_release_port(struct uart_port *port)
911{
912}
913
914static int sunsu_request_port(struct uart_port *port)
915{
916 return 0;
917}
918
919static void sunsu_config_port(struct uart_port *port, int flags)
920{
921 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
922
923 if (flags & UART_CONFIG_TYPE) {
924 /*
925 * We are supposed to call autoconfig here, but this requires
926 * splitting all the OBP probing crap from the UART probing.
927 * We'll do it when we kill sunsu.c altogether.
928 */
929 port->type = up->type_probed; /* XXX */
930 }
931}
932
933static int
934sunsu_verify_port(struct uart_port *port, struct serial_struct *ser)
935{
936 return -EINVAL;
937}
938
939static const char *
940sunsu_type(struct uart_port *port)
941{
942 int type = port->type;
943
944 if (type >= ARRAY_SIZE(uart_config))
945 type = 0;
946 return uart_config[type].name;
947}
948
949static struct uart_ops sunsu_pops = {
950 .tx_empty = sunsu_tx_empty,
951 .set_mctrl = sunsu_set_mctrl,
952 .get_mctrl = sunsu_get_mctrl,
953 .stop_tx = sunsu_stop_tx,
954 .start_tx = sunsu_start_tx,
955 .stop_rx = sunsu_stop_rx,
956 .enable_ms = sunsu_enable_ms,
957 .break_ctl = sunsu_break_ctl,
958 .startup = sunsu_startup,
959 .shutdown = sunsu_shutdown,
960 .set_termios = sunsu_set_termios,
961 .type = sunsu_type,
962 .release_port = sunsu_release_port,
963 .request_port = sunsu_request_port,
964 .config_port = sunsu_config_port,
965 .verify_port = sunsu_verify_port,
966};
967
968#define UART_NR 4
969
970static struct uart_sunsu_port sunsu_ports[UART_NR];
971
972#ifdef CONFIG_SERIO
973
974static DEFINE_SPINLOCK(sunsu_serio_lock);
975
976static int sunsu_serio_write(struct serio *serio, unsigned char ch)
977{
978 struct uart_sunsu_port *up = serio->port_data;
979 unsigned long flags;
980 int lsr;
981
982 spin_lock_irqsave(&sunsu_serio_lock, flags);
983
984 do {
985 lsr = serial_in(up, UART_LSR);
986 } while (!(lsr & UART_LSR_THRE));
987
988 /* Send the character out. */
989 serial_out(up, UART_TX, ch);
990
991 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
992
993 return 0;
994}
995
996static int sunsu_serio_open(struct serio *serio)
997{
998 struct uart_sunsu_port *up = serio->port_data;
999 unsigned long flags;
1000 int ret;
1001
1002 spin_lock_irqsave(&sunsu_serio_lock, flags);
1003 if (!up->serio_open) {
1004 up->serio_open = 1;
1005 ret = 0;
1006 } else
1007 ret = -EBUSY;
1008 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1009
1010 return ret;
1011}
1012
1013static void sunsu_serio_close(struct serio *serio)
1014{
1015 struct uart_sunsu_port *up = serio->port_data;
1016 unsigned long flags;
1017
1018 spin_lock_irqsave(&sunsu_serio_lock, flags);
1019 up->serio_open = 0;
1020 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1021}
1022
1023#endif /* CONFIG_SERIO */
1024
1025static void sunsu_autoconfig(struct uart_sunsu_port *up)
1026{
1027 unsigned char status1, status2, scratch, scratch2, scratch3;
1028 unsigned char save_lcr, save_mcr;
1da177e4
LT		 1029 unsigned long flags;
1030
1708d242 1031 if (up->su_type == SU_PORT_NONE)
1da177e4
LT		 1032 return;
1033
1034 up->type_probed = PORT_UNKNOWN;
9b4a1617 1035 up->port.iotype = UPIO_MEM;
1da177e4 1036
1da177e4
LT		 1037 spin_lock_irqsave(&up->port.lock, flags);
1038
ce8337cb 1039 if (!(up->port.flags & UPF_BUGGY_UART)) {
1da177e4
LT		 1040 /*
1041 * Do a simple existence test first; if we fail this, there's
1042 * no point trying anything else.
1043 *
1044 * 0x80 is used as a nonsense port to prevent against false
1045 * positives due to ISA bus float. The assumption is that
1046 * 0x80 is a non-existent port; which should be safe since
1047 * include/asm/io.h also makes this assumption.
1048 */
1049 scratch = serial_inp(up, UART_IER);
1050 serial_outp(up, UART_IER, 0);
1051#ifdef __i386__
1052 outb(0xff, 0x080);
1053#endif
1054 scratch2 = serial_inp(up, UART_IER);
1055 serial_outp(up, UART_IER, 0x0f);
1056#ifdef __i386__
1057 outb(0, 0x080);
1058#endif
1059 scratch3 = serial_inp(up, UART_IER);
1060 serial_outp(up, UART_IER, scratch);
1061 if (scratch2 != 0 || scratch3 != 0x0F)
1062 goto out; /* We failed; there's nothing here */
1063 }
1064
1065 save_mcr = serial_in(up, UART_MCR);
1066 save_lcr = serial_in(up, UART_LCR);
1067
1068 /*
1069 * Check to see if a UART is really there. Certain broken
1070 * internal modems based on the Rockwell chipset fail this
1071 * test, because they apparently don't implement the loopback
1072 * test mode. So this test is skipped on the COM 1 through
1073 * COM 4 ports. This *should* be safe, since no board
1074 * manufacturer would be stupid enough to design a board
1075 * that conflicts with COM 1-4 --- we hope!
1076 */
ce8337cb 1077 if (!(up->port.flags & UPF_SKIP_TEST)) {
1da177e4
LT		 1078 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1079 status1 = serial_inp(up, UART_MSR) & 0xF0;
1080 serial_outp(up, UART_MCR, save_mcr);
1081 if (status1 != 0x90)
1082 goto out; /* We failed loopback test */
1083 }
1084 serial_outp(up, UART_LCR, 0xBF); /* set up for StarTech test */
1085 serial_outp(up, UART_EFR, 0); /* EFR is the same as FCR */
1086 serial_outp(up, UART_LCR, 0);
1087 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1088 scratch = serial_in(up, UART_IIR) >> 6;
1089 switch (scratch) {
1090 case 0:
1091 up->port.type = PORT_16450;
1092 break;
1093 case 1:
1094 up->port.type = PORT_UNKNOWN;
1095 break;
1096 case 2:
1097 up->port.type = PORT_16550;
1098 break;
1099 case 3:
1100 up->port.type = PORT_16550A;
1101 break;
1102 }
1103 if (up->port.type == PORT_16550A) {
1104 /* Check for Startech UART's */
1105 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1106 if (serial_in(up, UART_EFR) == 0) {
1107 up->port.type = PORT_16650;
1108 } else {
1109 serial_outp(up, UART_LCR, 0xBF);
1110 if (serial_in(up, UART_EFR) == 0)
1111 up->port.type = PORT_16650V2;
1112 }
1113 }
1114 if (up->port.type == PORT_16550A) {
1115 /* Check for TI 16750 */
1116 serial_outp(up, UART_LCR, save_lcr | UART_LCR_DLAB);
1117 serial_outp(up, UART_FCR,
1118 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1119 scratch = serial_in(up, UART_IIR) >> 5;
1120 if (scratch == 7) {
1121 /*
1122 * If this is a 16750, and not a cheap UART
1123 * clone, then it should only go into 64 byte
1124 * mode if the UART_FCR7_64BYTE bit was set
1125 * while UART_LCR_DLAB was latched.
1126 */
1127 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1128 serial_outp(up, UART_LCR, 0);
1129 serial_outp(up, UART_FCR,
1130 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1131 scratch = serial_in(up, UART_IIR) >> 5;
1132 if (scratch == 6)
1133 up->port.type = PORT_16750;
1134 }
1135 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1136 }
1137 serial_outp(up, UART_LCR, save_lcr);
1138 if (up->port.type == PORT_16450) {
1139 scratch = serial_in(up, UART_SCR);
1140 serial_outp(up, UART_SCR, 0xa5);
1141 status1 = serial_in(up, UART_SCR);
1142 serial_outp(up, UART_SCR, 0x5a);
1143 status2 = serial_in(up, UART_SCR);
1144 serial_outp(up, UART_SCR, scratch);
1145
1146 if ((status1 != 0xa5) || (status2 != 0x5a))
1147 up->port.type = PORT_8250;
1148 }
1149
1150 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
1151
1152 if (up->port.type == PORT_UNKNOWN)
1153 goto out;
1154 up->type_probed = up->port.type; /* XXX */
1155
1156 /*
1157 * Reset the UART.
1158 */
1159#ifdef CONFIG_SERIAL_8250_RSA
1160 if (up->port.type == PORT_RSA)
1161 serial_outp(up, UART_RSA_FRR, 0);
1162#endif
1163 serial_outp(up, UART_MCR, save_mcr);
1164 serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO |
1165 UART_FCR_CLEAR_RCVR |
1166 UART_FCR_CLEAR_XMIT));
1167 serial_outp(up, UART_FCR, 0);
1168 (void)serial_in(up, UART_RX);
1169 serial_outp(up, UART_IER, 0);
1170
1171out:
1172 spin_unlock_irqrestore(&up->port.lock, flags);
1173}
1174
1175static struct uart_driver sunsu_reg = {
1176 .owner = THIS_MODULE,
32039f49 1177 .driver_name = "sunsu",
1da177e4
LT		 1178 .dev_name = "ttyS",
1179 .major = TTY_MAJOR,
1180};
1181
9671f099 1182static int sunsu_kbd_ms_init(struct uart_sunsu_port *up)
1da177e4 1183{
623f41eb 1184 int quot, baud;
1da177e4
LT		 1185#ifdef CONFIG_SERIO
1186 struct serio *serio;
1187#endif
1188
623f41eb 1189 if (up->su_type == SU_PORT_KBD) {
1da177e4 1190 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
623f41eb
DM		 1191 baud = 1200;
1192 } else {
1da177e4 1193 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
623f41eb
DM		 1194 baud = 4800;
1195 }
1196 quot = up->port.uartclk / (16 * baud);
1da177e4
LT		 1197
1198 sunsu_autoconfig(up);
1199 if (up->port.type == PORT_UNKNOWN)
1708d242 1200 return -ENODEV;
1da177e4 1201
4f1296a5 1202 printk("%s: %s port at %llx, irq %u\n",
2dc11581 1203 up->port.dev->of_node->full_name,
c964521c 1204 (up->su_type == SU_PORT_KBD) ? "Keyboard" : "Mouse",
4f1296a5
DM		 1205 (unsigned long long) up->port.mapbase,
1206 up->port.irq);
c964521c 1207
1da177e4 1208#ifdef CONFIG_SERIO
1708d242
DM		 1209 serio = &up->serio;
1210 serio->port_data = up;
1da177e4 1211
1708d242
DM		 1212 serio->id.type = SERIO_RS232;
1213 if (up->su_type == SU_PORT_KBD) {
1214 serio->id.proto = SERIO_SUNKBD;
1215 strlcpy(serio->name, "sukbd", sizeof(serio->name));
1da177e4 1216 } else {
1708d242
DM		 1217 serio->id.proto = SERIO_SUN;
1218 serio->id.extra = 1;
1219 strlcpy(serio->name, "sums", sizeof(serio->name));
1da177e4 1220 }
1708d242
DM		 1221 strlcpy(serio->phys,
1222 (!(up->port.line & 1) ? "su/serio0" : "su/serio1"),
1223 sizeof(serio->phys));
1224
1225 serio->write = sunsu_serio_write;
1226 serio->open = sunsu_serio_open;
1227 serio->close = sunsu_serio_close;
1228 serio->dev.parent = up->port.dev;
1229
1230 serio_register_port(serio);
1da177e4
LT		 1231#endif
1232
623f41eb
DM		 1233 sunsu_change_speed(&up->port, up->cflag, 0, quot);
1234
1da177e4
LT		 1235 sunsu_startup(&up->port);
1236 return 0;
1237}
1238
1239/*
1240 * ------------------------------------------------------------
1241 * Serial console driver
1242 * ------------------------------------------------------------
1243 */
1244
1245#ifdef CONFIG_SERIAL_SUNSU_CONSOLE
1246
1247#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1248
1249/*
1250 * Wait for transmitter & holding register to empty
1251 */
1252static __inline__ void wait_for_xmitr(struct uart_sunsu_port *up)
1253{
1254 unsigned int status, tmout = 10000;
1255
1256 /* Wait up to 10ms for the character(s) to be sent. */
1257 do {
1258 status = serial_in(up, UART_LSR);
1259
1260 if (status & UART_LSR_BI)
1261 up->lsr_break_flag = UART_LSR_BI;
1262
1263 if (--tmout == 0)
1264 break;
1265 udelay(1);
1266 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1267
1268 /* Wait up to 1s for flow control if necessary */
ce8337cb 1269 if (up->port.flags & UPF_CONS_FLOW) {
1da177e4
LT		 1270 tmout = 1000000;
1271 while (--tmout &&
1272 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1273 udelay(1);
1274 }
1275}
1276
d358788f
RK		 1277static void sunsu_console_putchar(struct uart_port *port, int ch)
1278{
1279 struct uart_sunsu_port *up = (struct uart_sunsu_port *)port;
1280
1281 wait_for_xmitr(up);
1282 serial_out(up, UART_TX, ch);
1283}
1284
1da177e4
LT		 1285/*
1286 * Print a string to the serial port trying not to disturb
1287 * any possible real use of the port...
1288 */
1289static void sunsu_console_write(struct console *co, const char *s,
1290 unsigned int count)
1291{
1292 struct uart_sunsu_port *up = &sunsu_ports[co->index];
f3c681c0 1293 unsigned long flags;
1da177e4 1294 unsigned int ier;
f3c681c0
DM		 1295 int locked = 1;
1296
1297 local_irq_save(flags);
1298 if (up->port.sysrq) {
1299 locked = 0;
1300 } else if (oops_in_progress) {
1301 locked = spin_trylock(&up->port.lock);
1302 } else
1303 spin_lock(&up->port.lock);
1da177e4
LT		 1304
1305 /*
1306 * First save the UER then disable the interrupts
1307 */
1308 ier = serial_in(up, UART_IER);
1309 serial_out(up, UART_IER, 0);
1310
d358788f 1311 uart_console_write(&up->port, s, count, sunsu_console_putchar);
1da177e4
LT		 1312
1313 /*
1314 * Finally, wait for transmitter to become empty
1315 * and restore the IER
1316 */
1317 wait_for_xmitr(up);
1318 serial_out(up, UART_IER, ier);
f3c681c0
DM		 1319
1320 if (locked)
1321 spin_unlock(&up->port.lock);
1322 local_irq_restore(flags);
1da177e4
LT		 1323}
1324
1325/*
1326 * Setup initial baud/bits/parity. We do two things here:
1327 * - construct a cflag setting for the first su_open()
1328 * - initialize the serial port
1329 * Return non-zero if we didn't find a serial port.
1330 */
90a660a4 1331static int __init sunsu_console_setup(struct console *co, char *options)
1da177e4 1332{
be24656a
DM		 1333 static struct ktermios dummy;
1334 struct ktermios termios;
1da177e4 1335 struct uart_port *port;
1da177e4
LT		 1336
1337 printk("Console: ttyS%d (SU)\n",
1338 (sunsu_reg.minor - 64) + co->index);
1339
1340 /*
1341 * Check whether an invalid uart number has been specified, and
1342 * if so, search for the first available port that does have
1343 * console support.
1344 */
1345 if (co->index >= UART_NR)
1346 co->index = 0;
1347 port = &sunsu_ports[co->index].port;
1348
1349 /*
1350 * Temporary fix.
1351 */
1352 spin_lock_init(&port->lock);
1353
be24656a 1354 /* Get firmware console settings. */
2dc11581 1355 sunserial_console_termios(co, port->dev->of_node);
1da177e4 1356
be24656a
DM		 1357 memset(&termios, 0, sizeof(struct ktermios));
1358 termios.c_cflag = co->cflag;
1359 port->mctrl |= TIOCM_DTR;
1360 port->ops->set_termios(port, &termios, &dummy);
1361
1362 return 0;
1da177e4
LT		 1363}
1364
90a660a4 1365static struct console sunsu_console = {
1da177e4
LT		 1366 .name = "ttyS",
1367 .write = sunsu_console_write,
1368 .device = uart_console_device,
1369 .setup = sunsu_console_setup,
1370 .flags = CON_PRINTBUFFER,
1371 .index = -1,
1372 .data = &sunsu_reg,
1373};
1da177e4
LT		 1374
1375/*
1376 * Register console.
1377 */
1378
c73fcc84 1379static inline struct console *SUNSU_CONSOLE(void)
1da177e4 1380{
90a660a4 1381 return &sunsu_console;
1da177e4
LT		 1382}
1383#else
c73fcc84 1384#define SUNSU_CONSOLE() (NULL)
1da177e4
LT		 1385#define sunsu_serial_console_init() do { } while (0)
1386#endif
1387
9671f099 1388static enum su_type su_get_type(struct device_node *dp)
1da177e4 1389{
1708d242 1390 struct device_node *ap = of_find_node_by_path("/aliases");
1da177e4 1391
1708d242 1392 if (ap) {
ccf0dec6
SR		 1393 const char *keyb = of_get_property(ap, "keyboard", NULL);
1394 const char *ms = of_get_property(ap, "mouse", NULL);
1da177e4 1395
1708d242
DM		 1396 if (keyb) {
1397 if (dp == of_find_node_by_path(keyb))
1398 return SU_PORT_KBD;
1399 }
1400 if (ms) {
1401 if (dp == of_find_node_by_path(ms))
1402 return SU_PORT_MS;
1403 }
1404 }
1da177e4 1405
1708d242
DM		 1406 return SU_PORT_PORT;
1407}
1da177e4 1408
9671f099 1409static int su_probe(struct platform_device *op)
1708d242
DM		 1410{
1411 static int inst;
61c7a080 1412 struct device_node *dp = op->dev.of_node;
1708d242
DM		 1413 struct uart_sunsu_port *up;
1414 struct resource *rp;
91d1ed1a 1415 enum su_type type;
1917d17b 1416 bool ignore_line;
1708d242 1417 int err;
1da177e4 1418
91d1ed1a
DM		 1419 type = su_get_type(dp);
1420 if (type == SU_PORT_PORT) {
1421 if (inst >= UART_NR)
1422 return -EINVAL;
1423 up = &sunsu_ports[inst];
1424 } else {
1425 up = kzalloc(sizeof(*up), GFP_KERNEL);
1426 if (!up)
1427 return -ENOMEM;
1428 }
1da177e4 1429
1708d242 1430 up->port.line = inst;
1da177e4 1431
1708d242 1432 spin_lock_init(&up->port.lock);
1da177e4 1433
91d1ed1a 1434 up->su_type = type;
f5deb807 1435
1708d242 1436 rp = &op->resource[0];
91d1ed1a 1437 up->port.mapbase = rp->start;
28f65c11 1438 up->reg_size = resource_size(rp);
1708d242 1439 up->port.membase = of_ioremap(rp, 0, up->reg_size, "su");
91d1ed1a
DM		 1440 if (!up->port.membase) {
1441 if (type != SU_PORT_PORT)
1442 kfree(up);
1708d242 1443 return -ENOMEM;
91d1ed1a 1444 }
1ddb7c98 1445
1636f8ac 1446 up->port.irq = op->archdata.irqs[0];
1da177e4 1447
1708d242 1448 up->port.dev = &op->dev;
1da177e4 1449
1708d242
DM		 1450 up->port.type = PORT_UNKNOWN;
1451 up->port.uartclk = (SU_BASE_BAUD * 16);
1da177e4 1452
1708d242
DM		 1453 err = 0;
1454 if (up->su_type == SU_PORT_KBD || up->su_type == SU_PORT_MS) {
1455 err = sunsu_kbd_ms_init(up);
91d1ed1a 1456 if (err) {
c4a3987f
JL		 1457 of_iounmap(&op->resource[0],
1458 up->port.membase, up->reg_size);
91d1ed1a 1459 kfree(up);
c4a3987f 1460 return err;
91d1ed1a
DM		 1461 }
1462 dev_set_drvdata(&op->dev, up);
a1d22d32
DM		 1463
1464 return 0;
1da177e4
LT		 1465 }
1466
1708d242 1467 up->port.flags |= UPF_BOOT_AUTOCONF;
1da177e4 1468
1708d242 1469 sunsu_autoconfig(up);
1da177e4 1470
1708d242
DM		 1471 err = -ENODEV;
1472 if (up->port.type == PORT_UNKNOWN)
1473 goto out_unmap;
1da177e4 1474
1708d242 1475 up->port.ops = &sunsu_pops;
1da177e4 1476
1917d17b
DM		 1477 ignore_line = false;
1478 if (!strcmp(dp->name, "rsc-console") ||
1479 !strcmp(dp->name, "lom-console"))
1480 ignore_line = true;
1481
c73fcc84 1482 sunserial_console_match(SUNSU_CONSOLE(), dp,
4e3533d0 1483 &sunsu_reg, up->port.line,
1917d17b 1484 ignore_line);
1708d242
DM		 1485 err = uart_add_one_port(&sunsu_reg, &up->port);
1486 if (err)
1487 goto out_unmap;
1da177e4 1488
1708d242 1489 dev_set_drvdata(&op->dev, up);
1da177e4 1490
1708d242 1491 inst++;
1da177e4 1492
1708d242
DM		 1493 return 0;
1494
1495out_unmap:
e3a411a3 1496 of_iounmap(&op->resource[0], up->port.membase, up->reg_size);
1708d242 1497 return err;
1da177e4
LT		 1498}
1499
ae8d8a14 1500static int su_remove(struct platform_device *op)
1da177e4 1501{
e3a411a3 1502 struct uart_sunsu_port *up = dev_get_drvdata(&op->dev);
9616ff43 1503 bool kbdms = false;
1da177e4 1504
1708d242 1505 if (up->su_type == SU_PORT_MS ||
9616ff43
DM		 1506 up->su_type == SU_PORT_KBD)
1507 kbdms = true;
1508
1509 if (kbdms) {
1708d242
DM		 1510#ifdef CONFIG_SERIO
1511 serio_unregister_port(&up->serio);
1512#endif
9616ff43 1513 } else if (up->port.type != PORT_UNKNOWN)
1708d242 1514 uart_remove_one_port(&sunsu_reg, &up->port);
91d1ed1a 1515
65da4d81 1516 if (up->port.membase)
e3a411a3 1517 of_iounmap(&op->resource[0], up->port.membase, up->reg_size);
65da4d81 1518
9616ff43
DM		 1519 if (kbdms)
1520 kfree(up);
1521
e3a411a3 1522 dev_set_drvdata(&op->dev, NULL);
1da177e4 1523
1708d242
DM		 1524 return 0;
1525}
1da177e4 1526
fd098316 1527static const struct of_device_id su_match[] = {
1708d242
DM		 1528 {
1529 .name = "su",
1530 },
1531 {
1532 .name = "su_pnp",
1533 },
1534 {
1535 .name = "serial",
1536 .compatible = "su",
1537 },
8301d386
DM		 1538 {
1539 .type = "serial",
1540 .compatible = "su",
1541 },
1708d242
DM		 1542 {},
1543};
1544MODULE_DEVICE_TABLE(of, su_match);
1da177e4 1545
793218df 1546static struct platform_driver su_driver = {
4018294b
GL		 1547 .driver = {
1548 .name = "su",
1549 .owner = THIS_MODULE,
1550 .of_match_table = su_match,
1551 },
1708d242 1552 .probe = su_probe,
2d47b716 1553 .remove = su_remove,
1708d242 1554};
1da177e4 1555
1708d242
DM		 1556static int __init sunsu_init(void)
1557{
1558 struct device_node *dp;
1559 int err;
58d784a5 1560 int num_uart = 0;
1da177e4 1561
1708d242
DM		 1562 for_each_node_by_name(dp, "su") {
1563 if (su_get_type(dp) == SU_PORT_PORT)
1564 num_uart++;
1da177e4 1565 }
1708d242
DM		 1566 for_each_node_by_name(dp, "su_pnp") {
1567 if (su_get_type(dp) == SU_PORT_PORT)
1568 num_uart++;
1569 }
1570 for_each_node_by_name(dp, "serial") {
1571 if (of_device_is_compatible(dp, "su")) {
1572 if (su_get_type(dp) == SU_PORT_PORT)
1573 num_uart++;
1574 }
1da177e4 1575 }
8301d386
DM		 1576 for_each_node_by_type(dp, "serial") {
1577 if (of_device_is_compatible(dp, "su")) {
1578 if (su_get_type(dp) == SU_PORT_PORT)
1579 num_uart++;
1580 }
1581 }
1da177e4 1582
1708d242 1583 if (num_uart) {
58d784a5 1584 err = sunserial_register_minors(&sunsu_reg, num_uart);
1708d242
DM		 1585 if (err)
1586 return err;
1708d242 1587 }
1da177e4 1588
793218df 1589 err = platform_driver_register(&su_driver);
1708d242 1590 if (err && num_uart)
58d784a5 1591 sunserial_unregister_minors(&sunsu_reg, num_uart);
1da177e4 1592
1708d242 1593 return err;
1da177e4
LT		 1594}
1595
1596static void __exit sunsu_exit(void)
1597{
58d784a5
MH		 1598 if (sunsu_reg.nr)
1599 sunserial_unregister_minors(&sunsu_reg, sunsu_reg.nr);
1da177e4
LT		 1600}
1601
1708d242 1602module_init(sunsu_init);
1da177e4 1603module_exit(sunsu_exit);
9efc3715
DM		 1604
1605MODULE_AUTHOR("Eddie C. Dost, Peter Zaitcev, and David S. Miller");
1606MODULE_DESCRIPTION("Sun SU serial port driver");
1607MODULE_VERSION("2.0");
9a2a9bb2 1608MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)