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Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/module.h>
32#include <linux/ioport.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/init.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/delay.h>
43#include <linux/clk.h>
30555476 44#include <linux/cpufreq.h>
26c919e1 45#include <linux/of.h>
b497549a
BD		 46
47#include <asm/irq.h>
48
a09e64fb 49#include <mach/hardware.h>
b497549a 50
a2b7ba9c 51#include <plat/regs-serial.h>
5f5a7a55 52#include <plat/clock.h>
b497549a
BD		 53
54#include "samsung.h"
55
56/* UART name and device definitions */
57
58#define S3C24XX_SERIAL_NAME "ttySAC"
59#define S3C24XX_SERIAL_MAJOR 204
60#define S3C24XX_SERIAL_MINOR 64
61
b497549a
BD		 62/* macros to change one thing to another */
63
64#define tx_enabled(port) ((port)->unused[0])
65#define rx_enabled(port) ((port)->unused[1])
66
25985edc 67/* flag to ignore all characters coming in */
b497549a
BD		 68#define RXSTAT_DUMMY_READ (0x10000000)
69
70static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
71{
72 return container_of(port, struct s3c24xx_uart_port, port);
73}
74
75/* translate a port to the device name */
76
77static inline const char *s3c24xx_serial_portname(struct uart_port *port)
78{
79 return to_platform_device(port->dev)->name;
80}
81
82static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
83{
9303ac15 84 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 85}
86
88bb4ea1
TA		 87/*
88 * s3c64xx and later SoC's include the interrupt mask and status registers in
89 * the controller itself, unlike the s3c24xx SoC's which have these registers
90 * in the interrupt controller. Check if the port type is s3c64xx or higher.
91 */
92static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
93{
94 return to_ourport(port)->info->type == PORT_S3C6400;
95}
96
b497549a
BD		 97static void s3c24xx_serial_rx_enable(struct uart_port *port)
98{
99 unsigned long flags;
100 unsigned int ucon, ufcon;
101 int count = 10000;
102
103 spin_lock_irqsave(&port->lock, flags);
104
105 while (--count && !s3c24xx_serial_txempty_nofifo(port))
106 udelay(100);
107
108 ufcon = rd_regl(port, S3C2410_UFCON);
109 ufcon |= S3C2410_UFCON_RESETRX;
110 wr_regl(port, S3C2410_UFCON, ufcon);
111
112 ucon = rd_regl(port, S3C2410_UCON);
113 ucon |= S3C2410_UCON_RXIRQMODE;
114 wr_regl(port, S3C2410_UCON, ucon);
115
116 rx_enabled(port) = 1;
117 spin_unlock_irqrestore(&port->lock, flags);
118}
119
120static void s3c24xx_serial_rx_disable(struct uart_port *port)
121{
122 unsigned long flags;
123 unsigned int ucon;
124
125 spin_lock_irqsave(&port->lock, flags);
126
127 ucon = rd_regl(port, S3C2410_UCON);
128 ucon &= ~S3C2410_UCON_RXIRQMODE;
129 wr_regl(port, S3C2410_UCON, ucon);
130
131 rx_enabled(port) = 0;
132 spin_unlock_irqrestore(&port->lock, flags);
133}
134
135static void s3c24xx_serial_stop_tx(struct uart_port *port)
136{
b73c289c
BD		 137 struct s3c24xx_uart_port *ourport = to_ourport(port);
138
b497549a 139 if (tx_enabled(port)) {
88bb4ea1
TA		 140 if (s3c24xx_serial_has_interrupt_mask(port))
141 __set_bit(S3C64XX_UINTM_TXD,
142 portaddrl(port, S3C64XX_UINTM));
143 else
144 disable_irq_nosync(ourport->tx_irq);
b497549a
BD		 145 tx_enabled(port) = 0;
146 if (port->flags & UPF_CONS_FLOW)
147 s3c24xx_serial_rx_enable(port);
148 }
149}
150
151static void s3c24xx_serial_start_tx(struct uart_port *port)
152{
b73c289c
BD		 153 struct s3c24xx_uart_port *ourport = to_ourport(port);
154
b497549a
BD		 155 if (!tx_enabled(port)) {
156 if (port->flags & UPF_CONS_FLOW)
157 s3c24xx_serial_rx_disable(port);
158
88bb4ea1
TA		 159 if (s3c24xx_serial_has_interrupt_mask(port))
160 __clear_bit(S3C64XX_UINTM_TXD,
161 portaddrl(port, S3C64XX_UINTM));
162 else
163 enable_irq(ourport->tx_irq);
b497549a
BD		 164 tx_enabled(port) = 1;
165 }
166}
167
b497549a
BD		 168static void s3c24xx_serial_stop_rx(struct uart_port *port)
169{
b73c289c
BD		 170 struct s3c24xx_uart_port *ourport = to_ourport(port);
171
b497549a
BD		 172 if (rx_enabled(port)) {
173 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 174 if (s3c24xx_serial_has_interrupt_mask(port))
175 __set_bit(S3C64XX_UINTM_RXD,
176 portaddrl(port, S3C64XX_UINTM));
177 else
178 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 179 rx_enabled(port) = 0;
180 }
181}
182
183static void s3c24xx_serial_enable_ms(struct uart_port *port)
184{
185}
186
187static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
188{
189 return to_ourport(port)->info;
190}
191
192static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
193{
4d84e970
TA		 194 struct s3c24xx_uart_port *ourport;
195
b497549a
BD		 196 if (port->dev == NULL)
197 return NULL;
198
4d84e970
TA		 199 ourport = container_of(port, struct s3c24xx_uart_port, port);
200 return ourport->cfg;
b497549a
BD		 201}
202
203static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
204 unsigned long ufstat)
205{
206 struct s3c24xx_uart_info *info = ourport->info;
207
208 if (ufstat & info->rx_fifofull)
da121506 209 return ourport->port.fifosize;
b497549a
BD		 210
211 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
212}
213
214
215/* ? - where has parity gone?? */
216#define S3C2410_UERSTAT_PARITY (0x1000)
217
218static irqreturn_t
219s3c24xx_serial_rx_chars(int irq, void *dev_id)
220{
221 struct s3c24xx_uart_port *ourport = dev_id;
222 struct uart_port *port = &ourport->port;
b497549a 223 unsigned int ufcon, ch, flag, ufstat, uerstat;
c15c3747 224 unsigned long flags;
b497549a
BD		 225 int max_count = 64;
226
c15c3747
TA		 227 spin_lock_irqsave(&port->lock, flags);
228
b497549a
BD		 229 while (max_count-- > 0) {
230 ufcon = rd_regl(port, S3C2410_UFCON);
231 ufstat = rd_regl(port, S3C2410_UFSTAT);
232
233 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
234 break;
235
236 uerstat = rd_regl(port, S3C2410_UERSTAT);
237 ch = rd_regb(port, S3C2410_URXH);
238
239 if (port->flags & UPF_CONS_FLOW) {
240 int txe = s3c24xx_serial_txempty_nofifo(port);
241
242 if (rx_enabled(port)) {
243 if (!txe) {
244 rx_enabled(port) = 0;
245 continue;
246 }
247 } else {
248 if (txe) {
249 ufcon |= S3C2410_UFCON_RESETRX;
250 wr_regl(port, S3C2410_UFCON, ufcon);
251 rx_enabled(port) = 1;
252 goto out;
253 }
254 continue;
255 }
256 }
257
258 /* insert the character into the buffer */
259
260 flag = TTY_NORMAL;
261 port->icount.rx++;
262
263 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
264 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
265 ch, uerstat);
266
267 /* check for break */
268 if (uerstat & S3C2410_UERSTAT_BREAK) {
269 dbg("break!\n");
270 port->icount.brk++;
271 if (uart_handle_break(port))
9303ac15 272 goto ignore_char;
b497549a
BD		 273 }
274
275 if (uerstat & S3C2410_UERSTAT_FRAME)
276 port->icount.frame++;
277 if (uerstat & S3C2410_UERSTAT_OVERRUN)
278 port->icount.overrun++;
279
280 uerstat &= port->read_status_mask;
281
282 if (uerstat & S3C2410_UERSTAT_BREAK)
283 flag = TTY_BREAK;
284 else if (uerstat & S3C2410_UERSTAT_PARITY)
285 flag = TTY_PARITY;
286 else if (uerstat & (S3C2410_UERSTAT_FRAME |
287 S3C2410_UERSTAT_OVERRUN))
288 flag = TTY_FRAME;
289 }
290
291 if (uart_handle_sysrq_char(port, ch))
292 goto ignore_char;
293
294 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
295 ch, flag);
296
297 ignore_char:
298 continue;
299 }
2e124b4a 300 tty_flip_buffer_push(&port->state->port);
b497549a
BD		 301
302 out:
c15c3747 303 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 304 return IRQ_HANDLED;
305}
306
307static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
308{
309 struct s3c24xx_uart_port *ourport = id;
310 struct uart_port *port = &ourport->port;
ebd2c8f6 311 struct circ_buf *xmit = &port->state->xmit;
c15c3747 312 unsigned long flags;
b497549a
BD		 313 int count = 256;
314
c15c3747
TA		 315 spin_lock_irqsave(&port->lock, flags);
316
b497549a
BD		 317 if (port->x_char) {
318 wr_regb(port, S3C2410_UTXH, port->x_char);
319 port->icount.tx++;
320 port->x_char = 0;
321 goto out;
322 }
323
25985edc 324 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 325 * stopped, disable the uart and exit
326 */
327
328 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
329 s3c24xx_serial_stop_tx(port);
330 goto out;
331 }
332
333 /* try and drain the buffer... */
334
335 while (!uart_circ_empty(xmit) && count-- > 0) {
336 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
337 break;
338
339 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
340 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
341 port->icount.tx++;
342 }
343
c15c3747
TA		 344 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
345 spin_unlock(&port->lock);
b497549a 346 uart_write_wakeup(port);
c15c3747
TA		 347 spin_lock(&port->lock);
348 }
b497549a
BD		 349
350 if (uart_circ_empty(xmit))
351 s3c24xx_serial_stop_tx(port);
352
353 out:
c15c3747 354 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 355 return IRQ_HANDLED;
356}
357
88bb4ea1
TA		 358/* interrupt handler for s3c64xx and later SoC's.*/
359static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
360{
361 struct s3c24xx_uart_port *ourport = id;
362 struct uart_port *port = &ourport->port;
363 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 364 irqreturn_t ret = IRQ_HANDLED;
365
88bb4ea1
TA		 366 if (pend & S3C64XX_UINTM_RXD_MSK) {
367 ret = s3c24xx_serial_rx_chars(irq, id);
368 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
369 }
370 if (pend & S3C64XX_UINTM_TXD_MSK) {
371 ret = s3c24xx_serial_tx_chars(irq, id);
372 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
373 }
88bb4ea1
TA		 374 return ret;
375}
376
b497549a
BD		 377static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
378{
379 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
380 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
381 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
382
383 if (ufcon & S3C2410_UFCON_FIFOMODE) {
384 if ((ufstat & info->tx_fifomask) != 0 ||
385 (ufstat & info->tx_fifofull))
386 return 0;
387
388 return 1;
389 }
390
391 return s3c24xx_serial_txempty_nofifo(port);
392}
393
394/* no modem control lines */
395static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
396{
397 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
398
399 if (umstat & S3C2410_UMSTAT_CTS)
400 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
401 else
402 return TIOCM_CAR | TIOCM_DSR;
403}
404
405static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
406{
407 /* todo - possibly remove AFC and do manual CTS */
408}
409
410static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
411{
412 unsigned long flags;
413 unsigned int ucon;
414
415 spin_lock_irqsave(&port->lock, flags);
416
417 ucon = rd_regl(port, S3C2410_UCON);
418
419 if (break_state)
420 ucon |= S3C2410_UCON_SBREAK;
421 else
422 ucon &= ~S3C2410_UCON_SBREAK;
423
424 wr_regl(port, S3C2410_UCON, ucon);
425
426 spin_unlock_irqrestore(&port->lock, flags);
427}
428
429static void s3c24xx_serial_shutdown(struct uart_port *port)
430{
431 struct s3c24xx_uart_port *ourport = to_ourport(port);
432
433 if (ourport->tx_claimed) {
88bb4ea1
TA		 434 if (!s3c24xx_serial_has_interrupt_mask(port))
435 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 436 tx_enabled(port) = 0;
437 ourport->tx_claimed = 0;
438 }
439
440 if (ourport->rx_claimed) {
88bb4ea1
TA		 441 if (!s3c24xx_serial_has_interrupt_mask(port))
442 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 443 ourport->rx_claimed = 0;
444 rx_enabled(port) = 0;
445 }
b497549a 446
88bb4ea1
TA		 447 /* Clear pending interrupts and mask all interrupts */
448 if (s3c24xx_serial_has_interrupt_mask(port)) {
449 wr_regl(port, S3C64XX_UINTP, 0xf);
450 wr_regl(port, S3C64XX_UINTM, 0xf);
451 }
452}
b497549a
BD		 453
454static int s3c24xx_serial_startup(struct uart_port *port)
455{
456 struct s3c24xx_uart_port *ourport = to_ourport(port);
457 int ret;
458
459 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
460 port->mapbase, port->membase);
461
462 rx_enabled(port) = 1;
463
b73c289c 464 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 465 s3c24xx_serial_portname(port), ourport);
466
467 if (ret != 0) {
d20925e1 468 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 469 return ret;
470 }
471
472 ourport->rx_claimed = 1;
473
474 dbg("requesting tx irq...\n");
475
476 tx_enabled(port) = 1;
477
b73c289c 478 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 479 s3c24xx_serial_portname(port), ourport);
480
481 if (ret) {
d20925e1 482 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 483 goto err;
484 }
485
486 ourport->tx_claimed = 1;
487
488 dbg("s3c24xx_serial_startup ok\n");
489
490 /* the port reset code should have done the correct
491 * register setup for the port controls */
492
493 return ret;
494
495 err:
496 s3c24xx_serial_shutdown(port);
497 return ret;
498}
499
88bb4ea1
TA		 500static int s3c64xx_serial_startup(struct uart_port *port)
501{
502 struct s3c24xx_uart_port *ourport = to_ourport(port);
503 int ret;
504
505 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
506 port->mapbase, port->membase);
507
508 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
509 s3c24xx_serial_portname(port), ourport);
510 if (ret) {
d20925e1 511 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 512 return ret;
513 }
514
515 /* For compatibility with s3c24xx Soc's */
516 rx_enabled(port) = 1;
517 ourport->rx_claimed = 1;
518 tx_enabled(port) = 0;
519 ourport->tx_claimed = 1;
520
521 /* Enable Rx Interrupt */
522 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
523 dbg("s3c64xx_serial_startup ok\n");
524 return ret;
525}
526
b497549a
BD		 527/* power power management control */
528
529static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
530 unsigned int old)
531{
532 struct s3c24xx_uart_port *ourport = to_ourport(port);
533
30555476
BD		 534 ourport->pm_level = level;
535
b497549a
BD		 536 switch (level) {
537 case 3:
7cd88831 538 if (!IS_ERR(ourport->baudclk))
9484b009 539 clk_disable_unprepare(ourport->baudclk);
b497549a 540
9484b009 541 clk_disable_unprepare(ourport->clk);
b497549a
BD		 542 break;
543
544 case 0:
9484b009 545 clk_prepare_enable(ourport->clk);
b497549a 546
7cd88831 547 if (!IS_ERR(ourport->baudclk))
9484b009 548 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 549
550 break;
551 default:
d20925e1 552 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 553 }
554}
555
556/* baud rate calculation
557 *
558 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
559 * of different sources, including the peripheral clock ("pclk") and an
560 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
561 * with a programmable extra divisor.
562 *
563 * The following code goes through the clock sources, and calculates the
564 * baud clocks (and the resultant actual baud rates) and then tries to
565 * pick the closest one and select that.
566 *
567*/
568
5f5a7a55 569#define MAX_CLK_NAME_LENGTH 15
b497549a 570
5f5a7a55 571static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 572{
573 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 574 unsigned int ucon;
b497549a 575
5f5a7a55
TA		 576 if (info->num_clks == 1)
577 return 0;
b497549a 578
5f5a7a55
TA		 579 ucon = rd_regl(port, S3C2410_UCON);
580 ucon &= info->clksel_mask;
581 return ucon >> info->clksel_shift;
b497549a
BD		 582}
583
5f5a7a55
TA		 584static void s3c24xx_serial_setsource(struct uart_port *port,
585 unsigned int clk_sel)
b497549a 586{
5f5a7a55
TA		 587 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
588 unsigned int ucon;
b497549a 589
5f5a7a55
TA		 590 if (info->num_clks == 1)
591 return;
090f848d 592
5f5a7a55
TA		 593 ucon = rd_regl(port, S3C2410_UCON);
594 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
595 return;
b497549a 596
5f5a7a55
TA		 597 ucon &= ~info->clksel_mask;
598 ucon |= clk_sel << info->clksel_shift;
599 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 600}
601
5f5a7a55
TA		 602static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
603 unsigned int req_baud, struct clk **best_clk,
604 unsigned int *clk_num)
b497549a 605{
5f5a7a55
TA		 606 struct s3c24xx_uart_info *info = ourport->info;
607 struct clk *clk;
608 unsigned long rate;
609 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
610 char clkname[MAX_CLK_NAME_LENGTH];
611 int calc_deviation, deviation = (1 << 30) - 1;
612
5f5a7a55
TA		 613 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
614 ourport->info->def_clk_sel;
615 for (cnt = 0; cnt < info->num_clks; cnt++) {
616 if (!(clk_sel & (1 << cnt)))
617 continue;
618
619 sprintf(clkname, "clk_uart_baud%d", cnt);
620 clk = clk_get(ourport->port.dev, clkname);
7cd88831 621 if (IS_ERR(clk))
5f5a7a55
TA		 622 continue;
623
624 rate = clk_get_rate(clk);
625 if (!rate)
626 continue;
627
628 if (ourport->info->has_divslot) {
629 unsigned long div = rate / req_baud;
630
631 /* The UDIVSLOT register on the newer UARTs allows us to
632 * get a divisor adjustment of 1/16th on the baud clock.
633 *
634 * We don't keep the UDIVSLOT value (the 16ths we
635 * calculated by not multiplying the baud by 16) as it
636 * is easy enough to recalculate.
637 */
638
639 quot = div / 16;
640 baud = rate / div;
641 } else {
642 quot = (rate + (8 * req_baud)) / (16 * req_baud);
643 baud = rate / (quot * 16);
b497549a 644 }
5f5a7a55 645 quot--;
b497549a 646
5f5a7a55
TA		 647 calc_deviation = req_baud - baud;
648 if (calc_deviation < 0)
649 calc_deviation = -calc_deviation;
b497549a 650
5f5a7a55
TA		 651 if (calc_deviation < deviation) {
652 *best_clk = clk;
653 best_quot = quot;
654 *clk_num = cnt;
655 deviation = calc_deviation;
b497549a
BD		 656 }
657 }
658
5f5a7a55 659 return best_quot;
b497549a
BD		 660}
661
090f848d
BD		 662/* udivslot_table[]
663 *
664 * This table takes the fractional value of the baud divisor and gives
665 * the recommended setting for the UDIVSLOT register.
666 */
667static u16 udivslot_table[16] = {
668 [0] = 0x0000,
669 [1] = 0x0080,
670 [2] = 0x0808,
671 [3] = 0x0888,
672 [4] = 0x2222,
673 [5] = 0x4924,
674 [6] = 0x4A52,
675 [7] = 0x54AA,
676 [8] = 0x5555,
677 [9] = 0xD555,
678 [10] = 0xD5D5,
679 [11] = 0xDDD5,
680 [12] = 0xDDDD,
681 [13] = 0xDFDD,
682 [14] = 0xDFDF,
683 [15] = 0xFFDF,
684};
685
b497549a
BD		 686static void s3c24xx_serial_set_termios(struct uart_port *port,
687 struct ktermios *termios,
688 struct ktermios *old)
689{
690 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
691 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 692 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 693 unsigned long flags;
5f5a7a55 694 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 695 unsigned int ulcon;
696 unsigned int umcon;
090f848d 697 unsigned int udivslot = 0;
b497549a
BD		 698
699 /*
700 * We don't support modem control lines.
701 */
702 termios->c_cflag &= ~(HUPCL | CMSPAR);
703 termios->c_cflag |= CLOCAL;
704
705 /*
706 * Ask the core to calculate the divisor for us.
707 */
708
709 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 710 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 711 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
712 quot = port->custom_divisor;
7cd88831 713 if (IS_ERR(clk))
5f5a7a55 714 return;
b497549a
BD		 715
716 /* check to see if we need to change clock source */
717
5f5a7a55
TA		 718 if (ourport->baudclk != clk) {
719 s3c24xx_serial_setsource(port, clk_sel);
b497549a 720
7cd88831 721 if (!IS_ERR(ourport->baudclk)) {
9484b009 722 clk_disable_unprepare(ourport->baudclk);
7cd88831 723 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 724 }
725
9484b009 726 clk_prepare_enable(clk);
b497549a 727
b497549a 728 ourport->baudclk = clk;
30555476 729 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 730 }
731
090f848d
BD		 732 if (ourport->info->has_divslot) {
733 unsigned int div = ourport->baudclk_rate / baud;
734
8b526ae4
JL		 735 if (cfg->has_fracval) {
736 udivslot = (div & 15);
737 dbg("fracval = %04x\n", udivslot);
738 } else {
739 udivslot = udivslot_table[div & 15];
740 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
741 }
090f848d
BD		 742 }
743
b497549a
BD		 744 switch (termios->c_cflag & CSIZE) {
745 case CS5:
746 dbg("config: 5bits/char\n");
747 ulcon = S3C2410_LCON_CS5;
748 break;
749 case CS6:
750 dbg("config: 6bits/char\n");
751 ulcon = S3C2410_LCON_CS6;
752 break;
753 case CS7:
754 dbg("config: 7bits/char\n");
755 ulcon = S3C2410_LCON_CS7;
756 break;
757 case CS8:
758 default:
759 dbg("config: 8bits/char\n");
760 ulcon = S3C2410_LCON_CS8;
761 break;
762 }
763
764 /* preserve original lcon IR settings */
765 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
766
767 if (termios->c_cflag & CSTOPB)
768 ulcon |= S3C2410_LCON_STOPB;
769
770 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
771
772 if (termios->c_cflag & PARENB) {
773 if (termios->c_cflag & PARODD)
774 ulcon |= S3C2410_LCON_PODD;
775 else
776 ulcon |= S3C2410_LCON_PEVEN;
777 } else {
778 ulcon |= S3C2410_LCON_PNONE;
779 }
780
781 spin_lock_irqsave(&port->lock, flags);
782
090f848d
BD		 783 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
784 ulcon, quot, udivslot);
b497549a
BD		 785
786 wr_regl(port, S3C2410_ULCON, ulcon);
787 wr_regl(port, S3C2410_UBRDIV, quot);
788 wr_regl(port, S3C2410_UMCON, umcon);
789
090f848d
BD		 790 if (ourport->info->has_divslot)
791 wr_regl(port, S3C2443_DIVSLOT, udivslot);
792
b497549a
BD		 793 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
794 rd_regl(port, S3C2410_ULCON),
795 rd_regl(port, S3C2410_UCON),
796 rd_regl(port, S3C2410_UFCON));
797
798 /*
799 * Update the per-port timeout.
800 */
801 uart_update_timeout(port, termios->c_cflag, baud);
802
803 /*
804 * Which character status flags are we interested in?
805 */
806 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
807 if (termios->c_iflag & INPCK)
808 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
809
810 /*
811 * Which character status flags should we ignore?
812 */
813 port->ignore_status_mask = 0;
814 if (termios->c_iflag & IGNPAR)
815 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
816 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
817 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
818
819 /*
820 * Ignore all characters if CREAD is not set.
821 */
822 if ((termios->c_cflag & CREAD) == 0)
823 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
824
825 spin_unlock_irqrestore(&port->lock, flags);
826}
827
828static const char *s3c24xx_serial_type(struct uart_port *port)
829{
830 switch (port->type) {
831 case PORT_S3C2410:
832 return "S3C2410";
833 case PORT_S3C2440:
834 return "S3C2440";
835 case PORT_S3C2412:
836 return "S3C2412";
b690ace5
BD		 837 case PORT_S3C6400:
838 return "S3C6400/10";
b497549a
BD		 839 default:
840 return NULL;
841 }
842}
843
844#define MAP_SIZE (0x100)
845
846static void s3c24xx_serial_release_port(struct uart_port *port)
847{
848 release_mem_region(port->mapbase, MAP_SIZE);
849}
850
851static int s3c24xx_serial_request_port(struct uart_port *port)
852{
853 const char *name = s3c24xx_serial_portname(port);
854 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
855}
856
857static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
858{
859 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
860
861 if (flags & UART_CONFIG_TYPE &&
862 s3c24xx_serial_request_port(port) == 0)
863 port->type = info->type;
864}
865
866/*
867 * verify the new serial_struct (for TIOCSSERIAL).
868 */
869static int
870s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
871{
872 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
873
874 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
875 return -EINVAL;
876
877 return 0;
878}
879
880
881#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
882
883static struct console s3c24xx_serial_console;
884
93b5c032
JP		 885static int __init s3c24xx_serial_console_init(void)
886{
887 register_console(&s3c24xx_serial_console);
888 return 0;
889}
890console_initcall(s3c24xx_serial_console_init);
891
b497549a
BD		 892#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
893#else
894#define S3C24XX_SERIAL_CONSOLE NULL
895#endif
896
93b5c032
JP		 897#ifdef CONFIG_CONSOLE_POLL
898static int s3c24xx_serial_get_poll_char(struct uart_port *port);
899static void s3c24xx_serial_put_poll_char(struct uart_port *port,
900 unsigned char c);
901#endif
902
b497549a
BD		 903static struct uart_ops s3c24xx_serial_ops = {
904 .pm = s3c24xx_serial_pm,
905 .tx_empty = s3c24xx_serial_tx_empty,
906 .get_mctrl = s3c24xx_serial_get_mctrl,
907 .set_mctrl = s3c24xx_serial_set_mctrl,
908 .stop_tx = s3c24xx_serial_stop_tx,
909 .start_tx = s3c24xx_serial_start_tx,
910 .stop_rx = s3c24xx_serial_stop_rx,
911 .enable_ms = s3c24xx_serial_enable_ms,
912 .break_ctl = s3c24xx_serial_break_ctl,
913 .startup = s3c24xx_serial_startup,
914 .shutdown = s3c24xx_serial_shutdown,
915 .set_termios = s3c24xx_serial_set_termios,
916 .type = s3c24xx_serial_type,
917 .release_port = s3c24xx_serial_release_port,
918 .request_port = s3c24xx_serial_request_port,
919 .config_port = s3c24xx_serial_config_port,
920 .verify_port = s3c24xx_serial_verify_port,
93b5c032
JP		 921#ifdef CONFIG_CONSOLE_POLL
922 .poll_get_char = s3c24xx_serial_get_poll_char,
923 .poll_put_char = s3c24xx_serial_put_poll_char,
924#endif
b497549a
BD		 925};
926
b497549a
BD		 927static struct uart_driver s3c24xx_uart_drv = {
928 .owner = THIS_MODULE,
2cf0c58e 929 .driver_name = "s3c2410_serial",
bdd4915a 930 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 931 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 932 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 933 .major = S3C24XX_SERIAL_MAJOR,
934 .minor = S3C24XX_SERIAL_MINOR,
935};
936
03d5e77b 937static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 938 [0] = {
939 .port = {
940 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
941 .iotype = UPIO_MEM,
b497549a
BD		 942 .uartclk = 0,
943 .fifosize = 16,
944 .ops = &s3c24xx_serial_ops,
945 .flags = UPF_BOOT_AUTOCONF,
946 .line = 0,
947 }
948 },
949 [1] = {
950 .port = {
951 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
952 .iotype = UPIO_MEM,
b497549a
BD		 953 .uartclk = 0,
954 .fifosize = 16,
955 .ops = &s3c24xx_serial_ops,
956 .flags = UPF_BOOT_AUTOCONF,
957 .line = 1,
958 }
959 },
03d5e77b 960#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 961
962 [2] = {
963 .port = {
964 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
965 .iotype = UPIO_MEM,
b497549a
BD		 966 .uartclk = 0,
967 .fifosize = 16,
968 .ops = &s3c24xx_serial_ops,
969 .flags = UPF_BOOT_AUTOCONF,
970 .line = 2,
971 }
03d5e77b
BD		 972 },
973#endif
974#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
975 [3] = {
976 .port = {
977 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
978 .iotype = UPIO_MEM,
03d5e77b
BD		 979 .uartclk = 0,
980 .fifosize = 16,
981 .ops = &s3c24xx_serial_ops,
982 .flags = UPF_BOOT_AUTOCONF,
983 .line = 3,
984 }
b497549a
BD		 985 }
986#endif
987};
988
989/* s3c24xx_serial_resetport
990 *
0dfb3b41 991 * reset the fifos and other the settings.
b497549a
BD		 992*/
993
0dfb3b41
TA		 994static void s3c24xx_serial_resetport(struct uart_port *port,
995 struct s3c2410_uartcfg *cfg)
b497549a
BD		 996{
997 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 998 unsigned long ucon = rd_regl(port, S3C2410_UCON);
999 unsigned int ucon_mask;
b497549a 1000
0dfb3b41
TA		 1001 ucon_mask = info->clksel_mask;
1002 if (info->type == PORT_S3C2440)
1003 ucon_mask |= S3C2440_UCON0_DIVMASK;
1004
1005 ucon &= ucon_mask;
1006 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1007
1008 /* reset both fifos */
1009 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1010 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1011
1012 /* some delay is required after fifo reset */
1013 udelay(1);
b497549a
BD		 1014}
1015
30555476
BD		 1016
1017#ifdef CONFIG_CPU_FREQ
1018
1019static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1020 unsigned long val, void *data)
1021{
1022 struct s3c24xx_uart_port *port;
1023 struct uart_port *uport;
1024
1025 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1026 uport = &port->port;
1027
1028 /* check to see if port is enabled */
1029
1030 if (port->pm_level != 0)
1031 return 0;
1032
1033 /* try and work out if the baudrate is changing, we can detect
1034 * a change in rate, but we do not have support for detecting
1035 * a disturbance in the clock-rate over the change.
1036 */
1037
25f04ad4 1038 if (IS_ERR(port->baudclk))
30555476
BD		 1039 goto exit;
1040
25f04ad4 1041 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1042 goto exit;
1043
1044 if (val == CPUFREQ_PRECHANGE) {
1045 /* we should really shut the port down whilst the
1046 * frequency change is in progress. */
1047
1048 } else if (val == CPUFREQ_POSTCHANGE) {
1049 struct ktermios *termios;
1050 struct tty_struct *tty;
1051
ebd2c8f6 1052 if (uport->state == NULL)
30555476 1053 goto exit;
30555476 1054
ebd2c8f6 1055 tty = uport->state->port.tty;
30555476 1056
7de40c21 1057 if (tty == NULL)
30555476 1058 goto exit;
30555476 1059
adc8d746 1060 termios = &tty->termios;
30555476
BD		 1061
1062 if (termios == NULL) {
d20925e1 1063 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1064 goto exit;
1065 }
1066
1067 s3c24xx_serial_set_termios(uport, termios, NULL);
1068 }
1069
1070 exit:
1071 return 0;
1072}
1073
1074static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1075{
1076 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1077
1078 return cpufreq_register_notifier(&port->freq_transition,
1079 CPUFREQ_TRANSITION_NOTIFIER);
1080}
1081
1082static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1083{
1084 cpufreq_unregister_notifier(&port->freq_transition,
1085 CPUFREQ_TRANSITION_NOTIFIER);
1086}
1087
1088#else
1089static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1090{
1091 return 0;
1092}
1093
1094static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1095{
1096}
1097#endif
1098
b497549a
BD		 1099/* s3c24xx_serial_init_port
1100 *
1101 * initialise a single serial port from the platform device given
1102 */
1103
1104static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1105 struct platform_device *platdev)
1106{
1107 struct uart_port *port = &ourport->port;
da121506 1108 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1109 struct resource *res;
1110 int ret;
1111
1112 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1113
1114 if (platdev == NULL)
1115 return -ENODEV;
1116
b497549a
BD		 1117 if (port->mapbase != 0)
1118 return 0;
1119
b497549a
BD		 1120 /* setup info for port */
1121 port->dev = &platdev->dev;
b497549a 1122
88bb4ea1
TA		 1123 /* Startup sequence is different for s3c64xx and higher SoC's */
1124 if (s3c24xx_serial_has_interrupt_mask(port))
1125 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1126
b497549a
BD		 1127 port->uartclk = 1;
1128
1129 if (cfg->uart_flags & UPF_CONS_FLOW) {
1130 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1131 port->flags |= UPF_CONS_FLOW;
1132 }
1133
1134 /* sort our the physical and virtual addresses for each UART */
1135
1136 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1137 if (res == NULL) {
d20925e1 1138 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1139 return -EINVAL;
1140 }
1141
1142 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1143
41147bfd
TA		 1144 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1145 if (!port->membase) {
1146 dev_err(port->dev, "failed to remap controller address\n");
1147 return -EBUSY;
1148 }
1149
b690ace5 1150 port->mapbase = res->start;
b497549a
BD		 1151 ret = platform_get_irq(platdev, 0);
1152 if (ret < 0)
1153 port->irq = 0;
b73c289c 1154 else {
b497549a 1155 port->irq = ret;
b73c289c
BD		 1156 ourport->rx_irq = ret;
1157 ourport->tx_irq = ret + 1;
1158 }
9303ac15 1159
b73c289c
BD		 1160 ret = platform_get_irq(platdev, 1);
1161 if (ret > 0)
1162 ourport->tx_irq = ret;
b497549a
BD		 1163
1164 ourport->clk = clk_get(&platdev->dev, "uart");
1165
88bb4ea1
TA		 1166 /* Keep all interrupts masked and cleared */
1167 if (s3c24xx_serial_has_interrupt_mask(port)) {
1168 wr_regl(port, S3C64XX_UINTM, 0xf);
1169 wr_regl(port, S3C64XX_UINTP, 0xf);
1170 wr_regl(port, S3C64XX_UINTSP, 0xf);
1171 }
1172
b73c289c
BD		 1173 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1174 port->mapbase, port->membase, port->irq,
1175 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1176
1177 /* reset the fifos (and setup the uart) */
1178 s3c24xx_serial_resetport(port, cfg);
1179 return 0;
1180}
1181
1182static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1183 struct device_attribute *attr,
1184 char *buf)
1185{
1186 struct uart_port *port = s3c24xx_dev_to_port(dev);
1187 struct s3c24xx_uart_port *ourport = to_ourport(port);
1188
7cd88831
KK		 1189 if (IS_ERR(ourport->baudclk))
1190 return -EINVAL;
1191
7b15e1d9
KP		 1192 return snprintf(buf, PAGE_SIZE, "* %s\n",
1193 ourport->baudclk->name ?: "(null)");
b497549a
BD		 1194}
1195
1196static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1197
26c919e1 1198
b497549a
BD		 1199/* Device driver serial port probe */
1200
26c919e1 1201static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1202static int probe_index;
1203
26c919e1
TA		 1204static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1205 struct platform_device *pdev)
1206{
1207#ifdef CONFIG_OF
1208 if (pdev->dev.of_node) {
1209 const struct of_device_id *match;
1210 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1211 return (struct s3c24xx_serial_drv_data *)match->data;
1212 }
1213#endif
1214 return (struct s3c24xx_serial_drv_data *)
1215 platform_get_device_id(pdev)->driver_data;
1216}
1217
da121506 1218static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a
BD		 1219{
1220 struct s3c24xx_uart_port *ourport;
1221 int ret;
1222
da121506 1223 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
b497549a
BD		 1224
1225 ourport = &s3c24xx_serial_ports[probe_index];
da121506 1226
26c919e1
TA		 1227 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1228 if (!ourport->drv_data) {
1229 dev_err(&pdev->dev, "could not find driver data\n");
1230 return -ENODEV;
1231 }
da121506 1232
7cd88831 1233 ourport->baudclk = ERR_PTR(-EINVAL);
da121506
TA		 1234 ourport->info = ourport->drv_data->info;
1235 ourport->cfg = (pdev->dev.platform_data) ?
1236 (struct s3c2410_uartcfg *)pdev->dev.platform_data :
1237 ourport->drv_data->def_cfg;
1238
1239 ourport->port.fifosize = (ourport->info->fifosize) ?
1240 ourport->info->fifosize :
1241 ourport->drv_data->fifosize[probe_index];
1242
b497549a
BD		 1243 probe_index++;
1244
1245 dbg("%s: initialising port %p...\n", __func__, ourport);
1246
da121506 1247 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a
BD		 1248 if (ret < 0)
1249 goto probe_err;
1250
1251 dbg("%s: adding port\n", __func__);
1252 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1253 platform_set_drvdata(pdev, &ourport->port);
b497549a 1254
da121506 1255 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
b497549a 1256 if (ret < 0)
da121506 1257 dev_err(&pdev->dev, "failed to add clock source attr.\n");
b497549a 1258
30555476
BD		 1259 ret = s3c24xx_serial_cpufreq_register(ourport);
1260 if (ret < 0)
da121506 1261 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1262
b497549a
BD		 1263 return 0;
1264
1265 probe_err:
1266 return ret;
1267}
1268
ae8d8a14 1269static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1270{
1271 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1272
1273 if (port) {
30555476 1274 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
b497549a
BD		 1275 device_remove_file(&dev->dev, &dev_attr_clock_source);
1276 uart_remove_one_port(&s3c24xx_uart_drv, port);
1277 }
1278
1279 return 0;
1280}
1281
b497549a 1282/* UART power management code */
aef7fe52
MH		 1283#ifdef CONFIG_PM_SLEEP
1284static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1285{
aef7fe52 1286 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1287
1288 if (port)
1289 uart_suspend_port(&s3c24xx_uart_drv, port);
1290
1291 return 0;
1292}
1293
aef7fe52 1294static int s3c24xx_serial_resume(struct device *dev)
b497549a 1295{
aef7fe52 1296 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1297 struct s3c24xx_uart_port *ourport = to_ourport(port);
1298
1299 if (port) {
9484b009 1300 clk_prepare_enable(ourport->clk);
b497549a 1301 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1302 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1303
1304 uart_resume_port(&s3c24xx_uart_drv, port);
1305 }
1306
1307 return 0;
1308}
aef7fe52
MH		 1309
1310static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1311 .suspend = s3c24xx_serial_suspend,
1312 .resume = s3c24xx_serial_resume,
1313};
b882fc1b
KK		 1314#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1315
aef7fe52 1316#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1317
1318#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1319#endif /* CONFIG_PM_SLEEP */
b497549a 1320
b497549a
BD		 1321/* Console code */
1322
1323#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1324
1325static struct uart_port *cons_uart;
1326
1327static int
1328s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1329{
1330 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1331 unsigned long ufstat, utrstat;
1332
1333 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1334 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1335
1336 ufstat = rd_regl(port, S3C2410_UFSTAT);
1337 return (ufstat & info->tx_fifofull) ? 0 : 1;
1338 }
1339
1340 /* in non-fifo mode, we go and use the tx buffer empty */
1341
1342 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1343 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1344}
1345
93b5c032
JP		 1346#ifdef CONFIG_CONSOLE_POLL
1347/*
1348 * Console polling routines for writing and reading from the uart while
1349 * in an interrupt or debug context.
1350 */
1351
1352static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1353{
1354 struct s3c24xx_uart_port *ourport = to_ourport(port);
1355 unsigned int ufstat;
1356
1357 ufstat = rd_regl(port, S3C2410_UFSTAT);
1358 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1359 return NO_POLL_CHAR;
1360
1361 return rd_regb(port, S3C2410_URXH);
1362}
1363
1364static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1365 unsigned char c)
1366{
1367 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1368
1369 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1370 cpu_relax();
1371 wr_regb(cons_uart, S3C2410_UTXH, c);
1372}
1373
1374#endif /* CONFIG_CONSOLE_POLL */
1375
b497549a
BD		 1376static void
1377s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1378{
1379 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1380 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1381 barrier();
1382 wr_regb(cons_uart, S3C2410_UTXH, ch);
1383}
1384
1385static void
1386s3c24xx_serial_console_write(struct console *co, const char *s,
1387 unsigned int count)
1388{
1389 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1390}
1391
1392static void __init
1393s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1394 int *parity, int *bits)
1395{
b497549a
BD		 1396 struct clk *clk;
1397 unsigned int ulcon;
1398 unsigned int ucon;
1399 unsigned int ubrdiv;
1400 unsigned long rate;
5f5a7a55
TA		 1401 unsigned int clk_sel;
1402 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 1403
1404 ulcon = rd_regl(port, S3C2410_ULCON);
1405 ucon = rd_regl(port, S3C2410_UCON);
1406 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1407
1408 dbg("s3c24xx_serial_get_options: port=%p\n"
1409 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1410 port, ulcon, ucon, ubrdiv);
1411
1412 if ((ucon & 0xf) != 0) {
1413 /* consider the serial port configured if the tx/rx mode set */
1414
1415 switch (ulcon & S3C2410_LCON_CSMASK) {
1416 case S3C2410_LCON_CS5:
1417 *bits = 5;
1418 break;
1419 case S3C2410_LCON_CS6:
1420 *bits = 6;
1421 break;
1422 case S3C2410_LCON_CS7:
1423 *bits = 7;
1424 break;
1425 default:
1426 case S3C2410_LCON_CS8:
1427 *bits = 8;
1428 break;
1429 }
1430
1431 switch (ulcon & S3C2410_LCON_PMASK) {
1432 case S3C2410_LCON_PEVEN:
1433 *parity = 'e';
1434 break;
1435
1436 case S3C2410_LCON_PODD:
1437 *parity = 'o';
1438 break;
1439
1440 case S3C2410_LCON_PNONE:
1441 default:
1442 *parity = 'n';
1443 }
1444
1445 /* now calculate the baud rate */
1446
5f5a7a55
TA		 1447 clk_sel = s3c24xx_serial_getsource(port);
1448 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 1449
5f5a7a55 1450 clk = clk_get(port->dev, clk_name);
7cd88831 1451 if (!IS_ERR(clk))
5f5a7a55 1452 rate = clk_get_rate(clk);
b497549a
BD		 1453 else
1454 rate = 1;
1455
b497549a
BD		 1456 *baud = rate / (16 * (ubrdiv + 1));
1457 dbg("calculated baud %d\n", *baud);
1458 }
1459
1460}
1461
b497549a
BD		 1462static int __init
1463s3c24xx_serial_console_setup(struct console *co, char *options)
1464{
1465 struct uart_port *port;
1466 int baud = 9600;
1467 int bits = 8;
1468 int parity = 'n';
1469 int flow = 'n';
1470
1471 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1472 co, co->index, options);
1473
1474 /* is this a valid port */
1475
03d5e77b 1476 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 1477 co->index = 0;
1478
1479 port = &s3c24xx_serial_ports[co->index].port;
1480
1481 /* is the port configured? */
1482
ee430f16
TA		 1483 if (port->mapbase == 0x0)
1484 return -ENODEV;
b497549a
BD		 1485
1486 cons_uart = port;
1487
1488 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1489
1490 /*
1491 * Check whether an invalid uart number has been specified, and
1492 * if so, search for the first available port that does have
1493 * console support.
1494 */
1495 if (options)
1496 uart_parse_options(options, &baud, &parity, &bits, &flow);
1497 else
1498 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1499
1500 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1501
1502 return uart_set_options(port, co, baud, parity, bits, flow);
1503}
1504
b497549a
BD		 1505static struct console s3c24xx_serial_console = {
1506 .name = S3C24XX_SERIAL_NAME,
1507 .device = uart_console_device,
1508 .flags = CON_PRINTBUFFER,
1509 .index = -1,
1510 .write = s3c24xx_serial_console_write,
5822a5df
TA		 1511 .setup = s3c24xx_serial_console_setup,
1512 .data = &s3c24xx_uart_drv,
b497549a 1513};
da121506
TA		 1514#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1515
1516#ifdef CONFIG_CPU_S3C2410
1517static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1518 .info = &(struct s3c24xx_uart_info) {
1519 .name = "Samsung S3C2410 UART",
1520 .type = PORT_S3C2410,
1521 .fifosize = 16,
1522 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1523 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1524 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1525 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1526 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1527 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1528 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1529 .num_clks = 2,
1530 .clksel_mask = S3C2410_UCON_CLKMASK,
1531 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1532 },
1533 .def_cfg = &(struct s3c2410_uartcfg) {
1534 .ucon = S3C2410_UCON_DEFAULT,
1535 .ufcon = S3C2410_UFCON_DEFAULT,
1536 },
1537};
1538#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1539#else
1540#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1541#endif
b497549a 1542
da121506
TA		 1543#ifdef CONFIG_CPU_S3C2412
1544static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1545 .info = &(struct s3c24xx_uart_info) {
1546 .name = "Samsung S3C2412 UART",
1547 .type = PORT_S3C2412,
1548 .fifosize = 64,
1549 .has_divslot = 1,
1550 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1551 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1552 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1553 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1554 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1555 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1556 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1557 .num_clks = 4,
1558 .clksel_mask = S3C2412_UCON_CLKMASK,
1559 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1560 },
1561 .def_cfg = &(struct s3c2410_uartcfg) {
1562 .ucon = S3C2410_UCON_DEFAULT,
1563 .ufcon = S3C2410_UFCON_DEFAULT,
1564 },
1565};
1566#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1567#else
1568#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1569#endif
b497549a 1570
da121506 1571#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 1572 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 1573static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1574 .info = &(struct s3c24xx_uart_info) {
1575 .name = "Samsung S3C2440 UART",
1576 .type = PORT_S3C2440,
1577 .fifosize = 64,
1578 .has_divslot = 1,
1579 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1580 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1581 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1582 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1583 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1584 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1585 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1586 .num_clks = 4,
1587 .clksel_mask = S3C2412_UCON_CLKMASK,
1588 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1589 },
1590 .def_cfg = &(struct s3c2410_uartcfg) {
1591 .ucon = S3C2410_UCON_DEFAULT,
1592 .ufcon = S3C2410_UFCON_DEFAULT,
1593 },
1594};
1595#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1596#else
1597#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1598#endif
b497549a 1599
da121506
TA		 1600#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1601 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1602 defined(CONFIG_CPU_S5PC100)
1603static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1604 .info = &(struct s3c24xx_uart_info) {
1605 .name = "Samsung S3C6400 UART",
1606 .type = PORT_S3C6400,
1607 .fifosize = 64,
1608 .has_divslot = 1,
1609 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1610 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1611 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1612 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1613 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1614 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1615 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1616 .num_clks = 4,
1617 .clksel_mask = S3C6400_UCON_CLKMASK,
1618 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1619 },
1620 .def_cfg = &(struct s3c2410_uartcfg) {
1621 .ucon = S3C2410_UCON_DEFAULT,
1622 .ufcon = S3C2410_UFCON_DEFAULT,
1623 },
1624};
1625#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1626#else
1627#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1628#endif
b497549a 1629
da121506
TA		 1630#ifdef CONFIG_CPU_S5PV210
1631static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1632 .info = &(struct s3c24xx_uart_info) {
1633 .name = "Samsung S5PV210 UART",
1634 .type = PORT_S3C6400,
1635 .has_divslot = 1,
1636 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1637 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1638 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1639 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1640 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1641 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1642 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1643 .num_clks = 2,
1644 .clksel_mask = S5PV210_UCON_CLKMASK,
1645 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1646 },
1647 .def_cfg = &(struct s3c2410_uartcfg) {
1648 .ucon = S5PV210_UCON_DEFAULT,
1649 .ufcon = S5PV210_UFCON_DEFAULT,
1650 },
1651 .fifosize = { 256, 64, 16, 16 },
1652};
1653#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1654#else
1655#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1656#endif
b497549a 1657
5f7b6d19 1658#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
2edb36c4
KK		 1659 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
1660 defined(CONFIG_SOC_EXYNOS5440)
da121506
TA		 1661static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1662 .info = &(struct s3c24xx_uart_info) {
1663 .name = "Samsung Exynos4 UART",
1664 .type = PORT_S3C6400,
1665 .has_divslot = 1,
1666 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1667 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1668 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1669 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1670 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1671 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1672 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1673 .num_clks = 1,
1674 .clksel_mask = 0,
1675 .clksel_shift = 0,
1676 },
1677 .def_cfg = &(struct s3c2410_uartcfg) {
1678 .ucon = S5PV210_UCON_DEFAULT,
1679 .ufcon = S5PV210_UFCON_DEFAULT,
1680 .has_fracval = 1,
1681 },
1682 .fifosize = { 256, 64, 16, 16 },
1683};
1684#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1685#else
1686#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1687#endif
b497549a 1688
da121506
TA		 1689static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1690 {
1691 .name = "s3c2410-uart",
1692 .driver_data = S3C2410_SERIAL_DRV_DATA,
1693 }, {
1694 .name = "s3c2412-uart",
1695 .driver_data = S3C2412_SERIAL_DRV_DATA,
1696 }, {
1697 .name = "s3c2440-uart",
1698 .driver_data = S3C2440_SERIAL_DRV_DATA,
1699 }, {
1700 .name = "s3c6400-uart",
1701 .driver_data = S3C6400_SERIAL_DRV_DATA,
1702 }, {
1703 .name = "s5pv210-uart",
1704 .driver_data = S5PV210_SERIAL_DRV_DATA,
1705 }, {
1706 .name = "exynos4210-uart",
1707 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1708 },
1709 { },
1710};
1711MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1712
26c919e1
TA		 1713#ifdef CONFIG_OF
1714static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 1715 { .compatible = "samsung,s3c2410-uart",
1716 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1717 { .compatible = "samsung,s3c2412-uart",
1718 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1719 { .compatible = "samsung,s3c2440-uart",
1720 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1721 { .compatible = "samsung,s3c6400-uart",
1722 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1723 { .compatible = "samsung,s5pv210-uart",
1724 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 1725 { .compatible = "samsung,exynos4210-uart",
a169a888 1726 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
26c919e1
TA		 1727 {},
1728};
1729MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 1730#endif
1731
da121506
TA		 1732static struct platform_driver samsung_serial_driver = {
1733 .probe = s3c24xx_serial_probe,
2d47b716 1734 .remove = s3c24xx_serial_remove,
da121506
TA		 1735 .id_table = s3c24xx_serial_driver_ids,
1736 .driver = {
1737 .name = "samsung-uart",
1738 .owner = THIS_MODULE,
1739 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 1740 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 1741 },
1742};
b497549a 1743
da121506 1744/* module initialisation code */
b497549a 1745
da121506
TA		 1746static int __init s3c24xx_serial_modinit(void)
1747{
1748 int ret;
1749
1750 ret = uart_register_driver(&s3c24xx_uart_drv);
1751 if (ret < 0) {
d20925e1 1752 pr_err("Failed to register Samsung UART driver\n");
e740d8f1 1753 return ret;
da121506
TA		 1754 }
1755
1756 return platform_driver_register(&samsung_serial_driver);
b497549a
BD		 1757}
1758
da121506
TA		 1759static void __exit s3c24xx_serial_modexit(void)
1760{
1761 uart_unregister_driver(&s3c24xx_uart_drv);
1762}
1763
1764module_init(s3c24xx_serial_modinit);
1765module_exit(s3c24xx_serial_modexit);
b497549a 1766
da121506 1767MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 1768MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1769MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1770MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)