projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
TTY: switch tty_flip_buffer_push
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / efm32-uart.c
CommitLineData
3afbd89c
UKK		 1#if defined(CONFIG_SERIAL_EFM32_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2#define SUPPORT_SYSRQ
3#endif
4
5#include <linux/kernel.h>
6#include <linux/module.h>
7#include <linux/io.h>
8#include <linux/platform_device.h>
9#include <linux/console.h>
10#include <linux/sysrq.h>
11#include <linux/serial_core.h>
12#include <linux/tty_flip.h>
13#include <linux/slab.h>
14#include <linux/clk.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17
18#include <linux/platform_data/efm32-uart.h>
19
20#define DRIVER_NAME "efm32-uart"
21#define DEV_NAME "ttyefm"
22
23#define UARTn_CTRL 0x00
24#define UARTn_CTRL_SYNC 0x0001
25#define UARTn_CTRL_TXBIL 0x1000
26
27#define UARTn_FRAME 0x04
28#define UARTn_FRAME_DATABITS__MASK 0x000f
29#define UARTn_FRAME_DATABITS(n) ((n) - 3)
30#define UARTn_FRAME_PARITY_NONE 0x0000
31#define UARTn_FRAME_PARITY_EVEN 0x0200
32#define UARTn_FRAME_PARITY_ODD 0x0300
33#define UARTn_FRAME_STOPBITS_HALF 0x0000
34#define UARTn_FRAME_STOPBITS_ONE 0x1000
35#define UARTn_FRAME_STOPBITS_TWO 0x3000
36
37#define UARTn_CMD 0x0c
38#define UARTn_CMD_RXEN 0x0001
39#define UARTn_CMD_RXDIS 0x0002
40#define UARTn_CMD_TXEN 0x0004
41#define UARTn_CMD_TXDIS 0x0008
42
43#define UARTn_STATUS 0x10
44#define UARTn_STATUS_TXENS 0x0002
45#define UARTn_STATUS_TXC 0x0020
46#define UARTn_STATUS_TXBL 0x0040
47#define UARTn_STATUS_RXDATAV 0x0080
48
49#define UARTn_CLKDIV 0x14
50
51#define UARTn_RXDATAX 0x18
52#define UARTn_RXDATAX_RXDATA__MASK 0x01ff
53#define UARTn_RXDATAX_PERR 0x4000
54#define UARTn_RXDATAX_FERR 0x8000
55/*
56 * This is a software only flag used for ignore_status_mask and
57 * read_status_mask! It's used for breaks that the hardware doesn't report
58 * explicitly.
59 */
60#define SW_UARTn_RXDATAX_BERR 0x2000
61
62#define UARTn_TXDATA 0x34
63
64#define UARTn_IF 0x40
65#define UARTn_IF_TXC 0x0001
66#define UARTn_IF_TXBL 0x0002
67#define UARTn_IF_RXDATAV 0x0004
68#define UARTn_IF_RXOF 0x0010
69
70#define UARTn_IFS 0x44
71#define UARTn_IFC 0x48
72#define UARTn_IEN 0x4c
73
74#define UARTn_ROUTE 0x54
75#define UARTn_ROUTE_LOCATION__MASK 0x0700
76#define UARTn_ROUTE_LOCATION(n) (((n) << 8) & UARTn_ROUTE_LOCATION__MASK)
77#define UARTn_ROUTE_RXPEN 0x0001
78#define UARTn_ROUTE_TXPEN 0x0002
79
80struct efm32_uart_port {
81 struct uart_port port;
82 unsigned int txirq;
83 struct clk *clk;
84};
85#define to_efm_port(_port) container_of(_port, struct efm32_uart_port, port)
86#define efm_debug(efm_port, format, arg...) \
87 dev_dbg(efm_port->port.dev, format, ##arg)
88
89static void efm32_uart_write32(struct efm32_uart_port *efm_port,
90 u32 value, unsigned offset)
91{
92 writel_relaxed(value, efm_port->port.membase + offset);
93}
94
95static u32 efm32_uart_read32(struct efm32_uart_port *efm_port,
96 unsigned offset)
97{
98 return readl_relaxed(efm_port->port.membase + offset);
99}
100
101static unsigned int efm32_uart_tx_empty(struct uart_port *port)
102{
103 struct efm32_uart_port *efm_port = to_efm_port(port);
104 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
105
106 if (status & UARTn_STATUS_TXC)
107 return TIOCSER_TEMT;
108 else
109 return 0;
110}
111
112static void efm32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
113{
114 /* sorry, neither handshaking lines nor loop functionallity */
115}
116
117static unsigned int efm32_uart_get_mctrl(struct uart_port *port)
118{
119 /* sorry, no handshaking lines available */
120 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
121}
122
123static void efm32_uart_stop_tx(struct uart_port *port)
124{
125 struct efm32_uart_port *efm_port = to_efm_port(port);
126 u32 ien = efm32_uart_read32(efm_port, UARTn_IEN);
127
128 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
129 ien &= ~(UARTn_IF_TXC | UARTn_IF_TXBL);
130 efm32_uart_write32(efm_port, ien, UARTn_IEN);
131}
132
133static void efm32_uart_tx_chars(struct efm32_uart_port *efm_port)
134{
135 struct uart_port *port = &efm_port->port;
136 struct circ_buf *xmit = &port->state->xmit;
137
138 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
139 UARTn_STATUS_TXBL) {
140 if (port->x_char) {
141 port->icount.tx++;
142 efm32_uart_write32(efm_port, port->x_char,
143 UARTn_TXDATA);
144 port->x_char = 0;
145 continue;
146 }
147 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
148 port->icount.tx++;
149 efm32_uart_write32(efm_port, xmit->buf[xmit->tail],
150 UARTn_TXDATA);
151 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
152 } else
153 break;
154 }
155
156 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
157 uart_write_wakeup(port);
158
159 if (!port->x_char && uart_circ_empty(xmit) &&
160 efm32_uart_read32(efm_port, UARTn_STATUS) &
161 UARTn_STATUS_TXC)
162 efm32_uart_stop_tx(port);
163}
164
165static void efm32_uart_start_tx(struct uart_port *port)
166{
167 struct efm32_uart_port *efm_port = to_efm_port(port);
168 u32 ien;
169
170 efm32_uart_write32(efm_port,
171 UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IFC);
172 ien = efm32_uart_read32(efm_port, UARTn_IEN);
173 efm32_uart_write32(efm_port,
174 ien | UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IEN);
175 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
176
177 efm32_uart_tx_chars(efm_port);
178}
179
180static void efm32_uart_stop_rx(struct uart_port *port)
181{
182 struct efm32_uart_port *efm_port = to_efm_port(port);
183
184 efm32_uart_write32(efm_port, UARTn_CMD_RXDIS, UARTn_CMD);
185}
186
187static void efm32_uart_enable_ms(struct uart_port *port)
188{
189 /* no handshake lines, no modem status interrupts */
190}
191
192static void efm32_uart_break_ctl(struct uart_port *port, int ctl)
193{
194 /* not possible without fiddling with gpios */
195}
196
92a19f9c 197static void efm32_uart_rx_chars(struct efm32_uart_port *efm_port)
3afbd89c
UKK		 198{
199 struct uart_port *port = &efm_port->port;
200
201 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
202 UARTn_STATUS_RXDATAV) {
203 u32 rxdata = efm32_uart_read32(efm_port, UARTn_RXDATAX);
204 int flag = 0;
205
206 /*
207 * This is a reserved bit and I only saw it read as 0. But to be
208 * sure not to be confused too much by new devices adhere to the
209 * warning in the reference manual that reserverd bits might
210 * read as 1 in the future.
211 */
212 rxdata &= ~SW_UARTn_RXDATAX_BERR;
213
214 port->icount.rx++;
215
216 if ((rxdata & UARTn_RXDATAX_FERR) &&
217 !(rxdata & UARTn_RXDATAX_RXDATA__MASK)) {
218 rxdata |= SW_UARTn_RXDATAX_BERR;
219 port->icount.brk++;
220 if (uart_handle_break(port))
221 continue;
222 } else if (rxdata & UARTn_RXDATAX_PERR)
223 port->icount.parity++;
224 else if (rxdata & UARTn_RXDATAX_FERR)
225 port->icount.frame++;
226
227 rxdata &= port->read_status_mask;
228
229 if (rxdata & SW_UARTn_RXDATAX_BERR)
230 flag = TTY_BREAK;
231 else if (rxdata & UARTn_RXDATAX_PERR)
232 flag = TTY_PARITY;
233 else if (rxdata & UARTn_RXDATAX_FERR)
234 flag = TTY_FRAME;
235 else if (uart_handle_sysrq_char(port,
236 rxdata & UARTn_RXDATAX_RXDATA__MASK))
237 continue;
238
92a19f9c
JS		 239 if ((rxdata & port->ignore_status_mask) == 0)
240 tty_insert_flip_char(&port->state->port,
3afbd89c
UKK		 241 rxdata & UARTn_RXDATAX_RXDATA__MASK, flag);
242 }
243}
244
245static irqreturn_t efm32_uart_rxirq(int irq, void *data)
246{
247 struct efm32_uart_port *efm_port = data;
248 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
249 int handled = IRQ_NONE;
250 struct uart_port *port = &efm_port->port;
92a19f9c 251 struct tty_port *tport = &port->state->port;
3afbd89c
UKK		 252
253 spin_lock(&port->lock);
254
3afbd89c
UKK		 255 if (irqflag & UARTn_IF_RXDATAV) {
256 efm32_uart_write32(efm_port, UARTn_IF_RXDATAV, UARTn_IFC);
92a19f9c 257 efm32_uart_rx_chars(efm_port);
3afbd89c
UKK		 258
259 handled = IRQ_HANDLED;
260 }
261
262 if (irqflag & UARTn_IF_RXOF) {
263 efm32_uart_write32(efm_port, UARTn_IF_RXOF, UARTn_IFC);
264 port->icount.overrun++;
92a19f9c 265 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
3afbd89c
UKK		 266
267 handled = IRQ_HANDLED;
268 }
269
2e124b4a 270 tty_flip_buffer_push(tport);
3afbd89c
UKK		 271
272 spin_unlock(&port->lock);
273
274 return handled;
275}
276
277static irqreturn_t efm32_uart_txirq(int irq, void *data)
278{
279 struct efm32_uart_port *efm_port = data;
280 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
281
282 /* TXBL doesn't need to be cleared */
283 if (irqflag & UARTn_IF_TXC)
284 efm32_uart_write32(efm_port, UARTn_IF_TXC, UARTn_IFC);
285
286 if (irqflag & (UARTn_IF_TXC | UARTn_IF_TXBL)) {
287 efm32_uart_tx_chars(efm_port);
288 return IRQ_HANDLED;
289 } else
290 return IRQ_NONE;
291}
292
293static int efm32_uart_startup(struct uart_port *port)
294{
295 struct efm32_uart_port *efm_port = to_efm_port(port);
296 u32 location = 0;
297 struct efm32_uart_pdata *pdata = dev_get_platdata(port->dev);
298 int ret;
299
300 if (pdata)
301 location = UARTn_ROUTE_LOCATION(pdata->location);
302
303 ret = clk_enable(efm_port->clk);
304 if (ret) {
305 efm_debug(efm_port, "failed to enable clk\n");
306 goto err_clk_enable;
307 }
308 port->uartclk = clk_get_rate(efm_port->clk);
309
310 /* Enable pins at configured location */
311 efm32_uart_write32(efm_port, location | UARTn_ROUTE_RXPEN | UARTn_ROUTE_TXPEN,
312 UARTn_ROUTE);
313
314 ret = request_irq(port->irq, efm32_uart_rxirq, 0,
315 DRIVER_NAME, efm_port);
316 if (ret) {
317 efm_debug(efm_port, "failed to register rxirq\n");
318 goto err_request_irq_rx;
319 }
320
321 /* disable all irqs */
322 efm32_uart_write32(efm_port, 0, UARTn_IEN);
323
324 ret = request_irq(efm_port->txirq, efm32_uart_txirq, 0,
325 DRIVER_NAME, efm_port);
326 if (ret) {
327 efm_debug(efm_port, "failed to register txirq\n");
328 free_irq(port->irq, efm_port);
329err_request_irq_rx:
330
331 clk_disable(efm_port->clk);
332 } else {
333 efm32_uart_write32(efm_port,
334 UARTn_IF_RXDATAV | UARTn_IF_RXOF, UARTn_IEN);
335 efm32_uart_write32(efm_port, UARTn_CMD_RXEN, UARTn_CMD);
336 }
337
338err_clk_enable:
339 return ret;
340}
341
342static void efm32_uart_shutdown(struct uart_port *port)
343{
344 struct efm32_uart_port *efm_port = to_efm_port(port);
345
346 efm32_uart_write32(efm_port, 0, UARTn_IEN);
347 free_irq(port->irq, efm_port);
348
349 clk_disable(efm_port->clk);
350}
351
352static void efm32_uart_set_termios(struct uart_port *port,
353 struct ktermios *new, struct ktermios *old)
354{
355 struct efm32_uart_port *efm_port = to_efm_port(port);
356 unsigned long flags;
357 unsigned baud;
358 u32 clkdiv;
359 u32 frame = 0;
360
361 /* no modem control lines */
362 new->c_cflag &= ~(CRTSCTS | CMSPAR);
363
364 baud = uart_get_baud_rate(port, new, old,
365 DIV_ROUND_CLOSEST(port->uartclk, 16 * 8192),
366 DIV_ROUND_CLOSEST(port->uartclk, 16));
367
368 switch (new->c_cflag & CSIZE) {
369 case CS5:
370 frame |= UARTn_FRAME_DATABITS(5);
371 break;
372 case CS6:
373 frame |= UARTn_FRAME_DATABITS(6);
374 break;
375 case CS7:
376 frame |= UARTn_FRAME_DATABITS(7);
377 break;
378 case CS8:
379 frame |= UARTn_FRAME_DATABITS(8);
380 break;
381 }
382
383 if (new->c_cflag & CSTOPB)
384 /* the receiver only verifies the first stop bit */
385 frame |= UARTn_FRAME_STOPBITS_TWO;
386 else
387 frame |= UARTn_FRAME_STOPBITS_ONE;
388
389 if (new->c_cflag & PARENB) {
390 if (new->c_cflag & PARODD)
391 frame |= UARTn_FRAME_PARITY_ODD;
392 else
393 frame |= UARTn_FRAME_PARITY_EVEN;
394 } else
395 frame |= UARTn_FRAME_PARITY_NONE;
396
397 /*
398 * the 6 lowest bits of CLKDIV are dc, bit 6 has value 0.25.
399 * port->uartclk <= 14e6, so 4 * port->uartclk doesn't overflow.
400 */
401 clkdiv = (DIV_ROUND_CLOSEST(4 * port->uartclk, 16 * baud) - 4) << 6;
402
403 spin_lock_irqsave(&port->lock, flags);
404
405 efm32_uart_write32(efm_port,
406 UARTn_CMD_TXDIS | UARTn_CMD_RXDIS, UARTn_CMD);
407
408 port->read_status_mask = UARTn_RXDATAX_RXDATA__MASK;
409 if (new->c_iflag & INPCK)
410 port->read_status_mask |=
411 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
412 if (new->c_iflag & (BRKINT | PARMRK))
413 port->read_status_mask |= SW_UARTn_RXDATAX_BERR;
414
415 port->ignore_status_mask = 0;
416 if (new->c_iflag & IGNPAR)
417 port->ignore_status_mask |=
418 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
419 if (new->c_iflag & IGNBRK)
420 port->ignore_status_mask |= SW_UARTn_RXDATAX_BERR;
421
422 uart_update_timeout(port, new->c_cflag, baud);
423
424 efm32_uart_write32(efm_port, UARTn_CTRL_TXBIL, UARTn_CTRL);
425 efm32_uart_write32(efm_port, frame, UARTn_FRAME);
426 efm32_uart_write32(efm_port, clkdiv, UARTn_CLKDIV);
427
428 efm32_uart_write32(efm_port, UARTn_CMD_TXEN | UARTn_CMD_RXEN,
429 UARTn_CMD);
430
431 spin_unlock_irqrestore(&port->lock, flags);
432}
433
434static const char *efm32_uart_type(struct uart_port *port)
435{
436 return port->type == PORT_EFMUART ? "efm32-uart" : NULL;
437}
438
439static void efm32_uart_release_port(struct uart_port *port)
440{
441 struct efm32_uart_port *efm_port = to_efm_port(port);
442
443 clk_unprepare(efm_port->clk);
444 clk_put(efm_port->clk);
445 iounmap(port->membase);
446}
447
448static int efm32_uart_request_port(struct uart_port *port)
449{
450 struct efm32_uart_port *efm_port = to_efm_port(port);
451 int ret;
452
453 port->membase = ioremap(port->mapbase, 60);
454 if (!efm_port->port.membase) {
455 ret = -ENOMEM;
456 efm_debug(efm_port, "failed to remap\n");
457 goto err_ioremap;
458 }
459
460 efm_port->clk = clk_get(port->dev, NULL);
461 if (IS_ERR(efm_port->clk)) {
462 ret = PTR_ERR(efm_port->clk);
463 efm_debug(efm_port, "failed to get clock\n");
464 goto err_clk_get;
465 }
466
467 ret = clk_prepare(efm_port->clk);
468 if (ret) {
469 clk_put(efm_port->clk);
470err_clk_get:
471
472 iounmap(port->membase);
473err_ioremap:
474 return ret;
475 }
476 return 0;
477}
478
479static void efm32_uart_config_port(struct uart_port *port, int type)
480{
481 if (type & UART_CONFIG_TYPE &&
482 !efm32_uart_request_port(port))
483 port->type = PORT_EFMUART;
484}
485
486static int efm32_uart_verify_port(struct uart_port *port,
487 struct serial_struct *serinfo)
488{
489 int ret = 0;
490
491 if (serinfo->type != PORT_UNKNOWN && serinfo->type != PORT_EFMUART)
492 ret = -EINVAL;
493
494 return ret;
495}
496
497static struct uart_ops efm32_uart_pops = {
498 .tx_empty = efm32_uart_tx_empty,
499 .set_mctrl = efm32_uart_set_mctrl,
500 .get_mctrl = efm32_uart_get_mctrl,
501 .stop_tx = efm32_uart_stop_tx,
502 .start_tx = efm32_uart_start_tx,
503 .stop_rx = efm32_uart_stop_rx,
504 .enable_ms = efm32_uart_enable_ms,
505 .break_ctl = efm32_uart_break_ctl,
506 .startup = efm32_uart_startup,
507 .shutdown = efm32_uart_shutdown,
508 .set_termios = efm32_uart_set_termios,
509 .type = efm32_uart_type,
510 .release_port = efm32_uart_release_port,
511 .request_port = efm32_uart_request_port,
512 .config_port = efm32_uart_config_port,
513 .verify_port = efm32_uart_verify_port,
514};
515
516static struct efm32_uart_port *efm32_uart_ports[5];
517
518#ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE
519static void efm32_uart_console_putchar(struct uart_port *port, int ch)
520{
521 struct efm32_uart_port *efm_port = to_efm_port(port);
522 unsigned int timeout = 0x400;
523 u32 status;
524
525 while (1) {
526 status = efm32_uart_read32(efm_port, UARTn_STATUS);
527
528 if (status & UARTn_STATUS_TXBL)
529 break;
530 if (!timeout--)
531 return;
532 }
533 efm32_uart_write32(efm_port, ch, UARTn_TXDATA);
534}
535
536static void efm32_uart_console_write(struct console *co, const char *s,
537 unsigned int count)
538{
539 struct efm32_uart_port *efm_port = efm32_uart_ports[co->index];
540 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
541 unsigned int timeout = 0x400;
542
543 if (!(status & UARTn_STATUS_TXENS))
544 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
545
546 uart_console_write(&efm_port->port, s, count,
547 efm32_uart_console_putchar);
548
549 /* Wait for the transmitter to become empty */
550 while (1) {
551 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
552 if (status & UARTn_STATUS_TXC)
553 break;
554 if (!timeout--)
555 break;
556 }
557
558 if (!(status & UARTn_STATUS_TXENS))
559 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
560}
561
562static void efm32_uart_console_get_options(struct efm32_uart_port *efm_port,
563 int *baud, int *parity, int *bits)
564{
565 u32 ctrl = efm32_uart_read32(efm_port, UARTn_CTRL);
566 u32 route, clkdiv, frame;
567
568 if (ctrl & UARTn_CTRL_SYNC)
569 /* not operating in async mode */
570 return;
571
572 route = efm32_uart_read32(efm_port, UARTn_ROUTE);
573 if (!(route & UARTn_ROUTE_TXPEN))
574 /* tx pin not routed */
575 return;
576
577 clkdiv = efm32_uart_read32(efm_port, UARTn_CLKDIV);
578
579 *baud = DIV_ROUND_CLOSEST(4 * efm_port->port.uartclk,
580 16 * (4 + (clkdiv >> 6)));
581
582 frame = efm32_uart_read32(efm_port, UARTn_FRAME);
583 if (frame & UARTn_FRAME_PARITY_ODD)
584 *parity = 'o';
585 else if (frame & UARTn_FRAME_PARITY_EVEN)
586 *parity = 'e';
587 else
588 *parity = 'n';
589
590 *bits = (frame & UARTn_FRAME_DATABITS__MASK) -
591 UARTn_FRAME_DATABITS(4) + 4;
592
593 efm_debug(efm_port, "get_opts: options=%d%c%d\n",
594 *baud, *parity, *bits);
595}
596
597static int efm32_uart_console_setup(struct console *co, char *options)
598{
599 struct efm32_uart_port *efm_port;
600 int baud = 115200;
601 int bits = 8;
602 int parity = 'n';
603 int flow = 'n';
604 int ret;
605
606 if (co->index < 0 || co->index >= ARRAY_SIZE(efm32_uart_ports)) {
607 unsigned i;
608 for (i = 0; i < ARRAY_SIZE(efm32_uart_ports); ++i) {
609 if (efm32_uart_ports[i]) {
610 pr_warn("efm32-console: fall back to console index %u (from %hhi)\n",
611 i, co->index);
612 co->index = i;
613 break;
614 }
615 }
616 }
617
618 efm_port = efm32_uart_ports[co->index];
619 if (!efm_port) {
620 pr_warn("efm32-console: No port at %d\n", co->index);
621 return -ENODEV;
622 }
623
624 ret = clk_prepare(efm_port->clk);
625 if (ret) {
626 dev_warn(efm_port->port.dev,
627 "console: clk_prepare failed: %d\n", ret);
628 return ret;
629 }
630
631 efm_port->port.uartclk = clk_get_rate(efm_port->clk);
632
633 if (options)
634 uart_parse_options(options, &baud, &parity, &bits, &flow);
635 else
636 efm32_uart_console_get_options(efm_port,
637 &baud, &parity, &bits);
638
639 return uart_set_options(&efm_port->port, co, baud, parity, bits, flow);
640}
641
642static struct uart_driver efm32_uart_reg;
643
644static struct console efm32_uart_console = {
645 .name = DEV_NAME,
646 .write = efm32_uart_console_write,
647 .device = uart_console_device,
648 .setup = efm32_uart_console_setup,
649 .flags = CON_PRINTBUFFER,
650 .index = -1,
651 .data = &efm32_uart_reg,
652};
653
654#else
655#define efm32_uart_console (*(struct console *)NULL)
656#endif /* ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE / else */
657
658static struct uart_driver efm32_uart_reg = {
659 .owner = THIS_MODULE,
660 .driver_name = DRIVER_NAME,
661 .dev_name = DEV_NAME,
662 .nr = ARRAY_SIZE(efm32_uart_ports),
663 .cons = &efm32_uart_console,
664};
665
666static int efm32_uart_probe_dt(struct platform_device *pdev,
667 struct efm32_uart_port *efm_port)
668{
669 struct device_node *np = pdev->dev.of_node;
670 int ret;
671
672 if (!np)
673 return 1;
674
675 ret = of_alias_get_id(np, "serial");
676 if (ret < 0) {
677 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
678 return ret;
679 } else {
680 efm_port->port.line = ret;
681 return 0;
682 }
683
684}
685
9671f099 686static int efm32_uart_probe(struct platform_device *pdev)
3afbd89c
UKK		 687{
688 struct efm32_uart_port *efm_port;
689 struct resource *res;
690 int ret;
691
692 efm_port = kzalloc(sizeof(*efm_port), GFP_KERNEL);
693 if (!efm_port) {
694 dev_dbg(&pdev->dev, "failed to allocate private data\n");
695 return -ENOMEM;
696 }
697
698 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
699 if (!res) {
700 ret = -ENODEV;
701 dev_dbg(&pdev->dev, "failed to determine base address\n");
702 goto err_get_base;
703 }
704
705 if (resource_size(res) < 60) {
706 ret = -EINVAL;
707 dev_dbg(&pdev->dev, "memory resource too small\n");
708 goto err_too_small;
709 }
710
711 ret = platform_get_irq(pdev, 0);
712 if (ret <= 0) {
713 dev_dbg(&pdev->dev, "failed to get rx irq\n");
714 goto err_get_rxirq;
715 }
716
717 efm_port->port.irq = ret;
718
719 ret = platform_get_irq(pdev, 1);
720 if (ret <= 0)
721 ret = efm_port->port.irq + 1;
722
723 efm_port->txirq = ret;
724
725 efm_port->port.dev = &pdev->dev;
726 efm_port->port.mapbase = res->start;
727 efm_port->port.type = PORT_EFMUART;
728 efm_port->port.iotype = UPIO_MEM32;
729 efm_port->port.fifosize = 2;
730 efm_port->port.ops = &efm32_uart_pops;
731 efm_port->port.flags = UPF_BOOT_AUTOCONF;
732
733 ret = efm32_uart_probe_dt(pdev, efm_port);
734 if (ret > 0)
735 /* not created by device tree */
736 efm_port->port.line = pdev->id;
737
738 if (efm_port->port.line >= 0 &&
739 efm_port->port.line < ARRAY_SIZE(efm32_uart_ports))
740 efm32_uart_ports[efm_port->port.line] = efm_port;
741
742 ret = uart_add_one_port(&efm32_uart_reg, &efm_port->port);
743 if (ret) {
744 dev_dbg(&pdev->dev, "failed to add port: %d\n", ret);
745
746 if (pdev->id >= 0 && pdev->id < ARRAY_SIZE(efm32_uart_ports))
747 efm32_uart_ports[pdev->id] = NULL;
748err_get_rxirq:
749err_too_small:
750err_get_base:
751 kfree(efm_port);
752 } else {
753 platform_set_drvdata(pdev, efm_port);
754 dev_dbg(&pdev->dev, "\\o/\n");
755 }
756
757 return ret;
758}
759
ae8d8a14 760static int efm32_uart_remove(struct platform_device *pdev)
3afbd89c
UKK		 761{
762 struct efm32_uart_port *efm_port = platform_get_drvdata(pdev);
763
764 platform_set_drvdata(pdev, NULL);
765
766 uart_remove_one_port(&efm32_uart_reg, &efm_port->port);
767
768 if (pdev->id >= 0 && pdev->id < ARRAY_SIZE(efm32_uart_ports))
769 efm32_uart_ports[pdev->id] = NULL;
770
771 kfree(efm_port);
772
773 return 0;
774}
775
776static struct of_device_id efm32_uart_dt_ids[] = {
777 {
778 .compatible = "efm32,uart",
779 }, {
780 /* sentinel */
781 }
782};
783MODULE_DEVICE_TABLE(of, efm32_uart_dt_ids);
784
785static struct platform_driver efm32_uart_driver = {
786 .probe = efm32_uart_probe,
2d47b716 787 .remove = efm32_uart_remove,
3afbd89c
UKK		 788
789 .driver = {
790 .name = DRIVER_NAME,
791 .owner = THIS_MODULE,
792 .of_match_table = efm32_uart_dt_ids,
793 },
794};
795
796static int __init efm32_uart_init(void)
797{
798 int ret;
799
800 ret = uart_register_driver(&efm32_uart_reg);
801 if (ret)
802 return ret;
803
804 ret = platform_driver_register(&efm32_uart_driver);
805 if (ret)
806 uart_unregister_driver(&efm32_uart_reg);
807
808 pr_info("EFM32 UART/USART driver\n");
809
810 return ret;
811}
812module_init(efm32_uart_init);
813
814static void __exit efm32_uart_exit(void)
815{
816 platform_driver_unregister(&efm32_uart_driver);
817 uart_unregister_driver(&efm32_uart_reg);
818}
819
820MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
821MODULE_DESCRIPTION("EFM32 UART/USART driver");
822MODULE_LICENSE("GPL v2");
823MODULE_ALIAS("platform:" DRIVER_NAME);
kernel source for telekom puls (alcatel/mediatek)