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serial: make 8250 timeout use the specified IRQ handler
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / 8250.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
1da177e4
LT		 41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
b70ac771
DM		 47#ifdef CONFIG_SPARC
48#include "suncore.h"
49#endif
50
1da177e4
LT		 51/*
52 * Configuration:
40663cc7 53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 54 * is unsafe when used on edge-triggered interrupts.
55 */
408b664a 56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 57
a61c2d78
DJ		 58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
8440838b
DM		 60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
d41a4b51
CE		 67static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
1da177e4
LT		 69/*
70 * Debugging.
71 */
72#if 0
73#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74#else
75#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76#endif
77
78#if 0
79#define DEBUG_INTR(fmt...) printk(fmt)
80#else
81#define DEBUG_INTR(fmt...) do { } while (0)
82#endif
83
e7328ae1 84#define PASS_LIMIT 512
1da177e4 85
bca47613
DH		 86#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
1da177e4
LT		 89/*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94#define is_real_interrupt(irq) ((irq) != 0)
95
1da177e4
LT		 96#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97#define CONFIG_SERIAL_DETECT_IRQ 1
98#endif
1da177e4
LT		 99#ifdef CONFIG_SERIAL_8250_MANY_PORTS
100#define CONFIG_SERIAL_MANY_PORTS 1
101#endif
102
103/*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107#define CONFIG_HUB6 1
108
a4ed1e41 109#include <asm/serial.h>
1da177e4
LT		 110/*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115#ifndef SERIAL_PORT_DFNS
116#define SERIAL_PORT_DFNS
117#endif
118
cb3592be 119static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121};
122
026d02a2 123#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 124
125#ifdef CONFIG_SERIAL_8250_RSA
126
127#define PORT_RSA_MAX 4
128static unsigned long probe_rsa[PORT_RSA_MAX];
129static unsigned int probe_rsa_count;
130#endif /* CONFIG_SERIAL_8250_RSA */
131
1da177e4 132struct irq_info {
25db8ad5
AC		 133 struct hlist_node node;
134 int irq;
135 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 136 struct list_head *head;
137};
138
25db8ad5
AC		 139#define NR_IRQ_HASH 32 /* Can be adjusted later */
140static struct hlist_head irq_lists[NR_IRQ_HASH];
141static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 142
143/*
144 * Here we define the default xmit fifo size used for each type of UART.
145 */
146static const struct serial8250_config uart_config[] = {
147 [PORT_UNKNOWN] = {
148 .name = "unknown",
149 .fifo_size = 1,
150 .tx_loadsz = 1,
151 },
152 [PORT_8250] = {
153 .name = "8250",
154 .fifo_size = 1,
155 .tx_loadsz = 1,
156 },
157 [PORT_16450] = {
158 .name = "16450",
159 .fifo_size = 1,
160 .tx_loadsz = 1,
161 },
162 [PORT_16550] = {
163 .name = "16550",
164 .fifo_size = 1,
165 .tx_loadsz = 1,
166 },
167 [PORT_16550A] = {
168 .name = "16550A",
169 .fifo_size = 16,
170 .tx_loadsz = 16,
171 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 .flags = UART_CAP_FIFO,
173 },
174 [PORT_CIRRUS] = {
175 .name = "Cirrus",
176 .fifo_size = 1,
177 .tx_loadsz = 1,
178 },
179 [PORT_16650] = {
180 .name = "ST16650",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16650V2] = {
186 .name = "ST16650V2",
187 .fifo_size = 32,
188 .tx_loadsz = 16,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
190 UART_FCR_T_TRIG_00,
191 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
192 },
193 [PORT_16750] = {
194 .name = "TI16750",
195 .fifo_size = 64,
196 .tx_loadsz = 64,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
198 UART_FCR7_64BYTE,
199 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
200 },
201 [PORT_STARTECH] = {
202 .name = "Startech",
203 .fifo_size = 1,
204 .tx_loadsz = 1,
205 },
206 [PORT_16C950] = {
207 .name = "16C950/954",
208 .fifo_size = 128,
209 .tx_loadsz = 128,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 211 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
212 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 213 },
214 [PORT_16654] = {
215 .name = "ST16654",
216 .fifo_size = 64,
217 .tx_loadsz = 32,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
219 UART_FCR_T_TRIG_10,
220 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
221 },
222 [PORT_16850] = {
223 .name = "XR16850",
224 .fifo_size = 128,
225 .tx_loadsz = 128,
226 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
227 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
228 },
229 [PORT_RSA] = {
230 .name = "RSA",
231 .fifo_size = 2048,
232 .tx_loadsz = 2048,
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
234 .flags = UART_CAP_FIFO,
235 },
236 [PORT_NS16550A] = {
237 .name = "NS16550A",
238 .fifo_size = 16,
239 .tx_loadsz = 16,
240 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
241 .flags = UART_CAP_FIFO | UART_NATSEMI,
242 },
243 [PORT_XSCALE] = {
244 .name = "XScale",
245 .fifo_size = 32,
246 .tx_loadsz = 32,
247 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 248 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 249 },
bd71c182
TK		 250 [PORT_RM9000] = {
251 .name = "RM9000",
252 .fifo_size = 16,
253 .tx_loadsz = 16,
254 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 255 .flags = UART_CAP_FIFO,
256 },
257 [PORT_OCTEON] = {
258 .name = "OCTEON",
259 .fifo_size = 64,
260 .tx_loadsz = 64,
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 262 .flags = UART_CAP_FIFO,
263 },
08e0992f
FF		 264 [PORT_AR7] = {
265 .name = "AR7",
266 .fifo_size = 16,
267 .tx_loadsz = 16,
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
269 .flags = UART_CAP_FIFO | UART_CAP_AFE,
270 },
235dae5d
PL		 271 [PORT_U6_16550A] = {
272 .name = "U6_16550A",
273 .fifo_size = 64,
274 .tx_loadsz = 64,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276 .flags = UART_CAP_FIFO | UART_CAP_AFE,
277 },
4539c24f
SW		 278 [PORT_TEGRA] = {
279 .name = "Tegra",
280 .fifo_size = 32,
281 .tx_loadsz = 8,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
283 UART_FCR_T_TRIG_01,
284 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
285 },
06315348
SH		 286 [PORT_XR17D15X] = {
287 .name = "XR17D15X",
288 .fifo_size = 64,
289 .tx_loadsz = 64,
290 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
291 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
292 },
1da177e4
LT		 293};
294
12bf3f24 295#if defined(CONFIG_MIPS_ALCHEMY)
21c614a7
PA		 296
297/* Au1x00 UART hardware has a weird register layout */
298static const u8 au_io_in_map[] = {
299 [UART_RX] = 0,
300 [UART_IER] = 2,
301 [UART_IIR] = 3,
302 [UART_LCR] = 5,
303 [UART_MCR] = 6,
304 [UART_LSR] = 7,
305 [UART_MSR] = 8,
306};
307
308static const u8 au_io_out_map[] = {
309 [UART_TX] = 1,
310 [UART_IER] = 2,
311 [UART_FCR] = 4,
312 [UART_LCR] = 5,
313 [UART_MCR] = 6,
314};
315
316/* sane hardware needs no mapping */
7d6a07d1 317static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 318{
7d6a07d1 319 if (p->iotype != UPIO_AU)
21c614a7
PA		 320 return offset;
321 return au_io_in_map[offset];
322}
323
7d6a07d1 324static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 325{
7d6a07d1 326 if (p->iotype != UPIO_AU)
21c614a7
PA		 327 return offset;
328 return au_io_out_map[offset];
329}
330
6f803cd0 331#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 332
333static const u8
334 regmap_in[8] = {
335 [UART_RX] = 0x00,
336 [UART_IER] = 0x0c,
337 [UART_IIR] = 0x14,
338 [UART_LCR] = 0x1c,
339 [UART_MCR] = 0x20,
340 [UART_LSR] = 0x24,
341 [UART_MSR] = 0x28,
342 [UART_SCR] = 0x2c
343 },
344 regmap_out[8] = {
345 [UART_TX] = 0x04,
346 [UART_IER] = 0x0c,
347 [UART_FCR] = 0x18,
348 [UART_LCR] = 0x1c,
349 [UART_MCR] = 0x20,
350 [UART_LSR] = 0x24,
351 [UART_MSR] = 0x28,
352 [UART_SCR] = 0x2c
353 };
354
7d6a07d1 355static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 356{
7d6a07d1 357 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 358 return offset;
359 return regmap_in[offset];
360}
361
7d6a07d1 362static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 363{
7d6a07d1 364 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 365 return offset;
366 return regmap_out[offset];
367}
368
21c614a7
PA		 369#else
370
371/* sane hardware needs no mapping */
372#define map_8250_in_reg(up, offset) (offset)
373#define map_8250_out_reg(up, offset) (offset)
374
375#endif
376
7d6a07d1 377static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 378{
7d6a07d1
DD		 379 offset = map_8250_in_reg(p, offset) << p->regshift;
380 outb(p->hub6 - 1 + offset, p->iobase);
381 return inb(p->iobase + 1);
382}
1da177e4 383
7d6a07d1
DD		 384static void hub6_serial_out(struct uart_port *p, int offset, int value)
385{
386 offset = map_8250_out_reg(p, offset) << p->regshift;
387 outb(p->hub6 - 1 + offset, p->iobase);
388 outb(value, p->iobase + 1);
389}
1da177e4 390
7d6a07d1
DD		 391static unsigned int mem_serial_in(struct uart_port *p, int offset)
392{
393 offset = map_8250_in_reg(p, offset) << p->regshift;
394 return readb(p->membase + offset);
395}
1da177e4 396
7d6a07d1
DD		 397static void mem_serial_out(struct uart_port *p, int offset, int value)
398{
399 offset = map_8250_out_reg(p, offset) << p->regshift;
400 writeb(value, p->membase + offset);
401}
402
403static void mem32_serial_out(struct uart_port *p, int offset, int value)
404{
405 offset = map_8250_out_reg(p, offset) << p->regshift;
406 writel(value, p->membase + offset);
407}
408
409static unsigned int mem32_serial_in(struct uart_port *p, int offset)
410{
411 offset = map_8250_in_reg(p, offset) << p->regshift;
412 return readl(p->membase + offset);
413}
1da177e4 414
7d6a07d1
DD		 415static unsigned int au_serial_in(struct uart_port *p, int offset)
416{
417 offset = map_8250_in_reg(p, offset) << p->regshift;
418 return __raw_readl(p->membase + offset);
419}
420
421static void au_serial_out(struct uart_port *p, int offset, int value)
422{
423 offset = map_8250_out_reg(p, offset) << p->regshift;
424 __raw_writel(value, p->membase + offset);
425}
21c614a7 426
7d6a07d1
DD		 427static unsigned int io_serial_in(struct uart_port *p, int offset)
428{
429 offset = map_8250_in_reg(p, offset) << p->regshift;
430 return inb(p->iobase + offset);
431}
432
433static void io_serial_out(struct uart_port *p, int offset, int value)
434{
435 offset = map_8250_out_reg(p, offset) << p->regshift;
436 outb(value, p->iobase + offset);
437}
438
583d28e9
JI		 439static int serial8250_default_handle_irq(struct uart_port *port);
440
7d6a07d1
DD		 441static void set_io_from_upio(struct uart_port *p)
442{
49d5741b
JI		 443 struct uart_8250_port *up =
444 container_of(p, struct uart_8250_port, port);
7d6a07d1 445 switch (p->iotype) {
1da177e4 446 case UPIO_HUB6:
7d6a07d1
DD		 447 p->serial_in = hub6_serial_in;
448 p->serial_out = hub6_serial_out;
1da177e4
LT		 449 break;
450
451 case UPIO_MEM:
7d6a07d1
DD		 452 p->serial_in = mem_serial_in;
453 p->serial_out = mem_serial_out;
1da177e4
LT		 454 break;
455
bd71c182 456 case UPIO_RM9000:
1da177e4 457 case UPIO_MEM32:
7d6a07d1
DD		 458 p->serial_in = mem32_serial_in;
459 p->serial_out = mem32_serial_out;
1da177e4
LT		 460 break;
461
21c614a7 462 case UPIO_AU:
7d6a07d1
DD		 463 p->serial_in = au_serial_in;
464 p->serial_out = au_serial_out;
21c614a7 465 break;
12bf3f24 466
1da177e4 467 default:
7d6a07d1
DD		 468 p->serial_in = io_serial_in;
469 p->serial_out = io_serial_out;
470 break;
1da177e4 471 }
b8e7e40a
AC		 472 /* Remember loaded iotype */
473 up->cur_iotype = p->iotype;
583d28e9 474 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 475}
476
40b36daa
AW		 477static void
478serial_out_sync(struct uart_8250_port *up, int offset, int value)
479{
7d6a07d1
DD		 480 struct uart_port *p = &up->port;
481 switch (p->iotype) {
40b36daa
AW		 482 case UPIO_MEM:
483 case UPIO_MEM32:
40b36daa 484 case UPIO_AU:
7d6a07d1
DD		 485 p->serial_out(p, offset, value);
486 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 487 break;
488 default:
7d6a07d1 489 p->serial_out(p, offset, value);
40b36daa
AW		 490 }
491}
492
7d6a07d1
DD		 493#define serial_in(up, offset) \
494 (up->port.serial_in(&(up)->port, (offset)))
495#define serial_out(up, offset, value) \
496 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 497/*
498 * We used to support using pause I/O for certain machines. We
499 * haven't supported this for a while, but just in case it's badly
500 * needed for certain old 386 machines, I've left these #define's
501 * in....
502 */
503#define serial_inp(up, offset) serial_in(up, offset)
504#define serial_outp(up, offset, value) serial_out(up, offset, value)
505
b32b19b8
JAH		 506/* Uart divisor latch read */
507static inline int _serial_dl_read(struct uart_8250_port *up)
508{
509 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
510}
511
512/* Uart divisor latch write */
513static inline void _serial_dl_write(struct uart_8250_port *up, int value)
514{
515 serial_outp(up, UART_DLL, value & 0xff);
516 serial_outp(up, UART_DLM, value >> 8 & 0xff);
517}
518
12bf3f24 519#if defined(CONFIG_MIPS_ALCHEMY)
b32b19b8
JAH		 520/* Au1x00 haven't got a standard divisor latch */
521static int serial_dl_read(struct uart_8250_port *up)
522{
523 if (up->port.iotype == UPIO_AU)
524 return __raw_readl(up->port.membase + 0x28);
525 else
526 return _serial_dl_read(up);
527}
528
529static void serial_dl_write(struct uart_8250_port *up, int value)
530{
531 if (up->port.iotype == UPIO_AU)
532 __raw_writel(value, up->port.membase + 0x28);
533 else
534 _serial_dl_write(up, value);
535}
6f803cd0 536#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 537static int serial_dl_read(struct uart_8250_port *up)
538{
539 return (up->port.iotype == UPIO_RM9000) ?
540 (((__raw_readl(up->port.membase + 0x10) << 8) |
541 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
542 _serial_dl_read(up);
543}
544
545static void serial_dl_write(struct uart_8250_port *up, int value)
546{
547 if (up->port.iotype == UPIO_RM9000) {
548 __raw_writel(value, up->port.membase + 0x08);
549 __raw_writel(value >> 8, up->port.membase + 0x10);
550 } else {
551 _serial_dl_write(up, value);
552 }
553}
b32b19b8
JAH		 554#else
555#define serial_dl_read(up) _serial_dl_read(up)
556#define serial_dl_write(up, value) _serial_dl_write(up, value)
557#endif
1da177e4
LT		 558
559/*
560 * For the 16C950
561 */
562static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
563{
564 serial_out(up, UART_SCR, offset);
565 serial_out(up, UART_ICR, value);
566}
567
568static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
569{
570 unsigned int value;
571
572 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
573 serial_out(up, UART_SCR, offset);
574 value = serial_in(up, UART_ICR);
575 serial_icr_write(up, UART_ACR, up->acr);
576
577 return value;
578}
579
580/*
581 * FIFO support.
582 */
b5d674ab 583static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 584{
585 if (p->capabilities & UART_CAP_FIFO) {
586 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
587 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
588 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
589 serial_outp(p, UART_FCR, 0);
590 }
591}
592
593/*
594 * IER sleep support. UARTs which have EFRs need the "extended
595 * capability" bit enabled. Note that on XR16C850s, we need to
596 * reset LCR to write to IER.
597 */
b5d674ab 598static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 599{
600 if (p->capabilities & UART_CAP_SLEEP) {
601 if (p->capabilities & UART_CAP_EFR) {
662b083a 602 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 603 serial_outp(p, UART_EFR, UART_EFR_ECB);
604 serial_outp(p, UART_LCR, 0);
605 }
606 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
607 if (p->capabilities & UART_CAP_EFR) {
662b083a 608 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 609 serial_outp(p, UART_EFR, 0);
610 serial_outp(p, UART_LCR, 0);
611 }
612 }
613}
614
615#ifdef CONFIG_SERIAL_8250_RSA
616/*
617 * Attempts to turn on the RSA FIFO. Returns zero on failure.
618 * We set the port uart clock rate if we succeed.
619 */
620static int __enable_rsa(struct uart_8250_port *up)
621{
622 unsigned char mode;
623 int result;
624
625 mode = serial_inp(up, UART_RSA_MSR);
626 result = mode & UART_RSA_MSR_FIFO;
627
628 if (!result) {
629 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
630 mode = serial_inp(up, UART_RSA_MSR);
631 result = mode & UART_RSA_MSR_FIFO;
632 }
633
634 if (result)
635 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
636
637 return result;
638}
639
640static void enable_rsa(struct uart_8250_port *up)
641{
642 if (up->port.type == PORT_RSA) {
643 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
644 spin_lock_irq(&up->port.lock);
645 __enable_rsa(up);
646 spin_unlock_irq(&up->port.lock);
647 }
648 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
649 serial_outp(up, UART_RSA_FRR, 0);
650 }
651}
652
653/*
654 * Attempts to turn off the RSA FIFO. Returns zero on failure.
655 * It is unknown why interrupts were disabled in here. However,
656 * the caller is expected to preserve this behaviour by grabbing
657 * the spinlock before calling this function.
658 */
659static void disable_rsa(struct uart_8250_port *up)
660{
661 unsigned char mode;
662 int result;
663
664 if (up->port.type == PORT_RSA &&
665 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
666 spin_lock_irq(&up->port.lock);
667
668 mode = serial_inp(up, UART_RSA_MSR);
669 result = !(mode & UART_RSA_MSR_FIFO);
670
671 if (!result) {
672 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
673 mode = serial_inp(up, UART_RSA_MSR);
674 result = !(mode & UART_RSA_MSR_FIFO);
675 }
676
677 if (result)
678 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
679 spin_unlock_irq(&up->port.lock);
680 }
681}
682#endif /* CONFIG_SERIAL_8250_RSA */
683
684/*
685 * This is a quickie test to see how big the FIFO is.
686 * It doesn't work at all the time, more's the pity.
687 */
688static int size_fifo(struct uart_8250_port *up)
689{
b32b19b8
JAH		 690 unsigned char old_fcr, old_mcr, old_lcr;
691 unsigned short old_dl;
1da177e4
LT		 692 int count;
693
694 old_lcr = serial_inp(up, UART_LCR);
695 serial_outp(up, UART_LCR, 0);
696 old_fcr = serial_inp(up, UART_FCR);
697 old_mcr = serial_inp(up, UART_MCR);
698 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
699 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
700 serial_outp(up, UART_MCR, UART_MCR_LOOP);
662b083a 701 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 702 old_dl = serial_dl_read(up);
703 serial_dl_write(up, 0x0001);
1da177e4
LT		 704 serial_outp(up, UART_LCR, 0x03);
705 for (count = 0; count < 256; count++)
706 serial_outp(up, UART_TX, count);
707 mdelay(20);/* FIXME - schedule_timeout */
708 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
709 (count < 256); count++)
710 serial_inp(up, UART_RX);
711 serial_outp(up, UART_FCR, old_fcr);
712 serial_outp(up, UART_MCR, old_mcr);
662b083a 713 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 714 serial_dl_write(up, old_dl);
1da177e4
LT		 715 serial_outp(up, UART_LCR, old_lcr);
716
717 return count;
718}
719
720/*
721 * Read UART ID using the divisor method - set DLL and DLM to zero
722 * and the revision will be in DLL and device type in DLM. We
723 * preserve the device state across this.
724 */
725static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
726{
727 unsigned char old_dll, old_dlm, old_lcr;
728 unsigned int id;
729
730 old_lcr = serial_inp(p, UART_LCR);
662b083a 731 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 732
733 old_dll = serial_inp(p, UART_DLL);
734 old_dlm = serial_inp(p, UART_DLM);
735
736 serial_outp(p, UART_DLL, 0);
737 serial_outp(p, UART_DLM, 0);
738
739 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
740
741 serial_outp(p, UART_DLL, old_dll);
742 serial_outp(p, UART_DLM, old_dlm);
743 serial_outp(p, UART_LCR, old_lcr);
744
745 return id;
746}
747
748/*
749 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
750 * When this function is called we know it is at least a StarTech
751 * 16650 V2, but it might be one of several StarTech UARTs, or one of
752 * its clones. (We treat the broken original StarTech 16650 V1 as a
753 * 16550, and why not? Startech doesn't seem to even acknowledge its
754 * existence.)
bd71c182 755 *
1da177e4
LT		 756 * What evil have men's minds wrought...
757 */
758static void autoconfig_has_efr(struct uart_8250_port *up)
759{
760 unsigned int id1, id2, id3, rev;
761
762 /*
763 * Everything with an EFR has SLEEP
764 */
765 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
766
767 /*
768 * First we check to see if it's an Oxford Semiconductor UART.
769 *
770 * If we have to do this here because some non-National
771 * Semiconductor clone chips lock up if you try writing to the
772 * LSR register (which serial_icr_read does)
773 */
774
775 /*
776 * Check for Oxford Semiconductor 16C950.
777 *
778 * EFR [4] must be set else this test fails.
779 *
780 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
781 * claims that it's needed for 952 dual UART's (which are not
782 * recommended for new designs).
783 */
784 up->acr = 0;
662b083a 785 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 786 serial_out(up, UART_EFR, UART_EFR_ECB);
787 serial_out(up, UART_LCR, 0x00);
788 id1 = serial_icr_read(up, UART_ID1);
789 id2 = serial_icr_read(up, UART_ID2);
790 id3 = serial_icr_read(up, UART_ID3);
791 rev = serial_icr_read(up, UART_REV);
792
793 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
794
795 if (id1 == 0x16 && id2 == 0xC9 &&
796 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
797 up->port.type = PORT_16C950;
4ba5e35d
RK		 798
799 /*
800 * Enable work around for the Oxford Semiconductor 952 rev B
801 * chip which causes it to seriously miscalculate baud rates
802 * when DLL is 0.
803 */
804 if (id3 == 0x52 && rev == 0x01)
805 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 806 return;
807 }
bd71c182 808
1da177e4
LT		 809 /*
810 * We check for a XR16C850 by setting DLL and DLM to 0, and then
811 * reading back DLL and DLM. The chip type depends on the DLM
812 * value read back:
813 * 0x10 - XR16C850 and the DLL contains the chip revision.
814 * 0x12 - XR16C2850.
815 * 0x14 - XR16C854.
816 */
817 id1 = autoconfig_read_divisor_id(up);
818 DEBUG_AUTOCONF("850id=%04x ", id1);
819
820 id2 = id1 >> 8;
821 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 822 up->port.type = PORT_16850;
823 return;
824 }
825
826 /*
827 * It wasn't an XR16C850.
828 *
829 * We distinguish between the '654 and the '650 by counting
830 * how many bytes are in the FIFO. I'm using this for now,
831 * since that's the technique that was sent to me in the
832 * serial driver update, but I'm not convinced this works.
833 * I've had problems doing this in the past. -TYT
834 */
835 if (size_fifo(up) == 64)
836 up->port.type = PORT_16654;
837 else
838 up->port.type = PORT_16650V2;
839}
840
841/*
842 * We detected a chip without a FIFO. Only two fall into
843 * this category - the original 8250 and the 16450. The
844 * 16450 has a scratch register (accessible with LCR=0)
845 */
846static void autoconfig_8250(struct uart_8250_port *up)
847{
848 unsigned char scratch, status1, status2;
849
850 up->port.type = PORT_8250;
851
852 scratch = serial_in(up, UART_SCR);
853 serial_outp(up, UART_SCR, 0xa5);
854 status1 = serial_in(up, UART_SCR);
855 serial_outp(up, UART_SCR, 0x5a);
856 status2 = serial_in(up, UART_SCR);
857 serial_outp(up, UART_SCR, scratch);
858
859 if (status1 == 0xa5 && status2 == 0x5a)
860 up->port.type = PORT_16450;
861}
862
863static int broken_efr(struct uart_8250_port *up)
864{
865 /*
866 * Exar ST16C2550 "A2" devices incorrectly detect as
867 * having an EFR, and report an ID of 0x0201. See
631dd1a8 868 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 869 */
870 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
871 return 1;
872
873 return 0;
874}
875
0d0389e5
YK		 876static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
877{
878 unsigned char status;
879
880 status = serial_in(up, 0x04); /* EXCR2 */
881#define PRESL(x) ((x) & 0x30)
882 if (PRESL(status) == 0x10) {
883 /* already in high speed mode */
884 return 0;
885 } else {
886 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
887 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
888 serial_outp(up, 0x04, status);
889 }
890 return 1;
891}
892
1da177e4
LT		 893/*
894 * We know that the chip has FIFOs. Does it have an EFR? The
895 * EFR is located in the same register position as the IIR and
896 * we know the top two bits of the IIR are currently set. The
897 * EFR should contain zero. Try to read the EFR.
898 */
899static void autoconfig_16550a(struct uart_8250_port *up)
900{
901 unsigned char status1, status2;
902 unsigned int iersave;
903
904 up->port.type = PORT_16550A;
905 up->capabilities |= UART_CAP_FIFO;
906
907 /*
908 * Check for presence of the EFR when DLAB is set.
909 * Only ST16C650V1 UARTs pass this test.
910 */
662b083a 911 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 912 if (serial_in(up, UART_EFR) == 0) {
913 serial_outp(up, UART_EFR, 0xA8);
914 if (serial_in(up, UART_EFR) != 0) {
915 DEBUG_AUTOCONF("EFRv1 ");
916 up->port.type = PORT_16650;
917 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
918 } else {
919 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
920 }
921 serial_outp(up, UART_EFR, 0);
922 return;
923 }
924
925 /*
926 * Maybe it requires 0xbf to be written to the LCR.
927 * (other ST16C650V2 UARTs, TI16C752A, etc)
928 */
662b083a 929 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 930 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
931 DEBUG_AUTOCONF("EFRv2 ");
932 autoconfig_has_efr(up);
933 return;
934 }
935
936 /*
937 * Check for a National Semiconductor SuperIO chip.
938 * Attempt to switch to bank 2, read the value of the LOOP bit
939 * from EXCR1. Switch back to bank 0, change it in MCR. Then
940 * switch back to bank 2, read it from EXCR1 again and check
941 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 942 */
943 serial_outp(up, UART_LCR, 0);
944 status1 = serial_in(up, UART_MCR);
945 serial_outp(up, UART_LCR, 0xE0);
946 status2 = serial_in(up, 0x02); /* EXCR1 */
947
948 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
949 serial_outp(up, UART_LCR, 0);
950 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
951 serial_outp(up, UART_LCR, 0xE0);
952 status2 = serial_in(up, 0x02); /* EXCR1 */
953 serial_outp(up, UART_LCR, 0);
954 serial_outp(up, UART_MCR, status1);
955
956 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 957 unsigned short quot;
958
1da177e4 959 serial_outp(up, UART_LCR, 0xE0);
857dde2e 960
b32b19b8 961 quot = serial_dl_read(up);
857dde2e
DW		 962 quot <<= 3;
963
0d0389e5
YK		 964 if (ns16550a_goto_highspeed(up))
965 serial_dl_write(up, quot);
857dde2e 966
1da177e4 967 serial_outp(up, UART_LCR, 0);
1da177e4 968
857dde2e 969 up->port.uartclk = 921600*16;
1da177e4
LT		 970 up->port.type = PORT_NS16550A;
971 up->capabilities |= UART_NATSEMI;
972 return;
973 }
974 }
975
976 /*
977 * No EFR. Try to detect a TI16750, which only sets bit 5 of
978 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
979 * Try setting it with and without DLAB set. Cheap clones
980 * set bit 5 without DLAB set.
981 */
982 serial_outp(up, UART_LCR, 0);
983 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
984 status1 = serial_in(up, UART_IIR) >> 5;
985 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
662b083a 986 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 987 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
988 status2 = serial_in(up, UART_IIR) >> 5;
989 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
990 serial_outp(up, UART_LCR, 0);
991
992 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
993
994 if (status1 == 6 && status2 == 7) {
995 up->port.type = PORT_16750;
996 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
997 return;
998 }
999
1000 /*
1001 * Try writing and reading the UART_IER_UUE bit (b6).
1002 * If it works, this is probably one of the Xscale platform's
1003 * internal UARTs.
1004 * We're going to explicitly set the UUE bit to 0 before
1005 * trying to write and read a 1 just to make sure it's not
1006 * already a 1 and maybe locked there before we even start start.
1007 */
1008 iersave = serial_in(up, UART_IER);
1009 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1010 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1011 /*
1012 * OK it's in a known zero state, try writing and reading
1013 * without disturbing the current state of the other bits.
1014 */
1015 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1016 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1017 /*
1018 * It's an Xscale.
1019 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1020 */
1021 DEBUG_AUTOCONF("Xscale ");
1022 up->port.type = PORT_XSCALE;
5568181f 1023 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 1024 return;
1025 }
1026 } else {
1027 /*
1028 * If we got here we couldn't force the IER_UUE bit to 0.
1029 * Log it and continue.
1030 */
1031 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1032 }
1033 serial_outp(up, UART_IER, iersave);
235dae5d 1034
06315348
SH		 1035 /*
1036 * Exar uarts have EFR in a weird location
1037 */
1038 if (up->port.flags & UPF_EXAR_EFR) {
1039 up->port.type = PORT_XR17D15X;
1040 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1041 }
1042
235dae5d
PL		 1043 /*
1044 * We distinguish between 16550A and U6 16550A by counting
1045 * how many bytes are in the FIFO.
1046 */
1047 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1048 up->port.type = PORT_U6_16550A;
1049 up->capabilities |= UART_CAP_AFE;
1050 }
1da177e4
LT		 1051}
1052
1053/*
1054 * This routine is called by rs_init() to initialize a specific serial
1055 * port. It determines what type of UART chip this serial port is
1056 * using: 8250, 16450, 16550, 16550A. The important question is
1057 * whether or not this UART is a 16550A or not, since this will
1058 * determine whether or not we can use its FIFO features or not.
1059 */
1060static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1061{
1062 unsigned char status1, scratch, scratch2, scratch3;
1063 unsigned char save_lcr, save_mcr;
1064 unsigned long flags;
1065
1066 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1067 return;
1068
80647b95 1069 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
8440838b 1070 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1071
1072 /*
1073 * We really do need global IRQs disabled here - we're going to
1074 * be frobbing the chips IRQ enable register to see if it exists.
1075 */
1076 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1077
1078 up->capabilities = 0;
4ba5e35d 1079 up->bugs = 0;
1da177e4
LT		 1080
1081 if (!(up->port.flags & UPF_BUGGY_UART)) {
1082 /*
1083 * Do a simple existence test first; if we fail this,
1084 * there's no point trying anything else.
bd71c182 1085 *
1da177e4
LT		 1086 * 0x80 is used as a nonsense port to prevent against
1087 * false positives due to ISA bus float. The
1088 * assumption is that 0x80 is a non-existent port;
1089 * which should be safe since include/asm/io.h also
1090 * makes this assumption.
1091 *
1092 * Note: this is safe as long as MCR bit 4 is clear
1093 * and the device is in "PC" mode.
1094 */
1095 scratch = serial_inp(up, UART_IER);
1096 serial_outp(up, UART_IER, 0);
1097#ifdef __i386__
1098 outb(0xff, 0x080);
1099#endif
48212008
TH		 1100 /*
1101 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1102 * 16C754B) allow only to modify them if an EFR bit is set.
1103 */
1104 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1105 serial_outp(up, UART_IER, 0x0F);
1106#ifdef __i386__
1107 outb(0, 0x080);
1108#endif
48212008 1109 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1110 serial_outp(up, UART_IER, scratch);
1111 if (scratch2 != 0 || scratch3 != 0x0F) {
1112 /*
1113 * We failed; there's nothing here
1114 */
1115 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1116 scratch2, scratch3);
1117 goto out;
1118 }
1119 }
1120
1121 save_mcr = serial_in(up, UART_MCR);
1122 save_lcr = serial_in(up, UART_LCR);
1123
bd71c182 1124 /*
1da177e4
LT		 1125 * Check to see if a UART is really there. Certain broken
1126 * internal modems based on the Rockwell chipset fail this
1127 * test, because they apparently don't implement the loopback
1128 * test mode. So this test is skipped on the COM 1 through
1129 * COM 4 ports. This *should* be safe, since no board
1130 * manufacturer would be stupid enough to design a board
1131 * that conflicts with COM 1-4 --- we hope!
1132 */
1133 if (!(up->port.flags & UPF_SKIP_TEST)) {
1134 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1135 status1 = serial_inp(up, UART_MSR) & 0xF0;
1136 serial_outp(up, UART_MCR, save_mcr);
1137 if (status1 != 0x90) {
1138 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1139 status1);
1140 goto out;
1141 }
1142 }
1143
1144 /*
1145 * We're pretty sure there's a port here. Lets find out what
1146 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1147 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1148 * determines what we test for next.
1149 *
1150 * We also initialise the EFR (if any) to zero for later. The
1151 * EFR occupies the same register location as the FCR and IIR.
1152 */
662b083a 1153 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1154 serial_outp(up, UART_EFR, 0);
1155 serial_outp(up, UART_LCR, 0);
1156
1157 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1158 scratch = serial_in(up, UART_IIR) >> 6;
1159
1160 DEBUG_AUTOCONF("iir=%d ", scratch);
1161
1162 switch (scratch) {
1163 case 0:
1164 autoconfig_8250(up);
1165 break;
1166 case 1:
1167 up->port.type = PORT_UNKNOWN;
1168 break;
1169 case 2:
1170 up->port.type = PORT_16550;
1171 break;
1172 case 3:
1173 autoconfig_16550a(up);
1174 break;
1175 }
1176
1177#ifdef CONFIG_SERIAL_8250_RSA
1178 /*
1179 * Only probe for RSA ports if we got the region.
1180 */
1181 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1182 int i;
1183
1184 for (i = 0 ; i < probe_rsa_count; ++i) {
1185 if (probe_rsa[i] == up->port.iobase &&
1186 __enable_rsa(up)) {
1187 up->port.type = PORT_RSA;
1188 break;
1189 }
1190 }
1191 }
1192#endif
21c614a7 1193
1da177e4
LT		 1194 serial_outp(up, UART_LCR, save_lcr);
1195
1196 if (up->capabilities != uart_config[up->port.type].flags) {
1197 printk(KERN_WARNING
1198 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1199 serial_index(&up->port), up->capabilities,
1200 uart_config[up->port.type].flags);
1da177e4
LT		 1201 }
1202
1203 up->port.fifosize = uart_config[up->port.type].fifo_size;
1204 up->capabilities = uart_config[up->port.type].flags;
1205 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1206
1207 if (up->port.type == PORT_UNKNOWN)
1208 goto out;
1209
1210 /*
1211 * Reset the UART.
1212 */
1213#ifdef CONFIG_SERIAL_8250_RSA
1214 if (up->port.type == PORT_RSA)
1215 serial_outp(up, UART_RSA_FRR, 0);
1216#endif
1217 serial_outp(up, UART_MCR, save_mcr);
1218 serial8250_clear_fifos(up);
40b36daa 1219 serial_in(up, UART_RX);
5c8c755c
LB		 1220 if (up->capabilities & UART_CAP_UUE)
1221 serial_outp(up, UART_IER, UART_IER_UUE);
1222 else
1223 serial_outp(up, UART_IER, 0);
1da177e4 1224
bd71c182 1225 out:
1da177e4 1226 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1227 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1228}
1229
1230static void autoconfig_irq(struct uart_8250_port *up)
1231{
1232 unsigned char save_mcr, save_ier;
1233 unsigned char save_ICP = 0;
1234 unsigned int ICP = 0;
1235 unsigned long irqs;
1236 int irq;
1237
1238 if (up->port.flags & UPF_FOURPORT) {
1239 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1240 save_ICP = inb_p(ICP);
1241 outb_p(0x80, ICP);
1242 (void) inb_p(ICP);
1243 }
1244
1245 /* forget possible initially masked and pending IRQ */
1246 probe_irq_off(probe_irq_on());
1247 save_mcr = serial_inp(up, UART_MCR);
1248 save_ier = serial_inp(up, UART_IER);
1249 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1250
1da177e4
LT		 1251 irqs = probe_irq_on();
1252 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1253 udelay(10);
1254 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1255 serial_outp(up, UART_MCR,
1256 UART_MCR_DTR | UART_MCR_RTS);
1257 } else {
1258 serial_outp(up, UART_MCR,
1259 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1260 }
1261 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1262 (void)serial_inp(up, UART_LSR);
1263 (void)serial_inp(up, UART_RX);
1264 (void)serial_inp(up, UART_IIR);
1265 (void)serial_inp(up, UART_MSR);
1266 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1267 udelay(20);
1da177e4
LT		 1268 irq = probe_irq_off(irqs);
1269
1270 serial_outp(up, UART_MCR, save_mcr);
1271 serial_outp(up, UART_IER, save_ier);
1272
1273 if (up->port.flags & UPF_FOURPORT)
1274 outb_p(save_ICP, ICP);
1275
1276 up->port.irq = (irq > 0) ? irq : 0;
1277}
1278
e763b90c
RK		 1279static inline void __stop_tx(struct uart_8250_port *p)
1280{
1281 if (p->ier & UART_IER_THRI) {
1282 p->ier &= ~UART_IER_THRI;
1283 serial_out(p, UART_IER, p->ier);
1284 }
1285}
1286
b129a8cc 1287static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1288{
49d5741b
JI		 1289 struct uart_8250_port *up =
1290 container_of(port, struct uart_8250_port, port);
1da177e4 1291
e763b90c 1292 __stop_tx(up);
1da177e4
LT		 1293
1294 /*
e763b90c 1295 * We really want to stop the transmitter from sending.
1da177e4 1296 */
e763b90c 1297 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1298 up->acr |= UART_ACR_TXDIS;
1299 serial_icr_write(up, UART_ACR, up->acr);
1300 }
1301}
1302
b129a8cc 1303static void serial8250_start_tx(struct uart_port *port)
1da177e4 1304{
49d5741b
JI		 1305 struct uart_8250_port *up =
1306 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1307
1308 if (!(up->ier & UART_IER_THRI)) {
1309 up->ier |= UART_IER_THRI;
1310 serial_out(up, UART_IER, up->ier);
55d3b282 1311
67f7654e 1312 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1313 unsigned char lsr;
55d3b282 1314 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1315 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182 1316 if ((up->port.type == PORT_RM9000) ?
68cb4f8e
IJ		 1317 (lsr & UART_LSR_THRE) :
1318 (lsr & UART_LSR_TEMT))
3986fb2b 1319 serial8250_tx_chars(up);
55d3b282 1320 }
1da177e4 1321 }
e763b90c 1322
1da177e4 1323 /*
e763b90c 1324 * Re-enable the transmitter if we disabled it.
1da177e4 1325 */
e763b90c 1326 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1327 up->acr &= ~UART_ACR_TXDIS;
1328 serial_icr_write(up, UART_ACR, up->acr);
1329 }
1330}
1331
1332static void serial8250_stop_rx(struct uart_port *port)
1333{
49d5741b
JI		 1334 struct uart_8250_port *up =
1335 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1336
1337 up->ier &= ~UART_IER_RLSI;
1338 up->port.read_status_mask &= ~UART_LSR_DR;
1339 serial_out(up, UART_IER, up->ier);
1340}
1341
1342static void serial8250_enable_ms(struct uart_port *port)
1343{
49d5741b
JI		 1344 struct uart_8250_port *up =
1345 container_of(port, struct uart_8250_port, port);
1da177e4 1346
21c614a7
PA		 1347 /* no MSR capabilities */
1348 if (up->bugs & UART_BUG_NOMSR)
1349 return;
1350
1da177e4
LT		 1351 up->ier |= UART_IER_MSI;
1352 serial_out(up, UART_IER, up->ier);
1353}
1354
5f873bae
SW		 1355/*
1356 * Clear the Tegra rx fifo after a break
1357 *
1358 * FIXME: This needs to become a port specific callback once we have a
1359 * framework for this
1360 */
1361static void clear_rx_fifo(struct uart_8250_port *up)
1362{
1363 unsigned int status, tmout = 10000;
1364 do {
1365 status = serial_in(up, UART_LSR);
1366 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1367 status = serial_in(up, UART_RX);
1368 else
1369 break;
1370 if (--tmout == 0)
1371 break;
1372 udelay(1);
1373 } while (1);
1374}
1375
0690f41f 1376/*
3986fb2b 1377 * serial8250_rx_chars: processes according to the passed in LSR
0690f41f
PG		 1378 * value, and returns the remaining LSR bits not handled
1379 * by this Rx routine.
1380 */
3986fb2b
PG		 1381unsigned char
1382serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1da177e4 1383{
ebd2c8f6 1384 struct tty_struct *tty = up->port.state->port.tty;
0690f41f 1385 unsigned char ch;
1da177e4
LT		 1386 int max_count = 256;
1387 char flag;
1388
1389 do {
7500b1f6
AR		 1390 if (likely(lsr & UART_LSR_DR))
1391 ch = serial_inp(up, UART_RX);
1392 else
1393 /*
1394 * Intel 82571 has a Serial Over Lan device that will
1395 * set UART_LSR_BI without setting UART_LSR_DR when
1396 * it receives a break. To avoid reading from the
1397 * receive buffer without UART_LSR_DR bit set, we
1398 * just force the read character to be 0
1399 */
1400 ch = 0;
1401
1da177e4
LT		 1402 flag = TTY_NORMAL;
1403 up->port.icount.rx++;
1404
ad4c2aa6
CM		 1405 lsr |= up->lsr_saved_flags;
1406 up->lsr_saved_flags = 0;
1da177e4 1407
ad4c2aa6 1408 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1409 /*
1410 * For statistics only
1411 */
1412 if (lsr & UART_LSR_BI) {
1413 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1414 up->port.icount.brk++;
5f873bae
SW		 1415 /*
1416 * If tegra port then clear the rx fifo to
1417 * accept another break/character.
1418 */
1419 if (up->port.type == PORT_TEGRA)
1420 clear_rx_fifo(up);
1421
1da177e4
LT		 1422 /*
1423 * We do the SysRQ and SAK checking
1424 * here because otherwise the break
1425 * may get masked by ignore_status_mask
1426 * or read_status_mask.
1427 */
1428 if (uart_handle_break(&up->port))
1429 goto ignore_char;
1430 } else if (lsr & UART_LSR_PE)
1431 up->port.icount.parity++;
1432 else if (lsr & UART_LSR_FE)
1433 up->port.icount.frame++;
1434 if (lsr & UART_LSR_OE)
1435 up->port.icount.overrun++;
1436
1437 /*
23907eb8 1438 * Mask off conditions which should be ignored.
1da177e4
LT		 1439 */
1440 lsr &= up->port.read_status_mask;
1441
1442 if (lsr & UART_LSR_BI) {
1443 DEBUG_INTR("handling break....");
1444 flag = TTY_BREAK;
1445 } else if (lsr & UART_LSR_PE)
1446 flag = TTY_PARITY;
1447 else if (lsr & UART_LSR_FE)
1448 flag = TTY_FRAME;
1449 }
7d12e780 1450 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1451 goto ignore_char;
05ab3014
RK		 1452
1453 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1454
6f803cd0 1455ignore_char:
1da177e4 1456 lsr = serial_inp(up, UART_LSR);
7500b1f6 1457 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1458 spin_unlock(&up->port.lock);
1459 tty_flip_buffer_push(tty);
1460 spin_lock(&up->port.lock);
0690f41f 1461 return lsr;
1da177e4 1462}
3986fb2b 1463EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1da177e4 1464
3986fb2b 1465void serial8250_tx_chars(struct uart_8250_port *up)
1da177e4 1466{
ebd2c8f6 1467 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 1468 int count;
1469
1470 if (up->port.x_char) {
1471 serial_outp(up, UART_TX, up->port.x_char);
1472 up->port.icount.tx++;
1473 up->port.x_char = 0;
1474 return;
1475 }
b129a8cc
RK		 1476 if (uart_tx_stopped(&up->port)) {
1477 serial8250_stop_tx(&up->port);
1478 return;
1479 }
1480 if (uart_circ_empty(xmit)) {
e763b90c 1481 __stop_tx(up);
1da177e4
LT		 1482 return;
1483 }
1484
1485 count = up->tx_loadsz;
1486 do {
1487 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1488 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1489 up->port.icount.tx++;
1490 if (uart_circ_empty(xmit))
1491 break;
1492 } while (--count > 0);
1493
1494 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1495 uart_write_wakeup(&up->port);
1496
1497 DEBUG_INTR("THRE...");
1498
1499 if (uart_circ_empty(xmit))
e763b90c 1500 __stop_tx(up);
1da177e4 1501}
3986fb2b 1502EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1da177e4 1503
3986fb2b 1504unsigned int serial8250_modem_status(struct uart_8250_port *up)
1da177e4 1505{
2af7cd68
RK		 1506 unsigned int status = serial_in(up, UART_MSR);
1507
ad4c2aa6
CM		 1508 status |= up->msr_saved_flags;
1509 up->msr_saved_flags = 0;
fdc30b3d 1510 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
ebd2c8f6 1511 up->port.state != NULL) {
2af7cd68
RK		 1512 if (status & UART_MSR_TERI)
1513 up->port.icount.rng++;
1514 if (status & UART_MSR_DDSR)
1515 up->port.icount.dsr++;
1516 if (status & UART_MSR_DDCD)
1517 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1518 if (status & UART_MSR_DCTS)
1519 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1520
bdc04e31 1521 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
2af7cd68 1522 }
1da177e4 1523
2af7cd68 1524 return status;
1da177e4 1525}
3986fb2b 1526EXPORT_SYMBOL_GPL(serial8250_modem_status);
1da177e4
LT		 1527
1528/*
1529 * This handles the interrupt from one port.
1530 */
b5d674ab 1531static void serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1532{
0690f41f 1533 unsigned char status;
4bf3631c 1534 unsigned long flags;
45e24601 1535
4bf3631c 1536 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1537
1538 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1539
1540 DEBUG_INTR("status = %x...", status);
1541
7500b1f6 1542 if (status & (UART_LSR_DR | UART_LSR_BI))
3986fb2b
PG		 1543 status = serial8250_rx_chars(up, status);
1544 serial8250_modem_status(up);
1da177e4 1545 if (status & UART_LSR_THRE)
3986fb2b 1546 serial8250_tx_chars(up);
45e24601 1547
4bf3631c 1548 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1549}
1550
583d28e9
JI		 1551int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1552{
1553 struct uart_8250_port *up =
1554 container_of(port, struct uart_8250_port, port);
1555
1556 if (!(iir & UART_IIR_NO_INT)) {
1557 serial8250_handle_port(up);
1558 return 1;
1559 }
1560
1561 return 0;
1562}
c7a1bdc5 1563EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1564
1565static int serial8250_default_handle_irq(struct uart_port *port)
1566{
1567 struct uart_8250_port *up =
1568 container_of(port, struct uart_8250_port, port);
1569 unsigned int iir = serial_in(up, UART_IIR);
1570
1571 return serial8250_handle_irq(port, iir);
1572}
1573
1da177e4
LT		 1574/*
1575 * This is the serial driver's interrupt routine.
1576 *
1577 * Arjan thinks the old way was overly complex, so it got simplified.
1578 * Alan disagrees, saying that need the complexity to handle the weird
1579 * nature of ISA shared interrupts. (This is a special exception.)
1580 *
1581 * In order to handle ISA shared interrupts properly, we need to check
1582 * that all ports have been serviced, and therefore the ISA interrupt
1583 * line has been de-asserted.
1584 *
1585 * This means we need to loop through all ports. checking that they
1586 * don't have an interrupt pending.
1587 */
7d12e780 1588static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1589{
1590 struct irq_info *i = dev_id;
1591 struct list_head *l, *end = NULL;
1592 int pass_counter = 0, handled = 0;
1593
1594 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1595
1596 spin_lock(&i->lock);
1597
1598 l = i->head;
1599 do {
1600 struct uart_8250_port *up;
583d28e9 1601 struct uart_port *port;
448ac154 1602 bool skip;
1da177e4
LT		 1603
1604 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1605 port = &up->port;
448ac154 1606 skip = pass_counter && up->port.flags & UPF_IIR_ONCE;
1da177e4 1607
448ac154 1608 if (!skip && port->handle_irq(port)) {
1da177e4 1609 handled = 1;
1da177e4
LT		 1610 end = NULL;
1611 } else if (end == NULL)
1612 end = l;
1613
1614 l = l->next;
1615
1616 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1617 /* If we hit this, we're dead. */
cd3ecad1
DD		 1618 printk_ratelimited(KERN_ERR
1619 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1620 break;
1621 }
1622 } while (l != end);
1623
1624 spin_unlock(&i->lock);
1625
1626 DEBUG_INTR("end.\n");
1627
1628 return IRQ_RETVAL(handled);
1629}
1630
1631/*
1632 * To support ISA shared interrupts, we need to have one interrupt
1633 * handler that ensures that the IRQ line has been deasserted
1634 * before returning. Failing to do this will result in the IRQ
1635 * line being stuck active, and, since ISA irqs are edge triggered,
1636 * no more IRQs will be seen.
1637 */
1638static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1639{
1640 spin_lock_irq(&i->lock);
1641
1642 if (!list_empty(i->head)) {
1643 if (i->head == &up->list)
1644 i->head = i->head->next;
1645 list_del(&up->list);
1646 } else {
1647 BUG_ON(i->head != &up->list);
1648 i->head = NULL;
1649 }
1da177e4 1650 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1651 /* List empty so throw away the hash node */
1652 if (i->head == NULL) {
1653 hlist_del(&i->node);
1654 kfree(i);
1655 }
1da177e4
LT		 1656}
1657
1658static int serial_link_irq_chain(struct uart_8250_port *up)
1659{
25db8ad5
AC		 1660 struct hlist_head *h;
1661 struct hlist_node *n;
1662 struct irq_info *i;
40663cc7 1663 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1664
25db8ad5
AC		 1665 mutex_lock(&hash_mutex);
1666
1667 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1668
1669 hlist_for_each(n, h) {
1670 i = hlist_entry(n, struct irq_info, node);
1671 if (i->irq == up->port.irq)
1672 break;
1673 }
1674
1675 if (n == NULL) {
1676 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1677 if (i == NULL) {
1678 mutex_unlock(&hash_mutex);
1679 return -ENOMEM;
1680 }
1681 spin_lock_init(&i->lock);
1682 i->irq = up->port.irq;
1683 hlist_add_head(&i->node, h);
1684 }
1685 mutex_unlock(&hash_mutex);
1686
1da177e4
LT		 1687 spin_lock_irq(&i->lock);
1688
1689 if (i->head) {
1690 list_add(&up->list, i->head);
1691 spin_unlock_irq(&i->lock);
1692
1693 ret = 0;
1694 } else {
1695 INIT_LIST_HEAD(&up->list);
1696 i->head = &up->list;
1697 spin_unlock_irq(&i->lock);
1c2f0493 1698 irq_flags |= up->port.irqflags;
1da177e4
LT		 1699 ret = request_irq(up->port.irq, serial8250_interrupt,
1700 irq_flags, "serial", i);
1701 if (ret < 0)
1702 serial_do_unlink(i, up);
1703 }
1704
1705 return ret;
1706}
1707
1708static void serial_unlink_irq_chain(struct uart_8250_port *up)
1709{
25db8ad5
AC		 1710 struct irq_info *i;
1711 struct hlist_node *n;
1712 struct hlist_head *h;
1da177e4 1713
25db8ad5
AC		 1714 mutex_lock(&hash_mutex);
1715
1716 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1717
1718 hlist_for_each(n, h) {
1719 i = hlist_entry(n, struct irq_info, node);
1720 if (i->irq == up->port.irq)
1721 break;
1722 }
1723
1724 BUG_ON(n == NULL);
1da177e4
LT		 1725 BUG_ON(i->head == NULL);
1726
1727 if (list_empty(i->head))
1728 free_irq(up->port.irq, i);
1729
1730 serial_do_unlink(i, up);
25db8ad5 1731 mutex_unlock(&hash_mutex);
1da177e4
LT		 1732}
1733
1734/*
1735 * This function is used to handle ports that do not have an
1736 * interrupt. This doesn't work very well for 16450's, but gives
1737 * barely passable results for a 16550A. (Although at the expense
1738 * of much CPU overhead).
1739 */
1740static void serial8250_timeout(unsigned long data)
1741{
1742 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4 1743
a0431476 1744 up->port.handle_irq(&up->port);
54381067 1745 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1746}
1747
1748static void serial8250_backup_timeout(unsigned long data)
1749{
1750 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1751 unsigned int iir, ier = 0, lsr;
1752 unsigned long flags;
40b36daa 1753
dbb3b1ca
AC		 1754 spin_lock_irqsave(&up->port.lock, flags);
1755
40b36daa
AW		 1756 /*
1757 * Must disable interrupts or else we risk racing with the interrupt
1758 * based handler.
1759 */
1760 if (is_real_interrupt(up->port.irq)) {
1761 ier = serial_in(up, UART_IER);
1762 serial_out(up, UART_IER, 0);
1763 }
1da177e4 1764
40b36daa
AW		 1765 iir = serial_in(up, UART_IIR);
1766
1767 /*
1768 * This should be a safe test for anyone who doesn't trust the
1769 * IIR bits on their UART, but it's specifically designed for
1770 * the "Diva" UART used on the management processor on many HP
1771 * ia64 and parisc boxes.
1772 */
ad4c2aa6
CM		 1773 lsr = serial_in(up, UART_LSR);
1774 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1775 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1776 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1777 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1778 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1779 iir |= UART_IIR_THRI;
1780 }
1781
1782 if (!(iir & UART_IIR_NO_INT))
3986fb2b 1783 serial8250_tx_chars(up);
40b36daa
AW		 1784
1785 if (is_real_interrupt(up->port.irq))
1786 serial_out(up, UART_IER, ier);
1787
dbb3b1ca
AC		 1788 spin_unlock_irqrestore(&up->port.lock, flags);
1789
40b36daa 1790 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1791 mod_timer(&up->timer,
54381067 1792 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1793}
1794
1795static unsigned int serial8250_tx_empty(struct uart_port *port)
1796{
49d5741b
JI		 1797 struct uart_8250_port *up =
1798 container_of(port, struct uart_8250_port, port);
1da177e4 1799 unsigned long flags;
ad4c2aa6 1800 unsigned int lsr;
1da177e4
LT		 1801
1802 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1803 lsr = serial_in(up, UART_LSR);
1804 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1805 spin_unlock_irqrestore(&up->port.lock, flags);
1806
bca47613 1807 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1808}
1809
1810static unsigned int serial8250_get_mctrl(struct uart_port *port)
1811{
49d5741b
JI		 1812 struct uart_8250_port *up =
1813 container_of(port, struct uart_8250_port, port);
2af7cd68 1814 unsigned int status;
1da177e4
LT		 1815 unsigned int ret;
1816
3986fb2b 1817 status = serial8250_modem_status(up);
1da177e4
LT		 1818
1819 ret = 0;
1820 if (status & UART_MSR_DCD)
1821 ret |= TIOCM_CAR;
1822 if (status & UART_MSR_RI)
1823 ret |= TIOCM_RNG;
1824 if (status & UART_MSR_DSR)
1825 ret |= TIOCM_DSR;
1826 if (status & UART_MSR_CTS)
1827 ret |= TIOCM_CTS;
1828 return ret;
1829}
1830
1831static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1832{
49d5741b
JI		 1833 struct uart_8250_port *up =
1834 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1835 unsigned char mcr = 0;
1836
1837 if (mctrl & TIOCM_RTS)
1838 mcr |= UART_MCR_RTS;
1839 if (mctrl & TIOCM_DTR)
1840 mcr |= UART_MCR_DTR;
1841 if (mctrl & TIOCM_OUT1)
1842 mcr |= UART_MCR_OUT1;
1843 if (mctrl & TIOCM_OUT2)
1844 mcr |= UART_MCR_OUT2;
1845 if (mctrl & TIOCM_LOOP)
1846 mcr |= UART_MCR_LOOP;
1847
1848 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1849
1850 serial_out(up, UART_MCR, mcr);
1851}
1852
1853static void serial8250_break_ctl(struct uart_port *port, int break_state)
1854{
49d5741b
JI		 1855 struct uart_8250_port *up =
1856 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1857 unsigned long flags;
1858
1859 spin_lock_irqsave(&up->port.lock, flags);
1860 if (break_state == -1)
1861 up->lcr |= UART_LCR_SBC;
1862 else
1863 up->lcr &= ~UART_LCR_SBC;
1864 serial_out(up, UART_LCR, up->lcr);
1865 spin_unlock_irqrestore(&up->port.lock, flags);
1866}
1867
40b36daa
AW		 1868/*
1869 * Wait for transmitter & holding register to empty
1870 */
b5d674ab 1871static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1872{
1873 unsigned int status, tmout = 10000;
1874
1875 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1876 for (;;) {
40b36daa
AW		 1877 status = serial_in(up, UART_LSR);
1878
ad4c2aa6 1879 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1880
97d303b7
DD		 1881 if ((status & bits) == bits)
1882 break;
40b36daa
AW		 1883 if (--tmout == 0)
1884 break;
1885 udelay(1);
97d303b7 1886 }
40b36daa
AW		 1887
1888 /* Wait up to 1s for flow control if necessary */
1889 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1890 unsigned int tmout;
1891 for (tmout = 1000000; tmout; tmout--) {
1892 unsigned int msr = serial_in(up, UART_MSR);
1893 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1894 if (msr & UART_MSR_CTS)
1895 break;
40b36daa
AW		 1896 udelay(1);
1897 touch_nmi_watchdog();
1898 }
1899 }
1900}
1901
f2d937f3
JW		 1902#ifdef CONFIG_CONSOLE_POLL
1903/*
1904 * Console polling routines for writing and reading from the uart while
1905 * in an interrupt or debug context.
1906 */
1907
1908static int serial8250_get_poll_char(struct uart_port *port)
1909{
49d5741b
JI		 1910 struct uart_8250_port *up =
1911 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1912 unsigned char lsr = serial_inp(up, UART_LSR);
1913
f5316b4a
JW		 1914 if (!(lsr & UART_LSR_DR))
1915 return NO_POLL_CHAR;
f2d937f3
JW		 1916
1917 return serial_inp(up, UART_RX);
1918}
1919
1920
1921static void serial8250_put_poll_char(struct uart_port *port,
1922 unsigned char c)
1923{
1924 unsigned int ier;
49d5741b
JI		 1925 struct uart_8250_port *up =
1926 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1927
1928 /*
1929 * First save the IER then disable the interrupts
1930 */
1931 ier = serial_in(up, UART_IER);
1932 if (up->capabilities & UART_CAP_UUE)
1933 serial_out(up, UART_IER, UART_IER_UUE);
1934 else
1935 serial_out(up, UART_IER, 0);
1936
1937 wait_for_xmitr(up, BOTH_EMPTY);
1938 /*
1939 * Send the character out.
1940 * If a LF, also do CR...
1941 */
1942 serial_out(up, UART_TX, c);
1943 if (c == 10) {
1944 wait_for_xmitr(up, BOTH_EMPTY);
1945 serial_out(up, UART_TX, 13);
1946 }
1947
1948 /*
1949 * Finally, wait for transmitter to become empty
1950 * and restore the IER
1951 */
1952 wait_for_xmitr(up, BOTH_EMPTY);
1953 serial_out(up, UART_IER, ier);
1954}
1955
1956#endif /* CONFIG_CONSOLE_POLL */
1957
1da177e4
LT		 1958static int serial8250_startup(struct uart_port *port)
1959{
49d5741b
JI		 1960 struct uart_8250_port *up =
1961 container_of(port, struct uart_8250_port, port);
1da177e4 1962 unsigned long flags;
55d3b282 1963 unsigned char lsr, iir;
1da177e4
LT		 1964 int retval;
1965
e4f05af1
OP		 1966 up->port.fifosize = uart_config[up->port.type].fifo_size;
1967 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 1968 up->capabilities = uart_config[up->port.type].flags;
1969 up->mcr = 0;
1970
b8e7e40a
AC		 1971 if (up->port.iotype != up->cur_iotype)
1972 set_io_from_upio(port);
1973
1da177e4
LT		 1974 if (up->port.type == PORT_16C950) {
1975 /* Wake up and initialize UART */
1976 up->acr = 0;
662b083a 1977 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1978 serial_outp(up, UART_EFR, UART_EFR_ECB);
1979 serial_outp(up, UART_IER, 0);
1980 serial_outp(up, UART_LCR, 0);
1981 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
7d73aaf1 1982 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1983 serial_outp(up, UART_EFR, UART_EFR_ECB);
1984 serial_outp(up, UART_LCR, 0);
1985 }
1986
1987#ifdef CONFIG_SERIAL_8250_RSA
1988 /*
1989 * If this is an RSA port, see if we can kick it up to the
1990 * higher speed clock.
1991 */
1992 enable_rsa(up);
1993#endif
1994
1995 /*
1996 * Clear the FIFO buffers and disable them.
7f927fcc 1997 * (they will be reenabled in set_termios())
1da177e4
LT		 1998 */
1999 serial8250_clear_fifos(up);
2000
2001 /*
2002 * Clear the interrupt registers.
2003 */
2004 (void) serial_inp(up, UART_LSR);
2005 (void) serial_inp(up, UART_RX);
2006 (void) serial_inp(up, UART_IIR);
2007 (void) serial_inp(up, UART_MSR);
2008
2009 /*
2010 * At this point, there's no way the LSR could still be 0xff;
2011 * if it is, then bail out, because there's likely no UART
2012 * here.
2013 */
2014 if (!(up->port.flags & UPF_BUGGY_UART) &&
2015 (serial_inp(up, UART_LSR) == 0xff)) {
7808a4c4
KRW		 2016 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2017 serial_index(&up->port));
1da177e4
LT		 2018 return -ENODEV;
2019 }
2020
2021 /*
2022 * For a XR16C850, we need to set the trigger levels
2023 */
2024 if (up->port.type == PORT_16850) {
2025 unsigned char fctr;
2026
662b083a 2027 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 2028
2029 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2030 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2031 serial_outp(up, UART_TRG, UART_TRG_96);
2032 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2033 serial_outp(up, UART_TRG, UART_TRG_96);
2034
2035 serial_outp(up, UART_LCR, 0);
2036 }
2037
40b36daa 2038 if (is_real_interrupt(up->port.irq)) {
01c194d9 2039 unsigned char iir1;
40b36daa
AW		 2040 /*
2041 * Test for UARTs that do not reassert THRE when the
2042 * transmitter is idle and the interrupt has already
2043 * been cleared. Real 16550s should always reassert
2044 * this interrupt whenever the transmitter is idle and
2045 * the interrupt is enabled. Delays are necessary to
2046 * allow register changes to become visible.
2047 */
c389d27b 2048 spin_lock_irqsave(&up->port.lock, flags);
1c2f0493 2049 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2050 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2051
2052 wait_for_xmitr(up, UART_LSR_THRE);
2053 serial_out_sync(up, UART_IER, UART_IER_THRI);
2054 udelay(1); /* allow THRE to set */
01c194d9 2055 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2056 serial_out(up, UART_IER, 0);
2057 serial_out_sync(up, UART_IER, UART_IER_THRI);
2058 udelay(1); /* allow a working UART time to re-assert THRE */
2059 iir = serial_in(up, UART_IIR);
2060 serial_out(up, UART_IER, 0);
2061
1c2f0493 2062 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2063 enable_irq(up->port.irq);
c389d27b 2064 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2065
2066 /*
2067 * If the interrupt is not reasserted, setup a timer to
2068 * kick the UART on a regular basis.
2069 */
01c194d9 2070 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2071 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2072 pr_debug("ttyS%d - using backup timer\n",
2073 serial_index(port));
40b36daa
AW		 2074 }
2075 }
2076
363f66fe
WN		 2077 /*
2078 * The above check will only give an accurate result the first time
2079 * the port is opened so this value needs to be preserved.
2080 */
2081 if (up->bugs & UART_BUG_THRE) {
2082 up->timer.function = serial8250_backup_timeout;
2083 up->timer.data = (unsigned long)up;
2084 mod_timer(&up->timer, jiffies +
54381067 2085 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2086 }
2087
1da177e4
LT		 2088 /*
2089 * If the "interrupt" for this port doesn't correspond with any
2090 * hardware interrupt, we use a timer-based system. The original
2091 * driver used to do this with IRQ0.
2092 */
2093 if (!is_real_interrupt(up->port.irq)) {
1da177e4 2094 up->timer.data = (unsigned long)up;
54381067 2095 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2096 } else {
2097 retval = serial_link_irq_chain(up);
2098 if (retval)
2099 return retval;
2100 }
2101
2102 /*
2103 * Now, initialize the UART
2104 */
2105 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2106
2107 spin_lock_irqsave(&up->port.lock, flags);
2108 if (up->port.flags & UPF_FOURPORT) {
2109 if (!is_real_interrupt(up->port.irq))
2110 up->port.mctrl |= TIOCM_OUT1;
2111 } else
2112 /*
2113 * Most PC uarts need OUT2 raised to enable interrupts.
2114 */
2115 if (is_real_interrupt(up->port.irq))
2116 up->port.mctrl |= TIOCM_OUT2;
2117
2118 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2119
b6adea33
MCC		 2120 /* Serial over Lan (SoL) hack:
2121 Intel 8257x Gigabit ethernet chips have a
2122 16550 emulation, to be used for Serial Over Lan.
2123 Those chips take a longer time than a normal
2124 serial device to signalize that a transmission
2125 data was queued. Due to that, the above test generally
2126 fails. One solution would be to delay the reading of
2127 iir. However, this is not reliable, since the timeout
2128 is variable. So, let's just don't test if we receive
2129 TX irq. This way, we'll never enable UART_BUG_TXEN.
2130 */
d41a4b51 2131 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2132 goto dont_test_tx_en;
2133
55d3b282
RK		 2134 /*
2135 * Do a quick test to see if we receive an
2136 * interrupt when we enable the TX irq.
2137 */
2138 serial_outp(up, UART_IER, UART_IER_THRI);
2139 lsr = serial_in(up, UART_LSR);
2140 iir = serial_in(up, UART_IIR);
2141 serial_outp(up, UART_IER, 0);
2142
2143 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2144 if (!(up->bugs & UART_BUG_TXEN)) {
2145 up->bugs |= UART_BUG_TXEN;
55d3b282 2146 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2147 serial_index(port));
55d3b282
RK		 2148 }
2149 } else {
67f7654e 2150 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2151 }
2152
b6adea33 2153dont_test_tx_en:
1da177e4
LT		 2154 spin_unlock_irqrestore(&up->port.lock, flags);
2155
ad4c2aa6
CM		 2156 /*
2157 * Clear the interrupt registers again for luck, and clear the
2158 * saved flags to avoid getting false values from polling
2159 * routines or the previous session.
2160 */
2161 serial_inp(up, UART_LSR);
2162 serial_inp(up, UART_RX);
2163 serial_inp(up, UART_IIR);
2164 serial_inp(up, UART_MSR);
2165 up->lsr_saved_flags = 0;
2166 up->msr_saved_flags = 0;
2167
1da177e4
LT		 2168 /*
2169 * Finally, enable interrupts. Note: Modem status interrupts
2170 * are set via set_termios(), which will be occurring imminently
2171 * anyway, so we don't enable them here.
2172 */
2173 up->ier = UART_IER_RLSI | UART_IER_RDI;
2174 serial_outp(up, UART_IER, up->ier);
2175
2176 if (up->port.flags & UPF_FOURPORT) {
2177 unsigned int icp;
2178 /*
2179 * Enable interrupts on the AST Fourport board
2180 */
2181 icp = (up->port.iobase & 0xfe0) | 0x01f;
2182 outb_p(0x80, icp);
2183 (void) inb_p(icp);
2184 }
2185
1da177e4
LT		 2186 return 0;
2187}
2188
2189static void serial8250_shutdown(struct uart_port *port)
2190{
49d5741b
JI		 2191 struct uart_8250_port *up =
2192 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2193 unsigned long flags;
2194
2195 /*
2196 * Disable interrupts from this port
2197 */
2198 up->ier = 0;
2199 serial_outp(up, UART_IER, 0);
2200
2201 spin_lock_irqsave(&up->port.lock, flags);
2202 if (up->port.flags & UPF_FOURPORT) {
2203 /* reset interrupts on the AST Fourport board */
2204 inb((up->port.iobase & 0xfe0) | 0x1f);
2205 up->port.mctrl |= TIOCM_OUT1;
2206 } else
2207 up->port.mctrl &= ~TIOCM_OUT2;
2208
2209 serial8250_set_mctrl(&up->port, up->port.mctrl);
2210 spin_unlock_irqrestore(&up->port.lock, flags);
2211
2212 /*
2213 * Disable break condition and FIFOs
2214 */
2215 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2216 serial8250_clear_fifos(up);
2217
2218#ifdef CONFIG_SERIAL_8250_RSA
2219 /*
2220 * Reset the RSA board back to 115kbps compat mode.
2221 */
2222 disable_rsa(up);
2223#endif
2224
2225 /*
2226 * Read data port to reset things, and then unlink from
2227 * the IRQ chain.
2228 */
2229 (void) serial_in(up, UART_RX);
2230
40b36daa
AW		 2231 del_timer_sync(&up->timer);
2232 up->timer.function = serial8250_timeout;
2233 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2234 serial_unlink_irq_chain(up);
2235}
2236
2237static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2238{
2239 unsigned int quot;
2240
2241 /*
2242 * Handle magic divisors for baud rates above baud_base on
2243 * SMSC SuperIO chips.
2244 */
2245 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2246 baud == (port->uartclk/4))
2247 quot = 0x8001;
2248 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2249 baud == (port->uartclk/8))
2250 quot = 0x8002;
2251 else
2252 quot = uart_get_divisor(port, baud);
2253
2254 return quot;
2255}
2256
235dae5d
PL		 2257void
2258serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2259 struct ktermios *old)
1da177e4 2260{
49d5741b
JI		 2261 struct uart_8250_port *up =
2262 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2263 unsigned char cval, fcr = 0;
2264 unsigned long flags;
2265 unsigned int baud, quot;
2266
2267 switch (termios->c_cflag & CSIZE) {
2268 case CS5:
0a8b80c5 2269 cval = UART_LCR_WLEN5;
1da177e4
LT		 2270 break;
2271 case CS6:
0a8b80c5 2272 cval = UART_LCR_WLEN6;
1da177e4
LT		 2273 break;
2274 case CS7:
0a8b80c5 2275 cval = UART_LCR_WLEN7;
1da177e4
LT		 2276 break;
2277 default:
2278 case CS8:
0a8b80c5 2279 cval = UART_LCR_WLEN8;
1da177e4
LT		 2280 break;
2281 }
2282
2283 if (termios->c_cflag & CSTOPB)
0a8b80c5 2284 cval |= UART_LCR_STOP;
1da177e4
LT		 2285 if (termios->c_cflag & PARENB)
2286 cval |= UART_LCR_PARITY;
2287 if (!(termios->c_cflag & PARODD))
2288 cval |= UART_LCR_EPAR;
2289#ifdef CMSPAR
2290 if (termios->c_cflag & CMSPAR)
2291 cval |= UART_LCR_SPAR;
2292#endif
2293
2294 /*
2295 * Ask the core to calculate the divisor for us.
2296 */
24d481ec
AV		 2297 baud = uart_get_baud_rate(port, termios, old,
2298 port->uartclk / 16 / 0xffff,
2299 port->uartclk / 16);
1da177e4
LT		 2300 quot = serial8250_get_divisor(port, baud);
2301
2302 /*
4ba5e35d 2303 * Oxford Semi 952 rev B workaround
1da177e4 2304 */
4ba5e35d 2305 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2306 quot++;
1da177e4
LT		 2307
2308 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2309 if (baud < 2400)
2310 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2311 else
2312 fcr = uart_config[up->port.type].fcr;
2313 }
2314
2315 /*
2316 * MCR-based auto flow control. When AFE is enabled, RTS will be
2317 * deasserted when the receive FIFO contains more characters than
2318 * the trigger, or the MCR RTS bit is cleared. In the case where
2319 * the remote UART is not using CTS auto flow control, we must
2320 * have sufficient FIFO entries for the latency of the remote
2321 * UART to respond. IOW, at least 32 bytes of FIFO.
2322 */
2323 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2324 up->mcr &= ~UART_MCR_AFE;
2325 if (termios->c_cflag & CRTSCTS)
2326 up->mcr |= UART_MCR_AFE;
2327 }
2328
2329 /*
2330 * Ok, we're now changing the port state. Do it with
2331 * interrupts disabled.
2332 */
2333 spin_lock_irqsave(&up->port.lock, flags);
2334
2335 /*
2336 * Update the per-port timeout.
2337 */
2338 uart_update_timeout(port, termios->c_cflag, baud);
2339
2340 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2341 if (termios->c_iflag & INPCK)
2342 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2343 if (termios->c_iflag & (BRKINT | PARMRK))
2344 up->port.read_status_mask |= UART_LSR_BI;
2345
2346 /*
2347 * Characteres to ignore
2348 */
2349 up->port.ignore_status_mask = 0;
2350 if (termios->c_iflag & IGNPAR)
2351 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2352 if (termios->c_iflag & IGNBRK) {
2353 up->port.ignore_status_mask |= UART_LSR_BI;
2354 /*
2355 * If we're ignoring parity and break indicators,
2356 * ignore overruns too (for real raw support).
2357 */
2358 if (termios->c_iflag & IGNPAR)
2359 up->port.ignore_status_mask |= UART_LSR_OE;
2360 }
2361
2362 /*
2363 * ignore all characters if CREAD is not set
2364 */
2365 if ((termios->c_cflag & CREAD) == 0)
2366 up->port.ignore_status_mask |= UART_LSR_DR;
2367
2368 /*
2369 * CTS flow control flag and modem status interrupts
2370 */
f8b372a1 2371 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2372 if (!(up->bugs & UART_BUG_NOMSR) &&
2373 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2374 up->ier |= UART_IER_MSI;
2375 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2376 up->ier |= UART_IER_UUE;
2377 if (up->capabilities & UART_CAP_RTOIE)
2378 up->ier |= UART_IER_RTOIE;
1da177e4
LT		 2379
2380 serial_out(up, UART_IER, up->ier);
2381
2382 if (up->capabilities & UART_CAP_EFR) {
2383 unsigned char efr = 0;
2384 /*
2385 * TI16C752/Startech hardware flow control. FIXME:
2386 * - TI16C752 requires control thresholds to be set.
2387 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2388 */
2389 if (termios->c_cflag & CRTSCTS)
2390 efr |= UART_EFR_CTS;
2391
662b083a 2392 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
06315348
SH		 2393 if (up->port.flags & UPF_EXAR_EFR)
2394 serial_outp(up, UART_XR_EFR, efr);
2395 else
2396 serial_outp(up, UART_EFR, efr);
1da177e4
LT		 2397 }
2398
f2eda27d 2399#ifdef CONFIG_ARCH_OMAP
255341c6 2400 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2401 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2402 if (baud == 115200) {
2403 quot = 1;
2404 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2405 } else
2406 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2407 }
2408#endif
2409
1da177e4
LT		 2410 if (up->capabilities & UART_NATSEMI) {
2411 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2412 serial_outp(up, UART_LCR, 0xe0);
2413 } else {
2414 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2415 }
2416
b32b19b8 2417 serial_dl_write(up, quot);
1da177e4
LT		 2418
2419 /*
2420 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2421 * is written without DLAB set, this mode will be disabled.
2422 */
2423 if (up->port.type == PORT_16750)
2424 serial_outp(up, UART_FCR, fcr);
2425
2426 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2427 up->lcr = cval; /* Save LCR */
2428 if (up->port.type != PORT_16750) {
2429 if (fcr & UART_FCR_ENABLE_FIFO) {
2430 /* emulated UARTs (Lucent Venus 167x) need two steps */
2431 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2432 }
2433 serial_outp(up, UART_FCR, fcr); /* set fcr */
2434 }
2435 serial8250_set_mctrl(&up->port, up->port.mctrl);
2436 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2437 /* Don't rewrite B0 */
2438 if (tty_termios_baud_rate(termios))
2439 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2440}
235dae5d
PL		 2441EXPORT_SYMBOL(serial8250_do_set_termios);
2442
2443static void
2444serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2445 struct ktermios *old)
2446{
2447 if (port->set_termios)
2448 port->set_termios(port, termios, old);
2449 else
2450 serial8250_do_set_termios(port, termios, old);
2451}
1da177e4 2452
dc77f161 2453static void
a0821df6 2454serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2455{
a0821df6 2456 if (new == N_PPS) {
dc77f161
RG		 2457 port->flags |= UPF_HARDPPS_CD;
2458 serial8250_enable_ms(port);
2459 } else
2460 port->flags &= ~UPF_HARDPPS_CD;
2461}
2462
c161afe9
ML		 2463
2464void serial8250_do_pm(struct uart_port *port, unsigned int state,
2465 unsigned int oldstate)
1da177e4 2466{
49d5741b
JI		 2467 struct uart_8250_port *p =
2468 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2469
2470 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2471}
2472EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2473
c161afe9
ML		 2474static void
2475serial8250_pm(struct uart_port *port, unsigned int state,
2476 unsigned int oldstate)
2477{
2478 if (port->pm)
2479 port->pm(port, state, oldstate);
2480 else
2481 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2482}
2483
f2eda27d
RK		 2484static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2485{
2486 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2487 return 0x1000;
f2eda27d
RK		 2488#ifdef CONFIG_ARCH_OMAP
2489 if (is_omap_port(pt))
2490 return 0x16 << pt->port.regshift;
2491#endif
2492 return 8 << pt->port.regshift;
2493}
2494
1da177e4
LT		 2495/*
2496 * Resource handling.
2497 */
2498static int serial8250_request_std_resource(struct uart_8250_port *up)
2499{
f2eda27d 2500 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2501 int ret = 0;
2502
2503 switch (up->port.iotype) {
85835f44 2504 case UPIO_AU:
0b30d668
SS		 2505 case UPIO_TSI:
2506 case UPIO_MEM32:
1da177e4
LT		 2507 case UPIO_MEM:
2508 if (!up->port.mapbase)
2509 break;
2510
2511 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2512 ret = -EBUSY;
2513 break;
2514 }
2515
2516 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2517 up->port.membase = ioremap_nocache(up->port.mapbase,
2518 size);
1da177e4
LT		 2519 if (!up->port.membase) {
2520 release_mem_region(up->port.mapbase, size);
2521 ret = -ENOMEM;
2522 }
2523 }
2524 break;
2525
2526 case UPIO_HUB6:
2527 case UPIO_PORT:
2528 if (!request_region(up->port.iobase, size, "serial"))
2529 ret = -EBUSY;
2530 break;
2531 }
2532 return ret;
2533}
2534
2535static void serial8250_release_std_resource(struct uart_8250_port *up)
2536{
f2eda27d 2537 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2538
2539 switch (up->port.iotype) {
85835f44 2540 case UPIO_AU:
0b30d668
SS		 2541 case UPIO_TSI:
2542 case UPIO_MEM32:
1da177e4
LT		 2543 case UPIO_MEM:
2544 if (!up->port.mapbase)
2545 break;
2546
2547 if (up->port.flags & UPF_IOREMAP) {
2548 iounmap(up->port.membase);
2549 up->port.membase = NULL;
2550 }
2551
2552 release_mem_region(up->port.mapbase, size);
2553 break;
2554
2555 case UPIO_HUB6:
2556 case UPIO_PORT:
2557 release_region(up->port.iobase, size);
2558 break;
2559 }
2560}
2561
2562static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2563{
2564 unsigned long start = UART_RSA_BASE << up->port.regshift;
2565 unsigned int size = 8 << up->port.regshift;
0b30d668 2566 int ret = -EINVAL;
1da177e4
LT		 2567
2568 switch (up->port.iotype) {
1da177e4
LT		 2569 case UPIO_HUB6:
2570 case UPIO_PORT:
2571 start += up->port.iobase;
0b30d668
SS		 2572 if (request_region(start, size, "serial-rsa"))
2573 ret = 0;
2574 else
1da177e4
LT		 2575 ret = -EBUSY;
2576 break;
2577 }
2578
2579 return ret;
2580}
2581
2582static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2583{
2584 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2585 unsigned int size = 8 << up->port.regshift;
2586
2587 switch (up->port.iotype) {
1da177e4
LT		 2588 case UPIO_HUB6:
2589 case UPIO_PORT:
2590 release_region(up->port.iobase + offset, size);
2591 break;
2592 }
2593}
2594
2595static void serial8250_release_port(struct uart_port *port)
2596{
49d5741b
JI		 2597 struct uart_8250_port *up =
2598 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2599
2600 serial8250_release_std_resource(up);
2601 if (up->port.type == PORT_RSA)
2602 serial8250_release_rsa_resource(up);
2603}
2604
2605static int serial8250_request_port(struct uart_port *port)
2606{
49d5741b
JI		 2607 struct uart_8250_port *up =
2608 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2609 int ret = 0;
2610
2611 ret = serial8250_request_std_resource(up);
2612 if (ret == 0 && up->port.type == PORT_RSA) {
2613 ret = serial8250_request_rsa_resource(up);
2614 if (ret < 0)
2615 serial8250_release_std_resource(up);
2616 }
2617
2618 return ret;
2619}
2620
2621static void serial8250_config_port(struct uart_port *port, int flags)
2622{
49d5741b
JI		 2623 struct uart_8250_port *up =
2624 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2625 int probeflags = PROBE_ANY;
2626 int ret;
2627
1da177e4
LT		 2628 /*
2629 * Find the region that we can probe for. This in turn
2630 * tells us whether we can probe for the type of port.
2631 */
2632 ret = serial8250_request_std_resource(up);
2633 if (ret < 0)
2634 return;
2635
2636 ret = serial8250_request_rsa_resource(up);
2637 if (ret < 0)
2638 probeflags &= ~PROBE_RSA;
2639
b8e7e40a
AC		 2640 if (up->port.iotype != up->cur_iotype)
2641 set_io_from_upio(port);
2642
1da177e4
LT		 2643 if (flags & UART_CONFIG_TYPE)
2644 autoconfig(up, probeflags);
b2b13cdf 2645
b2b13cdf
ML		 2646 /* if access method is AU, it is a 16550 with a quirk */
2647 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2648 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2649
1da177e4
LT		 2650 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2651 autoconfig_irq(up);
2652
2653 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2654 serial8250_release_rsa_resource(up);
2655 if (up->port.type == PORT_UNKNOWN)
2656 serial8250_release_std_resource(up);
2657}
2658
2659static int
2660serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2661{
a62c4133 2662 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2663 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2664 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2665 ser->type == PORT_STARTECH)
2666 return -EINVAL;
2667 return 0;
2668}
2669
2670static const char *
2671serial8250_type(struct uart_port *port)
2672{
2673 int type = port->type;
2674
2675 if (type >= ARRAY_SIZE(uart_config))
2676 type = 0;
2677 return uart_config[type].name;
2678}
2679
2680static struct uart_ops serial8250_pops = {
2681 .tx_empty = serial8250_tx_empty,
2682 .set_mctrl = serial8250_set_mctrl,
2683 .get_mctrl = serial8250_get_mctrl,
2684 .stop_tx = serial8250_stop_tx,
2685 .start_tx = serial8250_start_tx,
2686 .stop_rx = serial8250_stop_rx,
2687 .enable_ms = serial8250_enable_ms,
2688 .break_ctl = serial8250_break_ctl,
2689 .startup = serial8250_startup,
2690 .shutdown = serial8250_shutdown,
2691 .set_termios = serial8250_set_termios,
dc77f161 2692 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2693 .pm = serial8250_pm,
2694 .type = serial8250_type,
2695 .release_port = serial8250_release_port,
2696 .request_port = serial8250_request_port,
2697 .config_port = serial8250_config_port,
2698 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2699#ifdef CONFIG_CONSOLE_POLL
2700 .poll_get_char = serial8250_get_poll_char,
2701 .poll_put_char = serial8250_put_poll_char,
2702#endif
1da177e4
LT		 2703};
2704
2705static struct uart_8250_port serial8250_ports[UART_NR];
2706
af7f3743
AC		 2707static void (*serial8250_isa_config)(int port, struct uart_port *up,
2708 unsigned short *capabilities);
2709
2710void serial8250_set_isa_configurator(
2711 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2712{
2713 serial8250_isa_config = v;
2714}
2715EXPORT_SYMBOL(serial8250_set_isa_configurator);
2716
1da177e4
LT		 2717static void __init serial8250_isa_init_ports(void)
2718{
2719 struct uart_8250_port *up;
2720 static int first = 1;
4c0ebb80 2721 int i, irqflag = 0;
1da177e4
LT		 2722
2723 if (!first)
2724 return;
2725 first = 0;
2726
a61c2d78 2727 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2728 struct uart_8250_port *up = &serial8250_ports[i];
2729
2730 up->port.line = i;
2731 spin_lock_init(&up->port.lock);
2732
2733 init_timer(&up->timer);
2734 up->timer.function = serial8250_timeout;
2735
2736 /*
2737 * ALPHA_KLUDGE_MCR needs to be killed.
2738 */
2739 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2740 up->mcr_force = ALPHA_KLUDGE_MCR;
2741
2742 up->port.ops = &serial8250_pops;
2743 }
2744
4c0ebb80
AGR		 2745 if (share_irqs)
2746 irqflag = IRQF_SHARED;
2747
44454bcd 2748 for (i = 0, up = serial8250_ports;
a61c2d78 2749 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2750 i++, up++) {
2751 up->port.iobase = old_serial_port[i].port;
2752 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
1c2f0493 2753 up->port.irqflags = old_serial_port[i].irqflags;
1da177e4
LT		 2754 up->port.uartclk = old_serial_port[i].baud_base * 16;
2755 up->port.flags = old_serial_port[i].flags;
2756 up->port.hub6 = old_serial_port[i].hub6;
2757 up->port.membase = old_serial_port[i].iomem_base;
2758 up->port.iotype = old_serial_port[i].io_type;
2759 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2760 set_io_from_upio(&up->port);
4c0ebb80 2761 up->port.irqflags |= irqflag;
af7f3743
AC		 2762 if (serial8250_isa_config != NULL)
2763 serial8250_isa_config(i, &up->port, &up->capabilities);
2764
1da177e4
LT		 2765 }
2766}
2767
b5d228cc
SL		 2768static void
2769serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2770{
2771 up->port.type = type;
2772 up->port.fifosize = uart_config[type].fifo_size;
2773 up->capabilities = uart_config[type].flags;
2774 up->tx_loadsz = uart_config[type].tx_loadsz;
2775}
2776
1da177e4
LT		 2777static void __init
2778serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2779{
2780 int i;
2781
b8e7e40a
AC		 2782 for (i = 0; i < nr_uarts; i++) {
2783 struct uart_8250_port *up = &serial8250_ports[i];
2784 up->cur_iotype = 0xFF;
2785 }
2786
1da177e4
LT		 2787 serial8250_isa_init_ports();
2788
a61c2d78 2789 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2790 struct uart_8250_port *up = &serial8250_ports[i];
2791
2792 up->port.dev = dev;
b5d228cc
SL		 2793
2794 if (up->port.flags & UPF_FIXED_TYPE)
2795 serial8250_init_fixed_type_port(up, up->port.type);
2796
1da177e4
LT		 2797 uart_add_one_port(drv, &up->port);
2798 }
2799}
2800
2801#ifdef CONFIG_SERIAL_8250_CONSOLE
2802
d358788f
RK		 2803static void serial8250_console_putchar(struct uart_port *port, int ch)
2804{
49d5741b
JI		 2805 struct uart_8250_port *up =
2806 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2807
2808 wait_for_xmitr(up, UART_LSR_THRE);
2809 serial_out(up, UART_TX, ch);
2810}
2811
1da177e4
LT		 2812/*
2813 * Print a string to the serial port trying not to disturb
2814 * any possible real use of the port...
2815 *
2816 * The console_lock must be held when we get here.
2817 */
2818static void
2819serial8250_console_write(struct console *co, const char *s, unsigned int count)
2820{
2821 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2822 unsigned long flags;
1da177e4 2823 unsigned int ier;
d8a5a8d7 2824 int locked = 1;
1da177e4 2825
78512ece
AM		 2826 touch_nmi_watchdog();
2827
68aa2c0d
AM		 2828 local_irq_save(flags);
2829 if (up->port.sysrq) {
2830 /* serial8250_handle_port() already took the lock */
2831 locked = 0;
2832 } else if (oops_in_progress) {
2833 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2834 } else
68aa2c0d 2835 spin_lock(&up->port.lock);
d8a5a8d7 2836
1da177e4 2837 /*
dc7bf130 2838 * First save the IER then disable the interrupts
1da177e4
LT		 2839 */
2840 ier = serial_in(up, UART_IER);
2841
2842 if (up->capabilities & UART_CAP_UUE)
2843 serial_out(up, UART_IER, UART_IER_UUE);
2844 else
2845 serial_out(up, UART_IER, 0);
2846
d358788f 2847 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2848
2849 /*
2850 * Finally, wait for transmitter to become empty
2851 * and restore the IER
2852 */
f91a3715 2853 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2854 serial_out(up, UART_IER, ier);
d8a5a8d7 2855
ad4c2aa6
CM		 2856 /*
2857 * The receive handling will happen properly because the
2858 * receive ready bit will still be set; it is not cleared
2859 * on read. However, modem control will not, we must
2860 * call it if we have saved something in the saved flags
2861 * while processing with interrupts off.
2862 */
2863 if (up->msr_saved_flags)
3986fb2b 2864 serial8250_modem_status(up);
ad4c2aa6 2865
d8a5a8d7 2866 if (locked)
68aa2c0d
AM		 2867 spin_unlock(&up->port.lock);
2868 local_irq_restore(flags);
1da177e4
LT		 2869}
2870
118c0ace 2871static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2872{
2873 struct uart_port *port;
2874 int baud = 9600;
2875 int bits = 8;
2876 int parity = 'n';
2877 int flow = 'n';
2878
2879 /*
2880 * Check whether an invalid uart number has been specified, and
2881 * if so, search for the first available port that does have
2882 * console support.
2883 */
a61c2d78 2884 if (co->index >= nr_uarts)
1da177e4
LT		 2885 co->index = 0;
2886 port = &serial8250_ports[co->index].port;
2887 if (!port->iobase && !port->membase)
2888 return -ENODEV;
2889
2890 if (options)
2891 uart_parse_options(options, &baud, &parity, &bits, &flow);
2892
2893 return uart_set_options(port, co, baud, parity, bits, flow);
2894}
2895
b6b1d877 2896static int serial8250_console_early_setup(void)
18a8bd94
YL		 2897{
2898 return serial8250_find_port_for_earlycon();
2899}
2900
1da177e4
LT		 2901static struct console serial8250_console = {
2902 .name = "ttyS",
2903 .write = serial8250_console_write,
2904 .device = uart_console_device,
2905 .setup = serial8250_console_setup,
18a8bd94 2906 .early_setup = serial8250_console_early_setup,
a80c49db 2907 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2908 .index = -1,
2909 .data = &serial8250_reg,
2910};
2911
2912static int __init serial8250_console_init(void)
2913{
05d81d22
EB		 2914 if (nr_uarts > UART_NR)
2915 nr_uarts = UART_NR;
2916
1da177e4
LT		 2917 serial8250_isa_init_ports();
2918 register_console(&serial8250_console);
2919 return 0;
2920}
2921console_initcall(serial8250_console_init);
2922
18a8bd94 2923int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2924{
2925 int line;
2926 struct uart_port *port;
2927
a61c2d78 2928 for (line = 0; line < nr_uarts; line++) {
1da177e4 2929 port = &serial8250_ports[line].port;
50aec3b5 2930 if (uart_match_port(p, port))
1da177e4
LT		 2931 return line;
2932 }
2933 return -ENODEV;
2934}
2935
1da177e4
LT		 2936#define SERIAL8250_CONSOLE &serial8250_console
2937#else
2938#define SERIAL8250_CONSOLE NULL
2939#endif
2940
2941static struct uart_driver serial8250_reg = {
2942 .owner = THIS_MODULE,
2943 .driver_name = "serial",
1da177e4
LT		 2944 .dev_name = "ttyS",
2945 .major = TTY_MAJOR,
2946 .minor = 64,
1da177e4
LT		 2947 .cons = SERIAL8250_CONSOLE,
2948};
2949
d856c666
RK		 2950/*
2951 * early_serial_setup - early registration for 8250 ports
2952 *
2953 * Setup an 8250 port structure prior to console initialisation. Use
2954 * after console initialisation will cause undefined behaviour.
2955 */
1da177e4
LT		 2956int __init early_serial_setup(struct uart_port *port)
2957{
b430428a
DD		 2958 struct uart_port *p;
2959
1da177e4
LT		 2960 if (port->line >= ARRAY_SIZE(serial8250_ports))
2961 return -ENODEV;
2962
2963 serial8250_isa_init_ports();
b430428a
DD		 2964 p = &serial8250_ports[port->line].port;
2965 p->iobase = port->iobase;
2966 p->membase = port->membase;
2967 p->irq = port->irq;
1c2f0493 2968 p->irqflags = port->irqflags;
b430428a
DD		 2969 p->uartclk = port->uartclk;
2970 p->fifosize = port->fifosize;
2971 p->regshift = port->regshift;
2972 p->iotype = port->iotype;
2973 p->flags = port->flags;
2974 p->mapbase = port->mapbase;
2975 p->private_data = port->private_data;
125c97d8
HD		 2976 p->type = port->type;
2977 p->line = port->line;
7d6a07d1
DD		 2978
2979 set_io_from_upio(p);
2980 if (port->serial_in)
2981 p->serial_in = port->serial_in;
2982 if (port->serial_out)
2983 p->serial_out = port->serial_out;
583d28e9
JI		 2984 if (port->handle_irq)
2985 p->handle_irq = port->handle_irq;
2986 else
2987 p->handle_irq = serial8250_default_handle_irq;
7d6a07d1 2988
1da177e4
LT		 2989 return 0;
2990}
2991
2992/**
2993 * serial8250_suspend_port - suspend one serial port
2994 * @line: serial line number
1da177e4
LT		 2995 *
2996 * Suspend one serial port.
2997 */
2998void serial8250_suspend_port(int line)
2999{
3000 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3001}
3002
3003/**
3004 * serial8250_resume_port - resume one serial port
3005 * @line: serial line number
1da177e4
LT		 3006 *
3007 * Resume one serial port.
3008 */
3009void serial8250_resume_port(int line)
3010{
b5b82df6
DW		 3011 struct uart_8250_port *up = &serial8250_ports[line];
3012
3013 if (up->capabilities & UART_NATSEMI) {
b5b82df6
DW		 3014 /* Ensure it's still in high speed mode */
3015 serial_outp(up, UART_LCR, 0xE0);
3016
0d0389e5 3017 ns16550a_goto_highspeed(up);
b5b82df6
DW		 3018
3019 serial_outp(up, UART_LCR, 0);
95926d2d 3020 up->port.uartclk = 921600*16;
b5b82df6
DW		 3021 }
3022 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 3023}
3024
3025/*
3026 * Register a set of serial devices attached to a platform device. The
3027 * list is terminated with a zero flags entry, which means we expect
3028 * all entries to have at least UPF_BOOT_AUTOCONF set.
3029 */
3ae5eaec 3030static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 3031{
3ae5eaec 3032 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 3033 struct uart_port port;
4c0ebb80 3034 int ret, i, irqflag = 0;
1da177e4
LT		 3035
3036 memset(&port, 0, sizeof(struct uart_port));
3037
4c0ebb80
AGR		 3038 if (share_irqs)
3039 irqflag = IRQF_SHARED;
3040
ec9f47cd 3041 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 3042 port.iobase = p->iobase;
3043 port.membase = p->membase;
3044 port.irq = p->irq;
1c2f0493 3045 port.irqflags = p->irqflags;
74a19741
WN		 3046 port.uartclk = p->uartclk;
3047 port.regshift = p->regshift;
3048 port.iotype = p->iotype;
3049 port.flags = p->flags;
3050 port.mapbase = p->mapbase;
3051 port.hub6 = p->hub6;
3052 port.private_data = p->private_data;
8e23fcc8 3053 port.type = p->type;
7d6a07d1
DD		 3054 port.serial_in = p->serial_in;
3055 port.serial_out = p->serial_out;
583d28e9 3056 port.handle_irq = p->handle_irq;
235dae5d 3057 port.set_termios = p->set_termios;
c161afe9 3058 port.pm = p->pm;
74a19741 3059 port.dev = &dev->dev;
4c0ebb80 3060 port.irqflags |= irqflag;
ec9f47cd
RK		 3061 ret = serial8250_register_port(&port);
3062 if (ret < 0) {
3ae5eaec 3063 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3064 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3065 p->iobase, (unsigned long long)p->mapbase,
3066 p->irq, ret);
ec9f47cd 3067 }
1da177e4
LT		 3068 }
3069 return 0;
3070}
3071
3072/*
3073 * Remove serial ports registered against a platform device.
3074 */
3ae5eaec 3075static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3076{
3077 int i;
3078
a61c2d78 3079 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3080 struct uart_8250_port *up = &serial8250_ports[i];
3081
3ae5eaec 3082 if (up->port.dev == &dev->dev)
1da177e4
LT		 3083 serial8250_unregister_port(i);
3084 }
3085 return 0;
3086}
3087
3ae5eaec 3088static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3089{
3090 int i;
3091
1da177e4
LT		 3092 for (i = 0; i < UART_NR; i++) {
3093 struct uart_8250_port *up = &serial8250_ports[i];
3094
3ae5eaec 3095 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3096 uart_suspend_port(&serial8250_reg, &up->port);
3097 }
3098
3099 return 0;
3100}
3101
3ae5eaec 3102static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3103{
3104 int i;
3105
1da177e4
LT		 3106 for (i = 0; i < UART_NR; i++) {
3107 struct uart_8250_port *up = &serial8250_ports[i];
3108
3ae5eaec 3109 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3110 serial8250_resume_port(i);
1da177e4
LT		 3111 }
3112
3113 return 0;
3114}
3115
3ae5eaec 3116static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3117 .probe = serial8250_probe,
3118 .remove = __devexit_p(serial8250_remove),
3119 .suspend = serial8250_suspend,
3120 .resume = serial8250_resume,
3ae5eaec
RK		 3121 .driver = {
3122 .name = "serial8250",
7493a314 3123 .owner = THIS_MODULE,
3ae5eaec 3124 },
1da177e4
LT		 3125};
3126
3127/*
3128 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3129 * in the table in include/asm/serial.h
3130 */
3131static struct platform_device *serial8250_isa_devs;
3132
3133/*
3134 * serial8250_register_port and serial8250_unregister_port allows for
3135 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3136 * modems and PCI multiport cards.
3137 */
f392ecfa 3138static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3139
3140static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3141{
3142 int i;
3143
3144 /*
3145 * First, find a port entry which matches.
3146 */
a61c2d78 3147 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3148 if (uart_match_port(&serial8250_ports[i].port, port))
3149 return &serial8250_ports[i];
3150
3151 /*
3152 * We didn't find a matching entry, so look for the first
3153 * free entry. We look for one which hasn't been previously
3154 * used (indicated by zero iobase).
3155 */
a61c2d78 3156 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3157 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3158 serial8250_ports[i].port.iobase == 0)
3159 return &serial8250_ports[i];
3160
3161 /*
3162 * That also failed. Last resort is to find any entry which
3163 * doesn't have a real port associated with it.
3164 */
a61c2d78 3165 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3166 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3167 return &serial8250_ports[i];
3168
3169 return NULL;
3170}
3171
3172/**
3173 * serial8250_register_port - register a serial port
3174 * @port: serial port template
3175 *
3176 * Configure the serial port specified by the request. If the
3177 * port exists and is in use, it is hung up and unregistered
3178 * first.
3179 *
3180 * The port is then probed and if necessary the IRQ is autodetected
3181 * If this fails an error is returned.
3182 *
3183 * On success the port is ready to use and the line number is returned.
3184 */
3185int serial8250_register_port(struct uart_port *port)
3186{
3187 struct uart_8250_port *uart;
3188 int ret = -ENOSPC;
3189
3190 if (port->uartclk == 0)
3191 return -EINVAL;
3192
f392ecfa 3193 mutex_lock(&serial_mutex);
1da177e4
LT		 3194
3195 uart = serial8250_find_match_or_unused(port);
3196 if (uart) {
3197 uart_remove_one_port(&serial8250_reg, &uart->port);
3198
74a19741
WN		 3199 uart->port.iobase = port->iobase;
3200 uart->port.membase = port->membase;
3201 uart->port.irq = port->irq;
1c2f0493 3202 uart->port.irqflags = port->irqflags;
74a19741
WN		 3203 uart->port.uartclk = port->uartclk;
3204 uart->port.fifosize = port->fifosize;
3205 uart->port.regshift = port->regshift;
3206 uart->port.iotype = port->iotype;
3207 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3208 uart->port.mapbase = port->mapbase;
3209 uart->port.private_data = port->private_data;
1da177e4
LT		 3210 if (port->dev)
3211 uart->port.dev = port->dev;
8e23fcc8 3212
b5d228cc
SL		 3213 if (port->flags & UPF_FIXED_TYPE)
3214 serial8250_init_fixed_type_port(uart, port->type);
8e23fcc8 3215
7d6a07d1
DD		 3216 set_io_from_upio(&uart->port);
3217 /* Possibly override default I/O functions. */
3218 if (port->serial_in)
3219 uart->port.serial_in = port->serial_in;
3220 if (port->serial_out)
3221 uart->port.serial_out = port->serial_out;
583d28e9
JI		 3222 if (port->handle_irq)
3223 uart->port.handle_irq = port->handle_irq;
235dae5d
PL		 3224 /* Possibly override set_termios call */
3225 if (port->set_termios)
3226 uart->port.set_termios = port->set_termios;
c161afe9
ML		 3227 if (port->pm)
3228 uart->port.pm = port->pm;
1da177e4 3229
af7f3743
AC		 3230 if (serial8250_isa_config != NULL)
3231 serial8250_isa_config(0, &uart->port,
3232 &uart->capabilities);
3233
1da177e4
LT		 3234 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3235 if (ret == 0)
3236 ret = uart->port.line;
3237 }
f392ecfa 3238 mutex_unlock(&serial_mutex);
1da177e4
LT		 3239
3240 return ret;
3241}
3242EXPORT_SYMBOL(serial8250_register_port);
3243
3244/**
3245 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3246 * @line: serial line number
3247 *
3248 * Remove one serial port. This may not be called from interrupt
3249 * context. We hand the port back to the our control.
3250 */
3251void serial8250_unregister_port(int line)
3252{
3253 struct uart_8250_port *uart = &serial8250_ports[line];
3254
f392ecfa 3255 mutex_lock(&serial_mutex);
1da177e4
LT		 3256 uart_remove_one_port(&serial8250_reg, &uart->port);
3257 if (serial8250_isa_devs) {
3258 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3259 uart->port.type = PORT_UNKNOWN;
3260 uart->port.dev = &serial8250_isa_devs->dev;
cb01ece3 3261 uart->capabilities = uart_config[uart->port.type].flags;
1da177e4
LT		 3262 uart_add_one_port(&serial8250_reg, &uart->port);
3263 } else {
3264 uart->port.dev = NULL;
3265 }
f392ecfa 3266 mutex_unlock(&serial_mutex);
1da177e4
LT		 3267}
3268EXPORT_SYMBOL(serial8250_unregister_port);
3269
3270static int __init serial8250_init(void)
3271{
25db8ad5 3272 int ret;
1da177e4 3273
a61c2d78
DJ		 3274 if (nr_uarts > UART_NR)
3275 nr_uarts = UART_NR;
3276
f1fb9bb8 3277 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3278 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3279 share_irqs ? "en" : "dis");
3280
b70ac771
DM		 3281#ifdef CONFIG_SPARC
3282 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3283#else
3284 serial8250_reg.nr = UART_NR;
1da177e4 3285 ret = uart_register_driver(&serial8250_reg);
b70ac771 3286#endif
1da177e4
LT		 3287 if (ret)
3288 goto out;
3289
7493a314
DT		 3290 serial8250_isa_devs = platform_device_alloc("serial8250",
3291 PLAT8250_DEV_LEGACY);
3292 if (!serial8250_isa_devs) {
3293 ret = -ENOMEM;
bc965a7f 3294 goto unreg_uart_drv;
1da177e4
LT		 3295 }
3296
7493a314
DT		 3297 ret = platform_device_add(serial8250_isa_devs);
3298 if (ret)
3299 goto put_dev;
3300
1da177e4
LT		 3301 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3302
bc965a7f
RK		 3303 ret = platform_driver_register(&serial8250_isa_driver);
3304 if (ret == 0)
3305 goto out;
1da177e4 3306
bc965a7f 3307 platform_device_del(serial8250_isa_devs);
25db8ad5 3308put_dev:
7493a314 3309 platform_device_put(serial8250_isa_devs);
25db8ad5 3310unreg_uart_drv:
b70ac771
DM		 3311#ifdef CONFIG_SPARC
3312 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3313#else
1da177e4 3314 uart_unregister_driver(&serial8250_reg);
b70ac771 3315#endif
25db8ad5 3316out:
1da177e4
LT		 3317 return ret;
3318}
3319
3320static void __exit serial8250_exit(void)
3321{
3322 struct platform_device *isa_dev = serial8250_isa_devs;
3323
3324 /*
3325 * This tells serial8250_unregister_port() not to re-register
3326 * the ports (thereby making serial8250_isa_driver permanently
3327 * in use.)
3328 */
3329 serial8250_isa_devs = NULL;
3330
3ae5eaec 3331 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3332 platform_device_unregister(isa_dev);
3333
b70ac771
DM		 3334#ifdef CONFIG_SPARC
3335 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3336#else
1da177e4 3337 uart_unregister_driver(&serial8250_reg);
b70ac771 3338#endif
1da177e4
LT		 3339}
3340
3341module_init(serial8250_init);
3342module_exit(serial8250_exit);
3343
3344EXPORT_SYMBOL(serial8250_suspend_port);
3345EXPORT_SYMBOL(serial8250_resume_port);
3346
3347MODULE_LICENSE("GPL");
d87a6d95 3348MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3349
3350module_param(share_irqs, uint, 0644);
3351MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3352 " (unsafe)");
3353
a61c2d78
DJ		 3354module_param(nr_uarts, uint, 0644);
3355MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3356
d41a4b51
CE		 3357module_param(skip_txen_test, uint, 0644);
3358MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3359
1da177e4
LT		 3360#ifdef CONFIG_SERIAL_8250_RSA
3361module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3362MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3363#endif
3364MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
kernel source for telekom puls (alcatel/mediatek)