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Merge tag 'tty-3.3-rc3' tty-next
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / 8250 / 8250.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
1da177e4
LT		 41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
b70ac771 47#ifdef CONFIG_SPARC
e7c9bba7 48#include "../suncore.h"
b70ac771
DM		 49#endif
50
1da177e4
LT		 51/*
52 * Configuration:
40663cc7 53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 54 * is unsafe when used on edge-triggered interrupts.
55 */
408b664a 56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 57
a61c2d78
DJ		 58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
8440838b
DM		 60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
d41a4b51
CE		 67static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
1da177e4
LT		 69/*
70 * Debugging.
71 */
72#if 0
73#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74#else
75#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76#endif
77
78#if 0
79#define DEBUG_INTR(fmt...) printk(fmt)
80#else
81#define DEBUG_INTR(fmt...) do { } while (0)
82#endif
83
e7328ae1 84#define PASS_LIMIT 512
1da177e4 85
bca47613
DH		 86#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
1da177e4
LT		 89#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
90#define CONFIG_SERIAL_DETECT_IRQ 1
91#endif
1da177e4
LT		 92#ifdef CONFIG_SERIAL_8250_MANY_PORTS
93#define CONFIG_SERIAL_MANY_PORTS 1
94#endif
95
96/*
97 * HUB6 is always on. This will be removed once the header
98 * files have been cleaned.
99 */
100#define CONFIG_HUB6 1
101
a4ed1e41 102#include <asm/serial.h>
1da177e4
LT		 103/*
104 * SERIAL_PORT_DFNS tells us about built-in ports that have no
105 * standard enumeration mechanism. Platforms that can find all
106 * serial ports via mechanisms like ACPI or PCI need not supply it.
107 */
108#ifndef SERIAL_PORT_DFNS
109#define SERIAL_PORT_DFNS
110#endif
111
cb3592be 112static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 113 SERIAL_PORT_DFNS /* defined in asm/serial.h */
114};
115
026d02a2 116#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 117
118#ifdef CONFIG_SERIAL_8250_RSA
119
120#define PORT_RSA_MAX 4
121static unsigned long probe_rsa[PORT_RSA_MAX];
122static unsigned int probe_rsa_count;
123#endif /* CONFIG_SERIAL_8250_RSA */
124
1da177e4 125struct irq_info {
25db8ad5
AC		 126 struct hlist_node node;
127 int irq;
128 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 129 struct list_head *head;
130};
131
25db8ad5
AC		 132#define NR_IRQ_HASH 32 /* Can be adjusted later */
133static struct hlist_head irq_lists[NR_IRQ_HASH];
134static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 135
136/*
137 * Here we define the default xmit fifo size used for each type of UART.
138 */
139static const struct serial8250_config uart_config[] = {
140 [PORT_UNKNOWN] = {
141 .name = "unknown",
142 .fifo_size = 1,
143 .tx_loadsz = 1,
144 },
145 [PORT_8250] = {
146 .name = "8250",
147 .fifo_size = 1,
148 .tx_loadsz = 1,
149 },
150 [PORT_16450] = {
151 .name = "16450",
152 .fifo_size = 1,
153 .tx_loadsz = 1,
154 },
155 [PORT_16550] = {
156 .name = "16550",
157 .fifo_size = 1,
158 .tx_loadsz = 1,
159 },
160 [PORT_16550A] = {
161 .name = "16550A",
162 .fifo_size = 16,
163 .tx_loadsz = 16,
164 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
165 .flags = UART_CAP_FIFO,
166 },
167 [PORT_CIRRUS] = {
168 .name = "Cirrus",
169 .fifo_size = 1,
170 .tx_loadsz = 1,
171 },
172 [PORT_16650] = {
173 .name = "ST16650",
174 .fifo_size = 1,
175 .tx_loadsz = 1,
176 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
177 },
178 [PORT_16650V2] = {
179 .name = "ST16650V2",
180 .fifo_size = 32,
181 .tx_loadsz = 16,
182 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
183 UART_FCR_T_TRIG_00,
184 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
185 },
186 [PORT_16750] = {
187 .name = "TI16750",
188 .fifo_size = 64,
189 .tx_loadsz = 64,
190 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
191 UART_FCR7_64BYTE,
192 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
193 },
194 [PORT_STARTECH] = {
195 .name = "Startech",
196 .fifo_size = 1,
197 .tx_loadsz = 1,
198 },
199 [PORT_16C950] = {
200 .name = "16C950/954",
201 .fifo_size = 128,
202 .tx_loadsz = 128,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 204 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
205 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 206 },
207 [PORT_16654] = {
208 .name = "ST16654",
209 .fifo_size = 64,
210 .tx_loadsz = 32,
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
212 UART_FCR_T_TRIG_10,
213 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
214 },
215 [PORT_16850] = {
216 .name = "XR16850",
217 .fifo_size = 128,
218 .tx_loadsz = 128,
219 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
220 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
221 },
222 [PORT_RSA] = {
223 .name = "RSA",
224 .fifo_size = 2048,
225 .tx_loadsz = 2048,
226 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
227 .flags = UART_CAP_FIFO,
228 },
229 [PORT_NS16550A] = {
230 .name = "NS16550A",
231 .fifo_size = 16,
232 .tx_loadsz = 16,
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
234 .flags = UART_CAP_FIFO | UART_NATSEMI,
235 },
236 [PORT_XSCALE] = {
237 .name = "XScale",
238 .fifo_size = 32,
239 .tx_loadsz = 32,
240 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 241 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 242 },
bd71c182
TK		 243 [PORT_RM9000] = {
244 .name = "RM9000",
245 .fifo_size = 16,
246 .tx_loadsz = 16,
247 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 248 .flags = UART_CAP_FIFO,
249 },
250 [PORT_OCTEON] = {
251 .name = "OCTEON",
252 .fifo_size = 64,
253 .tx_loadsz = 64,
254 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 255 .flags = UART_CAP_FIFO,
256 },
08e0992f
FF		 257 [PORT_AR7] = {
258 .name = "AR7",
259 .fifo_size = 16,
260 .tx_loadsz = 16,
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
262 .flags = UART_CAP_FIFO | UART_CAP_AFE,
263 },
235dae5d
PL		 264 [PORT_U6_16550A] = {
265 .name = "U6_16550A",
266 .fifo_size = 64,
267 .tx_loadsz = 64,
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
269 .flags = UART_CAP_FIFO | UART_CAP_AFE,
270 },
4539c24f
SW		 271 [PORT_TEGRA] = {
272 .name = "Tegra",
273 .fifo_size = 32,
274 .tx_loadsz = 8,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
276 UART_FCR_T_TRIG_01,
277 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
278 },
06315348
SH		 279 [PORT_XR17D15X] = {
280 .name = "XR17D15X",
281 .fifo_size = 64,
282 .tx_loadsz = 64,
283 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
284 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
285 },
1da177e4
LT		 286};
287
12bf3f24 288#if defined(CONFIG_MIPS_ALCHEMY)
21c614a7
PA		 289
290/* Au1x00 UART hardware has a weird register layout */
291static const u8 au_io_in_map[] = {
292 [UART_RX] = 0,
293 [UART_IER] = 2,
294 [UART_IIR] = 3,
295 [UART_LCR] = 5,
296 [UART_MCR] = 6,
297 [UART_LSR] = 7,
298 [UART_MSR] = 8,
299};
300
301static const u8 au_io_out_map[] = {
302 [UART_TX] = 1,
303 [UART_IER] = 2,
304 [UART_FCR] = 4,
305 [UART_LCR] = 5,
306 [UART_MCR] = 6,
307};
308
309/* sane hardware needs no mapping */
7d6a07d1 310static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 311{
7d6a07d1 312 if (p->iotype != UPIO_AU)
21c614a7
PA		 313 return offset;
314 return au_io_in_map[offset];
315}
316
7d6a07d1 317static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 318{
7d6a07d1 319 if (p->iotype != UPIO_AU)
21c614a7
PA		 320 return offset;
321 return au_io_out_map[offset];
322}
323
6f803cd0 324#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 325
326static const u8
327 regmap_in[8] = {
328 [UART_RX] = 0x00,
329 [UART_IER] = 0x0c,
330 [UART_IIR] = 0x14,
331 [UART_LCR] = 0x1c,
332 [UART_MCR] = 0x20,
333 [UART_LSR] = 0x24,
334 [UART_MSR] = 0x28,
335 [UART_SCR] = 0x2c
336 },
337 regmap_out[8] = {
338 [UART_TX] = 0x04,
339 [UART_IER] = 0x0c,
340 [UART_FCR] = 0x18,
341 [UART_LCR] = 0x1c,
342 [UART_MCR] = 0x20,
343 [UART_LSR] = 0x24,
344 [UART_MSR] = 0x28,
345 [UART_SCR] = 0x2c
346 };
347
7d6a07d1 348static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 349{
7d6a07d1 350 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 351 return offset;
352 return regmap_in[offset];
353}
354
7d6a07d1 355static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 356{
7d6a07d1 357 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 358 return offset;
359 return regmap_out[offset];
360}
361
21c614a7
PA		 362#else
363
364/* sane hardware needs no mapping */
365#define map_8250_in_reg(up, offset) (offset)
366#define map_8250_out_reg(up, offset) (offset)
367
368#endif
369
7d6a07d1 370static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 371{
7d6a07d1
DD		 372 offset = map_8250_in_reg(p, offset) << p->regshift;
373 outb(p->hub6 - 1 + offset, p->iobase);
374 return inb(p->iobase + 1);
375}
1da177e4 376
7d6a07d1
DD		 377static void hub6_serial_out(struct uart_port *p, int offset, int value)
378{
379 offset = map_8250_out_reg(p, offset) << p->regshift;
380 outb(p->hub6 - 1 + offset, p->iobase);
381 outb(value, p->iobase + 1);
382}
1da177e4 383
7d6a07d1
DD		 384static unsigned int mem_serial_in(struct uart_port *p, int offset)
385{
386 offset = map_8250_in_reg(p, offset) << p->regshift;
387 return readb(p->membase + offset);
388}
1da177e4 389
7d6a07d1
DD		 390static void mem_serial_out(struct uart_port *p, int offset, int value)
391{
392 offset = map_8250_out_reg(p, offset) << p->regshift;
393 writeb(value, p->membase + offset);
394}
395
396static void mem32_serial_out(struct uart_port *p, int offset, int value)
397{
398 offset = map_8250_out_reg(p, offset) << p->regshift;
399 writel(value, p->membase + offset);
400}
401
402static unsigned int mem32_serial_in(struct uart_port *p, int offset)
403{
404 offset = map_8250_in_reg(p, offset) << p->regshift;
405 return readl(p->membase + offset);
406}
1da177e4 407
7d6a07d1
DD		 408static unsigned int au_serial_in(struct uart_port *p, int offset)
409{
410 offset = map_8250_in_reg(p, offset) << p->regshift;
411 return __raw_readl(p->membase + offset);
412}
413
414static void au_serial_out(struct uart_port *p, int offset, int value)
415{
416 offset = map_8250_out_reg(p, offset) << p->regshift;
417 __raw_writel(value, p->membase + offset);
418}
21c614a7 419
7d6a07d1
DD		 420static unsigned int io_serial_in(struct uart_port *p, int offset)
421{
422 offset = map_8250_in_reg(p, offset) << p->regshift;
423 return inb(p->iobase + offset);
424}
425
426static void io_serial_out(struct uart_port *p, int offset, int value)
427{
428 offset = map_8250_out_reg(p, offset) << p->regshift;
429 outb(value, p->iobase + offset);
430}
431
583d28e9
JI		 432static int serial8250_default_handle_irq(struct uart_port *port);
433
7d6a07d1
DD		 434static void set_io_from_upio(struct uart_port *p)
435{
49d5741b
JI		 436 struct uart_8250_port *up =
437 container_of(p, struct uart_8250_port, port);
7d6a07d1 438 switch (p->iotype) {
1da177e4 439 case UPIO_HUB6:
7d6a07d1
DD		 440 p->serial_in = hub6_serial_in;
441 p->serial_out = hub6_serial_out;
1da177e4
LT		 442 break;
443
444 case UPIO_MEM:
7d6a07d1
DD		 445 p->serial_in = mem_serial_in;
446 p->serial_out = mem_serial_out;
1da177e4
LT		 447 break;
448
bd71c182 449 case UPIO_RM9000:
1da177e4 450 case UPIO_MEM32:
7d6a07d1
DD		 451 p->serial_in = mem32_serial_in;
452 p->serial_out = mem32_serial_out;
1da177e4
LT		 453 break;
454
21c614a7 455 case UPIO_AU:
7d6a07d1
DD		 456 p->serial_in = au_serial_in;
457 p->serial_out = au_serial_out;
21c614a7 458 break;
12bf3f24 459
1da177e4 460 default:
7d6a07d1
DD		 461 p->serial_in = io_serial_in;
462 p->serial_out = io_serial_out;
463 break;
1da177e4 464 }
b8e7e40a
AC		 465 /* Remember loaded iotype */
466 up->cur_iotype = p->iotype;
583d28e9 467 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 468}
469
40b36daa
AW		 470static void
471serial_out_sync(struct uart_8250_port *up, int offset, int value)
472{
7d6a07d1
DD		 473 struct uart_port *p = &up->port;
474 switch (p->iotype) {
40b36daa
AW		 475 case UPIO_MEM:
476 case UPIO_MEM32:
40b36daa 477 case UPIO_AU:
7d6a07d1
DD		 478 p->serial_out(p, offset, value);
479 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 480 break;
481 default:
7d6a07d1 482 p->serial_out(p, offset, value);
40b36daa
AW		 483 }
484}
485
7d6a07d1
DD		 486#define serial_in(up, offset) \
487 (up->port.serial_in(&(up)->port, (offset)))
488#define serial_out(up, offset, value) \
489 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 490/*
491 * We used to support using pause I/O for certain machines. We
492 * haven't supported this for a while, but just in case it's badly
493 * needed for certain old 386 machines, I've left these #define's
494 * in....
495 */
496#define serial_inp(up, offset) serial_in(up, offset)
497#define serial_outp(up, offset, value) serial_out(up, offset, value)
498
b32b19b8
JAH		 499/* Uart divisor latch read */
500static inline int _serial_dl_read(struct uart_8250_port *up)
501{
502 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
503}
504
505/* Uart divisor latch write */
506static inline void _serial_dl_write(struct uart_8250_port *up, int value)
507{
508 serial_outp(up, UART_DLL, value & 0xff);
509 serial_outp(up, UART_DLM, value >> 8 & 0xff);
510}
511
12bf3f24 512#if defined(CONFIG_MIPS_ALCHEMY)
b32b19b8
JAH		 513/* Au1x00 haven't got a standard divisor latch */
514static int serial_dl_read(struct uart_8250_port *up)
515{
516 if (up->port.iotype == UPIO_AU)
517 return __raw_readl(up->port.membase + 0x28);
518 else
519 return _serial_dl_read(up);
520}
521
522static void serial_dl_write(struct uart_8250_port *up, int value)
523{
524 if (up->port.iotype == UPIO_AU)
525 __raw_writel(value, up->port.membase + 0x28);
526 else
527 _serial_dl_write(up, value);
528}
6f803cd0 529#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 530static int serial_dl_read(struct uart_8250_port *up)
531{
532 return (up->port.iotype == UPIO_RM9000) ?
533 (((__raw_readl(up->port.membase + 0x10) << 8) |
534 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
535 _serial_dl_read(up);
536}
537
538static void serial_dl_write(struct uart_8250_port *up, int value)
539{
540 if (up->port.iotype == UPIO_RM9000) {
541 __raw_writel(value, up->port.membase + 0x08);
542 __raw_writel(value >> 8, up->port.membase + 0x10);
543 } else {
544 _serial_dl_write(up, value);
545 }
546}
b32b19b8
JAH		 547#else
548#define serial_dl_read(up) _serial_dl_read(up)
549#define serial_dl_write(up, value) _serial_dl_write(up, value)
550#endif
1da177e4
LT		 551
552/*
553 * For the 16C950
554 */
555static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
556{
557 serial_out(up, UART_SCR, offset);
558 serial_out(up, UART_ICR, value);
559}
560
561static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
562{
563 unsigned int value;
564
565 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
566 serial_out(up, UART_SCR, offset);
567 value = serial_in(up, UART_ICR);
568 serial_icr_write(up, UART_ACR, up->acr);
569
570 return value;
571}
572
573/*
574 * FIFO support.
575 */
b5d674ab 576static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 577{
578 if (p->capabilities & UART_CAP_FIFO) {
579 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
580 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
581 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
582 serial_outp(p, UART_FCR, 0);
583 }
584}
585
586/*
587 * IER sleep support. UARTs which have EFRs need the "extended
588 * capability" bit enabled. Note that on XR16C850s, we need to
589 * reset LCR to write to IER.
590 */
b5d674ab 591static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 592{
593 if (p->capabilities & UART_CAP_SLEEP) {
594 if (p->capabilities & UART_CAP_EFR) {
662b083a 595 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 596 serial_outp(p, UART_EFR, UART_EFR_ECB);
597 serial_outp(p, UART_LCR, 0);
598 }
599 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
600 if (p->capabilities & UART_CAP_EFR) {
662b083a 601 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 602 serial_outp(p, UART_EFR, 0);
603 serial_outp(p, UART_LCR, 0);
604 }
605 }
606}
607
608#ifdef CONFIG_SERIAL_8250_RSA
609/*
610 * Attempts to turn on the RSA FIFO. Returns zero on failure.
611 * We set the port uart clock rate if we succeed.
612 */
613static int __enable_rsa(struct uart_8250_port *up)
614{
615 unsigned char mode;
616 int result;
617
618 mode = serial_inp(up, UART_RSA_MSR);
619 result = mode & UART_RSA_MSR_FIFO;
620
621 if (!result) {
622 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
623 mode = serial_inp(up, UART_RSA_MSR);
624 result = mode & UART_RSA_MSR_FIFO;
625 }
626
627 if (result)
628 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
629
630 return result;
631}
632
633static void enable_rsa(struct uart_8250_port *up)
634{
635 if (up->port.type == PORT_RSA) {
636 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
637 spin_lock_irq(&up->port.lock);
638 __enable_rsa(up);
639 spin_unlock_irq(&up->port.lock);
640 }
641 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
642 serial_outp(up, UART_RSA_FRR, 0);
643 }
644}
645
646/*
647 * Attempts to turn off the RSA FIFO. Returns zero on failure.
648 * It is unknown why interrupts were disabled in here. However,
649 * the caller is expected to preserve this behaviour by grabbing
650 * the spinlock before calling this function.
651 */
652static void disable_rsa(struct uart_8250_port *up)
653{
654 unsigned char mode;
655 int result;
656
657 if (up->port.type == PORT_RSA &&
658 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
659 spin_lock_irq(&up->port.lock);
660
661 mode = serial_inp(up, UART_RSA_MSR);
662 result = !(mode & UART_RSA_MSR_FIFO);
663
664 if (!result) {
665 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
666 mode = serial_inp(up, UART_RSA_MSR);
667 result = !(mode & UART_RSA_MSR_FIFO);
668 }
669
670 if (result)
671 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
672 spin_unlock_irq(&up->port.lock);
673 }
674}
675#endif /* CONFIG_SERIAL_8250_RSA */
676
677/*
678 * This is a quickie test to see how big the FIFO is.
679 * It doesn't work at all the time, more's the pity.
680 */
681static int size_fifo(struct uart_8250_port *up)
682{
b32b19b8
JAH		 683 unsigned char old_fcr, old_mcr, old_lcr;
684 unsigned short old_dl;
1da177e4
LT		 685 int count;
686
687 old_lcr = serial_inp(up, UART_LCR);
688 serial_outp(up, UART_LCR, 0);
689 old_fcr = serial_inp(up, UART_FCR);
690 old_mcr = serial_inp(up, UART_MCR);
691 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
692 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
693 serial_outp(up, UART_MCR, UART_MCR_LOOP);
662b083a 694 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 695 old_dl = serial_dl_read(up);
696 serial_dl_write(up, 0x0001);
1da177e4
LT		 697 serial_outp(up, UART_LCR, 0x03);
698 for (count = 0; count < 256; count++)
699 serial_outp(up, UART_TX, count);
700 mdelay(20);/* FIXME - schedule_timeout */
701 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
702 (count < 256); count++)
703 serial_inp(up, UART_RX);
704 serial_outp(up, UART_FCR, old_fcr);
705 serial_outp(up, UART_MCR, old_mcr);
662b083a 706 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 707 serial_dl_write(up, old_dl);
1da177e4
LT		 708 serial_outp(up, UART_LCR, old_lcr);
709
710 return count;
711}
712
713/*
714 * Read UART ID using the divisor method - set DLL and DLM to zero
715 * and the revision will be in DLL and device type in DLM. We
716 * preserve the device state across this.
717 */
718static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
719{
720 unsigned char old_dll, old_dlm, old_lcr;
721 unsigned int id;
722
723 old_lcr = serial_inp(p, UART_LCR);
662b083a 724 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 725
726 old_dll = serial_inp(p, UART_DLL);
727 old_dlm = serial_inp(p, UART_DLM);
728
729 serial_outp(p, UART_DLL, 0);
730 serial_outp(p, UART_DLM, 0);
731
732 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
733
734 serial_outp(p, UART_DLL, old_dll);
735 serial_outp(p, UART_DLM, old_dlm);
736 serial_outp(p, UART_LCR, old_lcr);
737
738 return id;
739}
740
741/*
742 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
743 * When this function is called we know it is at least a StarTech
744 * 16650 V2, but it might be one of several StarTech UARTs, or one of
745 * its clones. (We treat the broken original StarTech 16650 V1 as a
746 * 16550, and why not? Startech doesn't seem to even acknowledge its
747 * existence.)
bd71c182 748 *
1da177e4
LT		 749 * What evil have men's minds wrought...
750 */
751static void autoconfig_has_efr(struct uart_8250_port *up)
752{
753 unsigned int id1, id2, id3, rev;
754
755 /*
756 * Everything with an EFR has SLEEP
757 */
758 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
759
760 /*
761 * First we check to see if it's an Oxford Semiconductor UART.
762 *
763 * If we have to do this here because some non-National
764 * Semiconductor clone chips lock up if you try writing to the
765 * LSR register (which serial_icr_read does)
766 */
767
768 /*
769 * Check for Oxford Semiconductor 16C950.
770 *
771 * EFR [4] must be set else this test fails.
772 *
773 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
774 * claims that it's needed for 952 dual UART's (which are not
775 * recommended for new designs).
776 */
777 up->acr = 0;
662b083a 778 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 779 serial_out(up, UART_EFR, UART_EFR_ECB);
780 serial_out(up, UART_LCR, 0x00);
781 id1 = serial_icr_read(up, UART_ID1);
782 id2 = serial_icr_read(up, UART_ID2);
783 id3 = serial_icr_read(up, UART_ID3);
784 rev = serial_icr_read(up, UART_REV);
785
786 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
787
788 if (id1 == 0x16 && id2 == 0xC9 &&
789 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
790 up->port.type = PORT_16C950;
4ba5e35d
RK		 791
792 /*
793 * Enable work around for the Oxford Semiconductor 952 rev B
794 * chip which causes it to seriously miscalculate baud rates
795 * when DLL is 0.
796 */
797 if (id3 == 0x52 && rev == 0x01)
798 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 799 return;
800 }
bd71c182 801
1da177e4
LT		 802 /*
803 * We check for a XR16C850 by setting DLL and DLM to 0, and then
804 * reading back DLL and DLM. The chip type depends on the DLM
805 * value read back:
806 * 0x10 - XR16C850 and the DLL contains the chip revision.
807 * 0x12 - XR16C2850.
808 * 0x14 - XR16C854.
809 */
810 id1 = autoconfig_read_divisor_id(up);
811 DEBUG_AUTOCONF("850id=%04x ", id1);
812
813 id2 = id1 >> 8;
814 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 815 up->port.type = PORT_16850;
816 return;
817 }
818
819 /*
820 * It wasn't an XR16C850.
821 *
822 * We distinguish between the '654 and the '650 by counting
823 * how many bytes are in the FIFO. I'm using this for now,
824 * since that's the technique that was sent to me in the
825 * serial driver update, but I'm not convinced this works.
826 * I've had problems doing this in the past. -TYT
827 */
828 if (size_fifo(up) == 64)
829 up->port.type = PORT_16654;
830 else
831 up->port.type = PORT_16650V2;
832}
833
834/*
835 * We detected a chip without a FIFO. Only two fall into
836 * this category - the original 8250 and the 16450. The
837 * 16450 has a scratch register (accessible with LCR=0)
838 */
839static void autoconfig_8250(struct uart_8250_port *up)
840{
841 unsigned char scratch, status1, status2;
842
843 up->port.type = PORT_8250;
844
845 scratch = serial_in(up, UART_SCR);
846 serial_outp(up, UART_SCR, 0xa5);
847 status1 = serial_in(up, UART_SCR);
848 serial_outp(up, UART_SCR, 0x5a);
849 status2 = serial_in(up, UART_SCR);
850 serial_outp(up, UART_SCR, scratch);
851
852 if (status1 == 0xa5 && status2 == 0x5a)
853 up->port.type = PORT_16450;
854}
855
856static int broken_efr(struct uart_8250_port *up)
857{
858 /*
859 * Exar ST16C2550 "A2" devices incorrectly detect as
860 * having an EFR, and report an ID of 0x0201. See
631dd1a8 861 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 862 */
863 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
864 return 1;
865
866 return 0;
867}
868
0d0389e5
YK		 869static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
870{
871 unsigned char status;
872
873 status = serial_in(up, 0x04); /* EXCR2 */
874#define PRESL(x) ((x) & 0x30)
875 if (PRESL(status) == 0x10) {
876 /* already in high speed mode */
877 return 0;
878 } else {
879 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
880 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
881 serial_outp(up, 0x04, status);
882 }
883 return 1;
884}
885
1da177e4
LT		 886/*
887 * We know that the chip has FIFOs. Does it have an EFR? The
888 * EFR is located in the same register position as the IIR and
889 * we know the top two bits of the IIR are currently set. The
890 * EFR should contain zero. Try to read the EFR.
891 */
892static void autoconfig_16550a(struct uart_8250_port *up)
893{
894 unsigned char status1, status2;
895 unsigned int iersave;
896
897 up->port.type = PORT_16550A;
898 up->capabilities |= UART_CAP_FIFO;
899
900 /*
901 * Check for presence of the EFR when DLAB is set.
902 * Only ST16C650V1 UARTs pass this test.
903 */
662b083a 904 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 905 if (serial_in(up, UART_EFR) == 0) {
906 serial_outp(up, UART_EFR, 0xA8);
907 if (serial_in(up, UART_EFR) != 0) {
908 DEBUG_AUTOCONF("EFRv1 ");
909 up->port.type = PORT_16650;
910 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
911 } else {
912 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
913 }
914 serial_outp(up, UART_EFR, 0);
915 return;
916 }
917
918 /*
919 * Maybe it requires 0xbf to be written to the LCR.
920 * (other ST16C650V2 UARTs, TI16C752A, etc)
921 */
662b083a 922 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 923 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
924 DEBUG_AUTOCONF("EFRv2 ");
925 autoconfig_has_efr(up);
926 return;
927 }
928
929 /*
930 * Check for a National Semiconductor SuperIO chip.
931 * Attempt to switch to bank 2, read the value of the LOOP bit
932 * from EXCR1. Switch back to bank 0, change it in MCR. Then
933 * switch back to bank 2, read it from EXCR1 again and check
934 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 935 */
936 serial_outp(up, UART_LCR, 0);
937 status1 = serial_in(up, UART_MCR);
938 serial_outp(up, UART_LCR, 0xE0);
939 status2 = serial_in(up, 0x02); /* EXCR1 */
940
941 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
942 serial_outp(up, UART_LCR, 0);
943 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
944 serial_outp(up, UART_LCR, 0xE0);
945 status2 = serial_in(up, 0x02); /* EXCR1 */
946 serial_outp(up, UART_LCR, 0);
947 serial_outp(up, UART_MCR, status1);
948
949 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 950 unsigned short quot;
951
1da177e4 952 serial_outp(up, UART_LCR, 0xE0);
857dde2e 953
b32b19b8 954 quot = serial_dl_read(up);
857dde2e
DW		 955 quot <<= 3;
956
0d0389e5
YK		 957 if (ns16550a_goto_highspeed(up))
958 serial_dl_write(up, quot);
857dde2e 959
1da177e4 960 serial_outp(up, UART_LCR, 0);
1da177e4 961
857dde2e 962 up->port.uartclk = 921600*16;
1da177e4
LT		 963 up->port.type = PORT_NS16550A;
964 up->capabilities |= UART_NATSEMI;
965 return;
966 }
967 }
968
969 /*
970 * No EFR. Try to detect a TI16750, which only sets bit 5 of
971 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
972 * Try setting it with and without DLAB set. Cheap clones
973 * set bit 5 without DLAB set.
974 */
975 serial_outp(up, UART_LCR, 0);
976 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
977 status1 = serial_in(up, UART_IIR) >> 5;
978 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
662b083a 979 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 980 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
981 status2 = serial_in(up, UART_IIR) >> 5;
982 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
983 serial_outp(up, UART_LCR, 0);
984
985 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
986
987 if (status1 == 6 && status2 == 7) {
988 up->port.type = PORT_16750;
989 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
990 return;
991 }
992
993 /*
994 * Try writing and reading the UART_IER_UUE bit (b6).
995 * If it works, this is probably one of the Xscale platform's
996 * internal UARTs.
997 * We're going to explicitly set the UUE bit to 0 before
998 * trying to write and read a 1 just to make sure it's not
999 * already a 1 and maybe locked there before we even start start.
1000 */
1001 iersave = serial_in(up, UART_IER);
1002 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1003 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1004 /*
1005 * OK it's in a known zero state, try writing and reading
1006 * without disturbing the current state of the other bits.
1007 */
1008 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1009 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1010 /*
1011 * It's an Xscale.
1012 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1013 */
1014 DEBUG_AUTOCONF("Xscale ");
1015 up->port.type = PORT_XSCALE;
5568181f 1016 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 1017 return;
1018 }
1019 } else {
1020 /*
1021 * If we got here we couldn't force the IER_UUE bit to 0.
1022 * Log it and continue.
1023 */
1024 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1025 }
1026 serial_outp(up, UART_IER, iersave);
235dae5d 1027
06315348
SH		 1028 /*
1029 * Exar uarts have EFR in a weird location
1030 */
1031 if (up->port.flags & UPF_EXAR_EFR) {
1032 up->port.type = PORT_XR17D15X;
1033 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1034 }
1035
235dae5d
PL		 1036 /*
1037 * We distinguish between 16550A and U6 16550A by counting
1038 * how many bytes are in the FIFO.
1039 */
1040 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1041 up->port.type = PORT_U6_16550A;
1042 up->capabilities |= UART_CAP_AFE;
1043 }
1da177e4
LT		 1044}
1045
1046/*
1047 * This routine is called by rs_init() to initialize a specific serial
1048 * port. It determines what type of UART chip this serial port is
1049 * using: 8250, 16450, 16550, 16550A. The important question is
1050 * whether or not this UART is a 16550A or not, since this will
1051 * determine whether or not we can use its FIFO features or not.
1052 */
1053static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1054{
1055 unsigned char status1, scratch, scratch2, scratch3;
1056 unsigned char save_lcr, save_mcr;
1057 unsigned long flags;
1058
1059 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1060 return;
1061
80647b95 1062 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
8440838b 1063 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1064
1065 /*
1066 * We really do need global IRQs disabled here - we're going to
1067 * be frobbing the chips IRQ enable register to see if it exists.
1068 */
1069 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1070
1071 up->capabilities = 0;
4ba5e35d 1072 up->bugs = 0;
1da177e4
LT		 1073
1074 if (!(up->port.flags & UPF_BUGGY_UART)) {
1075 /*
1076 * Do a simple existence test first; if we fail this,
1077 * there's no point trying anything else.
bd71c182 1078 *
1da177e4
LT		 1079 * 0x80 is used as a nonsense port to prevent against
1080 * false positives due to ISA bus float. The
1081 * assumption is that 0x80 is a non-existent port;
1082 * which should be safe since include/asm/io.h also
1083 * makes this assumption.
1084 *
1085 * Note: this is safe as long as MCR bit 4 is clear
1086 * and the device is in "PC" mode.
1087 */
1088 scratch = serial_inp(up, UART_IER);
1089 serial_outp(up, UART_IER, 0);
1090#ifdef __i386__
1091 outb(0xff, 0x080);
1092#endif
48212008
TH		 1093 /*
1094 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1095 * 16C754B) allow only to modify them if an EFR bit is set.
1096 */
1097 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1098 serial_outp(up, UART_IER, 0x0F);
1099#ifdef __i386__
1100 outb(0, 0x080);
1101#endif
48212008 1102 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1103 serial_outp(up, UART_IER, scratch);
1104 if (scratch2 != 0 || scratch3 != 0x0F) {
1105 /*
1106 * We failed; there's nothing here
1107 */
1108 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1109 scratch2, scratch3);
1110 goto out;
1111 }
1112 }
1113
1114 save_mcr = serial_in(up, UART_MCR);
1115 save_lcr = serial_in(up, UART_LCR);
1116
bd71c182 1117 /*
1da177e4
LT		 1118 * Check to see if a UART is really there. Certain broken
1119 * internal modems based on the Rockwell chipset fail this
1120 * test, because they apparently don't implement the loopback
1121 * test mode. So this test is skipped on the COM 1 through
1122 * COM 4 ports. This *should* be safe, since no board
1123 * manufacturer would be stupid enough to design a board
1124 * that conflicts with COM 1-4 --- we hope!
1125 */
1126 if (!(up->port.flags & UPF_SKIP_TEST)) {
1127 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1128 status1 = serial_inp(up, UART_MSR) & 0xF0;
1129 serial_outp(up, UART_MCR, save_mcr);
1130 if (status1 != 0x90) {
1131 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1132 status1);
1133 goto out;
1134 }
1135 }
1136
1137 /*
1138 * We're pretty sure there's a port here. Lets find out what
1139 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1140 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1141 * determines what we test for next.
1142 *
1143 * We also initialise the EFR (if any) to zero for later. The
1144 * EFR occupies the same register location as the FCR and IIR.
1145 */
662b083a 1146 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1147 serial_outp(up, UART_EFR, 0);
1148 serial_outp(up, UART_LCR, 0);
1149
1150 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1151 scratch = serial_in(up, UART_IIR) >> 6;
1152
1153 DEBUG_AUTOCONF("iir=%d ", scratch);
1154
1155 switch (scratch) {
1156 case 0:
1157 autoconfig_8250(up);
1158 break;
1159 case 1:
1160 up->port.type = PORT_UNKNOWN;
1161 break;
1162 case 2:
1163 up->port.type = PORT_16550;
1164 break;
1165 case 3:
1166 autoconfig_16550a(up);
1167 break;
1168 }
1169
1170#ifdef CONFIG_SERIAL_8250_RSA
1171 /*
1172 * Only probe for RSA ports if we got the region.
1173 */
1174 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1175 int i;
1176
1177 for (i = 0 ; i < probe_rsa_count; ++i) {
1178 if (probe_rsa[i] == up->port.iobase &&
1179 __enable_rsa(up)) {
1180 up->port.type = PORT_RSA;
1181 break;
1182 }
1183 }
1184 }
1185#endif
21c614a7 1186
1da177e4
LT		 1187 serial_outp(up, UART_LCR, save_lcr);
1188
1189 if (up->capabilities != uart_config[up->port.type].flags) {
1190 printk(KERN_WARNING
1191 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1192 serial_index(&up->port), up->capabilities,
1193 uart_config[up->port.type].flags);
1da177e4
LT		 1194 }
1195
1196 up->port.fifosize = uart_config[up->port.type].fifo_size;
1197 up->capabilities = uart_config[up->port.type].flags;
1198 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1199
1200 if (up->port.type == PORT_UNKNOWN)
1201 goto out;
1202
1203 /*
1204 * Reset the UART.
1205 */
1206#ifdef CONFIG_SERIAL_8250_RSA
1207 if (up->port.type == PORT_RSA)
1208 serial_outp(up, UART_RSA_FRR, 0);
1209#endif
1210 serial_outp(up, UART_MCR, save_mcr);
1211 serial8250_clear_fifos(up);
40b36daa 1212 serial_in(up, UART_RX);
5c8c755c
LB		 1213 if (up->capabilities & UART_CAP_UUE)
1214 serial_outp(up, UART_IER, UART_IER_UUE);
1215 else
1216 serial_outp(up, UART_IER, 0);
1da177e4 1217
bd71c182 1218 out:
1da177e4 1219 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1220 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1221}
1222
1223static void autoconfig_irq(struct uart_8250_port *up)
1224{
1225 unsigned char save_mcr, save_ier;
1226 unsigned char save_ICP = 0;
1227 unsigned int ICP = 0;
1228 unsigned long irqs;
1229 int irq;
1230
1231 if (up->port.flags & UPF_FOURPORT) {
1232 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1233 save_ICP = inb_p(ICP);
1234 outb_p(0x80, ICP);
1235 (void) inb_p(ICP);
1236 }
1237
1238 /* forget possible initially masked and pending IRQ */
1239 probe_irq_off(probe_irq_on());
1240 save_mcr = serial_inp(up, UART_MCR);
1241 save_ier = serial_inp(up, UART_IER);
1242 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1243
1da177e4
LT		 1244 irqs = probe_irq_on();
1245 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1246 udelay(10);
1247 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1248 serial_outp(up, UART_MCR,
1249 UART_MCR_DTR | UART_MCR_RTS);
1250 } else {
1251 serial_outp(up, UART_MCR,
1252 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1253 }
1254 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1255 (void)serial_inp(up, UART_LSR);
1256 (void)serial_inp(up, UART_RX);
1257 (void)serial_inp(up, UART_IIR);
1258 (void)serial_inp(up, UART_MSR);
1259 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1260 udelay(20);
1da177e4
LT		 1261 irq = probe_irq_off(irqs);
1262
1263 serial_outp(up, UART_MCR, save_mcr);
1264 serial_outp(up, UART_IER, save_ier);
1265
1266 if (up->port.flags & UPF_FOURPORT)
1267 outb_p(save_ICP, ICP);
1268
1269 up->port.irq = (irq > 0) ? irq : 0;
1270}
1271
e763b90c
RK		 1272static inline void __stop_tx(struct uart_8250_port *p)
1273{
1274 if (p->ier & UART_IER_THRI) {
1275 p->ier &= ~UART_IER_THRI;
1276 serial_out(p, UART_IER, p->ier);
1277 }
1278}
1279
b129a8cc 1280static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1281{
49d5741b
JI		 1282 struct uart_8250_port *up =
1283 container_of(port, struct uart_8250_port, port);
1da177e4 1284
e763b90c 1285 __stop_tx(up);
1da177e4
LT		 1286
1287 /*
e763b90c 1288 * We really want to stop the transmitter from sending.
1da177e4 1289 */
e763b90c 1290 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1291 up->acr |= UART_ACR_TXDIS;
1292 serial_icr_write(up, UART_ACR, up->acr);
1293 }
1294}
1295
b129a8cc 1296static void serial8250_start_tx(struct uart_port *port)
1da177e4 1297{
49d5741b
JI		 1298 struct uart_8250_port *up =
1299 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1300
1301 if (!(up->ier & UART_IER_THRI)) {
1302 up->ier |= UART_IER_THRI;
1303 serial_out(up, UART_IER, up->ier);
55d3b282 1304
67f7654e 1305 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1306 unsigned char lsr;
55d3b282 1307 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1308 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182 1309 if ((up->port.type == PORT_RM9000) ?
68cb4f8e
IJ		 1310 (lsr & UART_LSR_THRE) :
1311 (lsr & UART_LSR_TEMT))
3986fb2b 1312 serial8250_tx_chars(up);
55d3b282 1313 }
1da177e4 1314 }
e763b90c 1315
1da177e4 1316 /*
e763b90c 1317 * Re-enable the transmitter if we disabled it.
1da177e4 1318 */
e763b90c 1319 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1320 up->acr &= ~UART_ACR_TXDIS;
1321 serial_icr_write(up, UART_ACR, up->acr);
1322 }
1323}
1324
1325static void serial8250_stop_rx(struct uart_port *port)
1326{
49d5741b
JI		 1327 struct uart_8250_port *up =
1328 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1329
1330 up->ier &= ~UART_IER_RLSI;
1331 up->port.read_status_mask &= ~UART_LSR_DR;
1332 serial_out(up, UART_IER, up->ier);
1333}
1334
1335static void serial8250_enable_ms(struct uart_port *port)
1336{
49d5741b
JI		 1337 struct uart_8250_port *up =
1338 container_of(port, struct uart_8250_port, port);
1da177e4 1339
21c614a7
PA		 1340 /* no MSR capabilities */
1341 if (up->bugs & UART_BUG_NOMSR)
1342 return;
1343
1da177e4
LT		 1344 up->ier |= UART_IER_MSI;
1345 serial_out(up, UART_IER, up->ier);
1346}
1347
5f873bae
SW		 1348/*
1349 * Clear the Tegra rx fifo after a break
1350 *
1351 * FIXME: This needs to become a port specific callback once we have a
1352 * framework for this
1353 */
1354static void clear_rx_fifo(struct uart_8250_port *up)
1355{
1356 unsigned int status, tmout = 10000;
1357 do {
1358 status = serial_in(up, UART_LSR);
1359 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1360 status = serial_in(up, UART_RX);
1361 else
1362 break;
1363 if (--tmout == 0)
1364 break;
1365 udelay(1);
1366 } while (1);
1367}
1368
0690f41f 1369/*
3986fb2b 1370 * serial8250_rx_chars: processes according to the passed in LSR
0690f41f
PG		 1371 * value, and returns the remaining LSR bits not handled
1372 * by this Rx routine.
1373 */
3986fb2b
PG		 1374unsigned char
1375serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1da177e4 1376{
ebd2c8f6 1377 struct tty_struct *tty = up->port.state->port.tty;
0690f41f 1378 unsigned char ch;
1da177e4
LT		 1379 int max_count = 256;
1380 char flag;
1381
1382 do {
7500b1f6
AR		 1383 if (likely(lsr & UART_LSR_DR))
1384 ch = serial_inp(up, UART_RX);
1385 else
1386 /*
1387 * Intel 82571 has a Serial Over Lan device that will
1388 * set UART_LSR_BI without setting UART_LSR_DR when
1389 * it receives a break. To avoid reading from the
1390 * receive buffer without UART_LSR_DR bit set, we
1391 * just force the read character to be 0
1392 */
1393 ch = 0;
1394
1da177e4
LT		 1395 flag = TTY_NORMAL;
1396 up->port.icount.rx++;
1397
ad4c2aa6
CM		 1398 lsr |= up->lsr_saved_flags;
1399 up->lsr_saved_flags = 0;
1da177e4 1400
ad4c2aa6 1401 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1402 /*
1403 * For statistics only
1404 */
1405 if (lsr & UART_LSR_BI) {
1406 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1407 up->port.icount.brk++;
5f873bae
SW		 1408 /*
1409 * If tegra port then clear the rx fifo to
1410 * accept another break/character.
1411 */
1412 if (up->port.type == PORT_TEGRA)
1413 clear_rx_fifo(up);
1414
1da177e4
LT		 1415 /*
1416 * We do the SysRQ and SAK checking
1417 * here because otherwise the break
1418 * may get masked by ignore_status_mask
1419 * or read_status_mask.
1420 */
1421 if (uart_handle_break(&up->port))
1422 goto ignore_char;
1423 } else if (lsr & UART_LSR_PE)
1424 up->port.icount.parity++;
1425 else if (lsr & UART_LSR_FE)
1426 up->port.icount.frame++;
1427 if (lsr & UART_LSR_OE)
1428 up->port.icount.overrun++;
1429
1430 /*
23907eb8 1431 * Mask off conditions which should be ignored.
1da177e4
LT		 1432 */
1433 lsr &= up->port.read_status_mask;
1434
1435 if (lsr & UART_LSR_BI) {
1436 DEBUG_INTR("handling break....");
1437 flag = TTY_BREAK;
1438 } else if (lsr & UART_LSR_PE)
1439 flag = TTY_PARITY;
1440 else if (lsr & UART_LSR_FE)
1441 flag = TTY_FRAME;
1442 }
7d12e780 1443 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1444 goto ignore_char;
05ab3014
RK		 1445
1446 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1447
6f803cd0 1448ignore_char:
1da177e4 1449 lsr = serial_inp(up, UART_LSR);
7500b1f6 1450 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1451 spin_unlock(&up->port.lock);
1452 tty_flip_buffer_push(tty);
1453 spin_lock(&up->port.lock);
0690f41f 1454 return lsr;
1da177e4 1455}
3986fb2b 1456EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1da177e4 1457
3986fb2b 1458void serial8250_tx_chars(struct uart_8250_port *up)
1da177e4 1459{
ebd2c8f6 1460 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 1461 int count;
1462
1463 if (up->port.x_char) {
1464 serial_outp(up, UART_TX, up->port.x_char);
1465 up->port.icount.tx++;
1466 up->port.x_char = 0;
1467 return;
1468 }
b129a8cc
RK		 1469 if (uart_tx_stopped(&up->port)) {
1470 serial8250_stop_tx(&up->port);
1471 return;
1472 }
1473 if (uart_circ_empty(xmit)) {
e763b90c 1474 __stop_tx(up);
1da177e4
LT		 1475 return;
1476 }
1477
1478 count = up->tx_loadsz;
1479 do {
1480 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1481 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1482 up->port.icount.tx++;
1483 if (uart_circ_empty(xmit))
1484 break;
1485 } while (--count > 0);
1486
1487 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1488 uart_write_wakeup(&up->port);
1489
1490 DEBUG_INTR("THRE...");
1491
1492 if (uart_circ_empty(xmit))
e763b90c 1493 __stop_tx(up);
1da177e4 1494}
3986fb2b 1495EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1da177e4 1496
3986fb2b 1497unsigned int serial8250_modem_status(struct uart_8250_port *up)
1da177e4 1498{
2af7cd68
RK		 1499 unsigned int status = serial_in(up, UART_MSR);
1500
ad4c2aa6
CM		 1501 status |= up->msr_saved_flags;
1502 up->msr_saved_flags = 0;
fdc30b3d 1503 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
ebd2c8f6 1504 up->port.state != NULL) {
2af7cd68
RK		 1505 if (status & UART_MSR_TERI)
1506 up->port.icount.rng++;
1507 if (status & UART_MSR_DDSR)
1508 up->port.icount.dsr++;
1509 if (status & UART_MSR_DDCD)
1510 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1511 if (status & UART_MSR_DCTS)
1512 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1513
bdc04e31 1514 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
2af7cd68 1515 }
1da177e4 1516
2af7cd68 1517 return status;
1da177e4 1518}
3986fb2b 1519EXPORT_SYMBOL_GPL(serial8250_modem_status);
1da177e4
LT		 1520
1521/*
1522 * This handles the interrupt from one port.
1523 */
86b21199 1524int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1da177e4 1525{
0690f41f 1526 unsigned char status;
4bf3631c 1527 unsigned long flags;
86b21199
PG		 1528 struct uart_8250_port *up =
1529 container_of(port, struct uart_8250_port, port);
1530
1531 if (iir & UART_IIR_NO_INT)
1532 return 0;
45e24601 1533
4bf3631c 1534 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1535
1536 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1537
1538 DEBUG_INTR("status = %x...", status);
1539
7500b1f6 1540 if (status & (UART_LSR_DR | UART_LSR_BI))
3986fb2b
PG		 1541 status = serial8250_rx_chars(up, status);
1542 serial8250_modem_status(up);
1da177e4 1543 if (status & UART_LSR_THRE)
3986fb2b 1544 serial8250_tx_chars(up);
45e24601 1545
4bf3631c 1546 spin_unlock_irqrestore(&up->port.lock, flags);
86b21199 1547 return 1;
583d28e9 1548}
c7a1bdc5 1549EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1550
1551static int serial8250_default_handle_irq(struct uart_port *port)
1552{
1553 struct uart_8250_port *up =
1554 container_of(port, struct uart_8250_port, port);
1555 unsigned int iir = serial_in(up, UART_IIR);
1556
1557 return serial8250_handle_irq(port, iir);
1558}
1559
1da177e4
LT		 1560/*
1561 * This is the serial driver's interrupt routine.
1562 *
1563 * Arjan thinks the old way was overly complex, so it got simplified.
1564 * Alan disagrees, saying that need the complexity to handle the weird
1565 * nature of ISA shared interrupts. (This is a special exception.)
1566 *
1567 * In order to handle ISA shared interrupts properly, we need to check
1568 * that all ports have been serviced, and therefore the ISA interrupt
1569 * line has been de-asserted.
1570 *
1571 * This means we need to loop through all ports. checking that they
1572 * don't have an interrupt pending.
1573 */
7d12e780 1574static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1575{
1576 struct irq_info *i = dev_id;
1577 struct list_head *l, *end = NULL;
1578 int pass_counter = 0, handled = 0;
1579
1580 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1581
1582 spin_lock(&i->lock);
1583
1584 l = i->head;
1585 do {
1586 struct uart_8250_port *up;
583d28e9 1587 struct uart_port *port;
448ac154 1588 bool skip;
1da177e4
LT		 1589
1590 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1591 port = &up->port;
448ac154 1592 skip = pass_counter && up->port.flags & UPF_IIR_ONCE;
1da177e4 1593
448ac154 1594 if (!skip && port->handle_irq(port)) {
1da177e4 1595 handled = 1;
1da177e4
LT		 1596 end = NULL;
1597 } else if (end == NULL)
1598 end = l;
1599
1600 l = l->next;
1601
1602 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1603 /* If we hit this, we're dead. */
cd3ecad1
DD		 1604 printk_ratelimited(KERN_ERR
1605 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1606 break;
1607 }
1608 } while (l != end);
1609
1610 spin_unlock(&i->lock);
1611
1612 DEBUG_INTR("end.\n");
1613
1614 return IRQ_RETVAL(handled);
1615}
1616
1617/*
1618 * To support ISA shared interrupts, we need to have one interrupt
1619 * handler that ensures that the IRQ line has been deasserted
1620 * before returning. Failing to do this will result in the IRQ
1621 * line being stuck active, and, since ISA irqs are edge triggered,
1622 * no more IRQs will be seen.
1623 */
1624static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1625{
1626 spin_lock_irq(&i->lock);
1627
1628 if (!list_empty(i->head)) {
1629 if (i->head == &up->list)
1630 i->head = i->head->next;
1631 list_del(&up->list);
1632 } else {
1633 BUG_ON(i->head != &up->list);
1634 i->head = NULL;
1635 }
1da177e4 1636 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1637 /* List empty so throw away the hash node */
1638 if (i->head == NULL) {
1639 hlist_del(&i->node);
1640 kfree(i);
1641 }
1da177e4
LT		 1642}
1643
1644static int serial_link_irq_chain(struct uart_8250_port *up)
1645{
25db8ad5
AC		 1646 struct hlist_head *h;
1647 struct hlist_node *n;
1648 struct irq_info *i;
40663cc7 1649 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1650
25db8ad5
AC		 1651 mutex_lock(&hash_mutex);
1652
1653 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1654
1655 hlist_for_each(n, h) {
1656 i = hlist_entry(n, struct irq_info, node);
1657 if (i->irq == up->port.irq)
1658 break;
1659 }
1660
1661 if (n == NULL) {
1662 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1663 if (i == NULL) {
1664 mutex_unlock(&hash_mutex);
1665 return -ENOMEM;
1666 }
1667 spin_lock_init(&i->lock);
1668 i->irq = up->port.irq;
1669 hlist_add_head(&i->node, h);
1670 }
1671 mutex_unlock(&hash_mutex);
1672
1da177e4
LT		 1673 spin_lock_irq(&i->lock);
1674
1675 if (i->head) {
1676 list_add(&up->list, i->head);
1677 spin_unlock_irq(&i->lock);
1678
1679 ret = 0;
1680 } else {
1681 INIT_LIST_HEAD(&up->list);
1682 i->head = &up->list;
1683 spin_unlock_irq(&i->lock);
1c2f0493 1684 irq_flags |= up->port.irqflags;
1da177e4
LT		 1685 ret = request_irq(up->port.irq, serial8250_interrupt,
1686 irq_flags, "serial", i);
1687 if (ret < 0)
1688 serial_do_unlink(i, up);
1689 }
1690
1691 return ret;
1692}
1693
1694static void serial_unlink_irq_chain(struct uart_8250_port *up)
1695{
25db8ad5
AC		 1696 struct irq_info *i;
1697 struct hlist_node *n;
1698 struct hlist_head *h;
1da177e4 1699
25db8ad5
AC		 1700 mutex_lock(&hash_mutex);
1701
1702 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1703
1704 hlist_for_each(n, h) {
1705 i = hlist_entry(n, struct irq_info, node);
1706 if (i->irq == up->port.irq)
1707 break;
1708 }
1709
1710 BUG_ON(n == NULL);
1da177e4
LT		 1711 BUG_ON(i->head == NULL);
1712
1713 if (list_empty(i->head))
1714 free_irq(up->port.irq, i);
1715
1716 serial_do_unlink(i, up);
25db8ad5 1717 mutex_unlock(&hash_mutex);
1da177e4
LT		 1718}
1719
1720/*
1721 * This function is used to handle ports that do not have an
1722 * interrupt. This doesn't work very well for 16450's, but gives
1723 * barely passable results for a 16550A. (Although at the expense
1724 * of much CPU overhead).
1725 */
1726static void serial8250_timeout(unsigned long data)
1727{
1728 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4 1729
a0431476 1730 up->port.handle_irq(&up->port);
54381067 1731 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1732}
1733
1734static void serial8250_backup_timeout(unsigned long data)
1735{
1736 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1737 unsigned int iir, ier = 0, lsr;
1738 unsigned long flags;
40b36daa 1739
dbb3b1ca
AC		 1740 spin_lock_irqsave(&up->port.lock, flags);
1741
40b36daa
AW		 1742 /*
1743 * Must disable interrupts or else we risk racing with the interrupt
1744 * based handler.
1745 */
d4e33fac 1746 if (up->port.irq) {
40b36daa
AW		 1747 ier = serial_in(up, UART_IER);
1748 serial_out(up, UART_IER, 0);
1749 }
1da177e4 1750
40b36daa
AW		 1751 iir = serial_in(up, UART_IIR);
1752
1753 /*
1754 * This should be a safe test for anyone who doesn't trust the
1755 * IIR bits on their UART, but it's specifically designed for
1756 * the "Diva" UART used on the management processor on many HP
1757 * ia64 and parisc boxes.
1758 */
ad4c2aa6
CM		 1759 lsr = serial_in(up, UART_LSR);
1760 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1761 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1762 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1763 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1764 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1765 iir |= UART_IIR_THRI;
1766 }
1767
1768 if (!(iir & UART_IIR_NO_INT))
3986fb2b 1769 serial8250_tx_chars(up);
40b36daa 1770
d4e33fac 1771 if (up->port.irq)
40b36daa
AW		 1772 serial_out(up, UART_IER, ier);
1773
dbb3b1ca
AC		 1774 spin_unlock_irqrestore(&up->port.lock, flags);
1775
40b36daa 1776 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1777 mod_timer(&up->timer,
54381067 1778 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1779}
1780
1781static unsigned int serial8250_tx_empty(struct uart_port *port)
1782{
49d5741b
JI		 1783 struct uart_8250_port *up =
1784 container_of(port, struct uart_8250_port, port);
1da177e4 1785 unsigned long flags;
ad4c2aa6 1786 unsigned int lsr;
1da177e4
LT		 1787
1788 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1789 lsr = serial_in(up, UART_LSR);
1790 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1791 spin_unlock_irqrestore(&up->port.lock, flags);
1792
bca47613 1793 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1794}
1795
1796static unsigned int serial8250_get_mctrl(struct uart_port *port)
1797{
49d5741b
JI		 1798 struct uart_8250_port *up =
1799 container_of(port, struct uart_8250_port, port);
2af7cd68 1800 unsigned int status;
1da177e4
LT		 1801 unsigned int ret;
1802
3986fb2b 1803 status = serial8250_modem_status(up);
1da177e4
LT		 1804
1805 ret = 0;
1806 if (status & UART_MSR_DCD)
1807 ret |= TIOCM_CAR;
1808 if (status & UART_MSR_RI)
1809 ret |= TIOCM_RNG;
1810 if (status & UART_MSR_DSR)
1811 ret |= TIOCM_DSR;
1812 if (status & UART_MSR_CTS)
1813 ret |= TIOCM_CTS;
1814 return ret;
1815}
1816
1817static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1818{
49d5741b
JI		 1819 struct uart_8250_port *up =
1820 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1821 unsigned char mcr = 0;
1822
1823 if (mctrl & TIOCM_RTS)
1824 mcr |= UART_MCR_RTS;
1825 if (mctrl & TIOCM_DTR)
1826 mcr |= UART_MCR_DTR;
1827 if (mctrl & TIOCM_OUT1)
1828 mcr |= UART_MCR_OUT1;
1829 if (mctrl & TIOCM_OUT2)
1830 mcr |= UART_MCR_OUT2;
1831 if (mctrl & TIOCM_LOOP)
1832 mcr |= UART_MCR_LOOP;
1833
1834 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1835
1836 serial_out(up, UART_MCR, mcr);
1837}
1838
1839static void serial8250_break_ctl(struct uart_port *port, int break_state)
1840{
49d5741b
JI		 1841 struct uart_8250_port *up =
1842 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1843 unsigned long flags;
1844
1845 spin_lock_irqsave(&up->port.lock, flags);
1846 if (break_state == -1)
1847 up->lcr |= UART_LCR_SBC;
1848 else
1849 up->lcr &= ~UART_LCR_SBC;
1850 serial_out(up, UART_LCR, up->lcr);
1851 spin_unlock_irqrestore(&up->port.lock, flags);
1852}
1853
40b36daa
AW		 1854/*
1855 * Wait for transmitter & holding register to empty
1856 */
b5d674ab 1857static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1858{
1859 unsigned int status, tmout = 10000;
1860
1861 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1862 for (;;) {
40b36daa
AW		 1863 status = serial_in(up, UART_LSR);
1864
ad4c2aa6 1865 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1866
97d303b7
DD		 1867 if ((status & bits) == bits)
1868 break;
40b36daa
AW		 1869 if (--tmout == 0)
1870 break;
1871 udelay(1);
97d303b7 1872 }
40b36daa
AW		 1873
1874 /* Wait up to 1s for flow control if necessary */
1875 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1876 unsigned int tmout;
1877 for (tmout = 1000000; tmout; tmout--) {
1878 unsigned int msr = serial_in(up, UART_MSR);
1879 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1880 if (msr & UART_MSR_CTS)
1881 break;
40b36daa
AW		 1882 udelay(1);
1883 touch_nmi_watchdog();
1884 }
1885 }
1886}
1887
f2d937f3
JW		 1888#ifdef CONFIG_CONSOLE_POLL
1889/*
1890 * Console polling routines for writing and reading from the uart while
1891 * in an interrupt or debug context.
1892 */
1893
1894static int serial8250_get_poll_char(struct uart_port *port)
1895{
49d5741b
JI		 1896 struct uart_8250_port *up =
1897 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1898 unsigned char lsr = serial_inp(up, UART_LSR);
1899
f5316b4a
JW		 1900 if (!(lsr & UART_LSR_DR))
1901 return NO_POLL_CHAR;
f2d937f3
JW		 1902
1903 return serial_inp(up, UART_RX);
1904}
1905
1906
1907static void serial8250_put_poll_char(struct uart_port *port,
1908 unsigned char c)
1909{
1910 unsigned int ier;
49d5741b
JI		 1911 struct uart_8250_port *up =
1912 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1913
1914 /*
1915 * First save the IER then disable the interrupts
1916 */
1917 ier = serial_in(up, UART_IER);
1918 if (up->capabilities & UART_CAP_UUE)
1919 serial_out(up, UART_IER, UART_IER_UUE);
1920 else
1921 serial_out(up, UART_IER, 0);
1922
1923 wait_for_xmitr(up, BOTH_EMPTY);
1924 /*
1925 * Send the character out.
1926 * If a LF, also do CR...
1927 */
1928 serial_out(up, UART_TX, c);
1929 if (c == 10) {
1930 wait_for_xmitr(up, BOTH_EMPTY);
1931 serial_out(up, UART_TX, 13);
1932 }
1933
1934 /*
1935 * Finally, wait for transmitter to become empty
1936 * and restore the IER
1937 */
1938 wait_for_xmitr(up, BOTH_EMPTY);
1939 serial_out(up, UART_IER, ier);
1940}
1941
1942#endif /* CONFIG_CONSOLE_POLL */
1943
1da177e4
LT		 1944static int serial8250_startup(struct uart_port *port)
1945{
49d5741b
JI		 1946 struct uart_8250_port *up =
1947 container_of(port, struct uart_8250_port, port);
1da177e4 1948 unsigned long flags;
55d3b282 1949 unsigned char lsr, iir;
1da177e4
LT		 1950 int retval;
1951
e4f05af1
OP		 1952 up->port.fifosize = uart_config[up->port.type].fifo_size;
1953 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 1954 up->capabilities = uart_config[up->port.type].flags;
1955 up->mcr = 0;
1956
b8e7e40a
AC		 1957 if (up->port.iotype != up->cur_iotype)
1958 set_io_from_upio(port);
1959
1da177e4
LT		 1960 if (up->port.type == PORT_16C950) {
1961 /* Wake up and initialize UART */
1962 up->acr = 0;
662b083a 1963 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1964 serial_outp(up, UART_EFR, UART_EFR_ECB);
1965 serial_outp(up, UART_IER, 0);
1966 serial_outp(up, UART_LCR, 0);
1967 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
7d73aaf1 1968 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1969 serial_outp(up, UART_EFR, UART_EFR_ECB);
1970 serial_outp(up, UART_LCR, 0);
1971 }
1972
1973#ifdef CONFIG_SERIAL_8250_RSA
1974 /*
1975 * If this is an RSA port, see if we can kick it up to the
1976 * higher speed clock.
1977 */
1978 enable_rsa(up);
1979#endif
1980
1981 /*
1982 * Clear the FIFO buffers and disable them.
7f927fcc 1983 * (they will be reenabled in set_termios())
1da177e4
LT		 1984 */
1985 serial8250_clear_fifos(up);
1986
1987 /*
1988 * Clear the interrupt registers.
1989 */
1990 (void) serial_inp(up, UART_LSR);
1991 (void) serial_inp(up, UART_RX);
1992 (void) serial_inp(up, UART_IIR);
1993 (void) serial_inp(up, UART_MSR);
1994
1995 /*
1996 * At this point, there's no way the LSR could still be 0xff;
1997 * if it is, then bail out, because there's likely no UART
1998 * here.
1999 */
2000 if (!(up->port.flags & UPF_BUGGY_UART) &&
2001 (serial_inp(up, UART_LSR) == 0xff)) {
7808a4c4
KRW		 2002 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2003 serial_index(&up->port));
1da177e4
LT		 2004 return -ENODEV;
2005 }
2006
2007 /*
2008 * For a XR16C850, we need to set the trigger levels
2009 */
2010 if (up->port.type == PORT_16850) {
2011 unsigned char fctr;
2012
662b083a 2013 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 2014
2015 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2016 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2017 serial_outp(up, UART_TRG, UART_TRG_96);
2018 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2019 serial_outp(up, UART_TRG, UART_TRG_96);
2020
2021 serial_outp(up, UART_LCR, 0);
2022 }
2023
d4e33fac 2024 if (up->port.irq) {
01c194d9 2025 unsigned char iir1;
40b36daa
AW		 2026 /*
2027 * Test for UARTs that do not reassert THRE when the
2028 * transmitter is idle and the interrupt has already
2029 * been cleared. Real 16550s should always reassert
2030 * this interrupt whenever the transmitter is idle and
2031 * the interrupt is enabled. Delays are necessary to
2032 * allow register changes to become visible.
2033 */
c389d27b 2034 spin_lock_irqsave(&up->port.lock, flags);
1c2f0493 2035 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2036 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2037
2038 wait_for_xmitr(up, UART_LSR_THRE);
2039 serial_out_sync(up, UART_IER, UART_IER_THRI);
2040 udelay(1); /* allow THRE to set */
01c194d9 2041 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2042 serial_out(up, UART_IER, 0);
2043 serial_out_sync(up, UART_IER, UART_IER_THRI);
2044 udelay(1); /* allow a working UART time to re-assert THRE */
2045 iir = serial_in(up, UART_IIR);
2046 serial_out(up, UART_IER, 0);
2047
1c2f0493 2048 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2049 enable_irq(up->port.irq);
c389d27b 2050 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2051
2052 /*
2053 * If the interrupt is not reasserted, setup a timer to
2054 * kick the UART on a regular basis.
2055 */
01c194d9 2056 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2057 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2058 pr_debug("ttyS%d - using backup timer\n",
2059 serial_index(port));
40b36daa
AW		 2060 }
2061 }
2062
363f66fe
WN		 2063 /*
2064 * The above check will only give an accurate result the first time
2065 * the port is opened so this value needs to be preserved.
2066 */
2067 if (up->bugs & UART_BUG_THRE) {
2068 up->timer.function = serial8250_backup_timeout;
2069 up->timer.data = (unsigned long)up;
2070 mod_timer(&up->timer, jiffies +
54381067 2071 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2072 }
2073
1da177e4
LT		 2074 /*
2075 * If the "interrupt" for this port doesn't correspond with any
2076 * hardware interrupt, we use a timer-based system. The original
2077 * driver used to do this with IRQ0.
2078 */
d4e33fac 2079 if (!up->port.irq) {
1da177e4 2080 up->timer.data = (unsigned long)up;
54381067 2081 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2082 } else {
2083 retval = serial_link_irq_chain(up);
2084 if (retval)
2085 return retval;
2086 }
2087
2088 /*
2089 * Now, initialize the UART
2090 */
2091 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2092
2093 spin_lock_irqsave(&up->port.lock, flags);
2094 if (up->port.flags & UPF_FOURPORT) {
d4e33fac 2095 if (!up->port.irq)
1da177e4
LT		 2096 up->port.mctrl |= TIOCM_OUT1;
2097 } else
2098 /*
2099 * Most PC uarts need OUT2 raised to enable interrupts.
2100 */
d4e33fac 2101 if (up->port.irq)
1da177e4
LT		 2102 up->port.mctrl |= TIOCM_OUT2;
2103
2104 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2105
b6adea33
MCC		 2106 /* Serial over Lan (SoL) hack:
2107 Intel 8257x Gigabit ethernet chips have a
2108 16550 emulation, to be used for Serial Over Lan.
2109 Those chips take a longer time than a normal
2110 serial device to signalize that a transmission
2111 data was queued. Due to that, the above test generally
2112 fails. One solution would be to delay the reading of
2113 iir. However, this is not reliable, since the timeout
2114 is variable. So, let's just don't test if we receive
2115 TX irq. This way, we'll never enable UART_BUG_TXEN.
2116 */
d41a4b51 2117 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2118 goto dont_test_tx_en;
2119
55d3b282
RK		 2120 /*
2121 * Do a quick test to see if we receive an
2122 * interrupt when we enable the TX irq.
2123 */
2124 serial_outp(up, UART_IER, UART_IER_THRI);
2125 lsr = serial_in(up, UART_LSR);
2126 iir = serial_in(up, UART_IIR);
2127 serial_outp(up, UART_IER, 0);
2128
2129 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2130 if (!(up->bugs & UART_BUG_TXEN)) {
2131 up->bugs |= UART_BUG_TXEN;
55d3b282 2132 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2133 serial_index(port));
55d3b282
RK		 2134 }
2135 } else {
67f7654e 2136 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2137 }
2138
b6adea33 2139dont_test_tx_en:
1da177e4
LT		 2140 spin_unlock_irqrestore(&up->port.lock, flags);
2141
ad4c2aa6
CM		 2142 /*
2143 * Clear the interrupt registers again for luck, and clear the
2144 * saved flags to avoid getting false values from polling
2145 * routines or the previous session.
2146 */
2147 serial_inp(up, UART_LSR);
2148 serial_inp(up, UART_RX);
2149 serial_inp(up, UART_IIR);
2150 serial_inp(up, UART_MSR);
2151 up->lsr_saved_flags = 0;
2152 up->msr_saved_flags = 0;
2153
1da177e4
LT		 2154 /*
2155 * Finally, enable interrupts. Note: Modem status interrupts
2156 * are set via set_termios(), which will be occurring imminently
2157 * anyway, so we don't enable them here.
2158 */
2159 up->ier = UART_IER_RLSI | UART_IER_RDI;
2160 serial_outp(up, UART_IER, up->ier);
2161
2162 if (up->port.flags & UPF_FOURPORT) {
2163 unsigned int icp;
2164 /*
2165 * Enable interrupts on the AST Fourport board
2166 */
2167 icp = (up->port.iobase & 0xfe0) | 0x01f;
2168 outb_p(0x80, icp);
2169 (void) inb_p(icp);
2170 }
2171
1da177e4
LT		 2172 return 0;
2173}
2174
2175static void serial8250_shutdown(struct uart_port *port)
2176{
49d5741b
JI		 2177 struct uart_8250_port *up =
2178 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2179 unsigned long flags;
2180
2181 /*
2182 * Disable interrupts from this port
2183 */
2184 up->ier = 0;
2185 serial_outp(up, UART_IER, 0);
2186
2187 spin_lock_irqsave(&up->port.lock, flags);
2188 if (up->port.flags & UPF_FOURPORT) {
2189 /* reset interrupts on the AST Fourport board */
2190 inb((up->port.iobase & 0xfe0) | 0x1f);
2191 up->port.mctrl |= TIOCM_OUT1;
2192 } else
2193 up->port.mctrl &= ~TIOCM_OUT2;
2194
2195 serial8250_set_mctrl(&up->port, up->port.mctrl);
2196 spin_unlock_irqrestore(&up->port.lock, flags);
2197
2198 /*
2199 * Disable break condition and FIFOs
2200 */
2201 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2202 serial8250_clear_fifos(up);
2203
2204#ifdef CONFIG_SERIAL_8250_RSA
2205 /*
2206 * Reset the RSA board back to 115kbps compat mode.
2207 */
2208 disable_rsa(up);
2209#endif
2210
2211 /*
2212 * Read data port to reset things, and then unlink from
2213 * the IRQ chain.
2214 */
2215 (void) serial_in(up, UART_RX);
2216
40b36daa
AW		 2217 del_timer_sync(&up->timer);
2218 up->timer.function = serial8250_timeout;
d4e33fac 2219 if (up->port.irq)
1da177e4
LT		 2220 serial_unlink_irq_chain(up);
2221}
2222
2223static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2224{
2225 unsigned int quot;
2226
2227 /*
2228 * Handle magic divisors for baud rates above baud_base on
2229 * SMSC SuperIO chips.
2230 */
2231 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2232 baud == (port->uartclk/4))
2233 quot = 0x8001;
2234 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2235 baud == (port->uartclk/8))
2236 quot = 0x8002;
2237 else
2238 quot = uart_get_divisor(port, baud);
2239
2240 return quot;
2241}
2242
235dae5d
PL		 2243void
2244serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2245 struct ktermios *old)
1da177e4 2246{
49d5741b
JI		 2247 struct uart_8250_port *up =
2248 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2249 unsigned char cval, fcr = 0;
2250 unsigned long flags;
2251 unsigned int baud, quot;
2252
2253 switch (termios->c_cflag & CSIZE) {
2254 case CS5:
0a8b80c5 2255 cval = UART_LCR_WLEN5;
1da177e4
LT		 2256 break;
2257 case CS6:
0a8b80c5 2258 cval = UART_LCR_WLEN6;
1da177e4
LT		 2259 break;
2260 case CS7:
0a8b80c5 2261 cval = UART_LCR_WLEN7;
1da177e4
LT		 2262 break;
2263 default:
2264 case CS8:
0a8b80c5 2265 cval = UART_LCR_WLEN8;
1da177e4
LT		 2266 break;
2267 }
2268
2269 if (termios->c_cflag & CSTOPB)
0a8b80c5 2270 cval |= UART_LCR_STOP;
1da177e4
LT		 2271 if (termios->c_cflag & PARENB)
2272 cval |= UART_LCR_PARITY;
2273 if (!(termios->c_cflag & PARODD))
2274 cval |= UART_LCR_EPAR;
2275#ifdef CMSPAR
2276 if (termios->c_cflag & CMSPAR)
2277 cval |= UART_LCR_SPAR;
2278#endif
2279
2280 /*
2281 * Ask the core to calculate the divisor for us.
2282 */
24d481ec
AV		 2283 baud = uart_get_baud_rate(port, termios, old,
2284 port->uartclk / 16 / 0xffff,
2285 port->uartclk / 16);
1da177e4
LT		 2286 quot = serial8250_get_divisor(port, baud);
2287
2288 /*
4ba5e35d 2289 * Oxford Semi 952 rev B workaround
1da177e4 2290 */
4ba5e35d 2291 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2292 quot++;
1da177e4
LT		 2293
2294 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2295 if (baud < 2400)
2296 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2297 else
2298 fcr = uart_config[up->port.type].fcr;
2299 }
2300
2301 /*
2302 * MCR-based auto flow control. When AFE is enabled, RTS will be
2303 * deasserted when the receive FIFO contains more characters than
2304 * the trigger, or the MCR RTS bit is cleared. In the case where
2305 * the remote UART is not using CTS auto flow control, we must
2306 * have sufficient FIFO entries for the latency of the remote
2307 * UART to respond. IOW, at least 32 bytes of FIFO.
2308 */
2309 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2310 up->mcr &= ~UART_MCR_AFE;
2311 if (termios->c_cflag & CRTSCTS)
2312 up->mcr |= UART_MCR_AFE;
2313 }
2314
2315 /*
2316 * Ok, we're now changing the port state. Do it with
2317 * interrupts disabled.
2318 */
2319 spin_lock_irqsave(&up->port.lock, flags);
2320
2321 /*
2322 * Update the per-port timeout.
2323 */
2324 uart_update_timeout(port, termios->c_cflag, baud);
2325
2326 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2327 if (termios->c_iflag & INPCK)
2328 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2329 if (termios->c_iflag & (BRKINT | PARMRK))
2330 up->port.read_status_mask |= UART_LSR_BI;
2331
2332 /*
2333 * Characteres to ignore
2334 */
2335 up->port.ignore_status_mask = 0;
2336 if (termios->c_iflag & IGNPAR)
2337 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2338 if (termios->c_iflag & IGNBRK) {
2339 up->port.ignore_status_mask |= UART_LSR_BI;
2340 /*
2341 * If we're ignoring parity and break indicators,
2342 * ignore overruns too (for real raw support).
2343 */
2344 if (termios->c_iflag & IGNPAR)
2345 up->port.ignore_status_mask |= UART_LSR_OE;
2346 }
2347
2348 /*
2349 * ignore all characters if CREAD is not set
2350 */
2351 if ((termios->c_cflag & CREAD) == 0)
2352 up->port.ignore_status_mask |= UART_LSR_DR;
2353
2354 /*
2355 * CTS flow control flag and modem status interrupts
2356 */
f8b372a1 2357 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2358 if (!(up->bugs & UART_BUG_NOMSR) &&
2359 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2360 up->ier |= UART_IER_MSI;
2361 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2362 up->ier |= UART_IER_UUE;
2363 if (up->capabilities & UART_CAP_RTOIE)
2364 up->ier |= UART_IER_RTOIE;
1da177e4
LT		 2365
2366 serial_out(up, UART_IER, up->ier);
2367
2368 if (up->capabilities & UART_CAP_EFR) {
2369 unsigned char efr = 0;
2370 /*
2371 * TI16C752/Startech hardware flow control. FIXME:
2372 * - TI16C752 requires control thresholds to be set.
2373 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2374 */
2375 if (termios->c_cflag & CRTSCTS)
2376 efr |= UART_EFR_CTS;
2377
662b083a 2378 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
06315348
SH		 2379 if (up->port.flags & UPF_EXAR_EFR)
2380 serial_outp(up, UART_XR_EFR, efr);
2381 else
2382 serial_outp(up, UART_EFR, efr);
1da177e4
LT		 2383 }
2384
f2eda27d 2385#ifdef CONFIG_ARCH_OMAP
255341c6 2386 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2387 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2388 if (baud == 115200) {
2389 quot = 1;
2390 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2391 } else
2392 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2393 }
2394#endif
2395
1da177e4
LT		 2396 if (up->capabilities & UART_NATSEMI) {
2397 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2398 serial_outp(up, UART_LCR, 0xe0);
2399 } else {
2400 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2401 }
2402
b32b19b8 2403 serial_dl_write(up, quot);
1da177e4
LT		 2404
2405 /*
2406 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2407 * is written without DLAB set, this mode will be disabled.
2408 */
2409 if (up->port.type == PORT_16750)
2410 serial_outp(up, UART_FCR, fcr);
2411
2412 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2413 up->lcr = cval; /* Save LCR */
2414 if (up->port.type != PORT_16750) {
2415 if (fcr & UART_FCR_ENABLE_FIFO) {
2416 /* emulated UARTs (Lucent Venus 167x) need two steps */
2417 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2418 }
2419 serial_outp(up, UART_FCR, fcr); /* set fcr */
2420 }
2421 serial8250_set_mctrl(&up->port, up->port.mctrl);
2422 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2423 /* Don't rewrite B0 */
2424 if (tty_termios_baud_rate(termios))
2425 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2426}
235dae5d
PL		 2427EXPORT_SYMBOL(serial8250_do_set_termios);
2428
2429static void
2430serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2431 struct ktermios *old)
2432{
2433 if (port->set_termios)
2434 port->set_termios(port, termios, old);
2435 else
2436 serial8250_do_set_termios(port, termios, old);
2437}
1da177e4 2438
dc77f161 2439static void
a0821df6 2440serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2441{
a0821df6 2442 if (new == N_PPS) {
dc77f161
RG		 2443 port->flags |= UPF_HARDPPS_CD;
2444 serial8250_enable_ms(port);
2445 } else
2446 port->flags &= ~UPF_HARDPPS_CD;
2447}
2448
c161afe9
ML		 2449
2450void serial8250_do_pm(struct uart_port *port, unsigned int state,
2451 unsigned int oldstate)
1da177e4 2452{
49d5741b
JI		 2453 struct uart_8250_port *p =
2454 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2455
2456 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2457}
2458EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2459
c161afe9
ML		 2460static void
2461serial8250_pm(struct uart_port *port, unsigned int state,
2462 unsigned int oldstate)
2463{
2464 if (port->pm)
2465 port->pm(port, state, oldstate);
2466 else
2467 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2468}
2469
f2eda27d
RK		 2470static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2471{
2472 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2473 return 0x1000;
f2eda27d
RK		 2474#ifdef CONFIG_ARCH_OMAP
2475 if (is_omap_port(pt))
2476 return 0x16 << pt->port.regshift;
2477#endif
2478 return 8 << pt->port.regshift;
2479}
2480
1da177e4
LT		 2481/*
2482 * Resource handling.
2483 */
2484static int serial8250_request_std_resource(struct uart_8250_port *up)
2485{
f2eda27d 2486 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2487 int ret = 0;
2488
2489 switch (up->port.iotype) {
85835f44 2490 case UPIO_AU:
0b30d668
SS		 2491 case UPIO_TSI:
2492 case UPIO_MEM32:
1da177e4
LT		 2493 case UPIO_MEM:
2494 if (!up->port.mapbase)
2495 break;
2496
2497 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2498 ret = -EBUSY;
2499 break;
2500 }
2501
2502 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2503 up->port.membase = ioremap_nocache(up->port.mapbase,
2504 size);
1da177e4
LT		 2505 if (!up->port.membase) {
2506 release_mem_region(up->port.mapbase, size);
2507 ret = -ENOMEM;
2508 }
2509 }
2510 break;
2511
2512 case UPIO_HUB6:
2513 case UPIO_PORT:
2514 if (!request_region(up->port.iobase, size, "serial"))
2515 ret = -EBUSY;
2516 break;
2517 }
2518 return ret;
2519}
2520
2521static void serial8250_release_std_resource(struct uart_8250_port *up)
2522{
f2eda27d 2523 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2524
2525 switch (up->port.iotype) {
85835f44 2526 case UPIO_AU:
0b30d668
SS		 2527 case UPIO_TSI:
2528 case UPIO_MEM32:
1da177e4
LT		 2529 case UPIO_MEM:
2530 if (!up->port.mapbase)
2531 break;
2532
2533 if (up->port.flags & UPF_IOREMAP) {
2534 iounmap(up->port.membase);
2535 up->port.membase = NULL;
2536 }
2537
2538 release_mem_region(up->port.mapbase, size);
2539 break;
2540
2541 case UPIO_HUB6:
2542 case UPIO_PORT:
2543 release_region(up->port.iobase, size);
2544 break;
2545 }
2546}
2547
2548static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2549{
2550 unsigned long start = UART_RSA_BASE << up->port.regshift;
2551 unsigned int size = 8 << up->port.regshift;
0b30d668 2552 int ret = -EINVAL;
1da177e4
LT		 2553
2554 switch (up->port.iotype) {
1da177e4
LT		 2555 case UPIO_HUB6:
2556 case UPIO_PORT:
2557 start += up->port.iobase;
0b30d668
SS		 2558 if (request_region(start, size, "serial-rsa"))
2559 ret = 0;
2560 else
1da177e4
LT		 2561 ret = -EBUSY;
2562 break;
2563 }
2564
2565 return ret;
2566}
2567
2568static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2569{
2570 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2571 unsigned int size = 8 << up->port.regshift;
2572
2573 switch (up->port.iotype) {
1da177e4
LT		 2574 case UPIO_HUB6:
2575 case UPIO_PORT:
2576 release_region(up->port.iobase + offset, size);
2577 break;
2578 }
2579}
2580
2581static void serial8250_release_port(struct uart_port *port)
2582{
49d5741b
JI		 2583 struct uart_8250_port *up =
2584 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2585
2586 serial8250_release_std_resource(up);
2587 if (up->port.type == PORT_RSA)
2588 serial8250_release_rsa_resource(up);
2589}
2590
2591static int serial8250_request_port(struct uart_port *port)
2592{
49d5741b
JI		 2593 struct uart_8250_port *up =
2594 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2595 int ret = 0;
2596
2597 ret = serial8250_request_std_resource(up);
2598 if (ret == 0 && up->port.type == PORT_RSA) {
2599 ret = serial8250_request_rsa_resource(up);
2600 if (ret < 0)
2601 serial8250_release_std_resource(up);
2602 }
2603
2604 return ret;
2605}
2606
2607static void serial8250_config_port(struct uart_port *port, int flags)
2608{
49d5741b
JI		 2609 struct uart_8250_port *up =
2610 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2611 int probeflags = PROBE_ANY;
2612 int ret;
2613
1da177e4
LT		 2614 /*
2615 * Find the region that we can probe for. This in turn
2616 * tells us whether we can probe for the type of port.
2617 */
2618 ret = serial8250_request_std_resource(up);
2619 if (ret < 0)
2620 return;
2621
2622 ret = serial8250_request_rsa_resource(up);
2623 if (ret < 0)
2624 probeflags &= ~PROBE_RSA;
2625
b8e7e40a
AC		 2626 if (up->port.iotype != up->cur_iotype)
2627 set_io_from_upio(port);
2628
1da177e4
LT		 2629 if (flags & UART_CONFIG_TYPE)
2630 autoconfig(up, probeflags);
b2b13cdf 2631
b2b13cdf
ML		 2632 /* if access method is AU, it is a 16550 with a quirk */
2633 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2634 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2635
1da177e4
LT		 2636 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2637 autoconfig_irq(up);
2638
2639 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2640 serial8250_release_rsa_resource(up);
2641 if (up->port.type == PORT_UNKNOWN)
2642 serial8250_release_std_resource(up);
2643}
2644
2645static int
2646serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2647{
a62c4133 2648 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2649 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2650 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2651 ser->type == PORT_STARTECH)
2652 return -EINVAL;
2653 return 0;
2654}
2655
2656static const char *
2657serial8250_type(struct uart_port *port)
2658{
2659 int type = port->type;
2660
2661 if (type >= ARRAY_SIZE(uart_config))
2662 type = 0;
2663 return uart_config[type].name;
2664}
2665
2666static struct uart_ops serial8250_pops = {
2667 .tx_empty = serial8250_tx_empty,
2668 .set_mctrl = serial8250_set_mctrl,
2669 .get_mctrl = serial8250_get_mctrl,
2670 .stop_tx = serial8250_stop_tx,
2671 .start_tx = serial8250_start_tx,
2672 .stop_rx = serial8250_stop_rx,
2673 .enable_ms = serial8250_enable_ms,
2674 .break_ctl = serial8250_break_ctl,
2675 .startup = serial8250_startup,
2676 .shutdown = serial8250_shutdown,
2677 .set_termios = serial8250_set_termios,
dc77f161 2678 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2679 .pm = serial8250_pm,
2680 .type = serial8250_type,
2681 .release_port = serial8250_release_port,
2682 .request_port = serial8250_request_port,
2683 .config_port = serial8250_config_port,
2684 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2685#ifdef CONFIG_CONSOLE_POLL
2686 .poll_get_char = serial8250_get_poll_char,
2687 .poll_put_char = serial8250_put_poll_char,
2688#endif
1da177e4
LT		 2689};
2690
2691static struct uart_8250_port serial8250_ports[UART_NR];
2692
af7f3743
AC		 2693static void (*serial8250_isa_config)(int port, struct uart_port *up,
2694 unsigned short *capabilities);
2695
2696void serial8250_set_isa_configurator(
2697 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2698{
2699 serial8250_isa_config = v;
2700}
2701EXPORT_SYMBOL(serial8250_set_isa_configurator);
2702
1da177e4
LT		 2703static void __init serial8250_isa_init_ports(void)
2704{
2705 struct uart_8250_port *up;
2706 static int first = 1;
4c0ebb80 2707 int i, irqflag = 0;
1da177e4
LT		 2708
2709 if (!first)
2710 return;
2711 first = 0;
2712
a61c2d78 2713 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2714 struct uart_8250_port *up = &serial8250_ports[i];
2715
2716 up->port.line = i;
2717 spin_lock_init(&up->port.lock);
2718
2719 init_timer(&up->timer);
2720 up->timer.function = serial8250_timeout;
2721
2722 /*
2723 * ALPHA_KLUDGE_MCR needs to be killed.
2724 */
2725 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2726 up->mcr_force = ALPHA_KLUDGE_MCR;
2727
2728 up->port.ops = &serial8250_pops;
2729 }
2730
4c0ebb80
AGR		 2731 if (share_irqs)
2732 irqflag = IRQF_SHARED;
2733
44454bcd 2734 for (i = 0, up = serial8250_ports;
a61c2d78 2735 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2736 i++, up++) {
2737 up->port.iobase = old_serial_port[i].port;
2738 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
1c2f0493 2739 up->port.irqflags = old_serial_port[i].irqflags;
1da177e4
LT		 2740 up->port.uartclk = old_serial_port[i].baud_base * 16;
2741 up->port.flags = old_serial_port[i].flags;
2742 up->port.hub6 = old_serial_port[i].hub6;
2743 up->port.membase = old_serial_port[i].iomem_base;
2744 up->port.iotype = old_serial_port[i].io_type;
2745 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2746 set_io_from_upio(&up->port);
4c0ebb80 2747 up->port.irqflags |= irqflag;
af7f3743
AC		 2748 if (serial8250_isa_config != NULL)
2749 serial8250_isa_config(i, &up->port, &up->capabilities);
2750
1da177e4
LT		 2751 }
2752}
2753
b5d228cc
SL		 2754static void
2755serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2756{
2757 up->port.type = type;
2758 up->port.fifosize = uart_config[type].fifo_size;
2759 up->capabilities = uart_config[type].flags;
2760 up->tx_loadsz = uart_config[type].tx_loadsz;
2761}
2762
1da177e4
LT		 2763static void __init
2764serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2765{
2766 int i;
2767
b8e7e40a
AC		 2768 for (i = 0; i < nr_uarts; i++) {
2769 struct uart_8250_port *up = &serial8250_ports[i];
2770 up->cur_iotype = 0xFF;
2771 }
2772
1da177e4
LT		 2773 serial8250_isa_init_ports();
2774
a61c2d78 2775 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2776 struct uart_8250_port *up = &serial8250_ports[i];
2777
2778 up->port.dev = dev;
b5d228cc
SL		 2779
2780 if (up->port.flags & UPF_FIXED_TYPE)
2781 serial8250_init_fixed_type_port(up, up->port.type);
2782
1da177e4
LT		 2783 uart_add_one_port(drv, &up->port);
2784 }
2785}
2786
2787#ifdef CONFIG_SERIAL_8250_CONSOLE
2788
d358788f
RK		 2789static void serial8250_console_putchar(struct uart_port *port, int ch)
2790{
49d5741b
JI		 2791 struct uart_8250_port *up =
2792 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2793
2794 wait_for_xmitr(up, UART_LSR_THRE);
2795 serial_out(up, UART_TX, ch);
2796}
2797
1da177e4
LT		 2798/*
2799 * Print a string to the serial port trying not to disturb
2800 * any possible real use of the port...
2801 *
2802 * The console_lock must be held when we get here.
2803 */
2804static void
2805serial8250_console_write(struct console *co, const char *s, unsigned int count)
2806{
2807 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2808 unsigned long flags;
1da177e4 2809 unsigned int ier;
d8a5a8d7 2810 int locked = 1;
1da177e4 2811
78512ece
AM		 2812 touch_nmi_watchdog();
2813
68aa2c0d
AM		 2814 local_irq_save(flags);
2815 if (up->port.sysrq) {
86b21199 2816 /* serial8250_handle_irq() already took the lock */
68aa2c0d
AM		 2817 locked = 0;
2818 } else if (oops_in_progress) {
2819 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2820 } else
68aa2c0d 2821 spin_lock(&up->port.lock);
d8a5a8d7 2822
1da177e4 2823 /*
dc7bf130 2824 * First save the IER then disable the interrupts
1da177e4
LT		 2825 */
2826 ier = serial_in(up, UART_IER);
2827
2828 if (up->capabilities & UART_CAP_UUE)
2829 serial_out(up, UART_IER, UART_IER_UUE);
2830 else
2831 serial_out(up, UART_IER, 0);
2832
d358788f 2833 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2834
2835 /*
2836 * Finally, wait for transmitter to become empty
2837 * and restore the IER
2838 */
f91a3715 2839 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2840 serial_out(up, UART_IER, ier);
d8a5a8d7 2841
ad4c2aa6
CM		 2842 /*
2843 * The receive handling will happen properly because the
2844 * receive ready bit will still be set; it is not cleared
2845 * on read. However, modem control will not, we must
2846 * call it if we have saved something in the saved flags
2847 * while processing with interrupts off.
2848 */
2849 if (up->msr_saved_flags)
3986fb2b 2850 serial8250_modem_status(up);
ad4c2aa6 2851
d8a5a8d7 2852 if (locked)
68aa2c0d
AM		 2853 spin_unlock(&up->port.lock);
2854 local_irq_restore(flags);
1da177e4
LT		 2855}
2856
118c0ace 2857static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2858{
2859 struct uart_port *port;
2860 int baud = 9600;
2861 int bits = 8;
2862 int parity = 'n';
2863 int flow = 'n';
2864
2865 /*
2866 * Check whether an invalid uart number has been specified, and
2867 * if so, search for the first available port that does have
2868 * console support.
2869 */
a61c2d78 2870 if (co->index >= nr_uarts)
1da177e4
LT		 2871 co->index = 0;
2872 port = &serial8250_ports[co->index].port;
2873 if (!port->iobase && !port->membase)
2874 return -ENODEV;
2875
2876 if (options)
2877 uart_parse_options(options, &baud, &parity, &bits, &flow);
2878
2879 return uart_set_options(port, co, baud, parity, bits, flow);
2880}
2881
b6b1d877 2882static int serial8250_console_early_setup(void)
18a8bd94
YL		 2883{
2884 return serial8250_find_port_for_earlycon();
2885}
2886
1da177e4
LT		 2887static struct console serial8250_console = {
2888 .name = "ttyS",
2889 .write = serial8250_console_write,
2890 .device = uart_console_device,
2891 .setup = serial8250_console_setup,
18a8bd94 2892 .early_setup = serial8250_console_early_setup,
a80c49db 2893 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2894 .index = -1,
2895 .data = &serial8250_reg,
2896};
2897
2898static int __init serial8250_console_init(void)
2899{
05d81d22
EB		 2900 if (nr_uarts > UART_NR)
2901 nr_uarts = UART_NR;
2902
1da177e4
LT		 2903 serial8250_isa_init_ports();
2904 register_console(&serial8250_console);
2905 return 0;
2906}
2907console_initcall(serial8250_console_init);
2908
18a8bd94 2909int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2910{
2911 int line;
2912 struct uart_port *port;
2913
a61c2d78 2914 for (line = 0; line < nr_uarts; line++) {
1da177e4 2915 port = &serial8250_ports[line].port;
50aec3b5 2916 if (uart_match_port(p, port))
1da177e4
LT		 2917 return line;
2918 }
2919 return -ENODEV;
2920}
2921
1da177e4
LT		 2922#define SERIAL8250_CONSOLE &serial8250_console
2923#else
2924#define SERIAL8250_CONSOLE NULL
2925#endif
2926
2927static struct uart_driver serial8250_reg = {
2928 .owner = THIS_MODULE,
2929 .driver_name = "serial",
1da177e4
LT		 2930 .dev_name = "ttyS",
2931 .major = TTY_MAJOR,
2932 .minor = 64,
1da177e4
LT		 2933 .cons = SERIAL8250_CONSOLE,
2934};
2935
d856c666
RK		 2936/*
2937 * early_serial_setup - early registration for 8250 ports
2938 *
2939 * Setup an 8250 port structure prior to console initialisation. Use
2940 * after console initialisation will cause undefined behaviour.
2941 */
1da177e4
LT		 2942int __init early_serial_setup(struct uart_port *port)
2943{
b430428a
DD		 2944 struct uart_port *p;
2945
1da177e4
LT		 2946 if (port->line >= ARRAY_SIZE(serial8250_ports))
2947 return -ENODEV;
2948
2949 serial8250_isa_init_ports();
b430428a
DD		 2950 p = &serial8250_ports[port->line].port;
2951 p->iobase = port->iobase;
2952 p->membase = port->membase;
2953 p->irq = port->irq;
1c2f0493 2954 p->irqflags = port->irqflags;
b430428a
DD		 2955 p->uartclk = port->uartclk;
2956 p->fifosize = port->fifosize;
2957 p->regshift = port->regshift;
2958 p->iotype = port->iotype;
2959 p->flags = port->flags;
2960 p->mapbase = port->mapbase;
2961 p->private_data = port->private_data;
125c97d8
HD		 2962 p->type = port->type;
2963 p->line = port->line;
7d6a07d1
DD		 2964
2965 set_io_from_upio(p);
2966 if (port->serial_in)
2967 p->serial_in = port->serial_in;
2968 if (port->serial_out)
2969 p->serial_out = port->serial_out;
583d28e9
JI		 2970 if (port->handle_irq)
2971 p->handle_irq = port->handle_irq;
2972 else
2973 p->handle_irq = serial8250_default_handle_irq;
7d6a07d1 2974
1da177e4
LT		 2975 return 0;
2976}
2977
2978/**
2979 * serial8250_suspend_port - suspend one serial port
2980 * @line: serial line number
1da177e4
LT		 2981 *
2982 * Suspend one serial port.
2983 */
2984void serial8250_suspend_port(int line)
2985{
2986 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2987}
2988
2989/**
2990 * serial8250_resume_port - resume one serial port
2991 * @line: serial line number
1da177e4
LT		 2992 *
2993 * Resume one serial port.
2994 */
2995void serial8250_resume_port(int line)
2996{
b5b82df6
DW		 2997 struct uart_8250_port *up = &serial8250_ports[line];
2998
2999 if (up->capabilities & UART_NATSEMI) {
b5b82df6
DW		 3000 /* Ensure it's still in high speed mode */
3001 serial_outp(up, UART_LCR, 0xE0);
3002
0d0389e5 3003 ns16550a_goto_highspeed(up);
b5b82df6
DW		 3004
3005 serial_outp(up, UART_LCR, 0);
95926d2d 3006 up->port.uartclk = 921600*16;
b5b82df6
DW		 3007 }
3008 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 3009}
3010
3011/*
3012 * Register a set of serial devices attached to a platform device. The
3013 * list is terminated with a zero flags entry, which means we expect
3014 * all entries to have at least UPF_BOOT_AUTOCONF set.
3015 */
3ae5eaec 3016static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 3017{
3ae5eaec 3018 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 3019 struct uart_port port;
4c0ebb80 3020 int ret, i, irqflag = 0;
1da177e4
LT		 3021
3022 memset(&port, 0, sizeof(struct uart_port));
3023
4c0ebb80
AGR		 3024 if (share_irqs)
3025 irqflag = IRQF_SHARED;
3026
ec9f47cd 3027 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 3028 port.iobase = p->iobase;
3029 port.membase = p->membase;
3030 port.irq = p->irq;
1c2f0493 3031 port.irqflags = p->irqflags;
74a19741
WN		 3032 port.uartclk = p->uartclk;
3033 port.regshift = p->regshift;
3034 port.iotype = p->iotype;
3035 port.flags = p->flags;
3036 port.mapbase = p->mapbase;
3037 port.hub6 = p->hub6;
3038 port.private_data = p->private_data;
8e23fcc8 3039 port.type = p->type;
7d6a07d1
DD		 3040 port.serial_in = p->serial_in;
3041 port.serial_out = p->serial_out;
583d28e9 3042 port.handle_irq = p->handle_irq;
235dae5d 3043 port.set_termios = p->set_termios;
c161afe9 3044 port.pm = p->pm;
74a19741 3045 port.dev = &dev->dev;
4c0ebb80 3046 port.irqflags |= irqflag;
ec9f47cd
RK		 3047 ret = serial8250_register_port(&port);
3048 if (ret < 0) {
3ae5eaec 3049 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3050 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3051 p->iobase, (unsigned long long)p->mapbase,
3052 p->irq, ret);
ec9f47cd 3053 }
1da177e4
LT		 3054 }
3055 return 0;
3056}
3057
3058/*
3059 * Remove serial ports registered against a platform device.
3060 */
3ae5eaec 3061static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3062{
3063 int i;
3064
a61c2d78 3065 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3066 struct uart_8250_port *up = &serial8250_ports[i];
3067
3ae5eaec 3068 if (up->port.dev == &dev->dev)
1da177e4
LT		 3069 serial8250_unregister_port(i);
3070 }
3071 return 0;
3072}
3073
3ae5eaec 3074static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3075{
3076 int i;
3077
1da177e4
LT		 3078 for (i = 0; i < UART_NR; i++) {
3079 struct uart_8250_port *up = &serial8250_ports[i];
3080
3ae5eaec 3081 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3082 uart_suspend_port(&serial8250_reg, &up->port);
3083 }
3084
3085 return 0;
3086}
3087
3ae5eaec 3088static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3089{
3090 int i;
3091
1da177e4
LT		 3092 for (i = 0; i < UART_NR; i++) {
3093 struct uart_8250_port *up = &serial8250_ports[i];
3094
3ae5eaec 3095 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3096 serial8250_resume_port(i);
1da177e4
LT		 3097 }
3098
3099 return 0;
3100}
3101
3ae5eaec 3102static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3103 .probe = serial8250_probe,
3104 .remove = __devexit_p(serial8250_remove),
3105 .suspend = serial8250_suspend,
3106 .resume = serial8250_resume,
3ae5eaec
RK		 3107 .driver = {
3108 .name = "serial8250",
7493a314 3109 .owner = THIS_MODULE,
3ae5eaec 3110 },
1da177e4
LT		 3111};
3112
3113/*
3114 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3115 * in the table in include/asm/serial.h
3116 */
3117static struct platform_device *serial8250_isa_devs;
3118
3119/*
3120 * serial8250_register_port and serial8250_unregister_port allows for
3121 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3122 * modems and PCI multiport cards.
3123 */
f392ecfa 3124static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3125
3126static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3127{
3128 int i;
3129
3130 /*
3131 * First, find a port entry which matches.
3132 */
a61c2d78 3133 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3134 if (uart_match_port(&serial8250_ports[i].port, port))
3135 return &serial8250_ports[i];
3136
3137 /*
3138 * We didn't find a matching entry, so look for the first
3139 * free entry. We look for one which hasn't been previously
3140 * used (indicated by zero iobase).
3141 */
a61c2d78 3142 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3143 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3144 serial8250_ports[i].port.iobase == 0)
3145 return &serial8250_ports[i];
3146
3147 /*
3148 * That also failed. Last resort is to find any entry which
3149 * doesn't have a real port associated with it.
3150 */
a61c2d78 3151 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3152 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3153 return &serial8250_ports[i];
3154
3155 return NULL;
3156}
3157
3158/**
3159 * serial8250_register_port - register a serial port
3160 * @port: serial port template
3161 *
3162 * Configure the serial port specified by the request. If the
3163 * port exists and is in use, it is hung up and unregistered
3164 * first.
3165 *
3166 * The port is then probed and if necessary the IRQ is autodetected
3167 * If this fails an error is returned.
3168 *
3169 * On success the port is ready to use and the line number is returned.
3170 */
3171int serial8250_register_port(struct uart_port *port)
3172{
3173 struct uart_8250_port *uart;
3174 int ret = -ENOSPC;
3175
3176 if (port->uartclk == 0)
3177 return -EINVAL;
3178
f392ecfa 3179 mutex_lock(&serial_mutex);
1da177e4
LT		 3180
3181 uart = serial8250_find_match_or_unused(port);
3182 if (uart) {
3183 uart_remove_one_port(&serial8250_reg, &uart->port);
3184
74a19741
WN		 3185 uart->port.iobase = port->iobase;
3186 uart->port.membase = port->membase;
3187 uart->port.irq = port->irq;
1c2f0493 3188 uart->port.irqflags = port->irqflags;
74a19741
WN		 3189 uart->port.uartclk = port->uartclk;
3190 uart->port.fifosize = port->fifosize;
3191 uart->port.regshift = port->regshift;
3192 uart->port.iotype = port->iotype;
3193 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3194 uart->port.mapbase = port->mapbase;
3195 uart->port.private_data = port->private_data;
1da177e4
LT		 3196 if (port->dev)
3197 uart->port.dev = port->dev;
8e23fcc8 3198
b5d228cc
SL		 3199 if (port->flags & UPF_FIXED_TYPE)
3200 serial8250_init_fixed_type_port(uart, port->type);
8e23fcc8 3201
7d6a07d1
DD		 3202 set_io_from_upio(&uart->port);
3203 /* Possibly override default I/O functions. */
3204 if (port->serial_in)
3205 uart->port.serial_in = port->serial_in;
3206 if (port->serial_out)
3207 uart->port.serial_out = port->serial_out;
583d28e9
JI		 3208 if (port->handle_irq)
3209 uart->port.handle_irq = port->handle_irq;
235dae5d
PL		 3210 /* Possibly override set_termios call */
3211 if (port->set_termios)
3212 uart->port.set_termios = port->set_termios;
c161afe9
ML		 3213 if (port->pm)
3214 uart->port.pm = port->pm;
1da177e4 3215
af7f3743
AC		 3216 if (serial8250_isa_config != NULL)
3217 serial8250_isa_config(0, &uart->port,
3218 &uart->capabilities);
3219
1da177e4
LT		 3220 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3221 if (ret == 0)
3222 ret = uart->port.line;
3223 }
f392ecfa 3224 mutex_unlock(&serial_mutex);
1da177e4
LT		 3225
3226 return ret;
3227}
3228EXPORT_SYMBOL(serial8250_register_port);
3229
3230/**
3231 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3232 * @line: serial line number
3233 *
3234 * Remove one serial port. This may not be called from interrupt
3235 * context. We hand the port back to the our control.
3236 */
3237void serial8250_unregister_port(int line)
3238{
3239 struct uart_8250_port *uart = &serial8250_ports[line];
3240
f392ecfa 3241 mutex_lock(&serial_mutex);
1da177e4
LT		 3242 uart_remove_one_port(&serial8250_reg, &uart->port);
3243 if (serial8250_isa_devs) {
3244 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3245 uart->port.type = PORT_UNKNOWN;
3246 uart->port.dev = &serial8250_isa_devs->dev;
cb01ece3 3247 uart->capabilities = uart_config[uart->port.type].flags;
1da177e4
LT		 3248 uart_add_one_port(&serial8250_reg, &uart->port);
3249 } else {
3250 uart->port.dev = NULL;
3251 }
f392ecfa 3252 mutex_unlock(&serial_mutex);
1da177e4
LT		 3253}
3254EXPORT_SYMBOL(serial8250_unregister_port);
3255
3256static int __init serial8250_init(void)
3257{
25db8ad5 3258 int ret;
1da177e4 3259
a61c2d78
DJ		 3260 if (nr_uarts > UART_NR)
3261 nr_uarts = UART_NR;
3262
f1fb9bb8 3263 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3264 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3265 share_irqs ? "en" : "dis");
3266
b70ac771
DM		 3267#ifdef CONFIG_SPARC
3268 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3269#else
3270 serial8250_reg.nr = UART_NR;
1da177e4 3271 ret = uart_register_driver(&serial8250_reg);
b70ac771 3272#endif
1da177e4
LT		 3273 if (ret)
3274 goto out;
3275
7493a314
DT		 3276 serial8250_isa_devs = platform_device_alloc("serial8250",
3277 PLAT8250_DEV_LEGACY);
3278 if (!serial8250_isa_devs) {
3279 ret = -ENOMEM;
bc965a7f 3280 goto unreg_uart_drv;
1da177e4
LT		 3281 }
3282
7493a314
DT		 3283 ret = platform_device_add(serial8250_isa_devs);
3284 if (ret)
3285 goto put_dev;
3286
1da177e4
LT		 3287 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3288
bc965a7f
RK		 3289 ret = platform_driver_register(&serial8250_isa_driver);
3290 if (ret == 0)
3291 goto out;
1da177e4 3292
bc965a7f 3293 platform_device_del(serial8250_isa_devs);
25db8ad5 3294put_dev:
7493a314 3295 platform_device_put(serial8250_isa_devs);
25db8ad5 3296unreg_uart_drv:
b70ac771
DM		 3297#ifdef CONFIG_SPARC
3298 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3299#else
1da177e4 3300 uart_unregister_driver(&serial8250_reg);
b70ac771 3301#endif
25db8ad5 3302out:
1da177e4
LT		 3303 return ret;
3304}
3305
3306static void __exit serial8250_exit(void)
3307{
3308 struct platform_device *isa_dev = serial8250_isa_devs;
3309
3310 /*
3311 * This tells serial8250_unregister_port() not to re-register
3312 * the ports (thereby making serial8250_isa_driver permanently
3313 * in use.)
3314 */
3315 serial8250_isa_devs = NULL;
3316
3ae5eaec 3317 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3318 platform_device_unregister(isa_dev);
3319
b70ac771
DM		 3320#ifdef CONFIG_SPARC
3321 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3322#else
1da177e4 3323 uart_unregister_driver(&serial8250_reg);
b70ac771 3324#endif
1da177e4
LT		 3325}
3326
3327module_init(serial8250_init);
3328module_exit(serial8250_exit);
3329
3330EXPORT_SYMBOL(serial8250_suspend_port);
3331EXPORT_SYMBOL(serial8250_resume_port);
3332
3333MODULE_LICENSE("GPL");
d87a6d95 3334MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3335
3336module_param(share_irqs, uint, 0644);
3337MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3338 " (unsafe)");
3339
a61c2d78
DJ		 3340module_param(nr_uarts, uint, 0644);
3341MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3342
d41a4b51
CE		 3343module_param(skip_txen_test, uint, 0644);
3344MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3345
1da177e4
LT		 3346#ifdef CONFIG_SERIAL_8250_RSA
3347module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3348MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3349#endif
3350MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
kernel source for telekom puls (alcatel/mediatek)