Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for 8250/16550-type serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright (C) 2001 Russell King. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
1da177e4 LT |
13 | * A note about mapbase / membase |
14 | * | |
15 | * mapbase is the physical address of the IO port. | |
16 | * membase is an 'ioremapped' cookie. | |
17 | */ | |
1da177e4 LT |
18 | |
19 | #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
20 | #define SUPPORT_SYSRQ | |
21 | #endif | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/console.h> | |
28 | #include <linux/sysrq.h> | |
1da177e4 | 29 | #include <linux/delay.h> |
d052d1be | 30 | #include <linux/platform_device.h> |
1da177e4 | 31 | #include <linux/tty.h> |
cd3ecad1 | 32 | #include <linux/ratelimit.h> |
1da177e4 LT |
33 | #include <linux/tty_flip.h> |
34 | #include <linux/serial_reg.h> | |
35 | #include <linux/serial_core.h> | |
36 | #include <linux/serial.h> | |
37 | #include <linux/serial_8250.h> | |
78512ece | 38 | #include <linux/nmi.h> |
f392ecfa | 39 | #include <linux/mutex.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
6816383a PG |
41 | #ifdef CONFIG_SPARC |
42 | #include <linux/sunserialcore.h> | |
43 | #endif | |
1da177e4 LT |
44 | |
45 | #include <asm/io.h> | |
46 | #include <asm/irq.h> | |
47 | ||
48 | #include "8250.h" | |
49 | ||
50 | /* | |
51 | * Configuration: | |
40663cc7 | 52 | * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option |
1da177e4 LT |
53 | * is unsafe when used on edge-triggered interrupts. |
54 | */ | |
408b664a | 55 | static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; |
1da177e4 | 56 | |
a61c2d78 DJ |
57 | static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; |
58 | ||
8440838b DM |
59 | static struct uart_driver serial8250_reg; |
60 | ||
61 | static int serial_index(struct uart_port *port) | |
62 | { | |
63 | return (serial8250_reg.minor - 64) + port->line; | |
64 | } | |
65 | ||
d41a4b51 CE |
66 | static unsigned int skip_txen_test; /* force skip of txen test at init time */ |
67 | ||
1da177e4 LT |
68 | /* |
69 | * Debugging. | |
70 | */ | |
71 | #if 0 | |
72 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) | |
73 | #else | |
74 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) | |
75 | #endif | |
76 | ||
77 | #if 0 | |
78 | #define DEBUG_INTR(fmt...) printk(fmt) | |
79 | #else | |
80 | #define DEBUG_INTR(fmt...) do { } while (0) | |
81 | #endif | |
82 | ||
e7328ae1 | 83 | #define PASS_LIMIT 512 |
1da177e4 | 84 | |
bca47613 DH |
85 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
86 | ||
87 | ||
1da177e4 LT |
88 | #ifdef CONFIG_SERIAL_8250_DETECT_IRQ |
89 | #define CONFIG_SERIAL_DETECT_IRQ 1 | |
90 | #endif | |
1da177e4 LT |
91 | #ifdef CONFIG_SERIAL_8250_MANY_PORTS |
92 | #define CONFIG_SERIAL_MANY_PORTS 1 | |
93 | #endif | |
94 | ||
95 | /* | |
96 | * HUB6 is always on. This will be removed once the header | |
97 | * files have been cleaned. | |
98 | */ | |
99 | #define CONFIG_HUB6 1 | |
100 | ||
a4ed1e41 | 101 | #include <asm/serial.h> |
1da177e4 LT |
102 | /* |
103 | * SERIAL_PORT_DFNS tells us about built-in ports that have no | |
104 | * standard enumeration mechanism. Platforms that can find all | |
105 | * serial ports via mechanisms like ACPI or PCI need not supply it. | |
106 | */ | |
107 | #ifndef SERIAL_PORT_DFNS | |
108 | #define SERIAL_PORT_DFNS | |
109 | #endif | |
110 | ||
cb3592be | 111 | static const struct old_serial_port old_serial_port[] = { |
1da177e4 LT |
112 | SERIAL_PORT_DFNS /* defined in asm/serial.h */ |
113 | }; | |
114 | ||
026d02a2 | 115 | #define UART_NR CONFIG_SERIAL_8250_NR_UARTS |
1da177e4 LT |
116 | |
117 | #ifdef CONFIG_SERIAL_8250_RSA | |
118 | ||
119 | #define PORT_RSA_MAX 4 | |
120 | static unsigned long probe_rsa[PORT_RSA_MAX]; | |
121 | static unsigned int probe_rsa_count; | |
122 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
123 | ||
1da177e4 | 124 | struct irq_info { |
25db8ad5 AC |
125 | struct hlist_node node; |
126 | int irq; | |
127 | spinlock_t lock; /* Protects list not the hash */ | |
1da177e4 LT |
128 | struct list_head *head; |
129 | }; | |
130 | ||
25db8ad5 AC |
131 | #define NR_IRQ_HASH 32 /* Can be adjusted later */ |
132 | static struct hlist_head irq_lists[NR_IRQ_HASH]; | |
133 | static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */ | |
1da177e4 LT |
134 | |
135 | /* | |
136 | * Here we define the default xmit fifo size used for each type of UART. | |
137 | */ | |
138 | static const struct serial8250_config uart_config[] = { | |
139 | [PORT_UNKNOWN] = { | |
140 | .name = "unknown", | |
141 | .fifo_size = 1, | |
142 | .tx_loadsz = 1, | |
143 | }, | |
144 | [PORT_8250] = { | |
145 | .name = "8250", | |
146 | .fifo_size = 1, | |
147 | .tx_loadsz = 1, | |
148 | }, | |
149 | [PORT_16450] = { | |
150 | .name = "16450", | |
151 | .fifo_size = 1, | |
152 | .tx_loadsz = 1, | |
153 | }, | |
154 | [PORT_16550] = { | |
155 | .name = "16550", | |
156 | .fifo_size = 1, | |
157 | .tx_loadsz = 1, | |
158 | }, | |
159 | [PORT_16550A] = { | |
160 | .name = "16550A", | |
161 | .fifo_size = 16, | |
162 | .tx_loadsz = 16, | |
163 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
164 | .flags = UART_CAP_FIFO, | |
165 | }, | |
166 | [PORT_CIRRUS] = { | |
167 | .name = "Cirrus", | |
168 | .fifo_size = 1, | |
169 | .tx_loadsz = 1, | |
170 | }, | |
171 | [PORT_16650] = { | |
172 | .name = "ST16650", | |
173 | .fifo_size = 1, | |
174 | .tx_loadsz = 1, | |
175 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
176 | }, | |
177 | [PORT_16650V2] = { | |
178 | .name = "ST16650V2", | |
179 | .fifo_size = 32, | |
180 | .tx_loadsz = 16, | |
181 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
182 | UART_FCR_T_TRIG_00, | |
183 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
184 | }, | |
185 | [PORT_16750] = { | |
186 | .name = "TI16750", | |
187 | .fifo_size = 64, | |
188 | .tx_loadsz = 64, | |
189 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | | |
190 | UART_FCR7_64BYTE, | |
191 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, | |
192 | }, | |
193 | [PORT_STARTECH] = { | |
194 | .name = "Startech", | |
195 | .fifo_size = 1, | |
196 | .tx_loadsz = 1, | |
197 | }, | |
198 | [PORT_16C950] = { | |
199 | .name = "16C950/954", | |
200 | .fifo_size = 128, | |
201 | .tx_loadsz = 128, | |
202 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
d0694e2a PM |
203 | /* UART_CAP_EFR breaks billionon CF bluetooth card. */ |
204 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP, | |
1da177e4 LT |
205 | }, |
206 | [PORT_16654] = { | |
207 | .name = "ST16654", | |
208 | .fifo_size = 64, | |
209 | .tx_loadsz = 32, | |
210 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
211 | UART_FCR_T_TRIG_10, | |
212 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
213 | }, | |
214 | [PORT_16850] = { | |
215 | .name = "XR16850", | |
216 | .fifo_size = 128, | |
217 | .tx_loadsz = 128, | |
218 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
219 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
220 | }, | |
221 | [PORT_RSA] = { | |
222 | .name = "RSA", | |
223 | .fifo_size = 2048, | |
224 | .tx_loadsz = 2048, | |
225 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, | |
226 | .flags = UART_CAP_FIFO, | |
227 | }, | |
228 | [PORT_NS16550A] = { | |
229 | .name = "NS16550A", | |
230 | .fifo_size = 16, | |
231 | .tx_loadsz = 16, | |
232 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
233 | .flags = UART_CAP_FIFO | UART_NATSEMI, | |
234 | }, | |
235 | [PORT_XSCALE] = { | |
236 | .name = "XScale", | |
237 | .fifo_size = 32, | |
238 | .tx_loadsz = 32, | |
239 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
4539c24f | 240 | .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE, |
1da177e4 | 241 | }, |
bd71c182 TK |
242 | [PORT_RM9000] = { |
243 | .name = "RM9000", | |
244 | .fifo_size = 16, | |
245 | .tx_loadsz = 16, | |
246 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
6b06f191 DD |
247 | .flags = UART_CAP_FIFO, |
248 | }, | |
249 | [PORT_OCTEON] = { | |
250 | .name = "OCTEON", | |
251 | .fifo_size = 64, | |
252 | .tx_loadsz = 64, | |
253 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
bd71c182 TK |
254 | .flags = UART_CAP_FIFO, |
255 | }, | |
08e0992f FF |
256 | [PORT_AR7] = { |
257 | .name = "AR7", | |
258 | .fifo_size = 16, | |
259 | .tx_loadsz = 16, | |
260 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, | |
261 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
262 | }, | |
235dae5d PL |
263 | [PORT_U6_16550A] = { |
264 | .name = "U6_16550A", | |
265 | .fifo_size = 64, | |
266 | .tx_loadsz = 64, | |
267 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
268 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
269 | }, | |
4539c24f SW |
270 | [PORT_TEGRA] = { |
271 | .name = "Tegra", | |
272 | .fifo_size = 32, | |
273 | .tx_loadsz = 8, | |
274 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
275 | UART_FCR_T_TRIG_01, | |
276 | .flags = UART_CAP_FIFO | UART_CAP_RTOIE, | |
277 | }, | |
06315348 SH |
278 | [PORT_XR17D15X] = { |
279 | .name = "XR17D15X", | |
280 | .fifo_size = 64, | |
281 | .tx_loadsz = 64, | |
282 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
283 | .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR, | |
284 | }, | |
7a514596 RS |
285 | [PORT_LPC3220] = { |
286 | .name = "LPC3220", | |
287 | .fifo_size = 64, | |
288 | .tx_loadsz = 32, | |
289 | .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO | | |
290 | UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00, | |
291 | .flags = UART_CAP_FIFO, | |
292 | }, | |
1da177e4 LT |
293 | }; |
294 | ||
cc419fa0 | 295 | /* Uart divisor latch read */ |
e8155629 | 296 | static int default_serial_dl_read(struct uart_8250_port *up) |
cc419fa0 MD |
297 | { |
298 | return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8; | |
299 | } | |
300 | ||
301 | /* Uart divisor latch write */ | |
e8155629 | 302 | static void default_serial_dl_write(struct uart_8250_port *up, int value) |
cc419fa0 MD |
303 | { |
304 | serial_out(up, UART_DLL, value & 0xff); | |
305 | serial_out(up, UART_DLM, value >> 8 & 0xff); | |
306 | } | |
307 | ||
6b416031 | 308 | #ifdef CONFIG_MIPS_ALCHEMY |
21c614a7 PA |
309 | |
310 | /* Au1x00 UART hardware has a weird register layout */ | |
311 | static const u8 au_io_in_map[] = { | |
312 | [UART_RX] = 0, | |
313 | [UART_IER] = 2, | |
314 | [UART_IIR] = 3, | |
315 | [UART_LCR] = 5, | |
316 | [UART_MCR] = 6, | |
317 | [UART_LSR] = 7, | |
318 | [UART_MSR] = 8, | |
319 | }; | |
320 | ||
321 | static const u8 au_io_out_map[] = { | |
322 | [UART_TX] = 1, | |
323 | [UART_IER] = 2, | |
324 | [UART_FCR] = 4, | |
325 | [UART_LCR] = 5, | |
326 | [UART_MCR] = 6, | |
327 | }; | |
328 | ||
6b416031 | 329 | static unsigned int au_serial_in(struct uart_port *p, int offset) |
21c614a7 | 330 | { |
6b416031 MD |
331 | offset = au_io_in_map[offset] << p->regshift; |
332 | return __raw_readl(p->membase + offset); | |
21c614a7 PA |
333 | } |
334 | ||
6b416031 | 335 | static void au_serial_out(struct uart_port *p, int offset, int value) |
21c614a7 | 336 | { |
6b416031 MD |
337 | offset = au_io_out_map[offset] << p->regshift; |
338 | __raw_writel(value, p->membase + offset); | |
339 | } | |
340 | ||
341 | /* Au1x00 haven't got a standard divisor latch */ | |
342 | static int au_serial_dl_read(struct uart_8250_port *up) | |
343 | { | |
344 | return __raw_readl(up->port.membase + 0x28); | |
345 | } | |
346 | ||
347 | static void au_serial_dl_write(struct uart_8250_port *up, int value) | |
348 | { | |
349 | __raw_writel(value, up->port.membase + 0x28); | |
21c614a7 PA |
350 | } |
351 | ||
6b416031 MD |
352 | #endif |
353 | ||
28bf4cf2 | 354 | #ifdef CONFIG_SERIAL_8250_RM9K |
bd71c182 TK |
355 | |
356 | static const u8 | |
357 | regmap_in[8] = { | |
358 | [UART_RX] = 0x00, | |
359 | [UART_IER] = 0x0c, | |
360 | [UART_IIR] = 0x14, | |
361 | [UART_LCR] = 0x1c, | |
362 | [UART_MCR] = 0x20, | |
363 | [UART_LSR] = 0x24, | |
364 | [UART_MSR] = 0x28, | |
365 | [UART_SCR] = 0x2c | |
366 | }, | |
367 | regmap_out[8] = { | |
368 | [UART_TX] = 0x04, | |
369 | [UART_IER] = 0x0c, | |
370 | [UART_FCR] = 0x18, | |
371 | [UART_LCR] = 0x1c, | |
372 | [UART_MCR] = 0x20, | |
373 | [UART_LSR] = 0x24, | |
374 | [UART_MSR] = 0x28, | |
375 | [UART_SCR] = 0x2c | |
376 | }; | |
377 | ||
28bf4cf2 | 378 | static unsigned int rm9k_serial_in(struct uart_port *p, int offset) |
bd71c182 | 379 | { |
28bf4cf2 MD |
380 | offset = regmap_in[offset] << p->regshift; |
381 | return readl(p->membase + offset); | |
bd71c182 TK |
382 | } |
383 | ||
28bf4cf2 | 384 | static void rm9k_serial_out(struct uart_port *p, int offset, int value) |
bd71c182 | 385 | { |
28bf4cf2 MD |
386 | offset = regmap_out[offset] << p->regshift; |
387 | writel(value, p->membase + offset); | |
bd71c182 TK |
388 | } |
389 | ||
28bf4cf2 MD |
390 | static int rm9k_serial_dl_read(struct uart_8250_port *up) |
391 | { | |
392 | return ((__raw_readl(up->port.membase + 0x10) << 8) | | |
393 | (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff; | |
394 | } | |
395 | ||
396 | static void rm9k_serial_dl_write(struct uart_8250_port *up, int value) | |
397 | { | |
398 | __raw_writel(value, up->port.membase + 0x08); | |
399 | __raw_writel(value >> 8, up->port.membase + 0x10); | |
400 | } | |
401 | ||
402 | #endif | |
21c614a7 | 403 | |
7d6a07d1 | 404 | static unsigned int hub6_serial_in(struct uart_port *p, int offset) |
1da177e4 | 405 | { |
e8155629 | 406 | offset = offset << p->regshift; |
7d6a07d1 DD |
407 | outb(p->hub6 - 1 + offset, p->iobase); |
408 | return inb(p->iobase + 1); | |
409 | } | |
1da177e4 | 410 | |
7d6a07d1 DD |
411 | static void hub6_serial_out(struct uart_port *p, int offset, int value) |
412 | { | |
e8155629 | 413 | offset = offset << p->regshift; |
7d6a07d1 DD |
414 | outb(p->hub6 - 1 + offset, p->iobase); |
415 | outb(value, p->iobase + 1); | |
416 | } | |
1da177e4 | 417 | |
7d6a07d1 DD |
418 | static unsigned int mem_serial_in(struct uart_port *p, int offset) |
419 | { | |
e8155629 | 420 | offset = offset << p->regshift; |
7d6a07d1 DD |
421 | return readb(p->membase + offset); |
422 | } | |
1da177e4 | 423 | |
7d6a07d1 DD |
424 | static void mem_serial_out(struct uart_port *p, int offset, int value) |
425 | { | |
e8155629 | 426 | offset = offset << p->regshift; |
7d6a07d1 DD |
427 | writeb(value, p->membase + offset); |
428 | } | |
429 | ||
430 | static void mem32_serial_out(struct uart_port *p, int offset, int value) | |
431 | { | |
e8155629 | 432 | offset = offset << p->regshift; |
7d6a07d1 DD |
433 | writel(value, p->membase + offset); |
434 | } | |
435 | ||
436 | static unsigned int mem32_serial_in(struct uart_port *p, int offset) | |
437 | { | |
e8155629 | 438 | offset = offset << p->regshift; |
7d6a07d1 DD |
439 | return readl(p->membase + offset); |
440 | } | |
1da177e4 | 441 | |
7d6a07d1 DD |
442 | static unsigned int io_serial_in(struct uart_port *p, int offset) |
443 | { | |
e8155629 | 444 | offset = offset << p->regshift; |
7d6a07d1 DD |
445 | return inb(p->iobase + offset); |
446 | } | |
447 | ||
448 | static void io_serial_out(struct uart_port *p, int offset, int value) | |
449 | { | |
e8155629 | 450 | offset = offset << p->regshift; |
7d6a07d1 DD |
451 | outb(value, p->iobase + offset); |
452 | } | |
453 | ||
583d28e9 JI |
454 | static int serial8250_default_handle_irq(struct uart_port *port); |
455 | ||
7d6a07d1 DD |
456 | static void set_io_from_upio(struct uart_port *p) |
457 | { | |
49d5741b JI |
458 | struct uart_8250_port *up = |
459 | container_of(p, struct uart_8250_port, port); | |
cc419fa0 | 460 | |
e8155629 MD |
461 | up->dl_read = default_serial_dl_read; |
462 | up->dl_write = default_serial_dl_write; | |
cc419fa0 | 463 | |
7d6a07d1 | 464 | switch (p->iotype) { |
1da177e4 | 465 | case UPIO_HUB6: |
7d6a07d1 DD |
466 | p->serial_in = hub6_serial_in; |
467 | p->serial_out = hub6_serial_out; | |
1da177e4 LT |
468 | break; |
469 | ||
470 | case UPIO_MEM: | |
7d6a07d1 DD |
471 | p->serial_in = mem_serial_in; |
472 | p->serial_out = mem_serial_out; | |
1da177e4 LT |
473 | break; |
474 | ||
475 | case UPIO_MEM32: | |
7d6a07d1 DD |
476 | p->serial_in = mem32_serial_in; |
477 | p->serial_out = mem32_serial_out; | |
1da177e4 LT |
478 | break; |
479 | ||
28bf4cf2 MD |
480 | #ifdef CONFIG_SERIAL_8250_RM9K |
481 | case UPIO_RM9000: | |
482 | p->serial_in = rm9k_serial_in; | |
483 | p->serial_out = rm9k_serial_out; | |
484 | up->dl_read = rm9k_serial_dl_read; | |
485 | up->dl_write = rm9k_serial_dl_write; | |
486 | break; | |
487 | #endif | |
488 | ||
6b416031 | 489 | #ifdef CONFIG_MIPS_ALCHEMY |
21c614a7 | 490 | case UPIO_AU: |
7d6a07d1 DD |
491 | p->serial_in = au_serial_in; |
492 | p->serial_out = au_serial_out; | |
6b416031 MD |
493 | up->dl_read = au_serial_dl_read; |
494 | up->dl_write = au_serial_dl_write; | |
21c614a7 | 495 | break; |
6b416031 | 496 | #endif |
12bf3f24 | 497 | |
1da177e4 | 498 | default: |
7d6a07d1 DD |
499 | p->serial_in = io_serial_in; |
500 | p->serial_out = io_serial_out; | |
501 | break; | |
1da177e4 | 502 | } |
b8e7e40a AC |
503 | /* Remember loaded iotype */ |
504 | up->cur_iotype = p->iotype; | |
583d28e9 | 505 | p->handle_irq = serial8250_default_handle_irq; |
1da177e4 LT |
506 | } |
507 | ||
40b36daa | 508 | static void |
55e4016d | 509 | serial_port_out_sync(struct uart_port *p, int offset, int value) |
40b36daa | 510 | { |
7d6a07d1 | 511 | switch (p->iotype) { |
40b36daa AW |
512 | case UPIO_MEM: |
513 | case UPIO_MEM32: | |
40b36daa | 514 | case UPIO_AU: |
7d6a07d1 DD |
515 | p->serial_out(p, offset, value); |
516 | p->serial_in(p, UART_LCR); /* safe, no side-effects */ | |
40b36daa AW |
517 | break; |
518 | default: | |
7d6a07d1 | 519 | p->serial_out(p, offset, value); |
40b36daa AW |
520 | } |
521 | } | |
522 | ||
1da177e4 LT |
523 | /* |
524 | * For the 16C950 | |
525 | */ | |
526 | static void serial_icr_write(struct uart_8250_port *up, int offset, int value) | |
527 | { | |
528 | serial_out(up, UART_SCR, offset); | |
529 | serial_out(up, UART_ICR, value); | |
530 | } | |
531 | ||
532 | static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) | |
533 | { | |
534 | unsigned int value; | |
535 | ||
536 | serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); | |
537 | serial_out(up, UART_SCR, offset); | |
538 | value = serial_in(up, UART_ICR); | |
539 | serial_icr_write(up, UART_ACR, up->acr); | |
540 | ||
541 | return value; | |
542 | } | |
543 | ||
544 | /* | |
545 | * FIFO support. | |
546 | */ | |
b5d674ab | 547 | static void serial8250_clear_fifos(struct uart_8250_port *p) |
1da177e4 LT |
548 | { |
549 | if (p->capabilities & UART_CAP_FIFO) { | |
0acf519f PG |
550 | serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO); |
551 | serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO | | |
1da177e4 | 552 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
0acf519f | 553 | serial_out(p, UART_FCR, 0); |
1da177e4 LT |
554 | } |
555 | } | |
556 | ||
0ad372b9 SM |
557 | void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p) |
558 | { | |
559 | unsigned char fcr; | |
560 | ||
561 | serial8250_clear_fifos(p); | |
562 | fcr = uart_config[p->port.type].fcr; | |
563 | serial_out(p, UART_FCR, fcr); | |
564 | } | |
565 | EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos); | |
566 | ||
1da177e4 LT |
567 | /* |
568 | * IER sleep support. UARTs which have EFRs need the "extended | |
569 | * capability" bit enabled. Note that on XR16C850s, we need to | |
570 | * reset LCR to write to IER. | |
571 | */ | |
b5d674ab | 572 | static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) |
1da177e4 LT |
573 | { |
574 | if (p->capabilities & UART_CAP_SLEEP) { | |
575 | if (p->capabilities & UART_CAP_EFR) { | |
0acf519f PG |
576 | serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); |
577 | serial_out(p, UART_EFR, UART_EFR_ECB); | |
578 | serial_out(p, UART_LCR, 0); | |
1da177e4 | 579 | } |
0acf519f | 580 | serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); |
1da177e4 | 581 | if (p->capabilities & UART_CAP_EFR) { |
0acf519f PG |
582 | serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); |
583 | serial_out(p, UART_EFR, 0); | |
584 | serial_out(p, UART_LCR, 0); | |
1da177e4 LT |
585 | } |
586 | } | |
587 | } | |
588 | ||
589 | #ifdef CONFIG_SERIAL_8250_RSA | |
590 | /* | |
591 | * Attempts to turn on the RSA FIFO. Returns zero on failure. | |
592 | * We set the port uart clock rate if we succeed. | |
593 | */ | |
594 | static int __enable_rsa(struct uart_8250_port *up) | |
595 | { | |
596 | unsigned char mode; | |
597 | int result; | |
598 | ||
0acf519f | 599 | mode = serial_in(up, UART_RSA_MSR); |
1da177e4 LT |
600 | result = mode & UART_RSA_MSR_FIFO; |
601 | ||
602 | if (!result) { | |
0acf519f PG |
603 | serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); |
604 | mode = serial_in(up, UART_RSA_MSR); | |
1da177e4 LT |
605 | result = mode & UART_RSA_MSR_FIFO; |
606 | } | |
607 | ||
608 | if (result) | |
609 | up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; | |
610 | ||
611 | return result; | |
612 | } | |
613 | ||
614 | static void enable_rsa(struct uart_8250_port *up) | |
615 | { | |
616 | if (up->port.type == PORT_RSA) { | |
617 | if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { | |
618 | spin_lock_irq(&up->port.lock); | |
619 | __enable_rsa(up); | |
620 | spin_unlock_irq(&up->port.lock); | |
621 | } | |
622 | if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) | |
0acf519f | 623 | serial_out(up, UART_RSA_FRR, 0); |
1da177e4 LT |
624 | } |
625 | } | |
626 | ||
627 | /* | |
628 | * Attempts to turn off the RSA FIFO. Returns zero on failure. | |
629 | * It is unknown why interrupts were disabled in here. However, | |
630 | * the caller is expected to preserve this behaviour by grabbing | |
631 | * the spinlock before calling this function. | |
632 | */ | |
633 | static void disable_rsa(struct uart_8250_port *up) | |
634 | { | |
635 | unsigned char mode; | |
636 | int result; | |
637 | ||
638 | if (up->port.type == PORT_RSA && | |
639 | up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { | |
640 | spin_lock_irq(&up->port.lock); | |
641 | ||
0acf519f | 642 | mode = serial_in(up, UART_RSA_MSR); |
1da177e4 LT |
643 | result = !(mode & UART_RSA_MSR_FIFO); |
644 | ||
645 | if (!result) { | |
0acf519f PG |
646 | serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); |
647 | mode = serial_in(up, UART_RSA_MSR); | |
1da177e4 LT |
648 | result = !(mode & UART_RSA_MSR_FIFO); |
649 | } | |
650 | ||
651 | if (result) | |
652 | up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; | |
653 | spin_unlock_irq(&up->port.lock); | |
654 | } | |
655 | } | |
656 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
657 | ||
658 | /* | |
659 | * This is a quickie test to see how big the FIFO is. | |
660 | * It doesn't work at all the time, more's the pity. | |
661 | */ | |
662 | static int size_fifo(struct uart_8250_port *up) | |
663 | { | |
b32b19b8 JAH |
664 | unsigned char old_fcr, old_mcr, old_lcr; |
665 | unsigned short old_dl; | |
1da177e4 LT |
666 | int count; |
667 | ||
0acf519f PG |
668 | old_lcr = serial_in(up, UART_LCR); |
669 | serial_out(up, UART_LCR, 0); | |
670 | old_fcr = serial_in(up, UART_FCR); | |
671 | old_mcr = serial_in(up, UART_MCR); | |
672 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
1da177e4 | 673 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
0acf519f PG |
674 | serial_out(up, UART_MCR, UART_MCR_LOOP); |
675 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
b32b19b8 JAH |
676 | old_dl = serial_dl_read(up); |
677 | serial_dl_write(up, 0x0001); | |
0acf519f | 678 | serial_out(up, UART_LCR, 0x03); |
1da177e4 | 679 | for (count = 0; count < 256; count++) |
0acf519f | 680 | serial_out(up, UART_TX, count); |
1da177e4 | 681 | mdelay(20);/* FIXME - schedule_timeout */ |
0acf519f | 682 | for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) && |
1da177e4 | 683 | (count < 256); count++) |
0acf519f PG |
684 | serial_in(up, UART_RX); |
685 | serial_out(up, UART_FCR, old_fcr); | |
686 | serial_out(up, UART_MCR, old_mcr); | |
687 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
b32b19b8 | 688 | serial_dl_write(up, old_dl); |
0acf519f | 689 | serial_out(up, UART_LCR, old_lcr); |
1da177e4 LT |
690 | |
691 | return count; | |
692 | } | |
693 | ||
694 | /* | |
695 | * Read UART ID using the divisor method - set DLL and DLM to zero | |
696 | * and the revision will be in DLL and device type in DLM. We | |
697 | * preserve the device state across this. | |
698 | */ | |
699 | static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) | |
700 | { | |
701 | unsigned char old_dll, old_dlm, old_lcr; | |
702 | unsigned int id; | |
703 | ||
0acf519f PG |
704 | old_lcr = serial_in(p, UART_LCR); |
705 | serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A); | |
1da177e4 | 706 | |
0acf519f PG |
707 | old_dll = serial_in(p, UART_DLL); |
708 | old_dlm = serial_in(p, UART_DLM); | |
1da177e4 | 709 | |
0acf519f PG |
710 | serial_out(p, UART_DLL, 0); |
711 | serial_out(p, UART_DLM, 0); | |
1da177e4 | 712 | |
0acf519f | 713 | id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8; |
1da177e4 | 714 | |
0acf519f PG |
715 | serial_out(p, UART_DLL, old_dll); |
716 | serial_out(p, UART_DLM, old_dlm); | |
717 | serial_out(p, UART_LCR, old_lcr); | |
1da177e4 LT |
718 | |
719 | return id; | |
720 | } | |
721 | ||
722 | /* | |
723 | * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. | |
724 | * When this function is called we know it is at least a StarTech | |
725 | * 16650 V2, but it might be one of several StarTech UARTs, or one of | |
726 | * its clones. (We treat the broken original StarTech 16650 V1 as a | |
727 | * 16550, and why not? Startech doesn't seem to even acknowledge its | |
728 | * existence.) | |
bd71c182 | 729 | * |
1da177e4 LT |
730 | * What evil have men's minds wrought... |
731 | */ | |
732 | static void autoconfig_has_efr(struct uart_8250_port *up) | |
733 | { | |
734 | unsigned int id1, id2, id3, rev; | |
735 | ||
736 | /* | |
737 | * Everything with an EFR has SLEEP | |
738 | */ | |
739 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
740 | ||
741 | /* | |
742 | * First we check to see if it's an Oxford Semiconductor UART. | |
743 | * | |
744 | * If we have to do this here because some non-National | |
745 | * Semiconductor clone chips lock up if you try writing to the | |
746 | * LSR register (which serial_icr_read does) | |
747 | */ | |
748 | ||
749 | /* | |
750 | * Check for Oxford Semiconductor 16C950. | |
751 | * | |
752 | * EFR [4] must be set else this test fails. | |
753 | * | |
754 | * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) | |
755 | * claims that it's needed for 952 dual UART's (which are not | |
756 | * recommended for new designs). | |
757 | */ | |
758 | up->acr = 0; | |
662b083a | 759 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1da177e4 LT |
760 | serial_out(up, UART_EFR, UART_EFR_ECB); |
761 | serial_out(up, UART_LCR, 0x00); | |
762 | id1 = serial_icr_read(up, UART_ID1); | |
763 | id2 = serial_icr_read(up, UART_ID2); | |
764 | id3 = serial_icr_read(up, UART_ID3); | |
765 | rev = serial_icr_read(up, UART_REV); | |
766 | ||
767 | DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); | |
768 | ||
769 | if (id1 == 0x16 && id2 == 0xC9 && | |
770 | (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { | |
771 | up->port.type = PORT_16C950; | |
4ba5e35d RK |
772 | |
773 | /* | |
774 | * Enable work around for the Oxford Semiconductor 952 rev B | |
775 | * chip which causes it to seriously miscalculate baud rates | |
776 | * when DLL is 0. | |
777 | */ | |
778 | if (id3 == 0x52 && rev == 0x01) | |
779 | up->bugs |= UART_BUG_QUOT; | |
1da177e4 LT |
780 | return; |
781 | } | |
bd71c182 | 782 | |
1da177e4 LT |
783 | /* |
784 | * We check for a XR16C850 by setting DLL and DLM to 0, and then | |
785 | * reading back DLL and DLM. The chip type depends on the DLM | |
786 | * value read back: | |
787 | * 0x10 - XR16C850 and the DLL contains the chip revision. | |
788 | * 0x12 - XR16C2850. | |
789 | * 0x14 - XR16C854. | |
790 | */ | |
791 | id1 = autoconfig_read_divisor_id(up); | |
792 | DEBUG_AUTOCONF("850id=%04x ", id1); | |
793 | ||
794 | id2 = id1 >> 8; | |
795 | if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { | |
1da177e4 LT |
796 | up->port.type = PORT_16850; |
797 | return; | |
798 | } | |
799 | ||
800 | /* | |
801 | * It wasn't an XR16C850. | |
802 | * | |
803 | * We distinguish between the '654 and the '650 by counting | |
804 | * how many bytes are in the FIFO. I'm using this for now, | |
805 | * since that's the technique that was sent to me in the | |
806 | * serial driver update, but I'm not convinced this works. | |
807 | * I've had problems doing this in the past. -TYT | |
808 | */ | |
809 | if (size_fifo(up) == 64) | |
810 | up->port.type = PORT_16654; | |
811 | else | |
812 | up->port.type = PORT_16650V2; | |
813 | } | |
814 | ||
815 | /* | |
816 | * We detected a chip without a FIFO. Only two fall into | |
817 | * this category - the original 8250 and the 16450. The | |
818 | * 16450 has a scratch register (accessible with LCR=0) | |
819 | */ | |
820 | static void autoconfig_8250(struct uart_8250_port *up) | |
821 | { | |
822 | unsigned char scratch, status1, status2; | |
823 | ||
824 | up->port.type = PORT_8250; | |
825 | ||
826 | scratch = serial_in(up, UART_SCR); | |
0acf519f | 827 | serial_out(up, UART_SCR, 0xa5); |
1da177e4 | 828 | status1 = serial_in(up, UART_SCR); |
0acf519f | 829 | serial_out(up, UART_SCR, 0x5a); |
1da177e4 | 830 | status2 = serial_in(up, UART_SCR); |
0acf519f | 831 | serial_out(up, UART_SCR, scratch); |
1da177e4 LT |
832 | |
833 | if (status1 == 0xa5 && status2 == 0x5a) | |
834 | up->port.type = PORT_16450; | |
835 | } | |
836 | ||
837 | static int broken_efr(struct uart_8250_port *up) | |
838 | { | |
839 | /* | |
840 | * Exar ST16C2550 "A2" devices incorrectly detect as | |
841 | * having an EFR, and report an ID of 0x0201. See | |
631dd1a8 | 842 | * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html |
1da177e4 LT |
843 | */ |
844 | if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) | |
845 | return 1; | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
0d0389e5 YK |
850 | static inline int ns16550a_goto_highspeed(struct uart_8250_port *up) |
851 | { | |
852 | unsigned char status; | |
853 | ||
854 | status = serial_in(up, 0x04); /* EXCR2 */ | |
855 | #define PRESL(x) ((x) & 0x30) | |
856 | if (PRESL(status) == 0x10) { | |
857 | /* already in high speed mode */ | |
858 | return 0; | |
859 | } else { | |
860 | status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ | |
861 | status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ | |
0acf519f | 862 | serial_out(up, 0x04, status); |
0d0389e5 YK |
863 | } |
864 | return 1; | |
865 | } | |
866 | ||
1da177e4 LT |
867 | /* |
868 | * We know that the chip has FIFOs. Does it have an EFR? The | |
869 | * EFR is located in the same register position as the IIR and | |
870 | * we know the top two bits of the IIR are currently set. The | |
871 | * EFR should contain zero. Try to read the EFR. | |
872 | */ | |
873 | static void autoconfig_16550a(struct uart_8250_port *up) | |
874 | { | |
875 | unsigned char status1, status2; | |
876 | unsigned int iersave; | |
877 | ||
878 | up->port.type = PORT_16550A; | |
879 | up->capabilities |= UART_CAP_FIFO; | |
880 | ||
881 | /* | |
882 | * Check for presence of the EFR when DLAB is set. | |
883 | * Only ST16C650V1 UARTs pass this test. | |
884 | */ | |
0acf519f | 885 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
1da177e4 | 886 | if (serial_in(up, UART_EFR) == 0) { |
0acf519f | 887 | serial_out(up, UART_EFR, 0xA8); |
1da177e4 LT |
888 | if (serial_in(up, UART_EFR) != 0) { |
889 | DEBUG_AUTOCONF("EFRv1 "); | |
890 | up->port.type = PORT_16650; | |
891 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
892 | } else { | |
893 | DEBUG_AUTOCONF("Motorola 8xxx DUART "); | |
894 | } | |
0acf519f | 895 | serial_out(up, UART_EFR, 0); |
1da177e4 LT |
896 | return; |
897 | } | |
898 | ||
899 | /* | |
900 | * Maybe it requires 0xbf to be written to the LCR. | |
901 | * (other ST16C650V2 UARTs, TI16C752A, etc) | |
902 | */ | |
0acf519f | 903 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1da177e4 LT |
904 | if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { |
905 | DEBUG_AUTOCONF("EFRv2 "); | |
906 | autoconfig_has_efr(up); | |
907 | return; | |
908 | } | |
909 | ||
910 | /* | |
911 | * Check for a National Semiconductor SuperIO chip. | |
912 | * Attempt to switch to bank 2, read the value of the LOOP bit | |
913 | * from EXCR1. Switch back to bank 0, change it in MCR. Then | |
914 | * switch back to bank 2, read it from EXCR1 again and check | |
915 | * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 | |
1da177e4 | 916 | */ |
0acf519f | 917 | serial_out(up, UART_LCR, 0); |
1da177e4 | 918 | status1 = serial_in(up, UART_MCR); |
0acf519f | 919 | serial_out(up, UART_LCR, 0xE0); |
1da177e4 LT |
920 | status2 = serial_in(up, 0x02); /* EXCR1 */ |
921 | ||
922 | if (!((status2 ^ status1) & UART_MCR_LOOP)) { | |
0acf519f PG |
923 | serial_out(up, UART_LCR, 0); |
924 | serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP); | |
925 | serial_out(up, UART_LCR, 0xE0); | |
1da177e4 | 926 | status2 = serial_in(up, 0x02); /* EXCR1 */ |
0acf519f PG |
927 | serial_out(up, UART_LCR, 0); |
928 | serial_out(up, UART_MCR, status1); | |
1da177e4 LT |
929 | |
930 | if ((status2 ^ status1) & UART_MCR_LOOP) { | |
857dde2e DW |
931 | unsigned short quot; |
932 | ||
0acf519f | 933 | serial_out(up, UART_LCR, 0xE0); |
857dde2e | 934 | |
b32b19b8 | 935 | quot = serial_dl_read(up); |
857dde2e DW |
936 | quot <<= 3; |
937 | ||
0d0389e5 YK |
938 | if (ns16550a_goto_highspeed(up)) |
939 | serial_dl_write(up, quot); | |
857dde2e | 940 | |
0acf519f | 941 | serial_out(up, UART_LCR, 0); |
1da177e4 | 942 | |
857dde2e | 943 | up->port.uartclk = 921600*16; |
1da177e4 LT |
944 | up->port.type = PORT_NS16550A; |
945 | up->capabilities |= UART_NATSEMI; | |
946 | return; | |
947 | } | |
948 | } | |
949 | ||
950 | /* | |
951 | * No EFR. Try to detect a TI16750, which only sets bit 5 of | |
952 | * the IIR when 64 byte FIFO mode is enabled when DLAB is set. | |
953 | * Try setting it with and without DLAB set. Cheap clones | |
954 | * set bit 5 without DLAB set. | |
955 | */ | |
0acf519f PG |
956 | serial_out(up, UART_LCR, 0); |
957 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
1da177e4 | 958 | status1 = serial_in(up, UART_IIR) >> 5; |
0acf519f PG |
959 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
960 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
961 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
1da177e4 | 962 | status2 = serial_in(up, UART_IIR) >> 5; |
0acf519f PG |
963 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
964 | serial_out(up, UART_LCR, 0); | |
1da177e4 LT |
965 | |
966 | DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); | |
967 | ||
968 | if (status1 == 6 && status2 == 7) { | |
969 | up->port.type = PORT_16750; | |
970 | up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; | |
971 | return; | |
972 | } | |
973 | ||
974 | /* | |
975 | * Try writing and reading the UART_IER_UUE bit (b6). | |
976 | * If it works, this is probably one of the Xscale platform's | |
977 | * internal UARTs. | |
978 | * We're going to explicitly set the UUE bit to 0 before | |
979 | * trying to write and read a 1 just to make sure it's not | |
980 | * already a 1 and maybe locked there before we even start start. | |
981 | */ | |
982 | iersave = serial_in(up, UART_IER); | |
0acf519f | 983 | serial_out(up, UART_IER, iersave & ~UART_IER_UUE); |
1da177e4 LT |
984 | if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { |
985 | /* | |
986 | * OK it's in a known zero state, try writing and reading | |
987 | * without disturbing the current state of the other bits. | |
988 | */ | |
0acf519f | 989 | serial_out(up, UART_IER, iersave | UART_IER_UUE); |
1da177e4 LT |
990 | if (serial_in(up, UART_IER) & UART_IER_UUE) { |
991 | /* | |
992 | * It's an Xscale. | |
993 | * We'll leave the UART_IER_UUE bit set to 1 (enabled). | |
994 | */ | |
995 | DEBUG_AUTOCONF("Xscale "); | |
996 | up->port.type = PORT_XSCALE; | |
5568181f | 997 | up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE; |
1da177e4 LT |
998 | return; |
999 | } | |
1000 | } else { | |
1001 | /* | |
1002 | * If we got here we couldn't force the IER_UUE bit to 0. | |
1003 | * Log it and continue. | |
1004 | */ | |
1005 | DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); | |
1006 | } | |
0acf519f | 1007 | serial_out(up, UART_IER, iersave); |
235dae5d | 1008 | |
06315348 SH |
1009 | /* |
1010 | * Exar uarts have EFR in a weird location | |
1011 | */ | |
1012 | if (up->port.flags & UPF_EXAR_EFR) { | |
1013 | up->port.type = PORT_XR17D15X; | |
1014 | up->capabilities |= UART_CAP_AFE | UART_CAP_EFR; | |
1015 | } | |
1016 | ||
235dae5d PL |
1017 | /* |
1018 | * We distinguish between 16550A and U6 16550A by counting | |
1019 | * how many bytes are in the FIFO. | |
1020 | */ | |
1021 | if (up->port.type == PORT_16550A && size_fifo(up) == 64) { | |
1022 | up->port.type = PORT_U6_16550A; | |
1023 | up->capabilities |= UART_CAP_AFE; | |
1024 | } | |
1da177e4 LT |
1025 | } |
1026 | ||
1027 | /* | |
1028 | * This routine is called by rs_init() to initialize a specific serial | |
1029 | * port. It determines what type of UART chip this serial port is | |
1030 | * using: 8250, 16450, 16550, 16550A. The important question is | |
1031 | * whether or not this UART is a 16550A or not, since this will | |
1032 | * determine whether or not we can use its FIFO features or not. | |
1033 | */ | |
1034 | static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) | |
1035 | { | |
1036 | unsigned char status1, scratch, scratch2, scratch3; | |
1037 | unsigned char save_lcr, save_mcr; | |
dfe42443 | 1038 | struct uart_port *port = &up->port; |
1da177e4 | 1039 | unsigned long flags; |
bd21f551 | 1040 | unsigned int old_capabilities; |
1da177e4 | 1041 | |
dfe42443 | 1042 | if (!port->iobase && !port->mapbase && !port->membase) |
1da177e4 LT |
1043 | return; |
1044 | ||
80647b95 | 1045 | DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ", |
dfe42443 | 1046 | serial_index(port), port->iobase, port->membase); |
1da177e4 LT |
1047 | |
1048 | /* | |
1049 | * We really do need global IRQs disabled here - we're going to | |
1050 | * be frobbing the chips IRQ enable register to see if it exists. | |
1051 | */ | |
dfe42443 | 1052 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 LT |
1053 | |
1054 | up->capabilities = 0; | |
4ba5e35d | 1055 | up->bugs = 0; |
1da177e4 | 1056 | |
dfe42443 | 1057 | if (!(port->flags & UPF_BUGGY_UART)) { |
1da177e4 LT |
1058 | /* |
1059 | * Do a simple existence test first; if we fail this, | |
1060 | * there's no point trying anything else. | |
bd71c182 | 1061 | * |
1da177e4 LT |
1062 | * 0x80 is used as a nonsense port to prevent against |
1063 | * false positives due to ISA bus float. The | |
1064 | * assumption is that 0x80 is a non-existent port; | |
1065 | * which should be safe since include/asm/io.h also | |
1066 | * makes this assumption. | |
1067 | * | |
1068 | * Note: this is safe as long as MCR bit 4 is clear | |
1069 | * and the device is in "PC" mode. | |
1070 | */ | |
0acf519f PG |
1071 | scratch = serial_in(up, UART_IER); |
1072 | serial_out(up, UART_IER, 0); | |
1da177e4 LT |
1073 | #ifdef __i386__ |
1074 | outb(0xff, 0x080); | |
1075 | #endif | |
48212008 TH |
1076 | /* |
1077 | * Mask out IER[7:4] bits for test as some UARTs (e.g. TL | |
1078 | * 16C754B) allow only to modify them if an EFR bit is set. | |
1079 | */ | |
0acf519f PG |
1080 | scratch2 = serial_in(up, UART_IER) & 0x0f; |
1081 | serial_out(up, UART_IER, 0x0F); | |
1da177e4 LT |
1082 | #ifdef __i386__ |
1083 | outb(0, 0x080); | |
1084 | #endif | |
0acf519f PG |
1085 | scratch3 = serial_in(up, UART_IER) & 0x0f; |
1086 | serial_out(up, UART_IER, scratch); | |
1da177e4 LT |
1087 | if (scratch2 != 0 || scratch3 != 0x0F) { |
1088 | /* | |
1089 | * We failed; there's nothing here | |
1090 | */ | |
bd21f551 | 1091 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
1092 | DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", |
1093 | scratch2, scratch3); | |
1094 | goto out; | |
1095 | } | |
1096 | } | |
1097 | ||
1098 | save_mcr = serial_in(up, UART_MCR); | |
1099 | save_lcr = serial_in(up, UART_LCR); | |
1100 | ||
bd71c182 | 1101 | /* |
1da177e4 LT |
1102 | * Check to see if a UART is really there. Certain broken |
1103 | * internal modems based on the Rockwell chipset fail this | |
1104 | * test, because they apparently don't implement the loopback | |
1105 | * test mode. So this test is skipped on the COM 1 through | |
1106 | * COM 4 ports. This *should* be safe, since no board | |
1107 | * manufacturer would be stupid enough to design a board | |
1108 | * that conflicts with COM 1-4 --- we hope! | |
1109 | */ | |
dfe42443 | 1110 | if (!(port->flags & UPF_SKIP_TEST)) { |
0acf519f PG |
1111 | serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A); |
1112 | status1 = serial_in(up, UART_MSR) & 0xF0; | |
1113 | serial_out(up, UART_MCR, save_mcr); | |
1da177e4 | 1114 | if (status1 != 0x90) { |
bd21f551 | 1115 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
1116 | DEBUG_AUTOCONF("LOOP test failed (%02x) ", |
1117 | status1); | |
1118 | goto out; | |
1119 | } | |
1120 | } | |
1121 | ||
1122 | /* | |
1123 | * We're pretty sure there's a port here. Lets find out what | |
1124 | * type of port it is. The IIR top two bits allows us to find | |
6f0d618f | 1125 | * out if it's 8250 or 16450, 16550, 16550A or later. This |
1da177e4 LT |
1126 | * determines what we test for next. |
1127 | * | |
1128 | * We also initialise the EFR (if any) to zero for later. The | |
1129 | * EFR occupies the same register location as the FCR and IIR. | |
1130 | */ | |
0acf519f PG |
1131 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1132 | serial_out(up, UART_EFR, 0); | |
1133 | serial_out(up, UART_LCR, 0); | |
1da177e4 | 1134 | |
0acf519f | 1135 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1da177e4 LT |
1136 | scratch = serial_in(up, UART_IIR) >> 6; |
1137 | ||
1da177e4 LT |
1138 | switch (scratch) { |
1139 | case 0: | |
1140 | autoconfig_8250(up); | |
1141 | break; | |
1142 | case 1: | |
dfe42443 | 1143 | port->type = PORT_UNKNOWN; |
1da177e4 LT |
1144 | break; |
1145 | case 2: | |
dfe42443 | 1146 | port->type = PORT_16550; |
1da177e4 LT |
1147 | break; |
1148 | case 3: | |
1149 | autoconfig_16550a(up); | |
1150 | break; | |
1151 | } | |
1152 | ||
1153 | #ifdef CONFIG_SERIAL_8250_RSA | |
1154 | /* | |
1155 | * Only probe for RSA ports if we got the region. | |
1156 | */ | |
dfe42443 | 1157 | if (port->type == PORT_16550A && probeflags & PROBE_RSA) { |
1da177e4 LT |
1158 | int i; |
1159 | ||
1160 | for (i = 0 ; i < probe_rsa_count; ++i) { | |
dfe42443 PG |
1161 | if (probe_rsa[i] == port->iobase && __enable_rsa(up)) { |
1162 | port->type = PORT_RSA; | |
1da177e4 LT |
1163 | break; |
1164 | } | |
1165 | } | |
1166 | } | |
1167 | #endif | |
21c614a7 | 1168 | |
0acf519f | 1169 | serial_out(up, UART_LCR, save_lcr); |
1da177e4 | 1170 | |
dfe42443 | 1171 | port->fifosize = uart_config[up->port.type].fifo_size; |
bd21f551 | 1172 | old_capabilities = up->capabilities; |
dfe42443 PG |
1173 | up->capabilities = uart_config[port->type].flags; |
1174 | up->tx_loadsz = uart_config[port->type].tx_loadsz; | |
1da177e4 | 1175 | |
dfe42443 | 1176 | if (port->type == PORT_UNKNOWN) |
bd21f551 | 1177 | goto out_lock; |
1da177e4 LT |
1178 | |
1179 | /* | |
1180 | * Reset the UART. | |
1181 | */ | |
1182 | #ifdef CONFIG_SERIAL_8250_RSA | |
dfe42443 | 1183 | if (port->type == PORT_RSA) |
0acf519f | 1184 | serial_out(up, UART_RSA_FRR, 0); |
1da177e4 | 1185 | #endif |
0acf519f | 1186 | serial_out(up, UART_MCR, save_mcr); |
1da177e4 | 1187 | serial8250_clear_fifos(up); |
40b36daa | 1188 | serial_in(up, UART_RX); |
5c8c755c | 1189 | if (up->capabilities & UART_CAP_UUE) |
0acf519f | 1190 | serial_out(up, UART_IER, UART_IER_UUE); |
5c8c755c | 1191 | else |
0acf519f | 1192 | serial_out(up, UART_IER, 0); |
1da177e4 | 1193 | |
bd21f551 | 1194 | out_lock: |
dfe42443 | 1195 | spin_unlock_irqrestore(&port->lock, flags); |
bd21f551 FL |
1196 | if (up->capabilities != old_capabilities) { |
1197 | printk(KERN_WARNING | |
1198 | "ttyS%d: detected caps %08x should be %08x\n", | |
1199 | serial_index(port), old_capabilities, | |
1200 | up->capabilities); | |
1201 | } | |
1202 | out: | |
1203 | DEBUG_AUTOCONF("iir=%d ", scratch); | |
dfe42443 | 1204 | DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name); |
1da177e4 LT |
1205 | } |
1206 | ||
1207 | static void autoconfig_irq(struct uart_8250_port *up) | |
1208 | { | |
dfe42443 | 1209 | struct uart_port *port = &up->port; |
1da177e4 LT |
1210 | unsigned char save_mcr, save_ier; |
1211 | unsigned char save_ICP = 0; | |
1212 | unsigned int ICP = 0; | |
1213 | unsigned long irqs; | |
1214 | int irq; | |
1215 | ||
dfe42443 PG |
1216 | if (port->flags & UPF_FOURPORT) { |
1217 | ICP = (port->iobase & 0xfe0) | 0x1f; | |
1da177e4 LT |
1218 | save_ICP = inb_p(ICP); |
1219 | outb_p(0x80, ICP); | |
0d263a26 | 1220 | inb_p(ICP); |
1da177e4 LT |
1221 | } |
1222 | ||
1223 | /* forget possible initially masked and pending IRQ */ | |
1224 | probe_irq_off(probe_irq_on()); | |
0acf519f PG |
1225 | save_mcr = serial_in(up, UART_MCR); |
1226 | save_ier = serial_in(up, UART_IER); | |
1227 | serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); | |
bd71c182 | 1228 | |
1da177e4 | 1229 | irqs = probe_irq_on(); |
0acf519f | 1230 | serial_out(up, UART_MCR, 0); |
6f803cd0 | 1231 | udelay(10); |
dfe42443 | 1232 | if (port->flags & UPF_FOURPORT) { |
0acf519f | 1233 | serial_out(up, UART_MCR, |
1da177e4 LT |
1234 | UART_MCR_DTR | UART_MCR_RTS); |
1235 | } else { | |
0acf519f | 1236 | serial_out(up, UART_MCR, |
1da177e4 LT |
1237 | UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); |
1238 | } | |
0acf519f | 1239 | serial_out(up, UART_IER, 0x0f); /* enable all intrs */ |
0d263a26 PG |
1240 | serial_in(up, UART_LSR); |
1241 | serial_in(up, UART_RX); | |
1242 | serial_in(up, UART_IIR); | |
1243 | serial_in(up, UART_MSR); | |
0acf519f | 1244 | serial_out(up, UART_TX, 0xFF); |
6f803cd0 | 1245 | udelay(20); |
1da177e4 LT |
1246 | irq = probe_irq_off(irqs); |
1247 | ||
0acf519f PG |
1248 | serial_out(up, UART_MCR, save_mcr); |
1249 | serial_out(up, UART_IER, save_ier); | |
1da177e4 | 1250 | |
dfe42443 | 1251 | if (port->flags & UPF_FOURPORT) |
1da177e4 LT |
1252 | outb_p(save_ICP, ICP); |
1253 | ||
dfe42443 | 1254 | port->irq = (irq > 0) ? irq : 0; |
1da177e4 LT |
1255 | } |
1256 | ||
e763b90c RK |
1257 | static inline void __stop_tx(struct uart_8250_port *p) |
1258 | { | |
1259 | if (p->ier & UART_IER_THRI) { | |
1260 | p->ier &= ~UART_IER_THRI; | |
1261 | serial_out(p, UART_IER, p->ier); | |
1262 | } | |
1263 | } | |
1264 | ||
b129a8cc | 1265 | static void serial8250_stop_tx(struct uart_port *port) |
1da177e4 | 1266 | { |
49d5741b JI |
1267 | struct uart_8250_port *up = |
1268 | container_of(port, struct uart_8250_port, port); | |
1da177e4 | 1269 | |
e763b90c | 1270 | __stop_tx(up); |
1da177e4 LT |
1271 | |
1272 | /* | |
e763b90c | 1273 | * We really want to stop the transmitter from sending. |
1da177e4 | 1274 | */ |
dfe42443 | 1275 | if (port->type == PORT_16C950) { |
1da177e4 LT |
1276 | up->acr |= UART_ACR_TXDIS; |
1277 | serial_icr_write(up, UART_ACR, up->acr); | |
1278 | } | |
1279 | } | |
1280 | ||
b129a8cc | 1281 | static void serial8250_start_tx(struct uart_port *port) |
1da177e4 | 1282 | { |
49d5741b JI |
1283 | struct uart_8250_port *up = |
1284 | container_of(port, struct uart_8250_port, port); | |
1da177e4 LT |
1285 | |
1286 | if (!(up->ier & UART_IER_THRI)) { | |
1287 | up->ier |= UART_IER_THRI; | |
4fd996a1 | 1288 | serial_port_out(port, UART_IER, up->ier); |
55d3b282 | 1289 | |
67f7654e | 1290 | if (up->bugs & UART_BUG_TXEN) { |
68cb4f8e | 1291 | unsigned char lsr; |
55d3b282 | 1292 | lsr = serial_in(up, UART_LSR); |
ad4c2aa6 | 1293 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
dfe42443 | 1294 | if ((port->type == PORT_RM9000) ? |
68cb4f8e IJ |
1295 | (lsr & UART_LSR_THRE) : |
1296 | (lsr & UART_LSR_TEMT)) | |
3986fb2b | 1297 | serial8250_tx_chars(up); |
55d3b282 | 1298 | } |
1da177e4 | 1299 | } |
e763b90c | 1300 | |
1da177e4 | 1301 | /* |
e763b90c | 1302 | * Re-enable the transmitter if we disabled it. |
1da177e4 | 1303 | */ |
dfe42443 | 1304 | if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { |
1da177e4 LT |
1305 | up->acr &= ~UART_ACR_TXDIS; |
1306 | serial_icr_write(up, UART_ACR, up->acr); | |
1307 | } | |
1308 | } | |
1309 | ||
1310 | static void serial8250_stop_rx(struct uart_port *port) | |
1311 | { | |
49d5741b JI |
1312 | struct uart_8250_port *up = |
1313 | container_of(port, struct uart_8250_port, port); | |
1da177e4 LT |
1314 | |
1315 | up->ier &= ~UART_IER_RLSI; | |
1316 | up->port.read_status_mask &= ~UART_LSR_DR; | |
4fd996a1 | 1317 | serial_port_out(port, UART_IER, up->ier); |
1da177e4 LT |
1318 | } |
1319 | ||
1320 | static void serial8250_enable_ms(struct uart_port *port) | |
1321 | { | |
49d5741b JI |
1322 | struct uart_8250_port *up = |
1323 | container_of(port, struct uart_8250_port, port); | |
1da177e4 | 1324 | |
21c614a7 PA |
1325 | /* no MSR capabilities */ |
1326 | if (up->bugs & UART_BUG_NOMSR) | |
1327 | return; | |
1328 | ||
1da177e4 | 1329 | up->ier |= UART_IER_MSI; |
4fd996a1 | 1330 | serial_port_out(port, UART_IER, up->ier); |
1da177e4 LT |
1331 | } |
1332 | ||
0690f41f | 1333 | /* |
3986fb2b | 1334 | * serial8250_rx_chars: processes according to the passed in LSR |
0690f41f PG |
1335 | * value, and returns the remaining LSR bits not handled |
1336 | * by this Rx routine. | |
1337 | */ | |
3986fb2b PG |
1338 | unsigned char |
1339 | serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr) | |
1da177e4 | 1340 | { |
dfe42443 PG |
1341 | struct uart_port *port = &up->port; |
1342 | struct tty_struct *tty = port->state->port.tty; | |
0690f41f | 1343 | unsigned char ch; |
1da177e4 LT |
1344 | int max_count = 256; |
1345 | char flag; | |
1346 | ||
1347 | do { | |
7500b1f6 | 1348 | if (likely(lsr & UART_LSR_DR)) |
0acf519f | 1349 | ch = serial_in(up, UART_RX); |
7500b1f6 AR |
1350 | else |
1351 | /* | |
1352 | * Intel 82571 has a Serial Over Lan device that will | |
1353 | * set UART_LSR_BI without setting UART_LSR_DR when | |
1354 | * it receives a break. To avoid reading from the | |
1355 | * receive buffer without UART_LSR_DR bit set, we | |
1356 | * just force the read character to be 0 | |
1357 | */ | |
1358 | ch = 0; | |
1359 | ||
1da177e4 | 1360 | flag = TTY_NORMAL; |
dfe42443 | 1361 | port->icount.rx++; |
1da177e4 | 1362 | |
ad4c2aa6 CM |
1363 | lsr |= up->lsr_saved_flags; |
1364 | up->lsr_saved_flags = 0; | |
1da177e4 | 1365 | |
ad4c2aa6 | 1366 | if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { |
1da177e4 LT |
1367 | if (lsr & UART_LSR_BI) { |
1368 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
dfe42443 | 1369 | port->icount.brk++; |
1da177e4 LT |
1370 | /* |
1371 | * We do the SysRQ and SAK checking | |
1372 | * here because otherwise the break | |
1373 | * may get masked by ignore_status_mask | |
1374 | * or read_status_mask. | |
1375 | */ | |
dfe42443 | 1376 | if (uart_handle_break(port)) |
1da177e4 LT |
1377 | goto ignore_char; |
1378 | } else if (lsr & UART_LSR_PE) | |
dfe42443 | 1379 | port->icount.parity++; |
1da177e4 | 1380 | else if (lsr & UART_LSR_FE) |
dfe42443 | 1381 | port->icount.frame++; |
1da177e4 | 1382 | if (lsr & UART_LSR_OE) |
dfe42443 | 1383 | port->icount.overrun++; |
1da177e4 LT |
1384 | |
1385 | /* | |
23907eb8 | 1386 | * Mask off conditions which should be ignored. |
1da177e4 | 1387 | */ |
dfe42443 | 1388 | lsr &= port->read_status_mask; |
1da177e4 LT |
1389 | |
1390 | if (lsr & UART_LSR_BI) { | |
1391 | DEBUG_INTR("handling break...."); | |
1392 | flag = TTY_BREAK; | |
1393 | } else if (lsr & UART_LSR_PE) | |
1394 | flag = TTY_PARITY; | |
1395 | else if (lsr & UART_LSR_FE) | |
1396 | flag = TTY_FRAME; | |
1397 | } | |
dfe42443 | 1398 | if (uart_handle_sysrq_char(port, ch)) |
1da177e4 | 1399 | goto ignore_char; |
05ab3014 | 1400 | |
dfe42443 | 1401 | uart_insert_char(port, lsr, UART_LSR_OE, ch, flag); |
05ab3014 | 1402 | |
6f803cd0 | 1403 | ignore_char: |
0acf519f | 1404 | lsr = serial_in(up, UART_LSR); |
7500b1f6 | 1405 | } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); |
dfe42443 | 1406 | spin_unlock(&port->lock); |
1da177e4 | 1407 | tty_flip_buffer_push(tty); |
dfe42443 | 1408 | spin_lock(&port->lock); |
0690f41f | 1409 | return lsr; |
1da177e4 | 1410 | } |
3986fb2b | 1411 | EXPORT_SYMBOL_GPL(serial8250_rx_chars); |
1da177e4 | 1412 | |
3986fb2b | 1413 | void serial8250_tx_chars(struct uart_8250_port *up) |
1da177e4 | 1414 | { |
dfe42443 PG |
1415 | struct uart_port *port = &up->port; |
1416 | struct circ_buf *xmit = &port->state->xmit; | |
1da177e4 LT |
1417 | int count; |
1418 | ||
dfe42443 PG |
1419 | if (port->x_char) { |
1420 | serial_out(up, UART_TX, port->x_char); | |
1421 | port->icount.tx++; | |
1422 | port->x_char = 0; | |
1da177e4 LT |
1423 | return; |
1424 | } | |
dfe42443 PG |
1425 | if (uart_tx_stopped(port)) { |
1426 | serial8250_stop_tx(port); | |
b129a8cc RK |
1427 | return; |
1428 | } | |
1429 | if (uart_circ_empty(xmit)) { | |
e763b90c | 1430 | __stop_tx(up); |
1da177e4 LT |
1431 | return; |
1432 | } | |
1433 | ||
1434 | count = up->tx_loadsz; | |
1435 | do { | |
1436 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
1437 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
dfe42443 | 1438 | port->icount.tx++; |
1da177e4 LT |
1439 | if (uart_circ_empty(xmit)) |
1440 | break; | |
1441 | } while (--count > 0); | |
1442 | ||
1443 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
dfe42443 | 1444 | uart_write_wakeup(port); |
1da177e4 LT |
1445 | |
1446 | DEBUG_INTR("THRE..."); | |
1447 | ||
1448 | if (uart_circ_empty(xmit)) | |
e763b90c | 1449 | __stop_tx(up); |
1da177e4 | 1450 | } |
3986fb2b | 1451 | EXPORT_SYMBOL_GPL(serial8250_tx_chars); |
1da177e4 | 1452 | |
3986fb2b | 1453 | unsigned int serial8250_modem_status(struct uart_8250_port *up) |
1da177e4 | 1454 | { |
dfe42443 | 1455 | struct uart_port *port = &up->port; |
2af7cd68 RK |
1456 | unsigned int status = serial_in(up, UART_MSR); |
1457 | ||
ad4c2aa6 CM |
1458 | status |= up->msr_saved_flags; |
1459 | up->msr_saved_flags = 0; | |
fdc30b3d | 1460 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && |
dfe42443 | 1461 | port->state != NULL) { |
2af7cd68 | 1462 | if (status & UART_MSR_TERI) |
dfe42443 | 1463 | port->icount.rng++; |
2af7cd68 | 1464 | if (status & UART_MSR_DDSR) |
dfe42443 | 1465 | port->icount.dsr++; |
2af7cd68 | 1466 | if (status & UART_MSR_DDCD) |
dfe42443 | 1467 | uart_handle_dcd_change(port, status & UART_MSR_DCD); |
2af7cd68 | 1468 | if (status & UART_MSR_DCTS) |
dfe42443 | 1469 | uart_handle_cts_change(port, status & UART_MSR_CTS); |
2af7cd68 | 1470 | |
dfe42443 | 1471 | wake_up_interruptible(&port->state->port.delta_msr_wait); |
2af7cd68 | 1472 | } |
1da177e4 | 1473 | |
2af7cd68 | 1474 | return status; |
1da177e4 | 1475 | } |
3986fb2b | 1476 | EXPORT_SYMBOL_GPL(serial8250_modem_status); |
1da177e4 LT |
1477 | |
1478 | /* | |
1479 | * This handles the interrupt from one port. | |
1480 | */ | |
86b21199 | 1481 | int serial8250_handle_irq(struct uart_port *port, unsigned int iir) |
1da177e4 | 1482 | { |
0690f41f | 1483 | unsigned char status; |
4bf3631c | 1484 | unsigned long flags; |
86b21199 PG |
1485 | struct uart_8250_port *up = |
1486 | container_of(port, struct uart_8250_port, port); | |
1487 | ||
1488 | if (iir & UART_IIR_NO_INT) | |
1489 | return 0; | |
45e24601 | 1490 | |
dfe42443 | 1491 | spin_lock_irqsave(&port->lock, flags); |
45e24601 | 1492 | |
4fd996a1 | 1493 | status = serial_port_in(port, UART_LSR); |
1da177e4 LT |
1494 | |
1495 | DEBUG_INTR("status = %x...", status); | |
1496 | ||
7500b1f6 | 1497 | if (status & (UART_LSR_DR | UART_LSR_BI)) |
3986fb2b PG |
1498 | status = serial8250_rx_chars(up, status); |
1499 | serial8250_modem_status(up); | |
1da177e4 | 1500 | if (status & UART_LSR_THRE) |
3986fb2b | 1501 | serial8250_tx_chars(up); |
45e24601 | 1502 | |
dfe42443 | 1503 | spin_unlock_irqrestore(&port->lock, flags); |
86b21199 | 1504 | return 1; |
583d28e9 | 1505 | } |
c7a1bdc5 | 1506 | EXPORT_SYMBOL_GPL(serial8250_handle_irq); |
583d28e9 JI |
1507 | |
1508 | static int serial8250_default_handle_irq(struct uart_port *port) | |
1509 | { | |
4fd996a1 | 1510 | unsigned int iir = serial_port_in(port, UART_IIR); |
583d28e9 JI |
1511 | |
1512 | return serial8250_handle_irq(port, iir); | |
1513 | } | |
1514 | ||
1da177e4 LT |
1515 | /* |
1516 | * This is the serial driver's interrupt routine. | |
1517 | * | |
1518 | * Arjan thinks the old way was overly complex, so it got simplified. | |
1519 | * Alan disagrees, saying that need the complexity to handle the weird | |
1520 | * nature of ISA shared interrupts. (This is a special exception.) | |
1521 | * | |
1522 | * In order to handle ISA shared interrupts properly, we need to check | |
1523 | * that all ports have been serviced, and therefore the ISA interrupt | |
1524 | * line has been de-asserted. | |
1525 | * | |
1526 | * This means we need to loop through all ports. checking that they | |
1527 | * don't have an interrupt pending. | |
1528 | */ | |
7d12e780 | 1529 | static irqreturn_t serial8250_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1530 | { |
1531 | struct irq_info *i = dev_id; | |
1532 | struct list_head *l, *end = NULL; | |
1533 | int pass_counter = 0, handled = 0; | |
1534 | ||
1535 | DEBUG_INTR("serial8250_interrupt(%d)...", irq); | |
1536 | ||
1537 | spin_lock(&i->lock); | |
1538 | ||
1539 | l = i->head; | |
1540 | do { | |
1541 | struct uart_8250_port *up; | |
583d28e9 | 1542 | struct uart_port *port; |
1da177e4 LT |
1543 | |
1544 | up = list_entry(l, struct uart_8250_port, list); | |
583d28e9 | 1545 | port = &up->port; |
1da177e4 | 1546 | |
49b532f9 | 1547 | if (port->handle_irq(port)) { |
1da177e4 | 1548 | handled = 1; |
1da177e4 LT |
1549 | end = NULL; |
1550 | } else if (end == NULL) | |
1551 | end = l; | |
1552 | ||
1553 | l = l->next; | |
1554 | ||
1555 | if (l == i->head && pass_counter++ > PASS_LIMIT) { | |
1556 | /* If we hit this, we're dead. */ | |
cd3ecad1 DD |
1557 | printk_ratelimited(KERN_ERR |
1558 | "serial8250: too much work for irq%d\n", irq); | |
1da177e4 LT |
1559 | break; |
1560 | } | |
1561 | } while (l != end); | |
1562 | ||
1563 | spin_unlock(&i->lock); | |
1564 | ||
1565 | DEBUG_INTR("end.\n"); | |
1566 | ||
1567 | return IRQ_RETVAL(handled); | |
1568 | } | |
1569 | ||
1570 | /* | |
1571 | * To support ISA shared interrupts, we need to have one interrupt | |
1572 | * handler that ensures that the IRQ line has been deasserted | |
1573 | * before returning. Failing to do this will result in the IRQ | |
1574 | * line being stuck active, and, since ISA irqs are edge triggered, | |
1575 | * no more IRQs will be seen. | |
1576 | */ | |
1577 | static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) | |
1578 | { | |
1579 | spin_lock_irq(&i->lock); | |
1580 | ||
1581 | if (!list_empty(i->head)) { | |
1582 | if (i->head == &up->list) | |
1583 | i->head = i->head->next; | |
1584 | list_del(&up->list); | |
1585 | } else { | |
1586 | BUG_ON(i->head != &up->list); | |
1587 | i->head = NULL; | |
1588 | } | |
1da177e4 | 1589 | spin_unlock_irq(&i->lock); |
25db8ad5 AC |
1590 | /* List empty so throw away the hash node */ |
1591 | if (i->head == NULL) { | |
1592 | hlist_del(&i->node); | |
1593 | kfree(i); | |
1594 | } | |
1da177e4 LT |
1595 | } |
1596 | ||
1597 | static int serial_link_irq_chain(struct uart_8250_port *up) | |
1598 | { | |
25db8ad5 AC |
1599 | struct hlist_head *h; |
1600 | struct hlist_node *n; | |
1601 | struct irq_info *i; | |
40663cc7 | 1602 | int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0; |
1da177e4 | 1603 | |
25db8ad5 AC |
1604 | mutex_lock(&hash_mutex); |
1605 | ||
1606 | h = &irq_lists[up->port.irq % NR_IRQ_HASH]; | |
1607 | ||
1608 | hlist_for_each(n, h) { | |
1609 | i = hlist_entry(n, struct irq_info, node); | |
1610 | if (i->irq == up->port.irq) | |
1611 | break; | |
1612 | } | |
1613 | ||
1614 | if (n == NULL) { | |
1615 | i = kzalloc(sizeof(struct irq_info), GFP_KERNEL); | |
1616 | if (i == NULL) { | |
1617 | mutex_unlock(&hash_mutex); | |
1618 | return -ENOMEM; | |
1619 | } | |
1620 | spin_lock_init(&i->lock); | |
1621 | i->irq = up->port.irq; | |
1622 | hlist_add_head(&i->node, h); | |
1623 | } | |
1624 | mutex_unlock(&hash_mutex); | |
1625 | ||
1da177e4 LT |
1626 | spin_lock_irq(&i->lock); |
1627 | ||
1628 | if (i->head) { | |
1629 | list_add(&up->list, i->head); | |
1630 | spin_unlock_irq(&i->lock); | |
1631 | ||
1632 | ret = 0; | |
1633 | } else { | |
1634 | INIT_LIST_HEAD(&up->list); | |
1635 | i->head = &up->list; | |
1636 | spin_unlock_irq(&i->lock); | |
1c2f0493 | 1637 | irq_flags |= up->port.irqflags; |
1da177e4 LT |
1638 | ret = request_irq(up->port.irq, serial8250_interrupt, |
1639 | irq_flags, "serial", i); | |
1640 | if (ret < 0) | |
1641 | serial_do_unlink(i, up); | |
1642 | } | |
1643 | ||
1644 | return ret; | |
1645 | } | |
1646 | ||
1647 | static void serial_unlink_irq_chain(struct uart_8250_port *up) | |
1648 | { | |
25db8ad5 AC |
1649 | struct irq_info *i; |
1650 | struct hlist_node *n; | |
1651 | struct hlist_head *h; | |
1da177e4 | 1652 | |
25db8ad5 AC |
1653 | mutex_lock(&hash_mutex); |
1654 | ||
1655 | h = &irq_lists[up->port.irq % NR_IRQ_HASH]; | |
1656 | ||
1657 | hlist_for_each(n, h) { | |
1658 | i = hlist_entry(n, struct irq_info, node); | |
1659 | if (i->irq == up->port.irq) | |
1660 | break; | |
1661 | } | |
1662 | ||
1663 | BUG_ON(n == NULL); | |
1da177e4 LT |
1664 | BUG_ON(i->head == NULL); |
1665 | ||
1666 | if (list_empty(i->head)) | |
1667 | free_irq(up->port.irq, i); | |
1668 | ||
1669 | serial_do_unlink(i, up); | |
25db8ad5 | 1670 | mutex_unlock(&hash_mutex); |
1da177e4 LT |
1671 | } |
1672 | ||
1673 | /* | |
1674 | * This function is used to handle ports that do not have an | |
1675 | * interrupt. This doesn't work very well for 16450's, but gives | |
1676 | * barely passable results for a 16550A. (Although at the expense | |
1677 | * of much CPU overhead). | |
1678 | */ | |
1679 | static void serial8250_timeout(unsigned long data) | |
1680 | { | |
1681 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
1da177e4 | 1682 | |
a0431476 | 1683 | up->port.handle_irq(&up->port); |
54381067 | 1684 | mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port)); |
40b36daa AW |
1685 | } |
1686 | ||
1687 | static void serial8250_backup_timeout(unsigned long data) | |
1688 | { | |
1689 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
ad4c2aa6 CM |
1690 | unsigned int iir, ier = 0, lsr; |
1691 | unsigned long flags; | |
40b36daa | 1692 | |
dbb3b1ca AC |
1693 | spin_lock_irqsave(&up->port.lock, flags); |
1694 | ||
40b36daa AW |
1695 | /* |
1696 | * Must disable interrupts or else we risk racing with the interrupt | |
1697 | * based handler. | |
1698 | */ | |
d4e33fac | 1699 | if (up->port.irq) { |
40b36daa AW |
1700 | ier = serial_in(up, UART_IER); |
1701 | serial_out(up, UART_IER, 0); | |
1702 | } | |
1da177e4 | 1703 | |
40b36daa AW |
1704 | iir = serial_in(up, UART_IIR); |
1705 | ||
1706 | /* | |
1707 | * This should be a safe test for anyone who doesn't trust the | |
1708 | * IIR bits on their UART, but it's specifically designed for | |
1709 | * the "Diva" UART used on the management processor on many HP | |
1710 | * ia64 and parisc boxes. | |
1711 | */ | |
ad4c2aa6 CM |
1712 | lsr = serial_in(up, UART_LSR); |
1713 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; | |
40b36daa | 1714 | if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) && |
ebd2c8f6 | 1715 | (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) && |
ad4c2aa6 | 1716 | (lsr & UART_LSR_THRE)) { |
40b36daa AW |
1717 | iir &= ~(UART_IIR_ID | UART_IIR_NO_INT); |
1718 | iir |= UART_IIR_THRI; | |
1719 | } | |
1720 | ||
1721 | if (!(iir & UART_IIR_NO_INT)) | |
3986fb2b | 1722 | serial8250_tx_chars(up); |
40b36daa | 1723 | |
d4e33fac | 1724 | if (up->port.irq) |
40b36daa AW |
1725 | serial_out(up, UART_IER, ier); |
1726 | ||
dbb3b1ca AC |
1727 | spin_unlock_irqrestore(&up->port.lock, flags); |
1728 | ||
40b36daa | 1729 | /* Standard timer interval plus 0.2s to keep the port running */ |
6f803cd0 | 1730 | mod_timer(&up->timer, |
54381067 | 1731 | jiffies + uart_poll_timeout(&up->port) + HZ / 5); |
1da177e4 LT |
1732 | } |
1733 | ||
1734 | static unsigned int serial8250_tx_empty(struct uart_port *port) | |
1735 | { | |
49d5741b JI |
1736 | struct uart_8250_port *up = |
1737 | container_of(port, struct uart_8250_port, port); | |
1da177e4 | 1738 | unsigned long flags; |
ad4c2aa6 | 1739 | unsigned int lsr; |
1da177e4 | 1740 | |
dfe42443 | 1741 | spin_lock_irqsave(&port->lock, flags); |
4fd996a1 | 1742 | lsr = serial_port_in(port, UART_LSR); |
ad4c2aa6 | 1743 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
dfe42443 | 1744 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 | 1745 | |
bca47613 | 1746 | return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; |
1da177e4 LT |
1747 | } |
1748 | ||
1749 | static unsigned int serial8250_get_mctrl(struct uart_port *port) | |
1750 | { | |
49d5741b JI |
1751 | struct uart_8250_port *up = |
1752 | container_of(port, struct uart_8250_port, port); | |
2af7cd68 | 1753 | unsigned int status; |
1da177e4 LT |
1754 | unsigned int ret; |
1755 | ||
3986fb2b | 1756 | status = serial8250_modem_status(up); |
1da177e4 LT |
1757 | |
1758 | ret = 0; | |
1759 | if (status & UART_MSR_DCD) | |
1760 | ret |= TIOCM_CAR; | |
1761 | if (status & UART_MSR_RI) | |
1762 | ret |= TIOCM_RNG; | |
1763 | if (status & UART_MSR_DSR) | |
1764 | ret |= TIOCM_DSR; | |
1765 | if (status & UART_MSR_CTS) | |
1766 | ret |= TIOCM_CTS; | |
1767 | return ret; | |
1768 | } | |
1769 | ||
1770 | static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1771 | { | |
49d5741b JI |
1772 | struct uart_8250_port *up = |
1773 | container_of(port, struct uart_8250_port, port); | |
1da177e4 LT |
1774 | unsigned char mcr = 0; |
1775 | ||
1776 | if (mctrl & TIOCM_RTS) | |
1777 | mcr |= UART_MCR_RTS; | |
1778 | if (mctrl & TIOCM_DTR) | |
1779 | mcr |= UART_MCR_DTR; | |
1780 | if (mctrl & TIOCM_OUT1) | |
1781 | mcr |= UART_MCR_OUT1; | |
1782 | if (mctrl & TIOCM_OUT2) | |
1783 | mcr |= UART_MCR_OUT2; | |
1784 | if (mctrl & TIOCM_LOOP) | |
1785 | mcr |= UART_MCR_LOOP; | |
1786 | ||
1787 | mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; | |
1788 | ||
4fd996a1 | 1789 | serial_port_out(port, UART_MCR, mcr); |
1da177e4 LT |
1790 | } |
1791 | ||
1792 | static void serial8250_break_ctl(struct uart_port *port, int break_state) | |
1793 | { | |
49d5741b JI |
1794 | struct uart_8250_port *up = |
1795 | container_of(port, struct uart_8250_port, port); | |
1da177e4 LT |
1796 | unsigned long flags; |
1797 | ||
dfe42443 | 1798 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 LT |
1799 | if (break_state == -1) |
1800 | up->lcr |= UART_LCR_SBC; | |
1801 | else | |
1802 | up->lcr &= ~UART_LCR_SBC; | |
4fd996a1 | 1803 | serial_port_out(port, UART_LCR, up->lcr); |
dfe42443 | 1804 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
1805 | } |
1806 | ||
40b36daa AW |
1807 | /* |
1808 | * Wait for transmitter & holding register to empty | |
1809 | */ | |
b5d674ab | 1810 | static void wait_for_xmitr(struct uart_8250_port *up, int bits) |
40b36daa AW |
1811 | { |
1812 | unsigned int status, tmout = 10000; | |
1813 | ||
1814 | /* Wait up to 10ms for the character(s) to be sent. */ | |
97d303b7 | 1815 | for (;;) { |
40b36daa AW |
1816 | status = serial_in(up, UART_LSR); |
1817 | ||
ad4c2aa6 | 1818 | up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; |
40b36daa | 1819 | |
97d303b7 DD |
1820 | if ((status & bits) == bits) |
1821 | break; | |
40b36daa AW |
1822 | if (--tmout == 0) |
1823 | break; | |
1824 | udelay(1); | |
97d303b7 | 1825 | } |
40b36daa AW |
1826 | |
1827 | /* Wait up to 1s for flow control if necessary */ | |
1828 | if (up->port.flags & UPF_CONS_FLOW) { | |
ad4c2aa6 CM |
1829 | unsigned int tmout; |
1830 | for (tmout = 1000000; tmout; tmout--) { | |
1831 | unsigned int msr = serial_in(up, UART_MSR); | |
1832 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; | |
1833 | if (msr & UART_MSR_CTS) | |
1834 | break; | |
40b36daa AW |
1835 | udelay(1); |
1836 | touch_nmi_watchdog(); | |
1837 | } | |
1838 | } | |
1839 | } | |
1840 | ||
f2d937f3 JW |
1841 | #ifdef CONFIG_CONSOLE_POLL |
1842 | /* | |
1843 | * Console polling routines for writing and reading from the uart while | |
1844 | * in an interrupt or debug context. | |
1845 | */ | |
1846 | ||
1847 | static int serial8250_get_poll_char(struct uart_port *port) | |
1848 | { | |
4fd996a1 | 1849 | unsigned char lsr = serial_port_in(port, UART_LSR); |
f2d937f3 | 1850 | |
f5316b4a JW |
1851 | if (!(lsr & UART_LSR_DR)) |
1852 | return NO_POLL_CHAR; | |
f2d937f3 | 1853 | |
4fd996a1 | 1854 | return serial_port_in(port, UART_RX); |
f2d937f3 JW |
1855 | } |
1856 | ||
1857 | ||
1858 | static void serial8250_put_poll_char(struct uart_port *port, | |
1859 | unsigned char c) | |
1860 | { | |
1861 | unsigned int ier; | |
49d5741b JI |
1862 | struct uart_8250_port *up = |
1863 | container_of(port, struct uart_8250_port, port); | |
f2d937f3 JW |
1864 | |
1865 | /* | |
1866 | * First save the IER then disable the interrupts | |
1867 | */ | |
4fd996a1 | 1868 | ier = serial_port_in(port, UART_IER); |
f2d937f3 | 1869 | if (up->capabilities & UART_CAP_UUE) |
4fd996a1 | 1870 | serial_port_out(port, UART_IER, UART_IER_UUE); |
f2d937f3 | 1871 | else |
4fd996a1 | 1872 | serial_port_out(port, UART_IER, 0); |
f2d937f3 JW |
1873 | |
1874 | wait_for_xmitr(up, BOTH_EMPTY); | |
1875 | /* | |
1876 | * Send the character out. | |
1877 | * If a LF, also do CR... | |
1878 | */ | |
4fd996a1 | 1879 | serial_port_out(port, UART_TX, c); |
f2d937f3 JW |
1880 | if (c == 10) { |
1881 | wait_for_xmitr(up, BOTH_EMPTY); | |
4fd996a1 | 1882 | serial_port_out(port, UART_TX, 13); |
f2d937f3 JW |
1883 | } |
1884 | ||
1885 | /* | |
1886 | * Finally, wait for transmitter to become empty | |
1887 | * and restore the IER | |
1888 | */ | |
1889 | wait_for_xmitr(up, BOTH_EMPTY); | |
4fd996a1 | 1890 | serial_port_out(port, UART_IER, ier); |
f2d937f3 JW |
1891 | } |
1892 | ||
1893 | #endif /* CONFIG_CONSOLE_POLL */ | |
1894 | ||
1da177e4 LT |
1895 | static int serial8250_startup(struct uart_port *port) |
1896 | { | |
49d5741b JI |
1897 | struct uart_8250_port *up = |
1898 | container_of(port, struct uart_8250_port, port); | |
1da177e4 | 1899 | unsigned long flags; |
55d3b282 | 1900 | unsigned char lsr, iir; |
1da177e4 LT |
1901 | int retval; |
1902 | ||
dfe42443 | 1903 | port->fifosize = uart_config[up->port.type].fifo_size; |
e4f05af1 | 1904 | up->tx_loadsz = uart_config[up->port.type].tx_loadsz; |
1da177e4 LT |
1905 | up->capabilities = uart_config[up->port.type].flags; |
1906 | up->mcr = 0; | |
1907 | ||
dfe42443 | 1908 | if (port->iotype != up->cur_iotype) |
b8e7e40a AC |
1909 | set_io_from_upio(port); |
1910 | ||
dfe42443 | 1911 | if (port->type == PORT_16C950) { |
1da177e4 LT |
1912 | /* Wake up and initialize UART */ |
1913 | up->acr = 0; | |
4fd996a1 PG |
1914 | serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); |
1915 | serial_port_out(port, UART_EFR, UART_EFR_ECB); | |
1916 | serial_port_out(port, UART_IER, 0); | |
1917 | serial_port_out(port, UART_LCR, 0); | |
1da177e4 | 1918 | serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ |
4fd996a1 PG |
1919 | serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); |
1920 | serial_port_out(port, UART_EFR, UART_EFR_ECB); | |
1921 | serial_port_out(port, UART_LCR, 0); | |
1da177e4 LT |
1922 | } |
1923 | ||
1924 | #ifdef CONFIG_SERIAL_8250_RSA | |
1925 | /* | |
1926 | * If this is an RSA port, see if we can kick it up to the | |
1927 | * higher speed clock. | |
1928 | */ | |
1929 | enable_rsa(up); | |
1930 | #endif | |
1931 | ||
1932 | /* | |
1933 | * Clear the FIFO buffers and disable them. | |
7f927fcc | 1934 | * (they will be reenabled in set_termios()) |
1da177e4 LT |
1935 | */ |
1936 | serial8250_clear_fifos(up); | |
1937 | ||
1938 | /* | |
1939 | * Clear the interrupt registers. | |
1940 | */ | |
4fd996a1 PG |
1941 | serial_port_in(port, UART_LSR); |
1942 | serial_port_in(port, UART_RX); | |
1943 | serial_port_in(port, UART_IIR); | |
1944 | serial_port_in(port, UART_MSR); | |
1da177e4 LT |
1945 | |
1946 | /* | |
1947 | * At this point, there's no way the LSR could still be 0xff; | |
1948 | * if it is, then bail out, because there's likely no UART | |
1949 | * here. | |
1950 | */ | |
dfe42443 | 1951 | if (!(port->flags & UPF_BUGGY_UART) && |
4fd996a1 | 1952 | (serial_port_in(port, UART_LSR) == 0xff)) { |
7808a4c4 | 1953 | printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n", |
dfe42443 | 1954 | serial_index(port)); |
1da177e4 LT |
1955 | return -ENODEV; |
1956 | } | |
1957 | ||
1958 | /* | |
1959 | * For a XR16C850, we need to set the trigger levels | |
1960 | */ | |
dfe42443 | 1961 | if (port->type == PORT_16850) { |
1da177e4 LT |
1962 | unsigned char fctr; |
1963 | ||
0acf519f | 1964 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1da177e4 | 1965 | |
0acf519f | 1966 | fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); |
4fd996a1 PG |
1967 | serial_port_out(port, UART_FCTR, |
1968 | fctr | UART_FCTR_TRGD | UART_FCTR_RX); | |
1969 | serial_port_out(port, UART_TRG, UART_TRG_96); | |
1970 | serial_port_out(port, UART_FCTR, | |
1971 | fctr | UART_FCTR_TRGD | UART_FCTR_TX); | |
1972 | serial_port_out(port, UART_TRG, UART_TRG_96); | |
1da177e4 | 1973 | |
4fd996a1 | 1974 | serial_port_out(port, UART_LCR, 0); |
1da177e4 LT |
1975 | } |
1976 | ||
dfe42443 | 1977 | if (port->irq) { |
01c194d9 | 1978 | unsigned char iir1; |
40b36daa AW |
1979 | /* |
1980 | * Test for UARTs that do not reassert THRE when the | |
1981 | * transmitter is idle and the interrupt has already | |
1982 | * been cleared. Real 16550s should always reassert | |
1983 | * this interrupt whenever the transmitter is idle and | |
1984 | * the interrupt is enabled. Delays are necessary to | |
1985 | * allow register changes to become visible. | |
1986 | */ | |
dfe42443 | 1987 | spin_lock_irqsave(&port->lock, flags); |
1c2f0493 | 1988 | if (up->port.irqflags & IRQF_SHARED) |
dfe42443 | 1989 | disable_irq_nosync(port->irq); |
40b36daa AW |
1990 | |
1991 | wait_for_xmitr(up, UART_LSR_THRE); | |
55e4016d | 1992 | serial_port_out_sync(port, UART_IER, UART_IER_THRI); |
40b36daa | 1993 | udelay(1); /* allow THRE to set */ |
4fd996a1 PG |
1994 | iir1 = serial_port_in(port, UART_IIR); |
1995 | serial_port_out(port, UART_IER, 0); | |
55e4016d | 1996 | serial_port_out_sync(port, UART_IER, UART_IER_THRI); |
40b36daa | 1997 | udelay(1); /* allow a working UART time to re-assert THRE */ |
4fd996a1 PG |
1998 | iir = serial_port_in(port, UART_IIR); |
1999 | serial_port_out(port, UART_IER, 0); | |
40b36daa | 2000 | |
dfe42443 PG |
2001 | if (port->irqflags & IRQF_SHARED) |
2002 | enable_irq(port->irq); | |
2003 | spin_unlock_irqrestore(&port->lock, flags); | |
40b36daa AW |
2004 | |
2005 | /* | |
bc02d15a DW |
2006 | * If the interrupt is not reasserted, or we otherwise |
2007 | * don't trust the iir, setup a timer to kick the UART | |
2008 | * on a regular basis. | |
40b36daa | 2009 | */ |
bc02d15a DW |
2010 | if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) || |
2011 | up->port.flags & UPF_BUG_THRE) { | |
363f66fe | 2012 | up->bugs |= UART_BUG_THRE; |
8440838b DM |
2013 | pr_debug("ttyS%d - using backup timer\n", |
2014 | serial_index(port)); | |
40b36daa AW |
2015 | } |
2016 | } | |
2017 | ||
363f66fe WN |
2018 | /* |
2019 | * The above check will only give an accurate result the first time | |
2020 | * the port is opened so this value needs to be preserved. | |
2021 | */ | |
2022 | if (up->bugs & UART_BUG_THRE) { | |
2023 | up->timer.function = serial8250_backup_timeout; | |
2024 | up->timer.data = (unsigned long)up; | |
2025 | mod_timer(&up->timer, jiffies + | |
54381067 | 2026 | uart_poll_timeout(port) + HZ / 5); |
363f66fe WN |
2027 | } |
2028 | ||
1da177e4 LT |
2029 | /* |
2030 | * If the "interrupt" for this port doesn't correspond with any | |
2031 | * hardware interrupt, we use a timer-based system. The original | |
2032 | * driver used to do this with IRQ0. | |
2033 | */ | |
dfe42443 | 2034 | if (!port->irq) { |
1da177e4 | 2035 | up->timer.data = (unsigned long)up; |
54381067 | 2036 | mod_timer(&up->timer, jiffies + uart_poll_timeout(port)); |
1da177e4 LT |
2037 | } else { |
2038 | retval = serial_link_irq_chain(up); | |
2039 | if (retval) | |
2040 | return retval; | |
2041 | } | |
2042 | ||
2043 | /* | |
2044 | * Now, initialize the UART | |
2045 | */ | |
4fd996a1 | 2046 | serial_port_out(port, UART_LCR, UART_LCR_WLEN8); |
1da177e4 | 2047 | |
dfe42443 | 2048 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 | 2049 | if (up->port.flags & UPF_FOURPORT) { |
d4e33fac | 2050 | if (!up->port.irq) |
1da177e4 LT |
2051 | up->port.mctrl |= TIOCM_OUT1; |
2052 | } else | |
2053 | /* | |
2054 | * Most PC uarts need OUT2 raised to enable interrupts. | |
2055 | */ | |
dfe42443 | 2056 | if (port->irq) |
1da177e4 LT |
2057 | up->port.mctrl |= TIOCM_OUT2; |
2058 | ||
dfe42443 | 2059 | serial8250_set_mctrl(port, port->mctrl); |
55d3b282 | 2060 | |
b6adea33 MCC |
2061 | /* Serial over Lan (SoL) hack: |
2062 | Intel 8257x Gigabit ethernet chips have a | |
2063 | 16550 emulation, to be used for Serial Over Lan. | |
2064 | Those chips take a longer time than a normal | |
2065 | serial device to signalize that a transmission | |
2066 | data was queued. Due to that, the above test generally | |
2067 | fails. One solution would be to delay the reading of | |
2068 | iir. However, this is not reliable, since the timeout | |
2069 | is variable. So, let's just don't test if we receive | |
2070 | TX irq. This way, we'll never enable UART_BUG_TXEN. | |
2071 | */ | |
d41a4b51 | 2072 | if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST) |
b6adea33 MCC |
2073 | goto dont_test_tx_en; |
2074 | ||
55d3b282 RK |
2075 | /* |
2076 | * Do a quick test to see if we receive an | |
2077 | * interrupt when we enable the TX irq. | |
2078 | */ | |
4fd996a1 PG |
2079 | serial_port_out(port, UART_IER, UART_IER_THRI); |
2080 | lsr = serial_port_in(port, UART_LSR); | |
2081 | iir = serial_port_in(port, UART_IIR); | |
2082 | serial_port_out(port, UART_IER, 0); | |
55d3b282 RK |
2083 | |
2084 | if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { | |
67f7654e RK |
2085 | if (!(up->bugs & UART_BUG_TXEN)) { |
2086 | up->bugs |= UART_BUG_TXEN; | |
55d3b282 | 2087 | pr_debug("ttyS%d - enabling bad tx status workarounds\n", |
8440838b | 2088 | serial_index(port)); |
55d3b282 RK |
2089 | } |
2090 | } else { | |
67f7654e | 2091 | up->bugs &= ~UART_BUG_TXEN; |
55d3b282 RK |
2092 | } |
2093 | ||
b6adea33 | 2094 | dont_test_tx_en: |
dfe42443 | 2095 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 | 2096 | |
ad4c2aa6 CM |
2097 | /* |
2098 | * Clear the interrupt registers again for luck, and clear the | |
2099 | * saved flags to avoid getting false values from polling | |
2100 | * routines or the previous session. | |
2101 | */ | |
4fd996a1 PG |
2102 | serial_port_in(port, UART_LSR); |
2103 | serial_port_in(port, UART_RX); | |
2104 | serial_port_in(port, UART_IIR); | |
2105 | serial_port_in(port, UART_MSR); | |
ad4c2aa6 CM |
2106 | up->lsr_saved_flags = 0; |
2107 | up->msr_saved_flags = 0; | |
2108 | ||
1da177e4 LT |
2109 | /* |
2110 | * Finally, enable interrupts. Note: Modem status interrupts | |
2111 | * are set via set_termios(), which will be occurring imminently | |
2112 | * anyway, so we don't enable them here. | |
2113 | */ | |
2114 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
4fd996a1 | 2115 | serial_port_out(port, UART_IER, up->ier); |
1da177e4 | 2116 | |
dfe42443 | 2117 | if (port->flags & UPF_FOURPORT) { |
1da177e4 LT |
2118 | unsigned int icp; |
2119 | /* | |
2120 | * Enable interrupts on the AST Fourport board | |
2121 | */ | |
dfe42443 | 2122 | icp = (port->iobase & 0xfe0) | 0x01f; |
1da177e4 | 2123 | outb_p(0x80, icp); |
0d263a26 | 2124 | inb_p(icp); |
1da177e4 LT |
2125 | } |
2126 | ||
1da177e4 LT |
2127 | return 0; |
2128 | } | |
2129 | ||
2130 | static void serial8250_shutdown(struct uart_port *port) | |
2131 | { | |
49d5741b JI |
2132 | struct uart_8250_port *up = |
2133 | container_of(port, struct uart_8250_port, port); | |
1da177e4 LT |
2134 | unsigned long flags; |
2135 | ||
2136 | /* | |
2137 | * Disable interrupts from this port | |
2138 | */ | |
2139 | up->ier = 0; | |
4fd996a1 | 2140 | serial_port_out(port, UART_IER, 0); |
1da177e4 | 2141 | |
dfe42443 PG |
2142 | spin_lock_irqsave(&port->lock, flags); |
2143 | if (port->flags & UPF_FOURPORT) { | |
1da177e4 | 2144 | /* reset interrupts on the AST Fourport board */ |
dfe42443 PG |
2145 | inb((port->iobase & 0xfe0) | 0x1f); |
2146 | port->mctrl |= TIOCM_OUT1; | |
1da177e4 | 2147 | } else |
dfe42443 | 2148 | port->mctrl &= ~TIOCM_OUT2; |
1da177e4 | 2149 | |
dfe42443 PG |
2150 | serial8250_set_mctrl(port, port->mctrl); |
2151 | spin_unlock_irqrestore(&port->lock, flags); | |
1da177e4 LT |
2152 | |
2153 | /* | |
2154 | * Disable break condition and FIFOs | |
2155 | */ | |
4fd996a1 PG |
2156 | serial_port_out(port, UART_LCR, |
2157 | serial_port_in(port, UART_LCR) & ~UART_LCR_SBC); | |
1da177e4 LT |
2158 | serial8250_clear_fifos(up); |
2159 | ||
2160 | #ifdef CONFIG_SERIAL_8250_RSA | |
2161 | /* | |
2162 | * Reset the RSA board back to 115kbps compat mode. | |
2163 | */ | |
2164 | disable_rsa(up); | |
2165 | #endif | |
2166 | ||
2167 | /* | |
2168 | * Read data port to reset things, and then unlink from | |
2169 | * the IRQ chain. | |
2170 | */ | |
4fd996a1 | 2171 | serial_port_in(port, UART_RX); |
1da177e4 | 2172 | |
40b36daa AW |
2173 | del_timer_sync(&up->timer); |
2174 | up->timer.function = serial8250_timeout; | |
dfe42443 | 2175 | if (port->irq) |
1da177e4 LT |
2176 | serial_unlink_irq_chain(up); |
2177 | } | |
2178 | ||
2179 | static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud) | |
2180 | { | |
2181 | unsigned int quot; | |
2182 | ||
2183 | /* | |
2184 | * Handle magic divisors for baud rates above baud_base on | |
2185 | * SMSC SuperIO chips. | |
2186 | */ | |
2187 | if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2188 | baud == (port->uartclk/4)) | |
2189 | quot = 0x8001; | |
2190 | else if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2191 | baud == (port->uartclk/8)) | |
2192 | quot = 0x8002; | |
2193 | else | |
2194 | quot = uart_get_divisor(port, baud); | |
2195 | ||
2196 | return quot; | |
2197 | } | |
2198 | ||
235dae5d PL |
2199 | void |
2200 | serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, | |
2201 | struct ktermios *old) | |
1da177e4 | 2202 | { |
49d5741b JI |
2203 | struct uart_8250_port *up = |
2204 | container_of(port, struct uart_8250_port, port); | |
1da177e4 LT |
2205 | unsigned char cval, fcr = 0; |
2206 | unsigned long flags; | |
2207 | unsigned int baud, quot; | |
eb26dfe8 | 2208 | int fifo_bug = 0; |
1da177e4 LT |
2209 | |
2210 | switch (termios->c_cflag & CSIZE) { | |
2211 | case CS5: | |
0a8b80c5 | 2212 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
2213 | break; |
2214 | case CS6: | |
0a8b80c5 | 2215 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
2216 | break; |
2217 | case CS7: | |
0a8b80c5 | 2218 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
2219 | break; |
2220 | default: | |
2221 | case CS8: | |
0a8b80c5 | 2222 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
2223 | break; |
2224 | } | |
2225 | ||
2226 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 2227 | cval |= UART_LCR_STOP; |
eb26dfe8 | 2228 | if (termios->c_cflag & PARENB) { |
1da177e4 | 2229 | cval |= UART_LCR_PARITY; |
eb26dfe8 AC |
2230 | if (up->bugs & UART_BUG_PARITY) |
2231 | fifo_bug = 1; | |
2232 | } | |
1da177e4 LT |
2233 | if (!(termios->c_cflag & PARODD)) |
2234 | cval |= UART_LCR_EPAR; | |
2235 | #ifdef CMSPAR | |
2236 | if (termios->c_cflag & CMSPAR) | |
2237 | cval |= UART_LCR_SPAR; | |
2238 | #endif | |
2239 | ||
2240 | /* | |
2241 | * Ask the core to calculate the divisor for us. | |
2242 | */ | |
24d481ec AV |
2243 | baud = uart_get_baud_rate(port, termios, old, |
2244 | port->uartclk / 16 / 0xffff, | |
2245 | port->uartclk / 16); | |
1da177e4 LT |
2246 | quot = serial8250_get_divisor(port, baud); |
2247 | ||
2248 | /* | |
4ba5e35d | 2249 | * Oxford Semi 952 rev B workaround |
1da177e4 | 2250 | */ |
4ba5e35d | 2251 | if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) |
3e8d4e20 | 2252 | quot++; |
1da177e4 | 2253 | |
dfe42443 | 2254 | if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) { |
f9a9111b | 2255 | fcr = uart_config[port->type].fcr; |
eb26dfe8 | 2256 | if (baud < 2400 || fifo_bug) { |
f9a9111b CM |
2257 | fcr &= ~UART_FCR_TRIGGER_MASK; |
2258 | fcr |= UART_FCR_TRIGGER_1; | |
2259 | } | |
1da177e4 LT |
2260 | } |
2261 | ||
2262 | /* | |
2263 | * MCR-based auto flow control. When AFE is enabled, RTS will be | |
2264 | * deasserted when the receive FIFO contains more characters than | |
2265 | * the trigger, or the MCR RTS bit is cleared. In the case where | |
2266 | * the remote UART is not using CTS auto flow control, we must | |
2267 | * have sufficient FIFO entries for the latency of the remote | |
2268 | * UART to respond. IOW, at least 32 bytes of FIFO. | |
2269 | */ | |
dfe42443 | 2270 | if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) { |
1da177e4 LT |
2271 | up->mcr &= ~UART_MCR_AFE; |
2272 | if (termios->c_cflag & CRTSCTS) | |
2273 | up->mcr |= UART_MCR_AFE; | |
2274 | } | |
2275 | ||
2276 | /* | |
2277 | * Ok, we're now changing the port state. Do it with | |
2278 | * interrupts disabled. | |
2279 | */ | |
dfe42443 | 2280 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 LT |
2281 | |
2282 | /* | |
2283 | * Update the per-port timeout. | |
2284 | */ | |
2285 | uart_update_timeout(port, termios->c_cflag, baud); | |
2286 | ||
dfe42443 | 2287 | port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
1da177e4 | 2288 | if (termios->c_iflag & INPCK) |
dfe42443 | 2289 | port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
1da177e4 | 2290 | if (termios->c_iflag & (BRKINT | PARMRK)) |
dfe42443 | 2291 | port->read_status_mask |= UART_LSR_BI; |
1da177e4 LT |
2292 | |
2293 | /* | |
2294 | * Characteres to ignore | |
2295 | */ | |
dfe42443 | 2296 | port->ignore_status_mask = 0; |
1da177e4 | 2297 | if (termios->c_iflag & IGNPAR) |
dfe42443 | 2298 | port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; |
1da177e4 | 2299 | if (termios->c_iflag & IGNBRK) { |
dfe42443 | 2300 | port->ignore_status_mask |= UART_LSR_BI; |
1da177e4 LT |
2301 | /* |
2302 | * If we're ignoring parity and break indicators, | |
2303 | * ignore overruns too (for real raw support). | |
2304 | */ | |
2305 | if (termios->c_iflag & IGNPAR) | |
dfe42443 | 2306 | port->ignore_status_mask |= UART_LSR_OE; |
1da177e4 LT |
2307 | } |
2308 | ||
2309 | /* | |
2310 | * ignore all characters if CREAD is not set | |
2311 | */ | |
2312 | if ((termios->c_cflag & CREAD) == 0) | |
dfe42443 | 2313 | port->ignore_status_mask |= UART_LSR_DR; |
1da177e4 LT |
2314 | |
2315 | /* | |
2316 | * CTS flow control flag and modem status interrupts | |
2317 | */ | |
f8b372a1 | 2318 | up->ier &= ~UART_IER_MSI; |
21c614a7 PA |
2319 | if (!(up->bugs & UART_BUG_NOMSR) && |
2320 | UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
1da177e4 LT |
2321 | up->ier |= UART_IER_MSI; |
2322 | if (up->capabilities & UART_CAP_UUE) | |
4539c24f SW |
2323 | up->ier |= UART_IER_UUE; |
2324 | if (up->capabilities & UART_CAP_RTOIE) | |
2325 | up->ier |= UART_IER_RTOIE; | |
1da177e4 | 2326 | |
4fd996a1 | 2327 | serial_port_out(port, UART_IER, up->ier); |
1da177e4 LT |
2328 | |
2329 | if (up->capabilities & UART_CAP_EFR) { | |
2330 | unsigned char efr = 0; | |
2331 | /* | |
2332 | * TI16C752/Startech hardware flow control. FIXME: | |
2333 | * - TI16C752 requires control thresholds to be set. | |
2334 | * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. | |
2335 | */ | |
2336 | if (termios->c_cflag & CRTSCTS) | |
2337 | efr |= UART_EFR_CTS; | |
2338 | ||
4fd996a1 | 2339 | serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); |
dfe42443 | 2340 | if (port->flags & UPF_EXAR_EFR) |
4fd996a1 | 2341 | serial_port_out(port, UART_XR_EFR, efr); |
06315348 | 2342 | else |
4fd996a1 | 2343 | serial_port_out(port, UART_EFR, efr); |
1da177e4 LT |
2344 | } |
2345 | ||
cdd86b27 | 2346 | #ifdef CONFIG_ARCH_OMAP1 |
255341c6 | 2347 | /* Workaround to enable 115200 baud on OMAP1510 internal ports */ |
5668545a | 2348 | if (cpu_is_omap1510() && is_omap_port(up)) { |
255341c6 JM |
2349 | if (baud == 115200) { |
2350 | quot = 1; | |
4fd996a1 | 2351 | serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1); |
255341c6 | 2352 | } else |
4fd996a1 | 2353 | serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0); |
255341c6 JM |
2354 | } |
2355 | #endif | |
2356 | ||
4fd996a1 PG |
2357 | /* |
2358 | * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2, | |
2359 | * otherwise just set DLAB | |
2360 | */ | |
2361 | if (up->capabilities & UART_NATSEMI) | |
2362 | serial_port_out(port, UART_LCR, 0xe0); | |
2363 | else | |
2364 | serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB); | |
1da177e4 | 2365 | |
b32b19b8 | 2366 | serial_dl_write(up, quot); |
1da177e4 LT |
2367 | |
2368 | /* | |
2369 | * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR | |
2370 | * is written without DLAB set, this mode will be disabled. | |
2371 | */ | |
dfe42443 | 2372 | if (port->type == PORT_16750) |
4fd996a1 | 2373 | serial_port_out(port, UART_FCR, fcr); |
1da177e4 | 2374 | |
4fd996a1 | 2375 | serial_port_out(port, UART_LCR, cval); /* reset DLAB */ |
1da177e4 | 2376 | up->lcr = cval; /* Save LCR */ |
dfe42443 | 2377 | if (port->type != PORT_16750) { |
4fd996a1 PG |
2378 | /* emulated UARTs (Lucent Venus 167x) need two steps */ |
2379 | if (fcr & UART_FCR_ENABLE_FIFO) | |
2380 | serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO); | |
2381 | serial_port_out(port, UART_FCR, fcr); /* set fcr */ | |
1da177e4 | 2382 | } |
dfe42443 PG |
2383 | serial8250_set_mctrl(port, port->mctrl); |
2384 | spin_unlock_irqrestore(&port->lock, flags); | |
e991a2bd AC |
2385 | /* Don't rewrite B0 */ |
2386 | if (tty_termios_baud_rate(termios)) | |
2387 | tty_termios_encode_baud_rate(termios, baud, baud); | |
1da177e4 | 2388 | } |
235dae5d PL |
2389 | EXPORT_SYMBOL(serial8250_do_set_termios); |
2390 | ||
2391 | static void | |
2392 | serial8250_set_termios(struct uart_port *port, struct ktermios *termios, | |
2393 | struct ktermios *old) | |
2394 | { | |
2395 | if (port->set_termios) | |
2396 | port->set_termios(port, termios, old); | |
2397 | else | |
2398 | serial8250_do_set_termios(port, termios, old); | |
2399 | } | |
1da177e4 | 2400 | |
dc77f161 | 2401 | static void |
a0821df6 | 2402 | serial8250_set_ldisc(struct uart_port *port, int new) |
dc77f161 | 2403 | { |
a0821df6 | 2404 | if (new == N_PPS) { |
dc77f161 RG |
2405 | port->flags |= UPF_HARDPPS_CD; |
2406 | serial8250_enable_ms(port); | |
2407 | } else | |
2408 | port->flags &= ~UPF_HARDPPS_CD; | |
2409 | } | |
2410 | ||
c161afe9 ML |
2411 | |
2412 | void serial8250_do_pm(struct uart_port *port, unsigned int state, | |
2413 | unsigned int oldstate) | |
1da177e4 | 2414 | { |
49d5741b JI |
2415 | struct uart_8250_port *p = |
2416 | container_of(port, struct uart_8250_port, port); | |
1da177e4 LT |
2417 | |
2418 | serial8250_set_sleep(p, state != 0); | |
c161afe9 ML |
2419 | } |
2420 | EXPORT_SYMBOL(serial8250_do_pm); | |
1da177e4 | 2421 | |
c161afe9 ML |
2422 | static void |
2423 | serial8250_pm(struct uart_port *port, unsigned int state, | |
2424 | unsigned int oldstate) | |
2425 | { | |
2426 | if (port->pm) | |
2427 | port->pm(port, state, oldstate); | |
2428 | else | |
2429 | serial8250_do_pm(port, state, oldstate); | |
1da177e4 LT |
2430 | } |
2431 | ||
f2eda27d RK |
2432 | static unsigned int serial8250_port_size(struct uart_8250_port *pt) |
2433 | { | |
2434 | if (pt->port.iotype == UPIO_AU) | |
b2b13cdf | 2435 | return 0x1000; |
cdd86b27 | 2436 | #ifdef CONFIG_ARCH_OMAP1 |
f2eda27d RK |
2437 | if (is_omap_port(pt)) |
2438 | return 0x16 << pt->port.regshift; | |
2439 | #endif | |
2440 | return 8 << pt->port.regshift; | |
2441 | } | |
2442 | ||
1da177e4 LT |
2443 | /* |
2444 | * Resource handling. | |
2445 | */ | |
2446 | static int serial8250_request_std_resource(struct uart_8250_port *up) | |
2447 | { | |
f2eda27d | 2448 | unsigned int size = serial8250_port_size(up); |
dfe42443 | 2449 | struct uart_port *port = &up->port; |
1da177e4 LT |
2450 | int ret = 0; |
2451 | ||
dfe42443 | 2452 | switch (port->iotype) { |
85835f44 | 2453 | case UPIO_AU: |
0b30d668 SS |
2454 | case UPIO_TSI: |
2455 | case UPIO_MEM32: | |
1da177e4 | 2456 | case UPIO_MEM: |
dfe42443 | 2457 | if (!port->mapbase) |
1da177e4 LT |
2458 | break; |
2459 | ||
dfe42443 | 2460 | if (!request_mem_region(port->mapbase, size, "serial")) { |
1da177e4 LT |
2461 | ret = -EBUSY; |
2462 | break; | |
2463 | } | |
2464 | ||
dfe42443 PG |
2465 | if (port->flags & UPF_IOREMAP) { |
2466 | port->membase = ioremap_nocache(port->mapbase, size); | |
2467 | if (!port->membase) { | |
2468 | release_mem_region(port->mapbase, size); | |
1da177e4 LT |
2469 | ret = -ENOMEM; |
2470 | } | |
2471 | } | |
2472 | break; | |
2473 | ||
2474 | case UPIO_HUB6: | |
2475 | case UPIO_PORT: | |
dfe42443 | 2476 | if (!request_region(port->iobase, size, "serial")) |
1da177e4 LT |
2477 | ret = -EBUSY; |
2478 | break; | |
2479 | } | |
2480 | return ret; | |
2481 | } | |
2482 | ||
2483 | static void serial8250_release_std_resource(struct uart_8250_port *up) | |
2484 | { | |
f2eda27d | 2485 | unsigned int size = serial8250_port_size(up); |
dfe42443 | 2486 | struct uart_port *port = &up->port; |
1da177e4 | 2487 | |
dfe42443 | 2488 | switch (port->iotype) { |
85835f44 | 2489 | case UPIO_AU: |
0b30d668 SS |
2490 | case UPIO_TSI: |
2491 | case UPIO_MEM32: | |
1da177e4 | 2492 | case UPIO_MEM: |
dfe42443 | 2493 | if (!port->mapbase) |
1da177e4 LT |
2494 | break; |
2495 | ||
dfe42443 PG |
2496 | if (port->flags & UPF_IOREMAP) { |
2497 | iounmap(port->membase); | |
2498 | port->membase = NULL; | |
1da177e4 LT |
2499 | } |
2500 | ||
dfe42443 | 2501 | release_mem_region(port->mapbase, size); |
1da177e4 LT |
2502 | break; |
2503 | ||
2504 | case UPIO_HUB6: | |
2505 | case UPIO_PORT: | |
dfe42443 | 2506 | release_region(port->iobase, size); |
1da177e4 LT |
2507 | break; |
2508 | } | |
2509 | } | |
2510 | ||
2511 | static int serial8250_request_rsa_resource(struct uart_8250_port *up) | |
2512 | { | |
2513 | unsigned long start = UART_RSA_BASE << up->port.regshift; | |
2514 | unsigned int size = 8 << up->port.regshift; | |
dfe42443 | 2515 | struct uart_port *port = &up->port; |
0b30d668 | 2516 | int ret = -EINVAL; |
1da177e4 | 2517 | |
dfe42443 | 2518 | switch (port->iotype) { |
1da177e4 LT |
2519 | case UPIO_HUB6: |
2520 | case UPIO_PORT: | |
dfe42443 | 2521 | start += port->iobase; |
0b30d668 SS |
2522 | if (request_region(start, size, "serial-rsa")) |
2523 | ret = 0; | |
2524 | else | |
1da177e4 LT |
2525 | ret = -EBUSY; |
2526 | break; | |
2527 | } | |
2528 | ||
2529 | return ret; | |
2530 | } | |
2531 | ||
2532 | static void serial8250_release_rsa_resource(struct uart_8250_port *up) | |
2533 | { | |
2534 | unsigned long offset = UART_RSA_BASE << up->port.regshift; | |
2535 | unsigned int size = 8 << up->port.regshift; | |
dfe42443 | 2536 | struct uart_port *port = &up->port; |
1da177e4 | 2537 | |
dfe42443 | 2538 | switch (port->iotype) { |
1da177e4 LT |
2539 | case UPIO_HUB6: |
2540 | case UPIO_PORT: | |
dfe42443 | 2541 | release_region(port->iobase + offset, size); |
1da177e4 LT |
2542 | break; |
2543 | } | |
2544 | } | |
2545 | ||
2546 | static void serial8250_release_port(struct uart_port *port) | |
2547 | { | |
49d5741b JI |
2548 | struct uart_8250_port *up = |
2549 | container_of(port, struct uart_8250_port, port); | |
1da177e4 LT |
2550 | |
2551 | serial8250_release_std_resource(up); | |
dfe42443 | 2552 | if (port->type == PORT_RSA) |
1da177e4 LT |
2553 | serial8250_release_rsa_resource(up); |
2554 | } | |
2555 | ||
2556 | static int serial8250_request_port(struct uart_port *port) | |
2557 | { | |
49d5741b JI |
2558 | struct uart_8250_port *up = |
2559 | container_of(port, struct uart_8250_port, port); | |
1da177e4 LT |
2560 | int ret = 0; |
2561 | ||
2562 | ret = serial8250_request_std_resource(up); | |
dfe42443 | 2563 | if (ret == 0 && port->type == PORT_RSA) { |
1da177e4 LT |
2564 | ret = serial8250_request_rsa_resource(up); |
2565 | if (ret < 0) | |
2566 | serial8250_release_std_resource(up); | |
2567 | } | |
2568 | ||
2569 | return ret; | |
2570 | } | |
2571 | ||
2572 | static void serial8250_config_port(struct uart_port *port, int flags) | |
2573 | { | |
49d5741b JI |
2574 | struct uart_8250_port *up = |
2575 | container_of(port, struct uart_8250_port, port); | |
1da177e4 LT |
2576 | int probeflags = PROBE_ANY; |
2577 | int ret; | |
2578 | ||
1da177e4 LT |
2579 | /* |
2580 | * Find the region that we can probe for. This in turn | |
2581 | * tells us whether we can probe for the type of port. | |
2582 | */ | |
2583 | ret = serial8250_request_std_resource(up); | |
2584 | if (ret < 0) | |
2585 | return; | |
2586 | ||
2587 | ret = serial8250_request_rsa_resource(up); | |
2588 | if (ret < 0) | |
2589 | probeflags &= ~PROBE_RSA; | |
2590 | ||
dfe42443 | 2591 | if (port->iotype != up->cur_iotype) |
b8e7e40a AC |
2592 | set_io_from_upio(port); |
2593 | ||
1da177e4 LT |
2594 | if (flags & UART_CONFIG_TYPE) |
2595 | autoconfig(up, probeflags); | |
b2b13cdf | 2596 | |
b2b13cdf | 2597 | /* if access method is AU, it is a 16550 with a quirk */ |
dfe42443 | 2598 | if (port->type == PORT_16550A && port->iotype == UPIO_AU) |
b2b13cdf | 2599 | up->bugs |= UART_BUG_NOMSR; |
b2b13cdf | 2600 | |
dfe42443 | 2601 | if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) |
1da177e4 LT |
2602 | autoconfig_irq(up); |
2603 | ||
dfe42443 | 2604 | if (port->type != PORT_RSA && probeflags & PROBE_RSA) |
1da177e4 | 2605 | serial8250_release_rsa_resource(up); |
dfe42443 | 2606 | if (port->type == PORT_UNKNOWN) |
1da177e4 LT |
2607 | serial8250_release_std_resource(up); |
2608 | } | |
2609 | ||
2610 | static int | |
2611 | serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) | |
2612 | { | |
a62c4133 | 2613 | if (ser->irq >= nr_irqs || ser->irq < 0 || |
1da177e4 LT |
2614 | ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || |
2615 | ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || | |
2616 | ser->type == PORT_STARTECH) | |
2617 | return -EINVAL; | |
2618 | return 0; | |
2619 | } | |
2620 | ||
2621 | static const char * | |
2622 | serial8250_type(struct uart_port *port) | |
2623 | { | |
2624 | int type = port->type; | |
2625 | ||
2626 | if (type >= ARRAY_SIZE(uart_config)) | |
2627 | type = 0; | |
2628 | return uart_config[type].name; | |
2629 | } | |
2630 | ||
2631 | static struct uart_ops serial8250_pops = { | |
2632 | .tx_empty = serial8250_tx_empty, | |
2633 | .set_mctrl = serial8250_set_mctrl, | |
2634 | .get_mctrl = serial8250_get_mctrl, | |
2635 | .stop_tx = serial8250_stop_tx, | |
2636 | .start_tx = serial8250_start_tx, | |
2637 | .stop_rx = serial8250_stop_rx, | |
2638 | .enable_ms = serial8250_enable_ms, | |
2639 | .break_ctl = serial8250_break_ctl, | |
2640 | .startup = serial8250_startup, | |
2641 | .shutdown = serial8250_shutdown, | |
2642 | .set_termios = serial8250_set_termios, | |
dc77f161 | 2643 | .set_ldisc = serial8250_set_ldisc, |
1da177e4 LT |
2644 | .pm = serial8250_pm, |
2645 | .type = serial8250_type, | |
2646 | .release_port = serial8250_release_port, | |
2647 | .request_port = serial8250_request_port, | |
2648 | .config_port = serial8250_config_port, | |
2649 | .verify_port = serial8250_verify_port, | |
f2d937f3 JW |
2650 | #ifdef CONFIG_CONSOLE_POLL |
2651 | .poll_get_char = serial8250_get_poll_char, | |
2652 | .poll_put_char = serial8250_put_poll_char, | |
2653 | #endif | |
1da177e4 LT |
2654 | }; |
2655 | ||
2656 | static struct uart_8250_port serial8250_ports[UART_NR]; | |
2657 | ||
af7f3743 AC |
2658 | static void (*serial8250_isa_config)(int port, struct uart_port *up, |
2659 | unsigned short *capabilities); | |
2660 | ||
2661 | void serial8250_set_isa_configurator( | |
2662 | void (*v)(int port, struct uart_port *up, unsigned short *capabilities)) | |
2663 | { | |
2664 | serial8250_isa_config = v; | |
2665 | } | |
2666 | EXPORT_SYMBOL(serial8250_set_isa_configurator); | |
2667 | ||
1da177e4 LT |
2668 | static void __init serial8250_isa_init_ports(void) |
2669 | { | |
2670 | struct uart_8250_port *up; | |
2671 | static int first = 1; | |
4c0ebb80 | 2672 | int i, irqflag = 0; |
1da177e4 LT |
2673 | |
2674 | if (!first) | |
2675 | return; | |
2676 | first = 0; | |
2677 | ||
a61c2d78 | 2678 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 | 2679 | struct uart_8250_port *up = &serial8250_ports[i]; |
dfe42443 | 2680 | struct uart_port *port = &up->port; |
1da177e4 | 2681 | |
dfe42443 PG |
2682 | port->line = i; |
2683 | spin_lock_init(&port->lock); | |
1da177e4 LT |
2684 | |
2685 | init_timer(&up->timer); | |
2686 | up->timer.function = serial8250_timeout; | |
2687 | ||
2688 | /* | |
2689 | * ALPHA_KLUDGE_MCR needs to be killed. | |
2690 | */ | |
2691 | up->mcr_mask = ~ALPHA_KLUDGE_MCR; | |
2692 | up->mcr_force = ALPHA_KLUDGE_MCR; | |
2693 | ||
dfe42443 | 2694 | port->ops = &serial8250_pops; |
1da177e4 LT |
2695 | } |
2696 | ||
4c0ebb80 AGR |
2697 | if (share_irqs) |
2698 | irqflag = IRQF_SHARED; | |
2699 | ||
44454bcd | 2700 | for (i = 0, up = serial8250_ports; |
a61c2d78 | 2701 | i < ARRAY_SIZE(old_serial_port) && i < nr_uarts; |
1da177e4 | 2702 | i++, up++) { |
dfe42443 PG |
2703 | struct uart_port *port = &up->port; |
2704 | ||
2705 | port->iobase = old_serial_port[i].port; | |
2706 | port->irq = irq_canonicalize(old_serial_port[i].irq); | |
2707 | port->irqflags = old_serial_port[i].irqflags; | |
2708 | port->uartclk = old_serial_port[i].baud_base * 16; | |
2709 | port->flags = old_serial_port[i].flags; | |
2710 | port->hub6 = old_serial_port[i].hub6; | |
2711 | port->membase = old_serial_port[i].iomem_base; | |
2712 | port->iotype = old_serial_port[i].io_type; | |
2713 | port->regshift = old_serial_port[i].iomem_reg_shift; | |
2714 | set_io_from_upio(port); | |
2715 | port->irqflags |= irqflag; | |
af7f3743 AC |
2716 | if (serial8250_isa_config != NULL) |
2717 | serial8250_isa_config(i, &up->port, &up->capabilities); | |
2718 | ||
1da177e4 LT |
2719 | } |
2720 | } | |
2721 | ||
b5d228cc SL |
2722 | static void |
2723 | serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type) | |
2724 | { | |
2725 | up->port.type = type; | |
2726 | up->port.fifosize = uart_config[type].fifo_size; | |
2727 | up->capabilities = uart_config[type].flags; | |
2728 | up->tx_loadsz = uart_config[type].tx_loadsz; | |
2729 | } | |
2730 | ||
1da177e4 LT |
2731 | static void __init |
2732 | serial8250_register_ports(struct uart_driver *drv, struct device *dev) | |
2733 | { | |
2734 | int i; | |
2735 | ||
b8e7e40a AC |
2736 | for (i = 0; i < nr_uarts; i++) { |
2737 | struct uart_8250_port *up = &serial8250_ports[i]; | |
2738 | up->cur_iotype = 0xFF; | |
2739 | } | |
2740 | ||
1da177e4 LT |
2741 | serial8250_isa_init_ports(); |
2742 | ||
a61c2d78 | 2743 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
2744 | struct uart_8250_port *up = &serial8250_ports[i]; |
2745 | ||
2746 | up->port.dev = dev; | |
b5d228cc SL |
2747 | |
2748 | if (up->port.flags & UPF_FIXED_TYPE) | |
2749 | serial8250_init_fixed_type_port(up, up->port.type); | |
2750 | ||
1da177e4 LT |
2751 | uart_add_one_port(drv, &up->port); |
2752 | } | |
2753 | } | |
2754 | ||
2755 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
2756 | ||
d358788f RK |
2757 | static void serial8250_console_putchar(struct uart_port *port, int ch) |
2758 | { | |
49d5741b JI |
2759 | struct uart_8250_port *up = |
2760 | container_of(port, struct uart_8250_port, port); | |
d358788f RK |
2761 | |
2762 | wait_for_xmitr(up, UART_LSR_THRE); | |
4fd996a1 | 2763 | serial_port_out(port, UART_TX, ch); |
d358788f RK |
2764 | } |
2765 | ||
1da177e4 LT |
2766 | /* |
2767 | * Print a string to the serial port trying not to disturb | |
2768 | * any possible real use of the port... | |
2769 | * | |
2770 | * The console_lock must be held when we get here. | |
2771 | */ | |
2772 | static void | |
2773 | serial8250_console_write(struct console *co, const char *s, unsigned int count) | |
2774 | { | |
2775 | struct uart_8250_port *up = &serial8250_ports[co->index]; | |
dfe42443 | 2776 | struct uart_port *port = &up->port; |
d8a5a8d7 | 2777 | unsigned long flags; |
1da177e4 | 2778 | unsigned int ier; |
d8a5a8d7 | 2779 | int locked = 1; |
1da177e4 | 2780 | |
78512ece AM |
2781 | touch_nmi_watchdog(); |
2782 | ||
68aa2c0d | 2783 | local_irq_save(flags); |
dfe42443 | 2784 | if (port->sysrq) { |
86b21199 | 2785 | /* serial8250_handle_irq() already took the lock */ |
68aa2c0d AM |
2786 | locked = 0; |
2787 | } else if (oops_in_progress) { | |
dfe42443 | 2788 | locked = spin_trylock(&port->lock); |
d8a5a8d7 | 2789 | } else |
dfe42443 | 2790 | spin_lock(&port->lock); |
d8a5a8d7 | 2791 | |
1da177e4 | 2792 | /* |
dc7bf130 | 2793 | * First save the IER then disable the interrupts |
1da177e4 | 2794 | */ |
4fd996a1 | 2795 | ier = serial_port_in(port, UART_IER); |
1da177e4 LT |
2796 | |
2797 | if (up->capabilities & UART_CAP_UUE) | |
4fd996a1 | 2798 | serial_port_out(port, UART_IER, UART_IER_UUE); |
1da177e4 | 2799 | else |
4fd996a1 | 2800 | serial_port_out(port, UART_IER, 0); |
1da177e4 | 2801 | |
dfe42443 | 2802 | uart_console_write(port, s, count, serial8250_console_putchar); |
1da177e4 LT |
2803 | |
2804 | /* | |
2805 | * Finally, wait for transmitter to become empty | |
2806 | * and restore the IER | |
2807 | */ | |
f91a3715 | 2808 | wait_for_xmitr(up, BOTH_EMPTY); |
4fd996a1 | 2809 | serial_port_out(port, UART_IER, ier); |
d8a5a8d7 | 2810 | |
ad4c2aa6 CM |
2811 | /* |
2812 | * The receive handling will happen properly because the | |
2813 | * receive ready bit will still be set; it is not cleared | |
2814 | * on read. However, modem control will not, we must | |
2815 | * call it if we have saved something in the saved flags | |
2816 | * while processing with interrupts off. | |
2817 | */ | |
2818 | if (up->msr_saved_flags) | |
3986fb2b | 2819 | serial8250_modem_status(up); |
ad4c2aa6 | 2820 | |
d8a5a8d7 | 2821 | if (locked) |
dfe42443 | 2822 | spin_unlock(&port->lock); |
68aa2c0d | 2823 | local_irq_restore(flags); |
1da177e4 LT |
2824 | } |
2825 | ||
118c0ace | 2826 | static int __init serial8250_console_setup(struct console *co, char *options) |
1da177e4 LT |
2827 | { |
2828 | struct uart_port *port; | |
2829 | int baud = 9600; | |
2830 | int bits = 8; | |
2831 | int parity = 'n'; | |
2832 | int flow = 'n'; | |
2833 | ||
2834 | /* | |
2835 | * Check whether an invalid uart number has been specified, and | |
2836 | * if so, search for the first available port that does have | |
2837 | * console support. | |
2838 | */ | |
a61c2d78 | 2839 | if (co->index >= nr_uarts) |
1da177e4 LT |
2840 | co->index = 0; |
2841 | port = &serial8250_ports[co->index].port; | |
2842 | if (!port->iobase && !port->membase) | |
2843 | return -ENODEV; | |
2844 | ||
2845 | if (options) | |
2846 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2847 | ||
2848 | return uart_set_options(port, co, baud, parity, bits, flow); | |
2849 | } | |
2850 | ||
b6b1d877 | 2851 | static int serial8250_console_early_setup(void) |
18a8bd94 YL |
2852 | { |
2853 | return serial8250_find_port_for_earlycon(); | |
2854 | } | |
2855 | ||
1da177e4 LT |
2856 | static struct console serial8250_console = { |
2857 | .name = "ttyS", | |
2858 | .write = serial8250_console_write, | |
2859 | .device = uart_console_device, | |
2860 | .setup = serial8250_console_setup, | |
18a8bd94 | 2861 | .early_setup = serial8250_console_early_setup, |
a80c49db | 2862 | .flags = CON_PRINTBUFFER | CON_ANYTIME, |
1da177e4 LT |
2863 | .index = -1, |
2864 | .data = &serial8250_reg, | |
2865 | }; | |
2866 | ||
2867 | static int __init serial8250_console_init(void) | |
2868 | { | |
05d81d22 EB |
2869 | if (nr_uarts > UART_NR) |
2870 | nr_uarts = UART_NR; | |
2871 | ||
1da177e4 LT |
2872 | serial8250_isa_init_ports(); |
2873 | register_console(&serial8250_console); | |
2874 | return 0; | |
2875 | } | |
2876 | console_initcall(serial8250_console_init); | |
2877 | ||
18a8bd94 | 2878 | int serial8250_find_port(struct uart_port *p) |
1da177e4 LT |
2879 | { |
2880 | int line; | |
2881 | struct uart_port *port; | |
2882 | ||
a61c2d78 | 2883 | for (line = 0; line < nr_uarts; line++) { |
1da177e4 | 2884 | port = &serial8250_ports[line].port; |
50aec3b5 | 2885 | if (uart_match_port(p, port)) |
1da177e4 LT |
2886 | return line; |
2887 | } | |
2888 | return -ENODEV; | |
2889 | } | |
2890 | ||
1da177e4 LT |
2891 | #define SERIAL8250_CONSOLE &serial8250_console |
2892 | #else | |
2893 | #define SERIAL8250_CONSOLE NULL | |
2894 | #endif | |
2895 | ||
2896 | static struct uart_driver serial8250_reg = { | |
2897 | .owner = THIS_MODULE, | |
2898 | .driver_name = "serial", | |
1da177e4 LT |
2899 | .dev_name = "ttyS", |
2900 | .major = TTY_MAJOR, | |
2901 | .minor = 64, | |
1da177e4 LT |
2902 | .cons = SERIAL8250_CONSOLE, |
2903 | }; | |
2904 | ||
d856c666 RK |
2905 | /* |
2906 | * early_serial_setup - early registration for 8250 ports | |
2907 | * | |
2908 | * Setup an 8250 port structure prior to console initialisation. Use | |
2909 | * after console initialisation will cause undefined behaviour. | |
2910 | */ | |
1da177e4 LT |
2911 | int __init early_serial_setup(struct uart_port *port) |
2912 | { | |
b430428a DD |
2913 | struct uart_port *p; |
2914 | ||
1da177e4 LT |
2915 | if (port->line >= ARRAY_SIZE(serial8250_ports)) |
2916 | return -ENODEV; | |
2917 | ||
2918 | serial8250_isa_init_ports(); | |
b430428a DD |
2919 | p = &serial8250_ports[port->line].port; |
2920 | p->iobase = port->iobase; | |
2921 | p->membase = port->membase; | |
2922 | p->irq = port->irq; | |
1c2f0493 | 2923 | p->irqflags = port->irqflags; |
b430428a DD |
2924 | p->uartclk = port->uartclk; |
2925 | p->fifosize = port->fifosize; | |
2926 | p->regshift = port->regshift; | |
2927 | p->iotype = port->iotype; | |
2928 | p->flags = port->flags; | |
2929 | p->mapbase = port->mapbase; | |
2930 | p->private_data = port->private_data; | |
125c97d8 HD |
2931 | p->type = port->type; |
2932 | p->line = port->line; | |
7d6a07d1 DD |
2933 | |
2934 | set_io_from_upio(p); | |
2935 | if (port->serial_in) | |
2936 | p->serial_in = port->serial_in; | |
2937 | if (port->serial_out) | |
2938 | p->serial_out = port->serial_out; | |
583d28e9 JI |
2939 | if (port->handle_irq) |
2940 | p->handle_irq = port->handle_irq; | |
2941 | else | |
2942 | p->handle_irq = serial8250_default_handle_irq; | |
7d6a07d1 | 2943 | |
1da177e4 LT |
2944 | return 0; |
2945 | } | |
2946 | ||
2947 | /** | |
2948 | * serial8250_suspend_port - suspend one serial port | |
2949 | * @line: serial line number | |
1da177e4 LT |
2950 | * |
2951 | * Suspend one serial port. | |
2952 | */ | |
2953 | void serial8250_suspend_port(int line) | |
2954 | { | |
2955 | uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port); | |
2956 | } | |
2957 | ||
2958 | /** | |
2959 | * serial8250_resume_port - resume one serial port | |
2960 | * @line: serial line number | |
1da177e4 LT |
2961 | * |
2962 | * Resume one serial port. | |
2963 | */ | |
2964 | void serial8250_resume_port(int line) | |
2965 | { | |
b5b82df6 | 2966 | struct uart_8250_port *up = &serial8250_ports[line]; |
dfe42443 | 2967 | struct uart_port *port = &up->port; |
b5b82df6 DW |
2968 | |
2969 | if (up->capabilities & UART_NATSEMI) { | |
b5b82df6 | 2970 | /* Ensure it's still in high speed mode */ |
4fd996a1 | 2971 | serial_port_out(port, UART_LCR, 0xE0); |
b5b82df6 | 2972 | |
0d0389e5 | 2973 | ns16550a_goto_highspeed(up); |
b5b82df6 | 2974 | |
4fd996a1 | 2975 | serial_port_out(port, UART_LCR, 0); |
dfe42443 | 2976 | port->uartclk = 921600*16; |
b5b82df6 | 2977 | } |
dfe42443 | 2978 | uart_resume_port(&serial8250_reg, port); |
1da177e4 LT |
2979 | } |
2980 | ||
2981 | /* | |
2982 | * Register a set of serial devices attached to a platform device. The | |
2983 | * list is terminated with a zero flags entry, which means we expect | |
2984 | * all entries to have at least UPF_BOOT_AUTOCONF set. | |
2985 | */ | |
3ae5eaec | 2986 | static int __devinit serial8250_probe(struct platform_device *dev) |
1da177e4 | 2987 | { |
3ae5eaec | 2988 | struct plat_serial8250_port *p = dev->dev.platform_data; |
2655a2c7 | 2989 | struct uart_8250_port uart; |
4c0ebb80 | 2990 | int ret, i, irqflag = 0; |
1da177e4 | 2991 | |
2655a2c7 | 2992 | memset(&uart, 0, sizeof(uart)); |
1da177e4 | 2993 | |
4c0ebb80 AGR |
2994 | if (share_irqs) |
2995 | irqflag = IRQF_SHARED; | |
2996 | ||
ec9f47cd | 2997 | for (i = 0; p && p->flags != 0; p++, i++) { |
2655a2c7 AC |
2998 | uart.port.iobase = p->iobase; |
2999 | uart.port.membase = p->membase; | |
3000 | uart.port.irq = p->irq; | |
3001 | uart.port.irqflags = p->irqflags; | |
3002 | uart.port.uartclk = p->uartclk; | |
3003 | uart.port.regshift = p->regshift; | |
3004 | uart.port.iotype = p->iotype; | |
3005 | uart.port.flags = p->flags; | |
3006 | uart.port.mapbase = p->mapbase; | |
3007 | uart.port.hub6 = p->hub6; | |
3008 | uart.port.private_data = p->private_data; | |
3009 | uart.port.type = p->type; | |
3010 | uart.port.serial_in = p->serial_in; | |
3011 | uart.port.serial_out = p->serial_out; | |
3012 | uart.port.handle_irq = p->handle_irq; | |
3013 | uart.port.handle_break = p->handle_break; | |
3014 | uart.port.set_termios = p->set_termios; | |
3015 | uart.port.pm = p->pm; | |
3016 | uart.port.dev = &dev->dev; | |
3017 | uart.port.irqflags |= irqflag; | |
3018 | ret = serial8250_register_8250_port(&uart); | |
ec9f47cd | 3019 | if (ret < 0) { |
3ae5eaec | 3020 | dev_err(&dev->dev, "unable to register port at index %d " |
4f640efb JB |
3021 | "(IO%lx MEM%llx IRQ%d): %d\n", i, |
3022 | p->iobase, (unsigned long long)p->mapbase, | |
3023 | p->irq, ret); | |
ec9f47cd | 3024 | } |
1da177e4 LT |
3025 | } |
3026 | return 0; | |
3027 | } | |
3028 | ||
3029 | /* | |
3030 | * Remove serial ports registered against a platform device. | |
3031 | */ | |
3ae5eaec | 3032 | static int __devexit serial8250_remove(struct platform_device *dev) |
1da177e4 LT |
3033 | { |
3034 | int i; | |
3035 | ||
a61c2d78 | 3036 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
3037 | struct uart_8250_port *up = &serial8250_ports[i]; |
3038 | ||
3ae5eaec | 3039 | if (up->port.dev == &dev->dev) |
1da177e4 LT |
3040 | serial8250_unregister_port(i); |
3041 | } | |
3042 | return 0; | |
3043 | } | |
3044 | ||
3ae5eaec | 3045 | static int serial8250_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 LT |
3046 | { |
3047 | int i; | |
3048 | ||
1da177e4 LT |
3049 | for (i = 0; i < UART_NR; i++) { |
3050 | struct uart_8250_port *up = &serial8250_ports[i]; | |
3051 | ||
3ae5eaec | 3052 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
1da177e4 LT |
3053 | uart_suspend_port(&serial8250_reg, &up->port); |
3054 | } | |
3055 | ||
3056 | return 0; | |
3057 | } | |
3058 | ||
3ae5eaec | 3059 | static int serial8250_resume(struct platform_device *dev) |
1da177e4 LT |
3060 | { |
3061 | int i; | |
3062 | ||
1da177e4 LT |
3063 | for (i = 0; i < UART_NR; i++) { |
3064 | struct uart_8250_port *up = &serial8250_ports[i]; | |
3065 | ||
3ae5eaec | 3066 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
b5b82df6 | 3067 | serial8250_resume_port(i); |
1da177e4 LT |
3068 | } |
3069 | ||
3070 | return 0; | |
3071 | } | |
3072 | ||
3ae5eaec | 3073 | static struct platform_driver serial8250_isa_driver = { |
1da177e4 LT |
3074 | .probe = serial8250_probe, |
3075 | .remove = __devexit_p(serial8250_remove), | |
3076 | .suspend = serial8250_suspend, | |
3077 | .resume = serial8250_resume, | |
3ae5eaec RK |
3078 | .driver = { |
3079 | .name = "serial8250", | |
7493a314 | 3080 | .owner = THIS_MODULE, |
3ae5eaec | 3081 | }, |
1da177e4 LT |
3082 | }; |
3083 | ||
3084 | /* | |
3085 | * This "device" covers _all_ ISA 8250-compatible serial devices listed | |
3086 | * in the table in include/asm/serial.h | |
3087 | */ | |
3088 | static struct platform_device *serial8250_isa_devs; | |
3089 | ||
3090 | /* | |
2655a2c7 | 3091 | * serial8250_register_8250_port and serial8250_unregister_port allows for |
1da177e4 LT |
3092 | * 16x50 serial ports to be configured at run-time, to support PCMCIA |
3093 | * modems and PCI multiport cards. | |
3094 | */ | |
f392ecfa | 3095 | static DEFINE_MUTEX(serial_mutex); |
1da177e4 LT |
3096 | |
3097 | static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) | |
3098 | { | |
3099 | int i; | |
3100 | ||
3101 | /* | |
3102 | * First, find a port entry which matches. | |
3103 | */ | |
a61c2d78 | 3104 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
3105 | if (uart_match_port(&serial8250_ports[i].port, port)) |
3106 | return &serial8250_ports[i]; | |
3107 | ||
3108 | /* | |
3109 | * We didn't find a matching entry, so look for the first | |
3110 | * free entry. We look for one which hasn't been previously | |
3111 | * used (indicated by zero iobase). | |
3112 | */ | |
a61c2d78 | 3113 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
3114 | if (serial8250_ports[i].port.type == PORT_UNKNOWN && |
3115 | serial8250_ports[i].port.iobase == 0) | |
3116 | return &serial8250_ports[i]; | |
3117 | ||
3118 | /* | |
3119 | * That also failed. Last resort is to find any entry which | |
3120 | * doesn't have a real port associated with it. | |
3121 | */ | |
a61c2d78 | 3122 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
3123 | if (serial8250_ports[i].port.type == PORT_UNKNOWN) |
3124 | return &serial8250_ports[i]; | |
3125 | ||
3126 | return NULL; | |
3127 | } | |
3128 | ||
3129 | /** | |
f73fa05b | 3130 | * serial8250_register_8250_port - register a serial port |
58bcd332 | 3131 | * @up: serial port template |
1da177e4 LT |
3132 | * |
3133 | * Configure the serial port specified by the request. If the | |
3134 | * port exists and is in use, it is hung up and unregistered | |
3135 | * first. | |
3136 | * | |
3137 | * The port is then probed and if necessary the IRQ is autodetected | |
3138 | * If this fails an error is returned. | |
3139 | * | |
3140 | * On success the port is ready to use and the line number is returned. | |
3141 | */ | |
f73fa05b | 3142 | int serial8250_register_8250_port(struct uart_8250_port *up) |
1da177e4 LT |
3143 | { |
3144 | struct uart_8250_port *uart; | |
3145 | int ret = -ENOSPC; | |
3146 | ||
f73fa05b | 3147 | if (up->port.uartclk == 0) |
1da177e4 LT |
3148 | return -EINVAL; |
3149 | ||
f392ecfa | 3150 | mutex_lock(&serial_mutex); |
1da177e4 | 3151 | |
f73fa05b | 3152 | uart = serial8250_find_match_or_unused(&up->port); |
1da177e4 LT |
3153 | if (uart) { |
3154 | uart_remove_one_port(&serial8250_reg, &uart->port); | |
3155 | ||
f73fa05b MD |
3156 | uart->port.iobase = up->port.iobase; |
3157 | uart->port.membase = up->port.membase; | |
3158 | uart->port.irq = up->port.irq; | |
3159 | uart->port.irqflags = up->port.irqflags; | |
3160 | uart->port.uartclk = up->port.uartclk; | |
3161 | uart->port.fifosize = up->port.fifosize; | |
3162 | uart->port.regshift = up->port.regshift; | |
3163 | uart->port.iotype = up->port.iotype; | |
3164 | uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF; | |
a2d33d87 | 3165 | uart->bugs = up->bugs; |
f73fa05b MD |
3166 | uart->port.mapbase = up->port.mapbase; |
3167 | uart->port.private_data = up->port.private_data; | |
3168 | if (up->port.dev) | |
3169 | uart->port.dev = up->port.dev; | |
3170 | ||
3171 | if (up->port.flags & UPF_FIXED_TYPE) | |
3172 | serial8250_init_fixed_type_port(uart, up->port.type); | |
8e23fcc8 | 3173 | |
7d6a07d1 DD |
3174 | set_io_from_upio(&uart->port); |
3175 | /* Possibly override default I/O functions. */ | |
f73fa05b MD |
3176 | if (up->port.serial_in) |
3177 | uart->port.serial_in = up->port.serial_in; | |
3178 | if (up->port.serial_out) | |
3179 | uart->port.serial_out = up->port.serial_out; | |
3180 | if (up->port.handle_irq) | |
3181 | uart->port.handle_irq = up->port.handle_irq; | |
235dae5d | 3182 | /* Possibly override set_termios call */ |
f73fa05b MD |
3183 | if (up->port.set_termios) |
3184 | uart->port.set_termios = up->port.set_termios; | |
3185 | if (up->port.pm) | |
3186 | uart->port.pm = up->port.pm; | |
3187 | if (up->port.handle_break) | |
3188 | uart->port.handle_break = up->port.handle_break; | |
3189 | if (up->dl_read) | |
3190 | uart->dl_read = up->dl_read; | |
3191 | if (up->dl_write) | |
3192 | uart->dl_write = up->dl_write; | |
1da177e4 | 3193 | |
af7f3743 AC |
3194 | if (serial8250_isa_config != NULL) |
3195 | serial8250_isa_config(0, &uart->port, | |
3196 | &uart->capabilities); | |
3197 | ||
1da177e4 LT |
3198 | ret = uart_add_one_port(&serial8250_reg, &uart->port); |
3199 | if (ret == 0) | |
3200 | ret = uart->port.line; | |
3201 | } | |
f392ecfa | 3202 | mutex_unlock(&serial_mutex); |
1da177e4 LT |
3203 | |
3204 | return ret; | |
3205 | } | |
f73fa05b MD |
3206 | EXPORT_SYMBOL(serial8250_register_8250_port); |
3207 | ||
1da177e4 LT |
3208 | /** |
3209 | * serial8250_unregister_port - remove a 16x50 serial port at runtime | |
3210 | * @line: serial line number | |
3211 | * | |
3212 | * Remove one serial port. This may not be called from interrupt | |
3213 | * context. We hand the port back to the our control. | |
3214 | */ | |
3215 | void serial8250_unregister_port(int line) | |
3216 | { | |
3217 | struct uart_8250_port *uart = &serial8250_ports[line]; | |
3218 | ||
f392ecfa | 3219 | mutex_lock(&serial_mutex); |
1da177e4 LT |
3220 | uart_remove_one_port(&serial8250_reg, &uart->port); |
3221 | if (serial8250_isa_devs) { | |
3222 | uart->port.flags &= ~UPF_BOOT_AUTOCONF; | |
3223 | uart->port.type = PORT_UNKNOWN; | |
3224 | uart->port.dev = &serial8250_isa_devs->dev; | |
cb01ece3 | 3225 | uart->capabilities = uart_config[uart->port.type].flags; |
1da177e4 LT |
3226 | uart_add_one_port(&serial8250_reg, &uart->port); |
3227 | } else { | |
3228 | uart->port.dev = NULL; | |
3229 | } | |
f392ecfa | 3230 | mutex_unlock(&serial_mutex); |
1da177e4 LT |
3231 | } |
3232 | EXPORT_SYMBOL(serial8250_unregister_port); | |
3233 | ||
3234 | static int __init serial8250_init(void) | |
3235 | { | |
25db8ad5 | 3236 | int ret; |
1da177e4 | 3237 | |
a61c2d78 DJ |
3238 | if (nr_uarts > UART_NR) |
3239 | nr_uarts = UART_NR; | |
3240 | ||
f1fb9bb8 | 3241 | printk(KERN_INFO "Serial: 8250/16550 driver, " |
a61c2d78 | 3242 | "%d ports, IRQ sharing %sabled\n", nr_uarts, |
1da177e4 LT |
3243 | share_irqs ? "en" : "dis"); |
3244 | ||
b70ac771 DM |
3245 | #ifdef CONFIG_SPARC |
3246 | ret = sunserial_register_minors(&serial8250_reg, UART_NR); | |
3247 | #else | |
3248 | serial8250_reg.nr = UART_NR; | |
1da177e4 | 3249 | ret = uart_register_driver(&serial8250_reg); |
b70ac771 | 3250 | #endif |
1da177e4 LT |
3251 | if (ret) |
3252 | goto out; | |
3253 | ||
7493a314 DT |
3254 | serial8250_isa_devs = platform_device_alloc("serial8250", |
3255 | PLAT8250_DEV_LEGACY); | |
3256 | if (!serial8250_isa_devs) { | |
3257 | ret = -ENOMEM; | |
bc965a7f | 3258 | goto unreg_uart_drv; |
1da177e4 LT |
3259 | } |
3260 | ||
7493a314 DT |
3261 | ret = platform_device_add(serial8250_isa_devs); |
3262 | if (ret) | |
3263 | goto put_dev; | |
3264 | ||
1da177e4 LT |
3265 | serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); |
3266 | ||
bc965a7f RK |
3267 | ret = platform_driver_register(&serial8250_isa_driver); |
3268 | if (ret == 0) | |
3269 | goto out; | |
1da177e4 | 3270 | |
bc965a7f | 3271 | platform_device_del(serial8250_isa_devs); |
25db8ad5 | 3272 | put_dev: |
7493a314 | 3273 | platform_device_put(serial8250_isa_devs); |
25db8ad5 | 3274 | unreg_uart_drv: |
b70ac771 DM |
3275 | #ifdef CONFIG_SPARC |
3276 | sunserial_unregister_minors(&serial8250_reg, UART_NR); | |
3277 | #else | |
1da177e4 | 3278 | uart_unregister_driver(&serial8250_reg); |
b70ac771 | 3279 | #endif |
25db8ad5 | 3280 | out: |
1da177e4 LT |
3281 | return ret; |
3282 | } | |
3283 | ||
3284 | static void __exit serial8250_exit(void) | |
3285 | { | |
3286 | struct platform_device *isa_dev = serial8250_isa_devs; | |
3287 | ||
3288 | /* | |
3289 | * This tells serial8250_unregister_port() not to re-register | |
3290 | * the ports (thereby making serial8250_isa_driver permanently | |
3291 | * in use.) | |
3292 | */ | |
3293 | serial8250_isa_devs = NULL; | |
3294 | ||
3ae5eaec | 3295 | platform_driver_unregister(&serial8250_isa_driver); |
1da177e4 LT |
3296 | platform_device_unregister(isa_dev); |
3297 | ||
b70ac771 DM |
3298 | #ifdef CONFIG_SPARC |
3299 | sunserial_unregister_minors(&serial8250_reg, UART_NR); | |
3300 | #else | |
1da177e4 | 3301 | uart_unregister_driver(&serial8250_reg); |
b70ac771 | 3302 | #endif |
1da177e4 LT |
3303 | } |
3304 | ||
3305 | module_init(serial8250_init); | |
3306 | module_exit(serial8250_exit); | |
3307 | ||
3308 | EXPORT_SYMBOL(serial8250_suspend_port); | |
3309 | EXPORT_SYMBOL(serial8250_resume_port); | |
3310 | ||
3311 | MODULE_LICENSE("GPL"); | |
d87a6d95 | 3312 | MODULE_DESCRIPTION("Generic 8250/16x50 serial driver"); |
1da177e4 LT |
3313 | |
3314 | module_param(share_irqs, uint, 0644); | |
3315 | MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" | |
3316 | " (unsafe)"); | |
3317 | ||
a61c2d78 DJ |
3318 | module_param(nr_uarts, uint, 0644); |
3319 | MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); | |
3320 | ||
d41a4b51 CE |
3321 | module_param(skip_txen_test, uint, 0644); |
3322 | MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time"); | |
3323 | ||
1da177e4 LT |
3324 | #ifdef CONFIG_SERIAL_8250_RSA |
3325 | module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); | |
3326 | MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); | |
3327 | #endif | |
3328 | MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); |