projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
serial8250: Use dl_read()/dl_write() on RM9K
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / 8250 / 8250.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
6816383a
PG		 41#ifdef CONFIG_SPARC
42#include <linux/sunserialcore.h>
43#endif
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
40663cc7 52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 56
a61c2d78
DJ		 57static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
8440838b
DM		 59static struct uart_driver serial8250_reg;
60
61static int serial_index(struct uart_port *port)
62{
63 return (serial8250_reg.minor - 64) + port->line;
64}
65
d41a4b51
CE		 66static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
1da177e4
LT		 68/*
69 * Debugging.
70 */
71#if 0
72#define DEBUG_AUTOCONF(fmt...) printk(fmt)
73#else
74#define DEBUG_AUTOCONF(fmt...) do { } while (0)
75#endif
76
77#if 0
78#define DEBUG_INTR(fmt...) printk(fmt)
79#else
80#define DEBUG_INTR(fmt...) do { } while (0)
81#endif
82
e7328ae1 83#define PASS_LIMIT 512
1da177e4 84
bca47613
DH		 85#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
1da177e4
LT		 88#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89#define CONFIG_SERIAL_DETECT_IRQ 1
90#endif
1da177e4
LT		 91#ifdef CONFIG_SERIAL_8250_MANY_PORTS
92#define CONFIG_SERIAL_MANY_PORTS 1
93#endif
94
95/*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99#define CONFIG_HUB6 1
100
a4ed1e41 101#include <asm/serial.h>
1da177e4
LT		 102/*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107#ifndef SERIAL_PORT_DFNS
108#define SERIAL_PORT_DFNS
109#endif
110
cb3592be 111static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113};
114
026d02a2 115#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 116
117#ifdef CONFIG_SERIAL_8250_RSA
118
119#define PORT_RSA_MAX 4
120static unsigned long probe_rsa[PORT_RSA_MAX];
121static unsigned int probe_rsa_count;
122#endif /* CONFIG_SERIAL_8250_RSA */
123
1da177e4 124struct irq_info {
25db8ad5
AC		 125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 128 struct list_head *head;
129};
130
25db8ad5
AC		 131#define NR_IRQ_HASH 32 /* Can be adjusted later */
132static struct hlist_head irq_lists[NR_IRQ_HASH];
133static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 134
135/*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 241 },
bd71c182
TK		 242 [PORT_RM9000] = {
243 .name = "RM9000",
244 .fifo_size = 16,
245 .tx_loadsz = 16,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 247 .flags = UART_CAP_FIFO,
248 },
249 [PORT_OCTEON] = {
250 .name = "OCTEON",
251 .fifo_size = 64,
252 .tx_loadsz = 64,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 254 .flags = UART_CAP_FIFO,
255 },
08e0992f
FF		 256 [PORT_AR7] = {
257 .name = "AR7",
258 .fifo_size = 16,
259 .tx_loadsz = 16,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
235dae5d
PL		 263 [PORT_U6_16550A] = {
264 .name = "U6_16550A",
265 .fifo_size = 64,
266 .tx_loadsz = 64,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
269 },
4539c24f
SW		 270 [PORT_TEGRA] = {
271 .name = "Tegra",
272 .fifo_size = 32,
273 .tx_loadsz = 8,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
275 UART_FCR_T_TRIG_01,
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
277 },
06315348
SH		 278 [PORT_XR17D15X] = {
279 .name = "XR17D15X",
280 .fifo_size = 64,
281 .tx_loadsz = 64,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
284 },
1da177e4
LT		 285};
286
cc419fa0
MD		 287/* Uart divisor latch read */
288static int default_dl_read(struct uart_8250_port *up)
289{
290 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
291}
292
293/* Uart divisor latch write */
294static void default_dl_write(struct uart_8250_port *up, int value)
295{
296 serial_out(up, UART_DLL, value & 0xff);
297 serial_out(up, UART_DLM, value >> 8 & 0xff);
298}
299
cc419fa0
MD		 300static int _serial_dl_read(struct uart_8250_port *up)
301{
302 return default_dl_read(up);
303}
304
305static void _serial_dl_write(struct uart_8250_port *up, int value)
306{
307 default_dl_write(up, value);
308}
cc419fa0 309
6b416031 310#ifdef CONFIG_MIPS_ALCHEMY
21c614a7
PA		 311
312/* Au1x00 UART hardware has a weird register layout */
313static const u8 au_io_in_map[] = {
314 [UART_RX] = 0,
315 [UART_IER] = 2,
316 [UART_IIR] = 3,
317 [UART_LCR] = 5,
318 [UART_MCR] = 6,
319 [UART_LSR] = 7,
320 [UART_MSR] = 8,
321};
322
323static const u8 au_io_out_map[] = {
324 [UART_TX] = 1,
325 [UART_IER] = 2,
326 [UART_FCR] = 4,
327 [UART_LCR] = 5,
328 [UART_MCR] = 6,
329};
330
6b416031 331static unsigned int au_serial_in(struct uart_port *p, int offset)
21c614a7 332{
6b416031
MD		 333 offset = au_io_in_map[offset] << p->regshift;
334 return __raw_readl(p->membase + offset);
21c614a7
PA		 335}
336
6b416031 337static void au_serial_out(struct uart_port *p, int offset, int value)
21c614a7 338{
6b416031
MD		 339 offset = au_io_out_map[offset] << p->regshift;
340 __raw_writel(value, p->membase + offset);
341}
342
343/* Au1x00 haven't got a standard divisor latch */
344static int au_serial_dl_read(struct uart_8250_port *up)
345{
346 return __raw_readl(up->port.membase + 0x28);
347}
348
349static void au_serial_dl_write(struct uart_8250_port *up, int value)
350{
351 __raw_writel(value, up->port.membase + 0x28);
21c614a7
PA		 352}
353
6b416031
MD		 354#endif
355
28bf4cf2 356#ifdef CONFIG_SERIAL_8250_RM9K
bd71c182
TK		 357
358static const u8
359 regmap_in[8] = {
360 [UART_RX] = 0x00,
361 [UART_IER] = 0x0c,
362 [UART_IIR] = 0x14,
363 [UART_LCR] = 0x1c,
364 [UART_MCR] = 0x20,
365 [UART_LSR] = 0x24,
366 [UART_MSR] = 0x28,
367 [UART_SCR] = 0x2c
368 },
369 regmap_out[8] = {
370 [UART_TX] = 0x04,
371 [UART_IER] = 0x0c,
372 [UART_FCR] = 0x18,
373 [UART_LCR] = 0x1c,
374 [UART_MCR] = 0x20,
375 [UART_LSR] = 0x24,
376 [UART_MSR] = 0x28,
377 [UART_SCR] = 0x2c
378 };
379
28bf4cf2 380static unsigned int rm9k_serial_in(struct uart_port *p, int offset)
bd71c182 381{
28bf4cf2
MD		 382 offset = regmap_in[offset] << p->regshift;
383 return readl(p->membase + offset);
bd71c182
TK		 384}
385
28bf4cf2 386static void rm9k_serial_out(struct uart_port *p, int offset, int value)
bd71c182 387{
28bf4cf2
MD		 388 offset = regmap_out[offset] << p->regshift;
389 writel(value, p->membase + offset);
bd71c182
TK		 390}
391
28bf4cf2
MD		 392static int rm9k_serial_dl_read(struct uart_8250_port *up)
393{
394 return ((__raw_readl(up->port.membase + 0x10) << 8) |
395 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff;
396}
397
398static void rm9k_serial_dl_write(struct uart_8250_port *up, int value)
399{
400 __raw_writel(value, up->port.membase + 0x08);
401 __raw_writel(value >> 8, up->port.membase + 0x10);
402}
403
404#endif
21c614a7
PA		 405
406/* sane hardware needs no mapping */
407#define map_8250_in_reg(up, offset) (offset)
408#define map_8250_out_reg(up, offset) (offset)
409
7d6a07d1 410static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 411{
7d6a07d1
DD		 412 offset = map_8250_in_reg(p, offset) << p->regshift;
413 outb(p->hub6 - 1 + offset, p->iobase);
414 return inb(p->iobase + 1);
415}
1da177e4 416
7d6a07d1
DD		 417static void hub6_serial_out(struct uart_port *p, int offset, int value)
418{
419 offset = map_8250_out_reg(p, offset) << p->regshift;
420 outb(p->hub6 - 1 + offset, p->iobase);
421 outb(value, p->iobase + 1);
422}
1da177e4 423
7d6a07d1
DD		 424static unsigned int mem_serial_in(struct uart_port *p, int offset)
425{
426 offset = map_8250_in_reg(p, offset) << p->regshift;
427 return readb(p->membase + offset);
428}
1da177e4 429
7d6a07d1
DD		 430static void mem_serial_out(struct uart_port *p, int offset, int value)
431{
432 offset = map_8250_out_reg(p, offset) << p->regshift;
433 writeb(value, p->membase + offset);
434}
435
436static void mem32_serial_out(struct uart_port *p, int offset, int value)
437{
438 offset = map_8250_out_reg(p, offset) << p->regshift;
439 writel(value, p->membase + offset);
440}
441
442static unsigned int mem32_serial_in(struct uart_port *p, int offset)
443{
444 offset = map_8250_in_reg(p, offset) << p->regshift;
445 return readl(p->membase + offset);
446}
1da177e4 447
7d6a07d1
DD		 448static unsigned int io_serial_in(struct uart_port *p, int offset)
449{
450 offset = map_8250_in_reg(p, offset) << p->regshift;
451 return inb(p->iobase + offset);
452}
453
454static void io_serial_out(struct uart_port *p, int offset, int value)
455{
456 offset = map_8250_out_reg(p, offset) << p->regshift;
457 outb(value, p->iobase + offset);
458}
459
583d28e9
JI		 460static int serial8250_default_handle_irq(struct uart_port *port);
461
7d6a07d1
DD		 462static void set_io_from_upio(struct uart_port *p)
463{
49d5741b
JI		 464 struct uart_8250_port *up =
465 container_of(p, struct uart_8250_port, port);
cc419fa0
MD		 466
467 up->dl_read = _serial_dl_read;
468 up->dl_write = _serial_dl_write;
469
7d6a07d1 470 switch (p->iotype) {
1da177e4 471 case UPIO_HUB6:
7d6a07d1
DD		 472 p->serial_in = hub6_serial_in;
473 p->serial_out = hub6_serial_out;
1da177e4
LT		 474 break;
475
476 case UPIO_MEM:
7d6a07d1
DD		 477 p->serial_in = mem_serial_in;
478 p->serial_out = mem_serial_out;
1da177e4
LT		 479 break;
480
481 case UPIO_MEM32:
7d6a07d1
DD		 482 p->serial_in = mem32_serial_in;
483 p->serial_out = mem32_serial_out;
1da177e4
LT		 484 break;
485
28bf4cf2
MD		 486#ifdef CONFIG_SERIAL_8250_RM9K
487 case UPIO_RM9000:
488 p->serial_in = rm9k_serial_in;
489 p->serial_out = rm9k_serial_out;
490 up->dl_read = rm9k_serial_dl_read;
491 up->dl_write = rm9k_serial_dl_write;
492 break;
493#endif
494
6b416031 495#ifdef CONFIG_MIPS_ALCHEMY
21c614a7 496 case UPIO_AU:
7d6a07d1
DD		 497 p->serial_in = au_serial_in;
498 p->serial_out = au_serial_out;
6b416031
MD		 499 up->dl_read = au_serial_dl_read;
500 up->dl_write = au_serial_dl_write;
21c614a7 501 break;
6b416031 502#endif
12bf3f24 503
1da177e4 504 default:
7d6a07d1
DD		 505 p->serial_in = io_serial_in;
506 p->serial_out = io_serial_out;
507 break;
1da177e4 508 }
b8e7e40a
AC		 509 /* Remember loaded iotype */
510 up->cur_iotype = p->iotype;
583d28e9 511 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 512}
513
40b36daa 514static void
55e4016d 515serial_port_out_sync(struct uart_port *p, int offset, int value)
40b36daa 516{
7d6a07d1 517 switch (p->iotype) {
40b36daa
AW		 518 case UPIO_MEM:
519 case UPIO_MEM32:
40b36daa 520 case UPIO_AU:
7d6a07d1
DD		 521 p->serial_out(p, offset, value);
522 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 523 break;
524 default:
7d6a07d1 525 p->serial_out(p, offset, value);
40b36daa
AW		 526 }
527}
528
1da177e4
LT		 529/*
530 * For the 16C950
531 */
532static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
533{
534 serial_out(up, UART_SCR, offset);
535 serial_out(up, UART_ICR, value);
536}
537
538static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
539{
540 unsigned int value;
541
542 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
543 serial_out(up, UART_SCR, offset);
544 value = serial_in(up, UART_ICR);
545 serial_icr_write(up, UART_ACR, up->acr);
546
547 return value;
548}
549
550/*
551 * FIFO support.
552 */
b5d674ab 553static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 554{
555 if (p->capabilities & UART_CAP_FIFO) {
0acf519f
PG		 556 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
557 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 558 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f 559 serial_out(p, UART_FCR, 0);
1da177e4
LT		 560 }
561}
562
0ad372b9
SM		 563void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
564{
565 unsigned char fcr;
566
567 serial8250_clear_fifos(p);
568 fcr = uart_config[p->port.type].fcr;
569 serial_out(p, UART_FCR, fcr);
570}
571EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
572
1da177e4
LT		 573/*
574 * IER sleep support. UARTs which have EFRs need the "extended
575 * capability" bit enabled. Note that on XR16C850s, we need to
576 * reset LCR to write to IER.
577 */
b5d674ab 578static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 579{
580 if (p->capabilities & UART_CAP_SLEEP) {
581 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 582 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
583 serial_out(p, UART_EFR, UART_EFR_ECB);
584 serial_out(p, UART_LCR, 0);
1da177e4 585 }
0acf519f 586 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
1da177e4 587 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 588 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
589 serial_out(p, UART_EFR, 0);
590 serial_out(p, UART_LCR, 0);
1da177e4
LT		 591 }
592 }
593}
594
595#ifdef CONFIG_SERIAL_8250_RSA
596/*
597 * Attempts to turn on the RSA FIFO. Returns zero on failure.
598 * We set the port uart clock rate if we succeed.
599 */
600static int __enable_rsa(struct uart_8250_port *up)
601{
602 unsigned char mode;
603 int result;
604
0acf519f 605 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 606 result = mode & UART_RSA_MSR_FIFO;
607
608 if (!result) {
0acf519f
PG		 609 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
610 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 611 result = mode & UART_RSA_MSR_FIFO;
612 }
613
614 if (result)
615 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
616
617 return result;
618}
619
620static void enable_rsa(struct uart_8250_port *up)
621{
622 if (up->port.type == PORT_RSA) {
623 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
624 spin_lock_irq(&up->port.lock);
625 __enable_rsa(up);
626 spin_unlock_irq(&up->port.lock);
627 }
628 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
0acf519f 629 serial_out(up, UART_RSA_FRR, 0);
1da177e4
LT		 630 }
631}
632
633/*
634 * Attempts to turn off the RSA FIFO. Returns zero on failure.
635 * It is unknown why interrupts were disabled in here. However,
636 * the caller is expected to preserve this behaviour by grabbing
637 * the spinlock before calling this function.
638 */
639static void disable_rsa(struct uart_8250_port *up)
640{
641 unsigned char mode;
642 int result;
643
644 if (up->port.type == PORT_RSA &&
645 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
646 spin_lock_irq(&up->port.lock);
647
0acf519f 648 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 649 result = !(mode & UART_RSA_MSR_FIFO);
650
651 if (!result) {
0acf519f
PG		 652 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
653 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 654 result = !(mode & UART_RSA_MSR_FIFO);
655 }
656
657 if (result)
658 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
659 spin_unlock_irq(&up->port.lock);
660 }
661}
662#endif /* CONFIG_SERIAL_8250_RSA */
663
664/*
665 * This is a quickie test to see how big the FIFO is.
666 * It doesn't work at all the time, more's the pity.
667 */
668static int size_fifo(struct uart_8250_port *up)
669{
b32b19b8
JAH		 670 unsigned char old_fcr, old_mcr, old_lcr;
671 unsigned short old_dl;
1da177e4
LT		 672 int count;
673
0acf519f
PG		 674 old_lcr = serial_in(up, UART_LCR);
675 serial_out(up, UART_LCR, 0);
676 old_fcr = serial_in(up, UART_FCR);
677 old_mcr = serial_in(up, UART_MCR);
678 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 679 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f
PG		 680 serial_out(up, UART_MCR, UART_MCR_LOOP);
681 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 682 old_dl = serial_dl_read(up);
683 serial_dl_write(up, 0x0001);
0acf519f 684 serial_out(up, UART_LCR, 0x03);
1da177e4 685 for (count = 0; count < 256; count++)
0acf519f 686 serial_out(up, UART_TX, count);
1da177e4 687 mdelay(20);/* FIXME - schedule_timeout */
0acf519f 688 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
1da177e4 689 (count < 256); count++)
0acf519f
PG		 690 serial_in(up, UART_RX);
691 serial_out(up, UART_FCR, old_fcr);
692 serial_out(up, UART_MCR, old_mcr);
693 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 694 serial_dl_write(up, old_dl);
0acf519f 695 serial_out(up, UART_LCR, old_lcr);
1da177e4
LT		 696
697 return count;
698}
699
700/*
701 * Read UART ID using the divisor method - set DLL and DLM to zero
702 * and the revision will be in DLL and device type in DLM. We
703 * preserve the device state across this.
704 */
705static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
706{
707 unsigned char old_dll, old_dlm, old_lcr;
708 unsigned int id;
709
0acf519f
PG		 710 old_lcr = serial_in(p, UART_LCR);
711 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 712
0acf519f
PG		 713 old_dll = serial_in(p, UART_DLL);
714 old_dlm = serial_in(p, UART_DLM);
1da177e4 715
0acf519f
PG		 716 serial_out(p, UART_DLL, 0);
717 serial_out(p, UART_DLM, 0);
1da177e4 718
0acf519f 719 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
1da177e4 720
0acf519f
PG		 721 serial_out(p, UART_DLL, old_dll);
722 serial_out(p, UART_DLM, old_dlm);
723 serial_out(p, UART_LCR, old_lcr);
1da177e4
LT		 724
725 return id;
726}
727
728/*
729 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
730 * When this function is called we know it is at least a StarTech
731 * 16650 V2, but it might be one of several StarTech UARTs, or one of
732 * its clones. (We treat the broken original StarTech 16650 V1 as a
733 * 16550, and why not? Startech doesn't seem to even acknowledge its
734 * existence.)
bd71c182 735 *
1da177e4
LT		 736 * What evil have men's minds wrought...
737 */
738static void autoconfig_has_efr(struct uart_8250_port *up)
739{
740 unsigned int id1, id2, id3, rev;
741
742 /*
743 * Everything with an EFR has SLEEP
744 */
745 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
746
747 /*
748 * First we check to see if it's an Oxford Semiconductor UART.
749 *
750 * If we have to do this here because some non-National
751 * Semiconductor clone chips lock up if you try writing to the
752 * LSR register (which serial_icr_read does)
753 */
754
755 /*
756 * Check for Oxford Semiconductor 16C950.
757 *
758 * EFR [4] must be set else this test fails.
759 *
760 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
761 * claims that it's needed for 952 dual UART's (which are not
762 * recommended for new designs).
763 */
764 up->acr = 0;
662b083a 765 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 766 serial_out(up, UART_EFR, UART_EFR_ECB);
767 serial_out(up, UART_LCR, 0x00);
768 id1 = serial_icr_read(up, UART_ID1);
769 id2 = serial_icr_read(up, UART_ID2);
770 id3 = serial_icr_read(up, UART_ID3);
771 rev = serial_icr_read(up, UART_REV);
772
773 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
774
775 if (id1 == 0x16 && id2 == 0xC9 &&
776 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
777 up->port.type = PORT_16C950;
4ba5e35d
RK		 778
779 /*
780 * Enable work around for the Oxford Semiconductor 952 rev B
781 * chip which causes it to seriously miscalculate baud rates
782 * when DLL is 0.
783 */
784 if (id3 == 0x52 && rev == 0x01)
785 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 786 return;
787 }
bd71c182 788
1da177e4
LT		 789 /*
790 * We check for a XR16C850 by setting DLL and DLM to 0, and then
791 * reading back DLL and DLM. The chip type depends on the DLM
792 * value read back:
793 * 0x10 - XR16C850 and the DLL contains the chip revision.
794 * 0x12 - XR16C2850.
795 * 0x14 - XR16C854.
796 */
797 id1 = autoconfig_read_divisor_id(up);
798 DEBUG_AUTOCONF("850id=%04x ", id1);
799
800 id2 = id1 >> 8;
801 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 802 up->port.type = PORT_16850;
803 return;
804 }
805
806 /*
807 * It wasn't an XR16C850.
808 *
809 * We distinguish between the '654 and the '650 by counting
810 * how many bytes are in the FIFO. I'm using this for now,
811 * since that's the technique that was sent to me in the
812 * serial driver update, but I'm not convinced this works.
813 * I've had problems doing this in the past. -TYT
814 */
815 if (size_fifo(up) == 64)
816 up->port.type = PORT_16654;
817 else
818 up->port.type = PORT_16650V2;
819}
820
821/*
822 * We detected a chip without a FIFO. Only two fall into
823 * this category - the original 8250 and the 16450. The
824 * 16450 has a scratch register (accessible with LCR=0)
825 */
826static void autoconfig_8250(struct uart_8250_port *up)
827{
828 unsigned char scratch, status1, status2;
829
830 up->port.type = PORT_8250;
831
832 scratch = serial_in(up, UART_SCR);
0acf519f 833 serial_out(up, UART_SCR, 0xa5);
1da177e4 834 status1 = serial_in(up, UART_SCR);
0acf519f 835 serial_out(up, UART_SCR, 0x5a);
1da177e4 836 status2 = serial_in(up, UART_SCR);
0acf519f 837 serial_out(up, UART_SCR, scratch);
1da177e4
LT		 838
839 if (status1 == 0xa5 && status2 == 0x5a)
840 up->port.type = PORT_16450;
841}
842
843static int broken_efr(struct uart_8250_port *up)
844{
845 /*
846 * Exar ST16C2550 "A2" devices incorrectly detect as
847 * having an EFR, and report an ID of 0x0201. See
631dd1a8 848 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 849 */
850 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
851 return 1;
852
853 return 0;
854}
855
0d0389e5
YK		 856static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
857{
858 unsigned char status;
859
860 status = serial_in(up, 0x04); /* EXCR2 */
861#define PRESL(x) ((x) & 0x30)
862 if (PRESL(status) == 0x10) {
863 /* already in high speed mode */
864 return 0;
865 } else {
866 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
867 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
0acf519f 868 serial_out(up, 0x04, status);
0d0389e5
YK		 869 }
870 return 1;
871}
872
1da177e4
LT		 873/*
874 * We know that the chip has FIFOs. Does it have an EFR? The
875 * EFR is located in the same register position as the IIR and
876 * we know the top two bits of the IIR are currently set. The
877 * EFR should contain zero. Try to read the EFR.
878 */
879static void autoconfig_16550a(struct uart_8250_port *up)
880{
881 unsigned char status1, status2;
882 unsigned int iersave;
883
884 up->port.type = PORT_16550A;
885 up->capabilities |= UART_CAP_FIFO;
886
887 /*
888 * Check for presence of the EFR when DLAB is set.
889 * Only ST16C650V1 UARTs pass this test.
890 */
0acf519f 891 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 892 if (serial_in(up, UART_EFR) == 0) {
0acf519f 893 serial_out(up, UART_EFR, 0xA8);
1da177e4
LT		 894 if (serial_in(up, UART_EFR) != 0) {
895 DEBUG_AUTOCONF("EFRv1 ");
896 up->port.type = PORT_16650;
897 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
898 } else {
899 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
900 }
0acf519f 901 serial_out(up, UART_EFR, 0);
1da177e4
LT		 902 return;
903 }
904
905 /*
906 * Maybe it requires 0xbf to be written to the LCR.
907 * (other ST16C650V2 UARTs, TI16C752A, etc)
908 */
0acf519f 909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 910 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
911 DEBUG_AUTOCONF("EFRv2 ");
912 autoconfig_has_efr(up);
913 return;
914 }
915
916 /*
917 * Check for a National Semiconductor SuperIO chip.
918 * Attempt to switch to bank 2, read the value of the LOOP bit
919 * from EXCR1. Switch back to bank 0, change it in MCR. Then
920 * switch back to bank 2, read it from EXCR1 again and check
921 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4 922 */
0acf519f 923 serial_out(up, UART_LCR, 0);
1da177e4 924 status1 = serial_in(up, UART_MCR);
0acf519f 925 serial_out(up, UART_LCR, 0xE0);
1da177e4
LT		 926 status2 = serial_in(up, 0x02); /* EXCR1 */
927
928 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
0acf519f
PG		 929 serial_out(up, UART_LCR, 0);
930 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
931 serial_out(up, UART_LCR, 0xE0);
1da177e4 932 status2 = serial_in(up, 0x02); /* EXCR1 */
0acf519f
PG		 933 serial_out(up, UART_LCR, 0);
934 serial_out(up, UART_MCR, status1);
1da177e4
LT		 935
936 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 937 unsigned short quot;
938
0acf519f 939 serial_out(up, UART_LCR, 0xE0);
857dde2e 940
b32b19b8 941 quot = serial_dl_read(up);
857dde2e
DW		 942 quot <<= 3;
943
0d0389e5
YK		 944 if (ns16550a_goto_highspeed(up))
945 serial_dl_write(up, quot);
857dde2e 946
0acf519f 947 serial_out(up, UART_LCR, 0);
1da177e4 948
857dde2e 949 up->port.uartclk = 921600*16;
1da177e4
LT		 950 up->port.type = PORT_NS16550A;
951 up->capabilities |= UART_NATSEMI;
952 return;
953 }
954 }
955
956 /*
957 * No EFR. Try to detect a TI16750, which only sets bit 5 of
958 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
959 * Try setting it with and without DLAB set. Cheap clones
960 * set bit 5 without DLAB set.
961 */
0acf519f
PG		 962 serial_out(up, UART_LCR, 0);
963 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 964 status1 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 965 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
966 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
967 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 968 status2 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 969 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
970 serial_out(up, UART_LCR, 0);
1da177e4
LT		 971
972 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
973
974 if (status1 == 6 && status2 == 7) {
975 up->port.type = PORT_16750;
976 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
977 return;
978 }
979
980 /*
981 * Try writing and reading the UART_IER_UUE bit (b6).
982 * If it works, this is probably one of the Xscale platform's
983 * internal UARTs.
984 * We're going to explicitly set the UUE bit to 0 before
985 * trying to write and read a 1 just to make sure it's not
986 * already a 1 and maybe locked there before we even start start.
987 */
988 iersave = serial_in(up, UART_IER);
0acf519f 989 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1da177e4
LT		 990 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
991 /*
992 * OK it's in a known zero state, try writing and reading
993 * without disturbing the current state of the other bits.
994 */
0acf519f 995 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1da177e4
LT		 996 if (serial_in(up, UART_IER) & UART_IER_UUE) {
997 /*
998 * It's an Xscale.
999 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1000 */
1001 DEBUG_AUTOCONF("Xscale ");
1002 up->port.type = PORT_XSCALE;
5568181f 1003 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 1004 return;
1005 }
1006 } else {
1007 /*
1008 * If we got here we couldn't force the IER_UUE bit to 0.
1009 * Log it and continue.
1010 */
1011 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1012 }
0acf519f 1013 serial_out(up, UART_IER, iersave);
235dae5d 1014
06315348
SH		 1015 /*
1016 * Exar uarts have EFR in a weird location
1017 */
1018 if (up->port.flags & UPF_EXAR_EFR) {
1019 up->port.type = PORT_XR17D15X;
1020 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1021 }
1022
235dae5d
PL		 1023 /*
1024 * We distinguish between 16550A and U6 16550A by counting
1025 * how many bytes are in the FIFO.
1026 */
1027 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1028 up->port.type = PORT_U6_16550A;
1029 up->capabilities |= UART_CAP_AFE;
1030 }
1da177e4
LT		 1031}
1032
1033/*
1034 * This routine is called by rs_init() to initialize a specific serial
1035 * port. It determines what type of UART chip this serial port is
1036 * using: 8250, 16450, 16550, 16550A. The important question is
1037 * whether or not this UART is a 16550A or not, since this will
1038 * determine whether or not we can use its FIFO features or not.
1039 */
1040static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1041{
1042 unsigned char status1, scratch, scratch2, scratch3;
1043 unsigned char save_lcr, save_mcr;
dfe42443 1044 struct uart_port *port = &up->port;
1da177e4
LT		 1045 unsigned long flags;
1046
dfe42443 1047 if (!port->iobase && !port->mapbase && !port->membase)
1da177e4
LT		 1048 return;
1049
80647b95 1050 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
dfe42443 1051 serial_index(port), port->iobase, port->membase);
1da177e4
LT		 1052
1053 /*
1054 * We really do need global IRQs disabled here - we're going to
1055 * be frobbing the chips IRQ enable register to see if it exists.
1056 */
dfe42443 1057 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1058
1059 up->capabilities = 0;
4ba5e35d 1060 up->bugs = 0;
1da177e4 1061
dfe42443 1062 if (!(port->flags & UPF_BUGGY_UART)) {
1da177e4
LT		 1063 /*
1064 * Do a simple existence test first; if we fail this,
1065 * there's no point trying anything else.
bd71c182 1066 *
1da177e4
LT		 1067 * 0x80 is used as a nonsense port to prevent against
1068 * false positives due to ISA bus float. The
1069 * assumption is that 0x80 is a non-existent port;
1070 * which should be safe since include/asm/io.h also
1071 * makes this assumption.
1072 *
1073 * Note: this is safe as long as MCR bit 4 is clear
1074 * and the device is in "PC" mode.
1075 */
0acf519f
PG		 1076 scratch = serial_in(up, UART_IER);
1077 serial_out(up, UART_IER, 0);
1da177e4
LT		 1078#ifdef __i386__
1079 outb(0xff, 0x080);
1080#endif
48212008
TH		 1081 /*
1082 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1083 * 16C754B) allow only to modify them if an EFR bit is set.
1084 */
0acf519f
PG		 1085 scratch2 = serial_in(up, UART_IER) & 0x0f;
1086 serial_out(up, UART_IER, 0x0F);
1da177e4
LT		 1087#ifdef __i386__
1088 outb(0, 0x080);
1089#endif
0acf519f
PG		 1090 scratch3 = serial_in(up, UART_IER) & 0x0f;
1091 serial_out(up, UART_IER, scratch);
1da177e4
LT		 1092 if (scratch2 != 0 || scratch3 != 0x0F) {
1093 /*
1094 * We failed; there's nothing here
1095 */
1096 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1097 scratch2, scratch3);
1098 goto out;
1099 }
1100 }
1101
1102 save_mcr = serial_in(up, UART_MCR);
1103 save_lcr = serial_in(up, UART_LCR);
1104
bd71c182 1105 /*
1da177e4
LT		 1106 * Check to see if a UART is really there. Certain broken
1107 * internal modems based on the Rockwell chipset fail this
1108 * test, because they apparently don't implement the loopback
1109 * test mode. So this test is skipped on the COM 1 through
1110 * COM 4 ports. This *should* be safe, since no board
1111 * manufacturer would be stupid enough to design a board
1112 * that conflicts with COM 1-4 --- we hope!
1113 */
dfe42443 1114 if (!(port->flags & UPF_SKIP_TEST)) {
0acf519f
PG		 1115 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1116 status1 = serial_in(up, UART_MSR) & 0xF0;
1117 serial_out(up, UART_MCR, save_mcr);
1da177e4
LT		 1118 if (status1 != 0x90) {
1119 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1120 status1);
1121 goto out;
1122 }
1123 }
1124
1125 /*
1126 * We're pretty sure there's a port here. Lets find out what
1127 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1128 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1129 * determines what we test for next.
1130 *
1131 * We also initialise the EFR (if any) to zero for later. The
1132 * EFR occupies the same register location as the FCR and IIR.
1133 */
0acf519f
PG		 1134 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1135 serial_out(up, UART_EFR, 0);
1136 serial_out(up, UART_LCR, 0);
1da177e4 1137
0acf519f 1138 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1da177e4
LT		 1139 scratch = serial_in(up, UART_IIR) >> 6;
1140
1141 DEBUG_AUTOCONF("iir=%d ", scratch);
1142
1143 switch (scratch) {
1144 case 0:
1145 autoconfig_8250(up);
1146 break;
1147 case 1:
dfe42443 1148 port->type = PORT_UNKNOWN;
1da177e4
LT		 1149 break;
1150 case 2:
dfe42443 1151 port->type = PORT_16550;
1da177e4
LT		 1152 break;
1153 case 3:
1154 autoconfig_16550a(up);
1155 break;
1156 }
1157
1158#ifdef CONFIG_SERIAL_8250_RSA
1159 /*
1160 * Only probe for RSA ports if we got the region.
1161 */
dfe42443 1162 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1da177e4
LT		 1163 int i;
1164
1165 for (i = 0 ; i < probe_rsa_count; ++i) {
dfe42443
PG		 1166 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1167 port->type = PORT_RSA;
1da177e4
LT		 1168 break;
1169 }
1170 }
1171 }
1172#endif
21c614a7 1173
0acf519f 1174 serial_out(up, UART_LCR, save_lcr);
1da177e4 1175
dfe42443 1176 if (up->capabilities != uart_config[port->type].flags) {
1da177e4
LT		 1177 printk(KERN_WARNING
1178 "ttyS%d: detected caps %08x should be %08x\n",
dfe42443
PG		 1179 serial_index(port), up->capabilities,
1180 uart_config[port->type].flags);
1da177e4
LT		 1181 }
1182
dfe42443
PG		 1183 port->fifosize = uart_config[up->port.type].fifo_size;
1184 up->capabilities = uart_config[port->type].flags;
1185 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1da177e4 1186
dfe42443 1187 if (port->type == PORT_UNKNOWN)
1da177e4
LT		 1188 goto out;
1189
1190 /*
1191 * Reset the UART.
1192 */
1193#ifdef CONFIG_SERIAL_8250_RSA
dfe42443 1194 if (port->type == PORT_RSA)
0acf519f 1195 serial_out(up, UART_RSA_FRR, 0);
1da177e4 1196#endif
0acf519f 1197 serial_out(up, UART_MCR, save_mcr);
1da177e4 1198 serial8250_clear_fifos(up);
40b36daa 1199 serial_in(up, UART_RX);
5c8c755c 1200 if (up->capabilities & UART_CAP_UUE)
0acf519f 1201 serial_out(up, UART_IER, UART_IER_UUE);
5c8c755c 1202 else
0acf519f 1203 serial_out(up, UART_IER, 0);
1da177e4 1204
bd71c182 1205 out:
dfe42443
PG		 1206 spin_unlock_irqrestore(&port->lock, flags);
1207 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1da177e4
LT		 1208}
1209
1210static void autoconfig_irq(struct uart_8250_port *up)
1211{
dfe42443 1212 struct uart_port *port = &up->port;
1da177e4
LT		 1213 unsigned char save_mcr, save_ier;
1214 unsigned char save_ICP = 0;
1215 unsigned int ICP = 0;
1216 unsigned long irqs;
1217 int irq;
1218
dfe42443
PG		 1219 if (port->flags & UPF_FOURPORT) {
1220 ICP = (port->iobase & 0xfe0) | 0x1f;
1da177e4
LT		 1221 save_ICP = inb_p(ICP);
1222 outb_p(0x80, ICP);
0d263a26 1223 inb_p(ICP);
1da177e4
LT		 1224 }
1225
1226 /* forget possible initially masked and pending IRQ */
1227 probe_irq_off(probe_irq_on());
0acf519f
PG		 1228 save_mcr = serial_in(up, UART_MCR);
1229 save_ier = serial_in(up, UART_IER);
1230 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1231
1da177e4 1232 irqs = probe_irq_on();
0acf519f 1233 serial_out(up, UART_MCR, 0);
6f803cd0 1234 udelay(10);
dfe42443 1235 if (port->flags & UPF_FOURPORT) {
0acf519f 1236 serial_out(up, UART_MCR,
1da177e4
LT		 1237 UART_MCR_DTR | UART_MCR_RTS);
1238 } else {
0acf519f 1239 serial_out(up, UART_MCR,
1da177e4
LT		 1240 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1241 }
0acf519f 1242 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
0d263a26
PG		 1243 serial_in(up, UART_LSR);
1244 serial_in(up, UART_RX);
1245 serial_in(up, UART_IIR);
1246 serial_in(up, UART_MSR);
0acf519f 1247 serial_out(up, UART_TX, 0xFF);
6f803cd0 1248 udelay(20);
1da177e4
LT		 1249 irq = probe_irq_off(irqs);
1250
0acf519f
PG		 1251 serial_out(up, UART_MCR, save_mcr);
1252 serial_out(up, UART_IER, save_ier);
1da177e4 1253
dfe42443 1254 if (port->flags & UPF_FOURPORT)
1da177e4
LT		 1255 outb_p(save_ICP, ICP);
1256
dfe42443 1257 port->irq = (irq > 0) ? irq : 0;
1da177e4
LT		 1258}
1259
e763b90c
RK		 1260static inline void __stop_tx(struct uart_8250_port *p)
1261{
1262 if (p->ier & UART_IER_THRI) {
1263 p->ier &= ~UART_IER_THRI;
1264 serial_out(p, UART_IER, p->ier);
1265 }
1266}
1267
b129a8cc 1268static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1269{
49d5741b
JI		 1270 struct uart_8250_port *up =
1271 container_of(port, struct uart_8250_port, port);
1da177e4 1272
e763b90c 1273 __stop_tx(up);
1da177e4
LT		 1274
1275 /*
e763b90c 1276 * We really want to stop the transmitter from sending.
1da177e4 1277 */
dfe42443 1278 if (port->type == PORT_16C950) {
1da177e4
LT		 1279 up->acr |= UART_ACR_TXDIS;
1280 serial_icr_write(up, UART_ACR, up->acr);
1281 }
1282}
1283
b129a8cc 1284static void serial8250_start_tx(struct uart_port *port)
1da177e4 1285{
49d5741b
JI		 1286 struct uart_8250_port *up =
1287 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1288
1289 if (!(up->ier & UART_IER_THRI)) {
1290 up->ier |= UART_IER_THRI;
4fd996a1 1291 serial_port_out(port, UART_IER, up->ier);
55d3b282 1292
67f7654e 1293 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1294 unsigned char lsr;
55d3b282 1295 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1296 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1297 if ((port->type == PORT_RM9000) ?
68cb4f8e
IJ		 1298 (lsr & UART_LSR_THRE) :
1299 (lsr & UART_LSR_TEMT))
3986fb2b 1300 serial8250_tx_chars(up);
55d3b282 1301 }
1da177e4 1302 }
e763b90c 1303
1da177e4 1304 /*
e763b90c 1305 * Re-enable the transmitter if we disabled it.
1da177e4 1306 */
dfe42443 1307 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1308 up->acr &= ~UART_ACR_TXDIS;
1309 serial_icr_write(up, UART_ACR, up->acr);
1310 }
1311}
1312
1313static void serial8250_stop_rx(struct uart_port *port)
1314{
49d5741b
JI		 1315 struct uart_8250_port *up =
1316 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1317
1318 up->ier &= ~UART_IER_RLSI;
1319 up->port.read_status_mask &= ~UART_LSR_DR;
4fd996a1 1320 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1321}
1322
1323static void serial8250_enable_ms(struct uart_port *port)
1324{
49d5741b
JI		 1325 struct uart_8250_port *up =
1326 container_of(port, struct uart_8250_port, port);
1da177e4 1327
21c614a7
PA		 1328 /* no MSR capabilities */
1329 if (up->bugs & UART_BUG_NOMSR)
1330 return;
1331
1da177e4 1332 up->ier |= UART_IER_MSI;
4fd996a1 1333 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1334}
1335
0690f41f 1336/*
3986fb2b 1337 * serial8250_rx_chars: processes according to the passed in LSR
0690f41f
PG		 1338 * value, and returns the remaining LSR bits not handled
1339 * by this Rx routine.
1340 */
3986fb2b
PG		 1341unsigned char
1342serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1da177e4 1343{
dfe42443
PG		 1344 struct uart_port *port = &up->port;
1345 struct tty_struct *tty = port->state->port.tty;
0690f41f 1346 unsigned char ch;
1da177e4
LT		 1347 int max_count = 256;
1348 char flag;
1349
1350 do {
7500b1f6 1351 if (likely(lsr & UART_LSR_DR))
0acf519f 1352 ch = serial_in(up, UART_RX);
7500b1f6
AR		 1353 else
1354 /*
1355 * Intel 82571 has a Serial Over Lan device that will
1356 * set UART_LSR_BI without setting UART_LSR_DR when
1357 * it receives a break. To avoid reading from the
1358 * receive buffer without UART_LSR_DR bit set, we
1359 * just force the read character to be 0
1360 */
1361 ch = 0;
1362
1da177e4 1363 flag = TTY_NORMAL;
dfe42443 1364 port->icount.rx++;
1da177e4 1365
ad4c2aa6
CM		 1366 lsr |= up->lsr_saved_flags;
1367 up->lsr_saved_flags = 0;
1da177e4 1368
ad4c2aa6 1369 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1370 if (lsr & UART_LSR_BI) {
1371 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
dfe42443 1372 port->icount.brk++;
1da177e4
LT		 1373 /*
1374 * We do the SysRQ and SAK checking
1375 * here because otherwise the break
1376 * may get masked by ignore_status_mask
1377 * or read_status_mask.
1378 */
dfe42443 1379 if (uart_handle_break(port))
1da177e4
LT		 1380 goto ignore_char;
1381 } else if (lsr & UART_LSR_PE)
dfe42443 1382 port->icount.parity++;
1da177e4 1383 else if (lsr & UART_LSR_FE)
dfe42443 1384 port->icount.frame++;
1da177e4 1385 if (lsr & UART_LSR_OE)
dfe42443 1386 port->icount.overrun++;
1da177e4
LT		 1387
1388 /*
23907eb8 1389 * Mask off conditions which should be ignored.
1da177e4 1390 */
dfe42443 1391 lsr &= port->read_status_mask;
1da177e4
LT		 1392
1393 if (lsr & UART_LSR_BI) {
1394 DEBUG_INTR("handling break....");
1395 flag = TTY_BREAK;
1396 } else if (lsr & UART_LSR_PE)
1397 flag = TTY_PARITY;
1398 else if (lsr & UART_LSR_FE)
1399 flag = TTY_FRAME;
1400 }
dfe42443 1401 if (uart_handle_sysrq_char(port, ch))
1da177e4 1402 goto ignore_char;
05ab3014 1403
dfe42443 1404 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
05ab3014 1405
6f803cd0 1406ignore_char:
0acf519f 1407 lsr = serial_in(up, UART_LSR);
7500b1f6 1408 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
dfe42443 1409 spin_unlock(&port->lock);
1da177e4 1410 tty_flip_buffer_push(tty);
dfe42443 1411 spin_lock(&port->lock);
0690f41f 1412 return lsr;
1da177e4 1413}
3986fb2b 1414EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1da177e4 1415
3986fb2b 1416void serial8250_tx_chars(struct uart_8250_port *up)
1da177e4 1417{
dfe42443
PG		 1418 struct uart_port *port = &up->port;
1419 struct circ_buf *xmit = &port->state->xmit;
1da177e4
LT		 1420 int count;
1421
dfe42443
PG		 1422 if (port->x_char) {
1423 serial_out(up, UART_TX, port->x_char);
1424 port->icount.tx++;
1425 port->x_char = 0;
1da177e4
LT		 1426 return;
1427 }
dfe42443
PG		 1428 if (uart_tx_stopped(port)) {
1429 serial8250_stop_tx(port);
b129a8cc
RK		 1430 return;
1431 }
1432 if (uart_circ_empty(xmit)) {
e763b90c 1433 __stop_tx(up);
1da177e4
LT		 1434 return;
1435 }
1436
1437 count = up->tx_loadsz;
1438 do {
1439 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1440 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
dfe42443 1441 port->icount.tx++;
1da177e4
LT		 1442 if (uart_circ_empty(xmit))
1443 break;
1444 } while (--count > 0);
1445
1446 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
dfe42443 1447 uart_write_wakeup(port);
1da177e4
LT		 1448
1449 DEBUG_INTR("THRE...");
1450
1451 if (uart_circ_empty(xmit))
e763b90c 1452 __stop_tx(up);
1da177e4 1453}
3986fb2b 1454EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1da177e4 1455
3986fb2b 1456unsigned int serial8250_modem_status(struct uart_8250_port *up)
1da177e4 1457{
dfe42443 1458 struct uart_port *port = &up->port;
2af7cd68
RK		 1459 unsigned int status = serial_in(up, UART_MSR);
1460
ad4c2aa6
CM		 1461 status |= up->msr_saved_flags;
1462 up->msr_saved_flags = 0;
fdc30b3d 1463 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
dfe42443 1464 port->state != NULL) {
2af7cd68 1465 if (status & UART_MSR_TERI)
dfe42443 1466 port->icount.rng++;
2af7cd68 1467 if (status & UART_MSR_DDSR)
dfe42443 1468 port->icount.dsr++;
2af7cd68 1469 if (status & UART_MSR_DDCD)
dfe42443 1470 uart_handle_dcd_change(port, status & UART_MSR_DCD);
2af7cd68 1471 if (status & UART_MSR_DCTS)
dfe42443 1472 uart_handle_cts_change(port, status & UART_MSR_CTS);
2af7cd68 1473
dfe42443 1474 wake_up_interruptible(&port->state->port.delta_msr_wait);
2af7cd68 1475 }
1da177e4 1476
2af7cd68 1477 return status;
1da177e4 1478}
3986fb2b 1479EXPORT_SYMBOL_GPL(serial8250_modem_status);
1da177e4
LT		 1480
1481/*
1482 * This handles the interrupt from one port.
1483 */
86b21199 1484int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1da177e4 1485{
0690f41f 1486 unsigned char status;
4bf3631c 1487 unsigned long flags;
86b21199
PG		 1488 struct uart_8250_port *up =
1489 container_of(port, struct uart_8250_port, port);
1490
1491 if (iir & UART_IIR_NO_INT)
1492 return 0;
45e24601 1493
dfe42443 1494 spin_lock_irqsave(&port->lock, flags);
45e24601 1495
4fd996a1 1496 status = serial_port_in(port, UART_LSR);
1da177e4
LT		 1497
1498 DEBUG_INTR("status = %x...", status);
1499
7500b1f6 1500 if (status & (UART_LSR_DR | UART_LSR_BI))
3986fb2b
PG		 1501 status = serial8250_rx_chars(up, status);
1502 serial8250_modem_status(up);
1da177e4 1503 if (status & UART_LSR_THRE)
3986fb2b 1504 serial8250_tx_chars(up);
45e24601 1505
dfe42443 1506 spin_unlock_irqrestore(&port->lock, flags);
86b21199 1507 return 1;
583d28e9 1508}
c7a1bdc5 1509EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1510
1511static int serial8250_default_handle_irq(struct uart_port *port)
1512{
4fd996a1 1513 unsigned int iir = serial_port_in(port, UART_IIR);
583d28e9
JI		 1514
1515 return serial8250_handle_irq(port, iir);
1516}
1517
1da177e4
LT		 1518/*
1519 * This is the serial driver's interrupt routine.
1520 *
1521 * Arjan thinks the old way was overly complex, so it got simplified.
1522 * Alan disagrees, saying that need the complexity to handle the weird
1523 * nature of ISA shared interrupts. (This is a special exception.)
1524 *
1525 * In order to handle ISA shared interrupts properly, we need to check
1526 * that all ports have been serviced, and therefore the ISA interrupt
1527 * line has been de-asserted.
1528 *
1529 * This means we need to loop through all ports. checking that they
1530 * don't have an interrupt pending.
1531 */
7d12e780 1532static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1533{
1534 struct irq_info *i = dev_id;
1535 struct list_head *l, *end = NULL;
1536 int pass_counter = 0, handled = 0;
1537
1538 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1539
1540 spin_lock(&i->lock);
1541
1542 l = i->head;
1543 do {
1544 struct uart_8250_port *up;
583d28e9 1545 struct uart_port *port;
1da177e4
LT		 1546
1547 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1548 port = &up->port;
1da177e4 1549
49b532f9 1550 if (port->handle_irq(port)) {
1da177e4 1551 handled = 1;
1da177e4
LT		 1552 end = NULL;
1553 } else if (end == NULL)
1554 end = l;
1555
1556 l = l->next;
1557
1558 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1559 /* If we hit this, we're dead. */
cd3ecad1
DD		 1560 printk_ratelimited(KERN_ERR
1561 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1562 break;
1563 }
1564 } while (l != end);
1565
1566 spin_unlock(&i->lock);
1567
1568 DEBUG_INTR("end.\n");
1569
1570 return IRQ_RETVAL(handled);
1571}
1572
1573/*
1574 * To support ISA shared interrupts, we need to have one interrupt
1575 * handler that ensures that the IRQ line has been deasserted
1576 * before returning. Failing to do this will result in the IRQ
1577 * line being stuck active, and, since ISA irqs are edge triggered,
1578 * no more IRQs will be seen.
1579 */
1580static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1581{
1582 spin_lock_irq(&i->lock);
1583
1584 if (!list_empty(i->head)) {
1585 if (i->head == &up->list)
1586 i->head = i->head->next;
1587 list_del(&up->list);
1588 } else {
1589 BUG_ON(i->head != &up->list);
1590 i->head = NULL;
1591 }
1da177e4 1592 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1593 /* List empty so throw away the hash node */
1594 if (i->head == NULL) {
1595 hlist_del(&i->node);
1596 kfree(i);
1597 }
1da177e4
LT		 1598}
1599
1600static int serial_link_irq_chain(struct uart_8250_port *up)
1601{
25db8ad5
AC		 1602 struct hlist_head *h;
1603 struct hlist_node *n;
1604 struct irq_info *i;
40663cc7 1605 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1606
25db8ad5
AC		 1607 mutex_lock(&hash_mutex);
1608
1609 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1610
1611 hlist_for_each(n, h) {
1612 i = hlist_entry(n, struct irq_info, node);
1613 if (i->irq == up->port.irq)
1614 break;
1615 }
1616
1617 if (n == NULL) {
1618 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1619 if (i == NULL) {
1620 mutex_unlock(&hash_mutex);
1621 return -ENOMEM;
1622 }
1623 spin_lock_init(&i->lock);
1624 i->irq = up->port.irq;
1625 hlist_add_head(&i->node, h);
1626 }
1627 mutex_unlock(&hash_mutex);
1628
1da177e4
LT		 1629 spin_lock_irq(&i->lock);
1630
1631 if (i->head) {
1632 list_add(&up->list, i->head);
1633 spin_unlock_irq(&i->lock);
1634
1635 ret = 0;
1636 } else {
1637 INIT_LIST_HEAD(&up->list);
1638 i->head = &up->list;
1639 spin_unlock_irq(&i->lock);
1c2f0493 1640 irq_flags |= up->port.irqflags;
1da177e4
LT		 1641 ret = request_irq(up->port.irq, serial8250_interrupt,
1642 irq_flags, "serial", i);
1643 if (ret < 0)
1644 serial_do_unlink(i, up);
1645 }
1646
1647 return ret;
1648}
1649
1650static void serial_unlink_irq_chain(struct uart_8250_port *up)
1651{
25db8ad5
AC		 1652 struct irq_info *i;
1653 struct hlist_node *n;
1654 struct hlist_head *h;
1da177e4 1655
25db8ad5
AC		 1656 mutex_lock(&hash_mutex);
1657
1658 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1659
1660 hlist_for_each(n, h) {
1661 i = hlist_entry(n, struct irq_info, node);
1662 if (i->irq == up->port.irq)
1663 break;
1664 }
1665
1666 BUG_ON(n == NULL);
1da177e4
LT		 1667 BUG_ON(i->head == NULL);
1668
1669 if (list_empty(i->head))
1670 free_irq(up->port.irq, i);
1671
1672 serial_do_unlink(i, up);
25db8ad5 1673 mutex_unlock(&hash_mutex);
1da177e4
LT		 1674}
1675
1676/*
1677 * This function is used to handle ports that do not have an
1678 * interrupt. This doesn't work very well for 16450's, but gives
1679 * barely passable results for a 16550A. (Although at the expense
1680 * of much CPU overhead).
1681 */
1682static void serial8250_timeout(unsigned long data)
1683{
1684 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4 1685
a0431476 1686 up->port.handle_irq(&up->port);
54381067 1687 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1688}
1689
1690static void serial8250_backup_timeout(unsigned long data)
1691{
1692 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1693 unsigned int iir, ier = 0, lsr;
1694 unsigned long flags;
40b36daa 1695
dbb3b1ca
AC		 1696 spin_lock_irqsave(&up->port.lock, flags);
1697
40b36daa
AW		 1698 /*
1699 * Must disable interrupts or else we risk racing with the interrupt
1700 * based handler.
1701 */
d4e33fac 1702 if (up->port.irq) {
40b36daa
AW		 1703 ier = serial_in(up, UART_IER);
1704 serial_out(up, UART_IER, 0);
1705 }
1da177e4 1706
40b36daa
AW		 1707 iir = serial_in(up, UART_IIR);
1708
1709 /*
1710 * This should be a safe test for anyone who doesn't trust the
1711 * IIR bits on their UART, but it's specifically designed for
1712 * the "Diva" UART used on the management processor on many HP
1713 * ia64 and parisc boxes.
1714 */
ad4c2aa6
CM		 1715 lsr = serial_in(up, UART_LSR);
1716 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1717 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1718 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1719 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1720 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1721 iir |= UART_IIR_THRI;
1722 }
1723
1724 if (!(iir & UART_IIR_NO_INT))
3986fb2b 1725 serial8250_tx_chars(up);
40b36daa 1726
d4e33fac 1727 if (up->port.irq)
40b36daa
AW		 1728 serial_out(up, UART_IER, ier);
1729
dbb3b1ca
AC		 1730 spin_unlock_irqrestore(&up->port.lock, flags);
1731
40b36daa 1732 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1733 mod_timer(&up->timer,
54381067 1734 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1735}
1736
1737static unsigned int serial8250_tx_empty(struct uart_port *port)
1738{
49d5741b
JI		 1739 struct uart_8250_port *up =
1740 container_of(port, struct uart_8250_port, port);
1da177e4 1741 unsigned long flags;
ad4c2aa6 1742 unsigned int lsr;
1da177e4 1743
dfe42443 1744 spin_lock_irqsave(&port->lock, flags);
4fd996a1 1745 lsr = serial_port_in(port, UART_LSR);
ad4c2aa6 1746 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1747 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 1748
bca47613 1749 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1750}
1751
1752static unsigned int serial8250_get_mctrl(struct uart_port *port)
1753{
49d5741b
JI		 1754 struct uart_8250_port *up =
1755 container_of(port, struct uart_8250_port, port);
2af7cd68 1756 unsigned int status;
1da177e4
LT		 1757 unsigned int ret;
1758
3986fb2b 1759 status = serial8250_modem_status(up);
1da177e4
LT		 1760
1761 ret = 0;
1762 if (status & UART_MSR_DCD)
1763 ret |= TIOCM_CAR;
1764 if (status & UART_MSR_RI)
1765 ret |= TIOCM_RNG;
1766 if (status & UART_MSR_DSR)
1767 ret |= TIOCM_DSR;
1768 if (status & UART_MSR_CTS)
1769 ret |= TIOCM_CTS;
1770 return ret;
1771}
1772
1773static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1774{
49d5741b
JI		 1775 struct uart_8250_port *up =
1776 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1777 unsigned char mcr = 0;
1778
1779 if (mctrl & TIOCM_RTS)
1780 mcr |= UART_MCR_RTS;
1781 if (mctrl & TIOCM_DTR)
1782 mcr |= UART_MCR_DTR;
1783 if (mctrl & TIOCM_OUT1)
1784 mcr |= UART_MCR_OUT1;
1785 if (mctrl & TIOCM_OUT2)
1786 mcr |= UART_MCR_OUT2;
1787 if (mctrl & TIOCM_LOOP)
1788 mcr |= UART_MCR_LOOP;
1789
1790 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1791
4fd996a1 1792 serial_port_out(port, UART_MCR, mcr);
1da177e4
LT		 1793}
1794
1795static void serial8250_break_ctl(struct uart_port *port, int break_state)
1796{
49d5741b
JI		 1797 struct uart_8250_port *up =
1798 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1799 unsigned long flags;
1800
dfe42443 1801 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1802 if (break_state == -1)
1803 up->lcr |= UART_LCR_SBC;
1804 else
1805 up->lcr &= ~UART_LCR_SBC;
4fd996a1 1806 serial_port_out(port, UART_LCR, up->lcr);
dfe42443 1807 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1808}
1809
40b36daa
AW		 1810/*
1811 * Wait for transmitter & holding register to empty
1812 */
b5d674ab 1813static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1814{
1815 unsigned int status, tmout = 10000;
1816
1817 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1818 for (;;) {
40b36daa
AW		 1819 status = serial_in(up, UART_LSR);
1820
ad4c2aa6 1821 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1822
97d303b7
DD		 1823 if ((status & bits) == bits)
1824 break;
40b36daa
AW		 1825 if (--tmout == 0)
1826 break;
1827 udelay(1);
97d303b7 1828 }
40b36daa
AW		 1829
1830 /* Wait up to 1s for flow control if necessary */
1831 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1832 unsigned int tmout;
1833 for (tmout = 1000000; tmout; tmout--) {
1834 unsigned int msr = serial_in(up, UART_MSR);
1835 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1836 if (msr & UART_MSR_CTS)
1837 break;
40b36daa
AW		 1838 udelay(1);
1839 touch_nmi_watchdog();
1840 }
1841 }
1842}
1843
f2d937f3
JW		 1844#ifdef CONFIG_CONSOLE_POLL
1845/*
1846 * Console polling routines for writing and reading from the uart while
1847 * in an interrupt or debug context.
1848 */
1849
1850static int serial8250_get_poll_char(struct uart_port *port)
1851{
4fd996a1 1852 unsigned char lsr = serial_port_in(port, UART_LSR);
f2d937f3 1853
f5316b4a
JW		 1854 if (!(lsr & UART_LSR_DR))
1855 return NO_POLL_CHAR;
f2d937f3 1856
4fd996a1 1857 return serial_port_in(port, UART_RX);
f2d937f3
JW		 1858}
1859
1860
1861static void serial8250_put_poll_char(struct uart_port *port,
1862 unsigned char c)
1863{
1864 unsigned int ier;
49d5741b
JI		 1865 struct uart_8250_port *up =
1866 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1867
1868 /*
1869 * First save the IER then disable the interrupts
1870 */
4fd996a1 1871 ier = serial_port_in(port, UART_IER);
f2d937f3 1872 if (up->capabilities & UART_CAP_UUE)
4fd996a1 1873 serial_port_out(port, UART_IER, UART_IER_UUE);
f2d937f3 1874 else
4fd996a1 1875 serial_port_out(port, UART_IER, 0);
f2d937f3
JW		 1876
1877 wait_for_xmitr(up, BOTH_EMPTY);
1878 /*
1879 * Send the character out.
1880 * If a LF, also do CR...
1881 */
4fd996a1 1882 serial_port_out(port, UART_TX, c);
f2d937f3
JW		 1883 if (c == 10) {
1884 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1885 serial_port_out(port, UART_TX, 13);
f2d937f3
JW		 1886 }
1887
1888 /*
1889 * Finally, wait for transmitter to become empty
1890 * and restore the IER
1891 */
1892 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1893 serial_port_out(port, UART_IER, ier);
f2d937f3
JW		 1894}
1895
1896#endif /* CONFIG_CONSOLE_POLL */
1897
1da177e4
LT		 1898static int serial8250_startup(struct uart_port *port)
1899{
49d5741b
JI		 1900 struct uart_8250_port *up =
1901 container_of(port, struct uart_8250_port, port);
1da177e4 1902 unsigned long flags;
55d3b282 1903 unsigned char lsr, iir;
1da177e4
LT		 1904 int retval;
1905
dfe42443 1906 port->fifosize = uart_config[up->port.type].fifo_size;
e4f05af1 1907 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 1908 up->capabilities = uart_config[up->port.type].flags;
1909 up->mcr = 0;
1910
dfe42443 1911 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 1912 set_io_from_upio(port);
1913
dfe42443 1914 if (port->type == PORT_16C950) {
1da177e4
LT		 1915 /* Wake up and initialize UART */
1916 up->acr = 0;
4fd996a1
PG		 1917 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1918 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1919 serial_port_out(port, UART_IER, 0);
1920 serial_port_out(port, UART_LCR, 0);
1da177e4 1921 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
4fd996a1
PG		 1922 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1923 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1924 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1925 }
1926
1927#ifdef CONFIG_SERIAL_8250_RSA
1928 /*
1929 * If this is an RSA port, see if we can kick it up to the
1930 * higher speed clock.
1931 */
1932 enable_rsa(up);
1933#endif
1934
1935 /*
1936 * Clear the FIFO buffers and disable them.
7f927fcc 1937 * (they will be reenabled in set_termios())
1da177e4
LT		 1938 */
1939 serial8250_clear_fifos(up);
1940
1941 /*
1942 * Clear the interrupt registers.
1943 */
4fd996a1
PG		 1944 serial_port_in(port, UART_LSR);
1945 serial_port_in(port, UART_RX);
1946 serial_port_in(port, UART_IIR);
1947 serial_port_in(port, UART_MSR);
1da177e4
LT		 1948
1949 /*
1950 * At this point, there's no way the LSR could still be 0xff;
1951 * if it is, then bail out, because there's likely no UART
1952 * here.
1953 */
dfe42443 1954 if (!(port->flags & UPF_BUGGY_UART) &&
4fd996a1 1955 (serial_port_in(port, UART_LSR) == 0xff)) {
7808a4c4 1956 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
dfe42443 1957 serial_index(port));
1da177e4
LT		 1958 return -ENODEV;
1959 }
1960
1961 /*
1962 * For a XR16C850, we need to set the trigger levels
1963 */
dfe42443 1964 if (port->type == PORT_16850) {
1da177e4
LT		 1965 unsigned char fctr;
1966
0acf519f 1967 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4 1968
0acf519f 1969 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
4fd996a1
PG		 1970 serial_port_out(port, UART_FCTR,
1971 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1972 serial_port_out(port, UART_TRG, UART_TRG_96);
1973 serial_port_out(port, UART_FCTR,
1974 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1975 serial_port_out(port, UART_TRG, UART_TRG_96);
1da177e4 1976
4fd996a1 1977 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1978 }
1979
dfe42443 1980 if (port->irq) {
01c194d9 1981 unsigned char iir1;
40b36daa
AW		 1982 /*
1983 * Test for UARTs that do not reassert THRE when the
1984 * transmitter is idle and the interrupt has already
1985 * been cleared. Real 16550s should always reassert
1986 * this interrupt whenever the transmitter is idle and
1987 * the interrupt is enabled. Delays are necessary to
1988 * allow register changes to become visible.
1989 */
dfe42443 1990 spin_lock_irqsave(&port->lock, flags);
1c2f0493 1991 if (up->port.irqflags & IRQF_SHARED)
dfe42443 1992 disable_irq_nosync(port->irq);
40b36daa
AW		 1993
1994 wait_for_xmitr(up, UART_LSR_THRE);
55e4016d 1995 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 1996 udelay(1); /* allow THRE to set */
4fd996a1
PG		 1997 iir1 = serial_port_in(port, UART_IIR);
1998 serial_port_out(port, UART_IER, 0);
55e4016d 1999 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 2000 udelay(1); /* allow a working UART time to re-assert THRE */
4fd996a1
PG		 2001 iir = serial_port_in(port, UART_IIR);
2002 serial_port_out(port, UART_IER, 0);
40b36daa 2003
dfe42443
PG		 2004 if (port->irqflags & IRQF_SHARED)
2005 enable_irq(port->irq);
2006 spin_unlock_irqrestore(&port->lock, flags);
40b36daa
AW		 2007
2008 /*
bc02d15a
DW		 2009 * If the interrupt is not reasserted, or we otherwise
2010 * don't trust the iir, setup a timer to kick the UART
2011 * on a regular basis.
40b36daa 2012 */
bc02d15a
DW		 2013 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2014 up->port.flags & UPF_BUG_THRE) {
363f66fe 2015 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2016 pr_debug("ttyS%d - using backup timer\n",
2017 serial_index(port));
40b36daa
AW		 2018 }
2019 }
2020
363f66fe
WN		 2021 /*
2022 * The above check will only give an accurate result the first time
2023 * the port is opened so this value needs to be preserved.
2024 */
2025 if (up->bugs & UART_BUG_THRE) {
2026 up->timer.function = serial8250_backup_timeout;
2027 up->timer.data = (unsigned long)up;
2028 mod_timer(&up->timer, jiffies +
54381067 2029 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2030 }
2031
1da177e4
LT		 2032 /*
2033 * If the "interrupt" for this port doesn't correspond with any
2034 * hardware interrupt, we use a timer-based system. The original
2035 * driver used to do this with IRQ0.
2036 */
dfe42443 2037 if (!port->irq) {
1da177e4 2038 up->timer.data = (unsigned long)up;
54381067 2039 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2040 } else {
2041 retval = serial_link_irq_chain(up);
2042 if (retval)
2043 return retval;
2044 }
2045
2046 /*
2047 * Now, initialize the UART
2048 */
4fd996a1 2049 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1da177e4 2050
dfe42443 2051 spin_lock_irqsave(&port->lock, flags);
1da177e4 2052 if (up->port.flags & UPF_FOURPORT) {
d4e33fac 2053 if (!up->port.irq)
1da177e4
LT		 2054 up->port.mctrl |= TIOCM_OUT1;
2055 } else
2056 /*
2057 * Most PC uarts need OUT2 raised to enable interrupts.
2058 */
dfe42443 2059 if (port->irq)
1da177e4
LT		 2060 up->port.mctrl |= TIOCM_OUT2;
2061
dfe42443 2062 serial8250_set_mctrl(port, port->mctrl);
55d3b282 2063
b6adea33
MCC		 2064 /* Serial over Lan (SoL) hack:
2065 Intel 8257x Gigabit ethernet chips have a
2066 16550 emulation, to be used for Serial Over Lan.
2067 Those chips take a longer time than a normal
2068 serial device to signalize that a transmission
2069 data was queued. Due to that, the above test generally
2070 fails. One solution would be to delay the reading of
2071 iir. However, this is not reliable, since the timeout
2072 is variable. So, let's just don't test if we receive
2073 TX irq. This way, we'll never enable UART_BUG_TXEN.
2074 */
d41a4b51 2075 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2076 goto dont_test_tx_en;
2077
55d3b282
RK		 2078 /*
2079 * Do a quick test to see if we receive an
2080 * interrupt when we enable the TX irq.
2081 */
4fd996a1
PG		 2082 serial_port_out(port, UART_IER, UART_IER_THRI);
2083 lsr = serial_port_in(port, UART_LSR);
2084 iir = serial_port_in(port, UART_IIR);
2085 serial_port_out(port, UART_IER, 0);
55d3b282
RK		 2086
2087 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2088 if (!(up->bugs & UART_BUG_TXEN)) {
2089 up->bugs |= UART_BUG_TXEN;
55d3b282 2090 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2091 serial_index(port));
55d3b282
RK		 2092 }
2093 } else {
67f7654e 2094 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2095 }
2096
b6adea33 2097dont_test_tx_en:
dfe42443 2098 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 2099
ad4c2aa6
CM		 2100 /*
2101 * Clear the interrupt registers again for luck, and clear the
2102 * saved flags to avoid getting false values from polling
2103 * routines or the previous session.
2104 */
4fd996a1
PG		 2105 serial_port_in(port, UART_LSR);
2106 serial_port_in(port, UART_RX);
2107 serial_port_in(port, UART_IIR);
2108 serial_port_in(port, UART_MSR);
ad4c2aa6
CM		 2109 up->lsr_saved_flags = 0;
2110 up->msr_saved_flags = 0;
2111
1da177e4
LT		 2112 /*
2113 * Finally, enable interrupts. Note: Modem status interrupts
2114 * are set via set_termios(), which will be occurring imminently
2115 * anyway, so we don't enable them here.
2116 */
2117 up->ier = UART_IER_RLSI | UART_IER_RDI;
4fd996a1 2118 serial_port_out(port, UART_IER, up->ier);
1da177e4 2119
dfe42443 2120 if (port->flags & UPF_FOURPORT) {
1da177e4
LT		 2121 unsigned int icp;
2122 /*
2123 * Enable interrupts on the AST Fourport board
2124 */
dfe42443 2125 icp = (port->iobase & 0xfe0) | 0x01f;
1da177e4 2126 outb_p(0x80, icp);
0d263a26 2127 inb_p(icp);
1da177e4
LT		 2128 }
2129
1da177e4
LT		 2130 return 0;
2131}
2132
2133static void serial8250_shutdown(struct uart_port *port)
2134{
49d5741b
JI		 2135 struct uart_8250_port *up =
2136 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2137 unsigned long flags;
2138
2139 /*
2140 * Disable interrupts from this port
2141 */
2142 up->ier = 0;
4fd996a1 2143 serial_port_out(port, UART_IER, 0);
1da177e4 2144
dfe42443
PG		 2145 spin_lock_irqsave(&port->lock, flags);
2146 if (port->flags & UPF_FOURPORT) {
1da177e4 2147 /* reset interrupts on the AST Fourport board */
dfe42443
PG		 2148 inb((port->iobase & 0xfe0) | 0x1f);
2149 port->mctrl |= TIOCM_OUT1;
1da177e4 2150 } else
dfe42443 2151 port->mctrl &= ~TIOCM_OUT2;
1da177e4 2152
dfe42443
PG		 2153 serial8250_set_mctrl(port, port->mctrl);
2154 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2155
2156 /*
2157 * Disable break condition and FIFOs
2158 */
4fd996a1
PG		 2159 serial_port_out(port, UART_LCR,
2160 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
1da177e4
LT		 2161 serial8250_clear_fifos(up);
2162
2163#ifdef CONFIG_SERIAL_8250_RSA
2164 /*
2165 * Reset the RSA board back to 115kbps compat mode.
2166 */
2167 disable_rsa(up);
2168#endif
2169
2170 /*
2171 * Read data port to reset things, and then unlink from
2172 * the IRQ chain.
2173 */
4fd996a1 2174 serial_port_in(port, UART_RX);
1da177e4 2175
40b36daa
AW		 2176 del_timer_sync(&up->timer);
2177 up->timer.function = serial8250_timeout;
dfe42443 2178 if (port->irq)
1da177e4
LT		 2179 serial_unlink_irq_chain(up);
2180}
2181
2182static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2183{
2184 unsigned int quot;
2185
2186 /*
2187 * Handle magic divisors for baud rates above baud_base on
2188 * SMSC SuperIO chips.
2189 */
2190 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2191 baud == (port->uartclk/4))
2192 quot = 0x8001;
2193 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2194 baud == (port->uartclk/8))
2195 quot = 0x8002;
2196 else
2197 quot = uart_get_divisor(port, baud);
2198
2199 return quot;
2200}
2201
235dae5d
PL		 2202void
2203serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2204 struct ktermios *old)
1da177e4 2205{
49d5741b
JI		 2206 struct uart_8250_port *up =
2207 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2208 unsigned char cval, fcr = 0;
2209 unsigned long flags;
2210 unsigned int baud, quot;
2211
2212 switch (termios->c_cflag & CSIZE) {
2213 case CS5:
0a8b80c5 2214 cval = UART_LCR_WLEN5;
1da177e4
LT		 2215 break;
2216 case CS6:
0a8b80c5 2217 cval = UART_LCR_WLEN6;
1da177e4
LT		 2218 break;
2219 case CS7:
0a8b80c5 2220 cval = UART_LCR_WLEN7;
1da177e4
LT		 2221 break;
2222 default:
2223 case CS8:
0a8b80c5 2224 cval = UART_LCR_WLEN8;
1da177e4
LT		 2225 break;
2226 }
2227
2228 if (termios->c_cflag & CSTOPB)
0a8b80c5 2229 cval |= UART_LCR_STOP;
1da177e4
LT		 2230 if (termios->c_cflag & PARENB)
2231 cval |= UART_LCR_PARITY;
2232 if (!(termios->c_cflag & PARODD))
2233 cval |= UART_LCR_EPAR;
2234#ifdef CMSPAR
2235 if (termios->c_cflag & CMSPAR)
2236 cval |= UART_LCR_SPAR;
2237#endif
2238
2239 /*
2240 * Ask the core to calculate the divisor for us.
2241 */
24d481ec
AV		 2242 baud = uart_get_baud_rate(port, termios, old,
2243 port->uartclk / 16 / 0xffff,
2244 port->uartclk / 16);
1da177e4
LT		 2245 quot = serial8250_get_divisor(port, baud);
2246
2247 /*
4ba5e35d 2248 * Oxford Semi 952 rev B workaround
1da177e4 2249 */
4ba5e35d 2250 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2251 quot++;
1da177e4 2252
dfe42443 2253 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
f9a9111b
CM		 2254 fcr = uart_config[port->type].fcr;
2255 if (baud < 2400) {
2256 fcr &= ~UART_FCR_TRIGGER_MASK;
2257 fcr |= UART_FCR_TRIGGER_1;
2258 }
1da177e4
LT		 2259 }
2260
2261 /*
2262 * MCR-based auto flow control. When AFE is enabled, RTS will be
2263 * deasserted when the receive FIFO contains more characters than
2264 * the trigger, or the MCR RTS bit is cleared. In the case where
2265 * the remote UART is not using CTS auto flow control, we must
2266 * have sufficient FIFO entries for the latency of the remote
2267 * UART to respond. IOW, at least 32 bytes of FIFO.
2268 */
dfe42443 2269 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
1da177e4
LT		 2270 up->mcr &= ~UART_MCR_AFE;
2271 if (termios->c_cflag & CRTSCTS)
2272 up->mcr |= UART_MCR_AFE;
2273 }
2274
2275 /*
2276 * Ok, we're now changing the port state. Do it with
2277 * interrupts disabled.
2278 */
dfe42443 2279 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 2280
2281 /*
2282 * Update the per-port timeout.
2283 */
2284 uart_update_timeout(port, termios->c_cflag, baud);
2285
dfe42443 2286 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1da177e4 2287 if (termios->c_iflag & INPCK)
dfe42443 2288 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1da177e4 2289 if (termios->c_iflag & (BRKINT | PARMRK))
dfe42443 2290 port->read_status_mask |= UART_LSR_BI;
1da177e4
LT		 2291
2292 /*
2293 * Characteres to ignore
2294 */
dfe42443 2295 port->ignore_status_mask = 0;
1da177e4 2296 if (termios->c_iflag & IGNPAR)
dfe42443 2297 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1da177e4 2298 if (termios->c_iflag & IGNBRK) {
dfe42443 2299 port->ignore_status_mask |= UART_LSR_BI;
1da177e4
LT		 2300 /*
2301 * If we're ignoring parity and break indicators,
2302 * ignore overruns too (for real raw support).
2303 */
2304 if (termios->c_iflag & IGNPAR)
dfe42443 2305 port->ignore_status_mask |= UART_LSR_OE;
1da177e4
LT		 2306 }
2307
2308 /*
2309 * ignore all characters if CREAD is not set
2310 */
2311 if ((termios->c_cflag & CREAD) == 0)
dfe42443 2312 port->ignore_status_mask |= UART_LSR_DR;
1da177e4
LT		 2313
2314 /*
2315 * CTS flow control flag and modem status interrupts
2316 */
f8b372a1 2317 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2318 if (!(up->bugs & UART_BUG_NOMSR) &&
2319 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2320 up->ier |= UART_IER_MSI;
2321 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2322 up->ier |= UART_IER_UUE;
2323 if (up->capabilities & UART_CAP_RTOIE)
2324 up->ier |= UART_IER_RTOIE;
1da177e4 2325
4fd996a1 2326 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 2327
2328 if (up->capabilities & UART_CAP_EFR) {
2329 unsigned char efr = 0;
2330 /*
2331 * TI16C752/Startech hardware flow control. FIXME:
2332 * - TI16C752 requires control thresholds to be set.
2333 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2334 */
2335 if (termios->c_cflag & CRTSCTS)
2336 efr |= UART_EFR_CTS;
2337
4fd996a1 2338 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
dfe42443 2339 if (port->flags & UPF_EXAR_EFR)
4fd996a1 2340 serial_port_out(port, UART_XR_EFR, efr);
06315348 2341 else
4fd996a1 2342 serial_port_out(port, UART_EFR, efr);
1da177e4
LT		 2343 }
2344
f2eda27d 2345#ifdef CONFIG_ARCH_OMAP
255341c6 2346 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2347 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2348 if (baud == 115200) {
2349 quot = 1;
4fd996a1 2350 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
255341c6 2351 } else
4fd996a1 2352 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
255341c6
JM		 2353 }
2354#endif
2355
4fd996a1
PG		 2356 /*
2357 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2358 * otherwise just set DLAB
2359 */
2360 if (up->capabilities & UART_NATSEMI)
2361 serial_port_out(port, UART_LCR, 0xe0);
2362 else
2363 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
1da177e4 2364
b32b19b8 2365 serial_dl_write(up, quot);
1da177e4
LT		 2366
2367 /*
2368 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2369 * is written without DLAB set, this mode will be disabled.
2370 */
dfe42443 2371 if (port->type == PORT_16750)
4fd996a1 2372 serial_port_out(port, UART_FCR, fcr);
1da177e4 2373
4fd996a1 2374 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
1da177e4 2375 up->lcr = cval; /* Save LCR */
dfe42443 2376 if (port->type != PORT_16750) {
4fd996a1
PG		 2377 /* emulated UARTs (Lucent Venus 167x) need two steps */
2378 if (fcr & UART_FCR_ENABLE_FIFO)
2379 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2380 serial_port_out(port, UART_FCR, fcr); /* set fcr */
1da177e4 2381 }
dfe42443
PG		 2382 serial8250_set_mctrl(port, port->mctrl);
2383 spin_unlock_irqrestore(&port->lock, flags);
e991a2bd
AC		 2384 /* Don't rewrite B0 */
2385 if (tty_termios_baud_rate(termios))
2386 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2387}
235dae5d
PL		 2388EXPORT_SYMBOL(serial8250_do_set_termios);
2389
2390static void
2391serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2392 struct ktermios *old)
2393{
2394 if (port->set_termios)
2395 port->set_termios(port, termios, old);
2396 else
2397 serial8250_do_set_termios(port, termios, old);
2398}
1da177e4 2399
dc77f161 2400static void
a0821df6 2401serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2402{
a0821df6 2403 if (new == N_PPS) {
dc77f161
RG		 2404 port->flags |= UPF_HARDPPS_CD;
2405 serial8250_enable_ms(port);
2406 } else
2407 port->flags &= ~UPF_HARDPPS_CD;
2408}
2409
c161afe9
ML		 2410
2411void serial8250_do_pm(struct uart_port *port, unsigned int state,
2412 unsigned int oldstate)
1da177e4 2413{
49d5741b
JI		 2414 struct uart_8250_port *p =
2415 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2416
2417 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2418}
2419EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2420
c161afe9
ML		 2421static void
2422serial8250_pm(struct uart_port *port, unsigned int state,
2423 unsigned int oldstate)
2424{
2425 if (port->pm)
2426 port->pm(port, state, oldstate);
2427 else
2428 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2429}
2430
f2eda27d
RK		 2431static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2432{
2433 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2434 return 0x1000;
f2eda27d
RK		 2435#ifdef CONFIG_ARCH_OMAP
2436 if (is_omap_port(pt))
2437 return 0x16 << pt->port.regshift;
2438#endif
2439 return 8 << pt->port.regshift;
2440}
2441
1da177e4
LT		 2442/*
2443 * Resource handling.
2444 */
2445static int serial8250_request_std_resource(struct uart_8250_port *up)
2446{
f2eda27d 2447 unsigned int size = serial8250_port_size(up);
dfe42443 2448 struct uart_port *port = &up->port;
1da177e4
LT		 2449 int ret = 0;
2450
dfe42443 2451 switch (port->iotype) {
85835f44 2452 case UPIO_AU:
0b30d668
SS		 2453 case UPIO_TSI:
2454 case UPIO_MEM32:
1da177e4 2455 case UPIO_MEM:
dfe42443 2456 if (!port->mapbase)
1da177e4
LT		 2457 break;
2458
dfe42443 2459 if (!request_mem_region(port->mapbase, size, "serial")) {
1da177e4
LT		 2460 ret = -EBUSY;
2461 break;
2462 }
2463
dfe42443
PG		 2464 if (port->flags & UPF_IOREMAP) {
2465 port->membase = ioremap_nocache(port->mapbase, size);
2466 if (!port->membase) {
2467 release_mem_region(port->mapbase, size);
1da177e4
LT		 2468 ret = -ENOMEM;
2469 }
2470 }
2471 break;
2472
2473 case UPIO_HUB6:
2474 case UPIO_PORT:
dfe42443 2475 if (!request_region(port->iobase, size, "serial"))
1da177e4
LT		 2476 ret = -EBUSY;
2477 break;
2478 }
2479 return ret;
2480}
2481
2482static void serial8250_release_std_resource(struct uart_8250_port *up)
2483{
f2eda27d 2484 unsigned int size = serial8250_port_size(up);
dfe42443 2485 struct uart_port *port = &up->port;
1da177e4 2486
dfe42443 2487 switch (port->iotype) {
85835f44 2488 case UPIO_AU:
0b30d668
SS		 2489 case UPIO_TSI:
2490 case UPIO_MEM32:
1da177e4 2491 case UPIO_MEM:
dfe42443 2492 if (!port->mapbase)
1da177e4
LT		 2493 break;
2494
dfe42443
PG		 2495 if (port->flags & UPF_IOREMAP) {
2496 iounmap(port->membase);
2497 port->membase = NULL;
1da177e4
LT		 2498 }
2499
dfe42443 2500 release_mem_region(port->mapbase, size);
1da177e4
LT		 2501 break;
2502
2503 case UPIO_HUB6:
2504 case UPIO_PORT:
dfe42443 2505 release_region(port->iobase, size);
1da177e4
LT		 2506 break;
2507 }
2508}
2509
2510static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2511{
2512 unsigned long start = UART_RSA_BASE << up->port.regshift;
2513 unsigned int size = 8 << up->port.regshift;
dfe42443 2514 struct uart_port *port = &up->port;
0b30d668 2515 int ret = -EINVAL;
1da177e4 2516
dfe42443 2517 switch (port->iotype) {
1da177e4
LT		 2518 case UPIO_HUB6:
2519 case UPIO_PORT:
dfe42443 2520 start += port->iobase;
0b30d668
SS		 2521 if (request_region(start, size, "serial-rsa"))
2522 ret = 0;
2523 else
1da177e4
LT		 2524 ret = -EBUSY;
2525 break;
2526 }
2527
2528 return ret;
2529}
2530
2531static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2532{
2533 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2534 unsigned int size = 8 << up->port.regshift;
dfe42443 2535 struct uart_port *port = &up->port;
1da177e4 2536
dfe42443 2537 switch (port->iotype) {
1da177e4
LT		 2538 case UPIO_HUB6:
2539 case UPIO_PORT:
dfe42443 2540 release_region(port->iobase + offset, size);
1da177e4
LT		 2541 break;
2542 }
2543}
2544
2545static void serial8250_release_port(struct uart_port *port)
2546{
49d5741b
JI		 2547 struct uart_8250_port *up =
2548 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2549
2550 serial8250_release_std_resource(up);
dfe42443 2551 if (port->type == PORT_RSA)
1da177e4
LT		 2552 serial8250_release_rsa_resource(up);
2553}
2554
2555static int serial8250_request_port(struct uart_port *port)
2556{
49d5741b
JI		 2557 struct uart_8250_port *up =
2558 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2559 int ret = 0;
2560
2561 ret = serial8250_request_std_resource(up);
dfe42443 2562 if (ret == 0 && port->type == PORT_RSA) {
1da177e4
LT		 2563 ret = serial8250_request_rsa_resource(up);
2564 if (ret < 0)
2565 serial8250_release_std_resource(up);
2566 }
2567
2568 return ret;
2569}
2570
2571static void serial8250_config_port(struct uart_port *port, int flags)
2572{
49d5741b
JI		 2573 struct uart_8250_port *up =
2574 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2575 int probeflags = PROBE_ANY;
2576 int ret;
2577
1da177e4
LT		 2578 /*
2579 * Find the region that we can probe for. This in turn
2580 * tells us whether we can probe for the type of port.
2581 */
2582 ret = serial8250_request_std_resource(up);
2583 if (ret < 0)
2584 return;
2585
2586 ret = serial8250_request_rsa_resource(up);
2587 if (ret < 0)
2588 probeflags &= ~PROBE_RSA;
2589
dfe42443 2590 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 2591 set_io_from_upio(port);
2592
1da177e4
LT		 2593 if (flags & UART_CONFIG_TYPE)
2594 autoconfig(up, probeflags);
b2b13cdf 2595
b2b13cdf 2596 /* if access method is AU, it is a 16550 with a quirk */
dfe42443 2597 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
b2b13cdf 2598 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2599
dfe42443 2600 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1da177e4
LT		 2601 autoconfig_irq(up);
2602
dfe42443 2603 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
1da177e4 2604 serial8250_release_rsa_resource(up);
dfe42443 2605 if (port->type == PORT_UNKNOWN)
1da177e4
LT		 2606 serial8250_release_std_resource(up);
2607}
2608
2609static int
2610serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2611{
a62c4133 2612 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2613 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2614 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2615 ser->type == PORT_STARTECH)
2616 return -EINVAL;
2617 return 0;
2618}
2619
2620static const char *
2621serial8250_type(struct uart_port *port)
2622{
2623 int type = port->type;
2624
2625 if (type >= ARRAY_SIZE(uart_config))
2626 type = 0;
2627 return uart_config[type].name;
2628}
2629
2630static struct uart_ops serial8250_pops = {
2631 .tx_empty = serial8250_tx_empty,
2632 .set_mctrl = serial8250_set_mctrl,
2633 .get_mctrl = serial8250_get_mctrl,
2634 .stop_tx = serial8250_stop_tx,
2635 .start_tx = serial8250_start_tx,
2636 .stop_rx = serial8250_stop_rx,
2637 .enable_ms = serial8250_enable_ms,
2638 .break_ctl = serial8250_break_ctl,
2639 .startup = serial8250_startup,
2640 .shutdown = serial8250_shutdown,
2641 .set_termios = serial8250_set_termios,
dc77f161 2642 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2643 .pm = serial8250_pm,
2644 .type = serial8250_type,
2645 .release_port = serial8250_release_port,
2646 .request_port = serial8250_request_port,
2647 .config_port = serial8250_config_port,
2648 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2649#ifdef CONFIG_CONSOLE_POLL
2650 .poll_get_char = serial8250_get_poll_char,
2651 .poll_put_char = serial8250_put_poll_char,
2652#endif
1da177e4
LT		 2653};
2654
2655static struct uart_8250_port serial8250_ports[UART_NR];
2656
af7f3743
AC		 2657static void (*serial8250_isa_config)(int port, struct uart_port *up,
2658 unsigned short *capabilities);
2659
2660void serial8250_set_isa_configurator(
2661 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2662{
2663 serial8250_isa_config = v;
2664}
2665EXPORT_SYMBOL(serial8250_set_isa_configurator);
2666
1da177e4
LT		 2667static void __init serial8250_isa_init_ports(void)
2668{
2669 struct uart_8250_port *up;
2670 static int first = 1;
4c0ebb80 2671 int i, irqflag = 0;
1da177e4
LT		 2672
2673 if (!first)
2674 return;
2675 first = 0;
2676
a61c2d78 2677 for (i = 0; i < nr_uarts; i++) {
1da177e4 2678 struct uart_8250_port *up = &serial8250_ports[i];
dfe42443 2679 struct uart_port *port = &up->port;
1da177e4 2680
dfe42443
PG		 2681 port->line = i;
2682 spin_lock_init(&port->lock);
1da177e4
LT		 2683
2684 init_timer(&up->timer);
2685 up->timer.function = serial8250_timeout;
2686
2687 /*
2688 * ALPHA_KLUDGE_MCR needs to be killed.
2689 */
2690 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2691 up->mcr_force = ALPHA_KLUDGE_MCR;
2692
dfe42443 2693 port->ops = &serial8250_pops;
1da177e4
LT		 2694 }
2695
4c0ebb80
AGR		 2696 if (share_irqs)
2697 irqflag = IRQF_SHARED;
2698
44454bcd 2699 for (i = 0, up = serial8250_ports;
a61c2d78 2700 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4 2701 i++, up++) {
dfe42443
PG		 2702 struct uart_port *port = &up->port;
2703
2704 port->iobase = old_serial_port[i].port;
2705 port->irq = irq_canonicalize(old_serial_port[i].irq);
2706 port->irqflags = old_serial_port[i].irqflags;
2707 port->uartclk = old_serial_port[i].baud_base * 16;
2708 port->flags = old_serial_port[i].flags;
2709 port->hub6 = old_serial_port[i].hub6;
2710 port->membase = old_serial_port[i].iomem_base;
2711 port->iotype = old_serial_port[i].io_type;
2712 port->regshift = old_serial_port[i].iomem_reg_shift;
2713 set_io_from_upio(port);
2714 port->irqflags |= irqflag;
af7f3743
AC		 2715 if (serial8250_isa_config != NULL)
2716 serial8250_isa_config(i, &up->port, &up->capabilities);
2717
1da177e4
LT		 2718 }
2719}
2720
b5d228cc
SL		 2721static void
2722serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2723{
2724 up->port.type = type;
2725 up->port.fifosize = uart_config[type].fifo_size;
2726 up->capabilities = uart_config[type].flags;
2727 up->tx_loadsz = uart_config[type].tx_loadsz;
2728}
2729
1da177e4
LT		 2730static void __init
2731serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2732{
2733 int i;
2734
b8e7e40a
AC		 2735 for (i = 0; i < nr_uarts; i++) {
2736 struct uart_8250_port *up = &serial8250_ports[i];
2737 up->cur_iotype = 0xFF;
2738 }
2739
1da177e4
LT		 2740 serial8250_isa_init_ports();
2741
a61c2d78 2742 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2743 struct uart_8250_port *up = &serial8250_ports[i];
2744
2745 up->port.dev = dev;
b5d228cc
SL		 2746
2747 if (up->port.flags & UPF_FIXED_TYPE)
2748 serial8250_init_fixed_type_port(up, up->port.type);
2749
1da177e4
LT		 2750 uart_add_one_port(drv, &up->port);
2751 }
2752}
2753
2754#ifdef CONFIG_SERIAL_8250_CONSOLE
2755
d358788f
RK		 2756static void serial8250_console_putchar(struct uart_port *port, int ch)
2757{
49d5741b
JI		 2758 struct uart_8250_port *up =
2759 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2760
2761 wait_for_xmitr(up, UART_LSR_THRE);
4fd996a1 2762 serial_port_out(port, UART_TX, ch);
d358788f
RK		 2763}
2764
1da177e4
LT		 2765/*
2766 * Print a string to the serial port trying not to disturb
2767 * any possible real use of the port...
2768 *
2769 * The console_lock must be held when we get here.
2770 */
2771static void
2772serial8250_console_write(struct console *co, const char *s, unsigned int count)
2773{
2774 struct uart_8250_port *up = &serial8250_ports[co->index];
dfe42443 2775 struct uart_port *port = &up->port;
d8a5a8d7 2776 unsigned long flags;
1da177e4 2777 unsigned int ier;
d8a5a8d7 2778 int locked = 1;
1da177e4 2779
78512ece
AM		 2780 touch_nmi_watchdog();
2781
68aa2c0d 2782 local_irq_save(flags);
dfe42443 2783 if (port->sysrq) {
86b21199 2784 /* serial8250_handle_irq() already took the lock */
68aa2c0d
AM		 2785 locked = 0;
2786 } else if (oops_in_progress) {
dfe42443 2787 locked = spin_trylock(&port->lock);
d8a5a8d7 2788 } else
dfe42443 2789 spin_lock(&port->lock);
d8a5a8d7 2790
1da177e4 2791 /*
dc7bf130 2792 * First save the IER then disable the interrupts
1da177e4 2793 */
4fd996a1 2794 ier = serial_port_in(port, UART_IER);
1da177e4
LT		 2795
2796 if (up->capabilities & UART_CAP_UUE)
4fd996a1 2797 serial_port_out(port, UART_IER, UART_IER_UUE);
1da177e4 2798 else
4fd996a1 2799 serial_port_out(port, UART_IER, 0);
1da177e4 2800
dfe42443 2801 uart_console_write(port, s, count, serial8250_console_putchar);
1da177e4
LT		 2802
2803 /*
2804 * Finally, wait for transmitter to become empty
2805 * and restore the IER
2806 */
f91a3715 2807 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 2808 serial_port_out(port, UART_IER, ier);
d8a5a8d7 2809
ad4c2aa6
CM		 2810 /*
2811 * The receive handling will happen properly because the
2812 * receive ready bit will still be set; it is not cleared
2813 * on read. However, modem control will not, we must
2814 * call it if we have saved something in the saved flags
2815 * while processing with interrupts off.
2816 */
2817 if (up->msr_saved_flags)
3986fb2b 2818 serial8250_modem_status(up);
ad4c2aa6 2819
d8a5a8d7 2820 if (locked)
dfe42443 2821 spin_unlock(&port->lock);
68aa2c0d 2822 local_irq_restore(flags);
1da177e4
LT		 2823}
2824
118c0ace 2825static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2826{
2827 struct uart_port *port;
2828 int baud = 9600;
2829 int bits = 8;
2830 int parity = 'n';
2831 int flow = 'n';
2832
2833 /*
2834 * Check whether an invalid uart number has been specified, and
2835 * if so, search for the first available port that does have
2836 * console support.
2837 */
a61c2d78 2838 if (co->index >= nr_uarts)
1da177e4
LT		 2839 co->index = 0;
2840 port = &serial8250_ports[co->index].port;
2841 if (!port->iobase && !port->membase)
2842 return -ENODEV;
2843
2844 if (options)
2845 uart_parse_options(options, &baud, &parity, &bits, &flow);
2846
2847 return uart_set_options(port, co, baud, parity, bits, flow);
2848}
2849
b6b1d877 2850static int serial8250_console_early_setup(void)
18a8bd94
YL		 2851{
2852 return serial8250_find_port_for_earlycon();
2853}
2854
1da177e4
LT		 2855static struct console serial8250_console = {
2856 .name = "ttyS",
2857 .write = serial8250_console_write,
2858 .device = uart_console_device,
2859 .setup = serial8250_console_setup,
18a8bd94 2860 .early_setup = serial8250_console_early_setup,
a80c49db 2861 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2862 .index = -1,
2863 .data = &serial8250_reg,
2864};
2865
2866static int __init serial8250_console_init(void)
2867{
05d81d22
EB		 2868 if (nr_uarts > UART_NR)
2869 nr_uarts = UART_NR;
2870
1da177e4
LT		 2871 serial8250_isa_init_ports();
2872 register_console(&serial8250_console);
2873 return 0;
2874}
2875console_initcall(serial8250_console_init);
2876
18a8bd94 2877int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2878{
2879 int line;
2880 struct uart_port *port;
2881
a61c2d78 2882 for (line = 0; line < nr_uarts; line++) {
1da177e4 2883 port = &serial8250_ports[line].port;
50aec3b5 2884 if (uart_match_port(p, port))
1da177e4
LT		 2885 return line;
2886 }
2887 return -ENODEV;
2888}
2889
1da177e4
LT		 2890#define SERIAL8250_CONSOLE &serial8250_console
2891#else
2892#define SERIAL8250_CONSOLE NULL
2893#endif
2894
2895static struct uart_driver serial8250_reg = {
2896 .owner = THIS_MODULE,
2897 .driver_name = "serial",
1da177e4
LT		 2898 .dev_name = "ttyS",
2899 .major = TTY_MAJOR,
2900 .minor = 64,
1da177e4
LT		 2901 .cons = SERIAL8250_CONSOLE,
2902};
2903
d856c666
RK		 2904/*
2905 * early_serial_setup - early registration for 8250 ports
2906 *
2907 * Setup an 8250 port structure prior to console initialisation. Use
2908 * after console initialisation will cause undefined behaviour.
2909 */
1da177e4
LT		 2910int __init early_serial_setup(struct uart_port *port)
2911{
b430428a
DD		 2912 struct uart_port *p;
2913
1da177e4
LT		 2914 if (port->line >= ARRAY_SIZE(serial8250_ports))
2915 return -ENODEV;
2916
2917 serial8250_isa_init_ports();
b430428a
DD		 2918 p = &serial8250_ports[port->line].port;
2919 p->iobase = port->iobase;
2920 p->membase = port->membase;
2921 p->irq = port->irq;
1c2f0493 2922 p->irqflags = port->irqflags;
b430428a
DD		 2923 p->uartclk = port->uartclk;
2924 p->fifosize = port->fifosize;
2925 p->regshift = port->regshift;
2926 p->iotype = port->iotype;
2927 p->flags = port->flags;
2928 p->mapbase = port->mapbase;
2929 p->private_data = port->private_data;
125c97d8
HD		 2930 p->type = port->type;
2931 p->line = port->line;
7d6a07d1
DD		 2932
2933 set_io_from_upio(p);
2934 if (port->serial_in)
2935 p->serial_in = port->serial_in;
2936 if (port->serial_out)
2937 p->serial_out = port->serial_out;
583d28e9
JI		 2938 if (port->handle_irq)
2939 p->handle_irq = port->handle_irq;
2940 else
2941 p->handle_irq = serial8250_default_handle_irq;
7d6a07d1 2942
1da177e4
LT		 2943 return 0;
2944}
2945
2946/**
2947 * serial8250_suspend_port - suspend one serial port
2948 * @line: serial line number
1da177e4
LT		 2949 *
2950 * Suspend one serial port.
2951 */
2952void serial8250_suspend_port(int line)
2953{
2954 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2955}
2956
2957/**
2958 * serial8250_resume_port - resume one serial port
2959 * @line: serial line number
1da177e4
LT		 2960 *
2961 * Resume one serial port.
2962 */
2963void serial8250_resume_port(int line)
2964{
b5b82df6 2965 struct uart_8250_port *up = &serial8250_ports[line];
dfe42443 2966 struct uart_port *port = &up->port;
b5b82df6
DW		 2967
2968 if (up->capabilities & UART_NATSEMI) {
b5b82df6 2969 /* Ensure it's still in high speed mode */
4fd996a1 2970 serial_port_out(port, UART_LCR, 0xE0);
b5b82df6 2971
0d0389e5 2972 ns16550a_goto_highspeed(up);
b5b82df6 2973
4fd996a1 2974 serial_port_out(port, UART_LCR, 0);
dfe42443 2975 port->uartclk = 921600*16;
b5b82df6 2976 }
dfe42443 2977 uart_resume_port(&serial8250_reg, port);
1da177e4
LT		 2978}
2979
2980/*
2981 * Register a set of serial devices attached to a platform device. The
2982 * list is terminated with a zero flags entry, which means we expect
2983 * all entries to have at least UPF_BOOT_AUTOCONF set.
2984 */
3ae5eaec 2985static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2986{
3ae5eaec 2987 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2988 struct uart_port port;
4c0ebb80 2989 int ret, i, irqflag = 0;
1da177e4
LT		 2990
2991 memset(&port, 0, sizeof(struct uart_port));
2992
4c0ebb80
AGR		 2993 if (share_irqs)
2994 irqflag = IRQF_SHARED;
2995
ec9f47cd 2996 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 2997 port.iobase = p->iobase;
2998 port.membase = p->membase;
2999 port.irq = p->irq;
1c2f0493 3000 port.irqflags = p->irqflags;
74a19741
WN		 3001 port.uartclk = p->uartclk;
3002 port.regshift = p->regshift;
3003 port.iotype = p->iotype;
3004 port.flags = p->flags;
3005 port.mapbase = p->mapbase;
3006 port.hub6 = p->hub6;
3007 port.private_data = p->private_data;
8e23fcc8 3008 port.type = p->type;
7d6a07d1
DD		 3009 port.serial_in = p->serial_in;
3010 port.serial_out = p->serial_out;
583d28e9 3011 port.handle_irq = p->handle_irq;
bf03f65b 3012 port.handle_break = p->handle_break;
235dae5d 3013 port.set_termios = p->set_termios;
c161afe9 3014 port.pm = p->pm;
74a19741 3015 port.dev = &dev->dev;
4c0ebb80 3016 port.irqflags |= irqflag;
ec9f47cd
RK		 3017 ret = serial8250_register_port(&port);
3018 if (ret < 0) {
3ae5eaec 3019 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3020 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3021 p->iobase, (unsigned long long)p->mapbase,
3022 p->irq, ret);
ec9f47cd 3023 }
1da177e4
LT		 3024 }
3025 return 0;
3026}
3027
3028/*
3029 * Remove serial ports registered against a platform device.
3030 */
3ae5eaec 3031static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3032{
3033 int i;
3034
a61c2d78 3035 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3036 struct uart_8250_port *up = &serial8250_ports[i];
3037
3ae5eaec 3038 if (up->port.dev == &dev->dev)
1da177e4
LT		 3039 serial8250_unregister_port(i);
3040 }
3041 return 0;
3042}
3043
3ae5eaec 3044static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3045{
3046 int i;
3047
1da177e4
LT		 3048 for (i = 0; i < UART_NR; i++) {
3049 struct uart_8250_port *up = &serial8250_ports[i];
3050
3ae5eaec 3051 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3052 uart_suspend_port(&serial8250_reg, &up->port);
3053 }
3054
3055 return 0;
3056}
3057
3ae5eaec 3058static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3059{
3060 int i;
3061
1da177e4
LT		 3062 for (i = 0; i < UART_NR; i++) {
3063 struct uart_8250_port *up = &serial8250_ports[i];
3064
3ae5eaec 3065 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3066 serial8250_resume_port(i);
1da177e4
LT		 3067 }
3068
3069 return 0;
3070}
3071
3ae5eaec 3072static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3073 .probe = serial8250_probe,
3074 .remove = __devexit_p(serial8250_remove),
3075 .suspend = serial8250_suspend,
3076 .resume = serial8250_resume,
3ae5eaec
RK		 3077 .driver = {
3078 .name = "serial8250",
7493a314 3079 .owner = THIS_MODULE,
3ae5eaec 3080 },
1da177e4
LT		 3081};
3082
3083/*
3084 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3085 * in the table in include/asm/serial.h
3086 */
3087static struct platform_device *serial8250_isa_devs;
3088
3089/*
3090 * serial8250_register_port and serial8250_unregister_port allows for
3091 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3092 * modems and PCI multiport cards.
3093 */
f392ecfa 3094static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3095
3096static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3097{
3098 int i;
3099
3100 /*
3101 * First, find a port entry which matches.
3102 */
a61c2d78 3103 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3104 if (uart_match_port(&serial8250_ports[i].port, port))
3105 return &serial8250_ports[i];
3106
3107 /*
3108 * We didn't find a matching entry, so look for the first
3109 * free entry. We look for one which hasn't been previously
3110 * used (indicated by zero iobase).
3111 */
a61c2d78 3112 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3113 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3114 serial8250_ports[i].port.iobase == 0)
3115 return &serial8250_ports[i];
3116
3117 /*
3118 * That also failed. Last resort is to find any entry which
3119 * doesn't have a real port associated with it.
3120 */
a61c2d78 3121 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3122 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3123 return &serial8250_ports[i];
3124
3125 return NULL;
3126}
3127
3128/**
3129 * serial8250_register_port - register a serial port
3130 * @port: serial port template
3131 *
3132 * Configure the serial port specified by the request. If the
3133 * port exists and is in use, it is hung up and unregistered
3134 * first.
3135 *
3136 * The port is then probed and if necessary the IRQ is autodetected
3137 * If this fails an error is returned.
3138 *
3139 * On success the port is ready to use and the line number is returned.
3140 */
3141int serial8250_register_port(struct uart_port *port)
3142{
3143 struct uart_8250_port *uart;
3144 int ret = -ENOSPC;
3145
3146 if (port->uartclk == 0)
3147 return -EINVAL;
3148
f392ecfa 3149 mutex_lock(&serial_mutex);
1da177e4
LT		 3150
3151 uart = serial8250_find_match_or_unused(port);
3152 if (uart) {
3153 uart_remove_one_port(&serial8250_reg, &uart->port);
3154
74a19741
WN		 3155 uart->port.iobase = port->iobase;
3156 uart->port.membase = port->membase;
3157 uart->port.irq = port->irq;
1c2f0493 3158 uart->port.irqflags = port->irqflags;
74a19741
WN		 3159 uart->port.uartclk = port->uartclk;
3160 uart->port.fifosize = port->fifosize;
3161 uart->port.regshift = port->regshift;
3162 uart->port.iotype = port->iotype;
3163 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3164 uart->port.mapbase = port->mapbase;
3165 uart->port.private_data = port->private_data;
1da177e4
LT		 3166 if (port->dev)
3167 uart->port.dev = port->dev;
8e23fcc8 3168
b5d228cc
SL		 3169 if (port->flags & UPF_FIXED_TYPE)
3170 serial8250_init_fixed_type_port(uart, port->type);
8e23fcc8 3171
7d6a07d1
DD		 3172 set_io_from_upio(&uart->port);
3173 /* Possibly override default I/O functions. */
3174 if (port->serial_in)
3175 uart->port.serial_in = port->serial_in;
3176 if (port->serial_out)
3177 uart->port.serial_out = port->serial_out;
583d28e9
JI		 3178 if (port->handle_irq)
3179 uart->port.handle_irq = port->handle_irq;
235dae5d
PL		 3180 /* Possibly override set_termios call */
3181 if (port->set_termios)
3182 uart->port.set_termios = port->set_termios;
c161afe9
ML		 3183 if (port->pm)
3184 uart->port.pm = port->pm;
bf03f65b
DW		 3185 if (port->handle_break)
3186 uart->port.handle_break = port->handle_break;
1da177e4 3187
af7f3743
AC		 3188 if (serial8250_isa_config != NULL)
3189 serial8250_isa_config(0, &uart->port,
3190 &uart->capabilities);
3191
1da177e4
LT		 3192 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3193 if (ret == 0)
3194 ret = uart->port.line;
3195 }
f392ecfa 3196 mutex_unlock(&serial_mutex);
1da177e4
LT		 3197
3198 return ret;
3199}
3200EXPORT_SYMBOL(serial8250_register_port);
3201
3202/**
3203 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3204 * @line: serial line number
3205 *
3206 * Remove one serial port. This may not be called from interrupt
3207 * context. We hand the port back to the our control.
3208 */
3209void serial8250_unregister_port(int line)
3210{
3211 struct uart_8250_port *uart = &serial8250_ports[line];
3212
f392ecfa 3213 mutex_lock(&serial_mutex);
1da177e4
LT		 3214 uart_remove_one_port(&serial8250_reg, &uart->port);
3215 if (serial8250_isa_devs) {
3216 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3217 uart->port.type = PORT_UNKNOWN;
3218 uart->port.dev = &serial8250_isa_devs->dev;
cb01ece3 3219 uart->capabilities = uart_config[uart->port.type].flags;
1da177e4
LT		 3220 uart_add_one_port(&serial8250_reg, &uart->port);
3221 } else {
3222 uart->port.dev = NULL;
3223 }
f392ecfa 3224 mutex_unlock(&serial_mutex);
1da177e4
LT		 3225}
3226EXPORT_SYMBOL(serial8250_unregister_port);
3227
3228static int __init serial8250_init(void)
3229{
25db8ad5 3230 int ret;
1da177e4 3231
a61c2d78
DJ		 3232 if (nr_uarts > UART_NR)
3233 nr_uarts = UART_NR;
3234
f1fb9bb8 3235 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3236 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3237 share_irqs ? "en" : "dis");
3238
b70ac771
DM		 3239#ifdef CONFIG_SPARC
3240 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3241#else
3242 serial8250_reg.nr = UART_NR;
1da177e4 3243 ret = uart_register_driver(&serial8250_reg);
b70ac771 3244#endif
1da177e4
LT		 3245 if (ret)
3246 goto out;
3247
7493a314
DT		 3248 serial8250_isa_devs = platform_device_alloc("serial8250",
3249 PLAT8250_DEV_LEGACY);
3250 if (!serial8250_isa_devs) {
3251 ret = -ENOMEM;
bc965a7f 3252 goto unreg_uart_drv;
1da177e4
LT		 3253 }
3254
7493a314
DT		 3255 ret = platform_device_add(serial8250_isa_devs);
3256 if (ret)
3257 goto put_dev;
3258
1da177e4
LT		 3259 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3260
bc965a7f
RK		 3261 ret = platform_driver_register(&serial8250_isa_driver);
3262 if (ret == 0)
3263 goto out;
1da177e4 3264
bc965a7f 3265 platform_device_del(serial8250_isa_devs);
25db8ad5 3266put_dev:
7493a314 3267 platform_device_put(serial8250_isa_devs);
25db8ad5 3268unreg_uart_drv:
b70ac771
DM		 3269#ifdef CONFIG_SPARC
3270 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3271#else
1da177e4 3272 uart_unregister_driver(&serial8250_reg);
b70ac771 3273#endif
25db8ad5 3274out:
1da177e4
LT		 3275 return ret;
3276}
3277
3278static void __exit serial8250_exit(void)
3279{
3280 struct platform_device *isa_dev = serial8250_isa_devs;
3281
3282 /*
3283 * This tells serial8250_unregister_port() not to re-register
3284 * the ports (thereby making serial8250_isa_driver permanently
3285 * in use.)
3286 */
3287 serial8250_isa_devs = NULL;
3288
3ae5eaec 3289 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3290 platform_device_unregister(isa_dev);
3291
b70ac771
DM		 3292#ifdef CONFIG_SPARC
3293 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3294#else
1da177e4 3295 uart_unregister_driver(&serial8250_reg);
b70ac771 3296#endif
1da177e4
LT		 3297}
3298
3299module_init(serial8250_init);
3300module_exit(serial8250_exit);
3301
3302EXPORT_SYMBOL(serial8250_suspend_port);
3303EXPORT_SYMBOL(serial8250_resume_port);
3304
3305MODULE_LICENSE("GPL");
d87a6d95 3306MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3307
3308module_param(share_irqs, uint, 0644);
3309MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3310 " (unsafe)");
3311
a61c2d78
DJ		 3312module_param(nr_uarts, uint, 0644);
3313MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3314
d41a4b51
CE		 3315module_param(skip_txen_test, uint, 0644);
3316MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3317
1da177e4
LT		 3318#ifdef CONFIG_SERIAL_8250_RSA
3319module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3320MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3321#endif
3322MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
kernel source for telekom puls (alcatel/mediatek)